TW201140664A - Method for acquiring recycled chips and method for fabricating semiconductor package - Google Patents

Method for acquiring recycled chips and method for fabricating semiconductor package Download PDF

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Publication number
TW201140664A
TW201140664A TW099114322A TW99114322A TW201140664A TW 201140664 A TW201140664 A TW 201140664A TW 099114322 A TW099114322 A TW 099114322A TW 99114322 A TW99114322 A TW 99114322A TW 201140664 A TW201140664 A TW 201140664A
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Taiwan
Prior art keywords
substrate
wafer
wafers
thickness
chips
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TW099114322A
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Chinese (zh)
Inventor
En-Min Jow
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Aptos Technology Inc
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Priority to TW099114322A priority Critical patent/TW201140664A/en
Priority to JP2011101540A priority patent/JP5226828B2/en
Publication of TW201140664A publication Critical patent/TW201140664A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

A method for acquiring recycled chips is proposed, comprising collecting chips that are abandoned after a first testing and placing the abandoned chips on a substrate; performing a singulation/cutting process to obtain individual chips; and conducting a second testing on the chips disposed on the substrate so as to pick out chips that are recyclable, thereby allowing a chip structure after the singulation to have a thickness sufficient for the subsequent processing of recycling. The invention further provides a method for fabricating a semiconductor package.

Description

201140664 六、發明說明: 【發明所屬之技術領域】 ? 本發明係有關於-種回收晶片之測試及供後製程易 •於處理之方法,尤指-種取得供再利用之晶片及其 封裝件之製法。 ' ' 【先前技術】 早期晶圓(wafer)之厚度約為1〇至3〇mil,經多道測 試階段後,會產生部分未通過測試之晶片(die),而經切單 鲁後該些晶片將被回收,且以較便宜的價格販賣至有需要的 廠商。隨著科技的進步及薄小化的需求,目前晶圓之厚度 約為1至3mil ;然而,因目前的晶片過薄,若將該捨棄: 晶片回收加王,往往於加工過程中晶片因強度不足而破 裂’故多數薇商只能將該些晶片報廢,而無法再利用該捨 棄之晶片,不僅不環保,也造成資源浪費。 因此,如何克服現有技術之瓶頸,取得供再利用之晶 片,實已成目前亟欲解決的課題。 曰曰 【發明内容】 鑑於上述習知技術之種種缺失,本發明之主要目的係 在提供一種自回收之複數晶片取得供再利用之晶片的方 法。 為達上述及其他目的,本發明揭露一種自回收之 ^料供再利用之晶片的方法,係包括:收集複數經第 —-人測5式後捨棄之晶將該些晶片放置於一基板上·切 m板’使各該晶片彼此分離;以及將該些置於該基板[s 111612 3 201140664 儿片進行第二次測試,以挑選出有用的晶片。 心2之方法中’該晶片之厚度係為1至3mU,且錢 或金^料5至㈤,又形成該基板之材質係為介電^ 且各法中,該基板表面上劃分有複數個置晶區, : = 各該趣上;— ^發明復揭露—種以回收之晶片製作半導體封裝件 之再利··㈣餘據㈣枝取狀設於基板上 件;开1 承餅上;電性連接該晶片與承载 7 f裝膠體’以包覆該晶片;以及 到複數半導體封裝件。 丁刀早以付 前述之方法中,該晶片之厚度係為U3mii,且該美 係為5至6mii,又該些基板藉由結合層以設於i 曰由上可知,本發明之自回收之複數晶片取得供再利用 =晶片的方法’藉由將薄晶片設於較厚之基板上以令切 2後之整體結構之厚度達到後續製程所需的厚度,可避免 白知技術中之晶片因過薄而破裂’故本發明設於該基板上 之晶片可繼續加工,以達到回收再利用之目的,且符合 保之需求。 义 【實施方式】 、以下藉由特疋的具體實施例說明本發明之實施方 式’熟悉此技藝之人士可由本說明#所揭示之内容輕易地 111612 4 201140664 瞭解本發明之其他優點及功效。 請參閱第1A至1C圖,係為本發明所揭露之一種自回 - 收之複數晶片取得供再利用之晶片的方法。 如第1A圖所示之晶圓的局部上視圖,從經切割後的 ^圓收集複數經第—次賴後捨棄(具有小瑕絲達需求 標準)之晶片10’如圖中標記△者;其中,該晶片1〇之厚 度係為1至3mil。於本發明中,小瑕疵係表示未符合原始 設計之瑕疫,例如可能因線路傳遞速率較慢、反應速度較 ·=容量較少等因素,但仍可用於後端應用產品且用於可 符口客戶規格之產品,又小瑕疫也可能是其他不影響晶片 10功I之缺失或僅僅是外觀上之細微破損。 ^詳細地,例如:NANDFlash搭配一控制器可組成一記 卡,當NAND Flash之晶片容量較少時,仍可利用控制器 補足,以組成一合格之記憶卡。因此,即便挑選具有容量 較少之瑕疯的晶片,仍可藉由其他裝置或配備之輔助,而 鲁達到產品規格之需求。 如第1B圖所示之基板剖面圖,將各該具有小瑕疵之 ,片10藉由結合層1〇a以放置於一基板丨丨上,再進行切 單乍業係/σ切吾叙想線S切割該基板1 1以使各該晶片 1〇彼此分離;其中’該基板11之厚度係為5至6mil,且 形成5亥基板11之材質可為介電材或金屬,又該結合層他 係可為黏膠或其他貼合元件。 〇所述之基板11表面上可劃分有複數置晶區A,該置晶 區A可為條狀、陣列式排設或依測試機具做其他排設,且 II16I2 5 201140664201140664 VI. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a method for testing a recovered wafer and a method for processing the same, and particularly for obtaining a wafer for re-use and a package thereof. The method of production. ''[Prior Art] Early wafers have a thickness of about 1 〇 to 3 〇 mil. After multiple test stages, some untested dies will be produced, and after cutting The wafers will be recycled and sold to manufacturers in need at a lower price. With the advancement of technology and the demand for thinning, the thickness of wafers is currently about 1 to 3 mils; however, because the current wafer is too thin, if it is abandoned: wafer recycling plus king, often due to the strength of the wafer during processing Insufficient and ruptured', so most Wei merchants can only scrap the chips, and can no longer use the discarded chips, which is not only environmentally friendly, but also wastes resources. Therefore, how to overcome the bottleneck of the prior art and obtain a wafer for reuse has become a problem that is currently being solved. SUMMARY OF THE INVENTION In view of the above-described deficiencies of the prior art, the primary object of the present invention is to provide a method for obtaining a wafer for reuse from a plurality of recovered wafers. To achieve the above and other objects, the present invention discloses a method for self-recycling a wafer for recycling, which comprises: collecting a plurality of crystals discarded by the first method and placing the wafer on a substrate. • Cutting the plate 'to separate the wafers from each other; and placing the portions on the substrate [s 111612 3 201140664 for a second test to pick out useful wafers. In the method of the core 2, the thickness of the wafer is 1 to 3 mU, and the material or the material 5 to 5 is formed, and the material of the substrate is dielectric ^ and in each method, the surface of the substrate is divided into a plurality of Crystallization area, : = Each of the interest; - ^ Invented re-exposure - the production of semiconductor packages by recycling wafers (4) Residual data (4) Branches are placed on the upper part of the substrate; open 1 on the cake; Electrically connecting the wafer with a 7f-loaded colloid' to coat the wafer; and to a plurality of semiconductor packages. In the method described above, the thickness of the wafer is U3mii, and the US system is 5 to 6 mii, and the substrates are known by the bonding layer, and the self-recycling of the present invention is known. The method of obtaining a plurality of wafers for reuse = wafers can be avoided by setting a thin wafer on a thick substrate so that the thickness of the entire structure after cutting 2 reaches the thickness required for the subsequent process. The wafer is too thin and ruptured. Therefore, the wafer provided on the substrate of the present invention can be further processed for the purpose of recycling and recycling, and meets the demand for protection. [Embodiment] The following describes the embodiments of the present invention by way of specific embodiments. Those skilled in the art can readily appreciate the other advantages and effects of the present invention from the disclosure of the present invention. Please refer to FIGS. 1A to 1C for a method for obtaining a wafer for reuse from a self-returning-receiving plurality of wafers. A partial top view of the wafer as shown in FIG. 1A, the wafer 10' which is collected from the cut circle after the first pass and discarded (with the small silk wire demand standard) is marked as Δ in the figure; Wherein, the thickness of the wafer is 1 to 3 mils. In the present invention, the small sputum indicates that the plague does not conform to the original design, for example, may be due to slower transmission rate of the line, less reaction speed, less capacity, etc., but can still be used for the back-end application product and can be used for The product of the customer's specification, and the small plague may also be the other that does not affect the lack of the wafer 10 or only the appearance of minor damage. ^ In detail, for example, NANDFlash can be combined with a controller to form a card. When the NAND Flash chip has a small capacity, the controller can still be used to make up a qualified memory card. Therefore, even if you choose a chip with less capacity, you can still meet the product specifications with the help of other devices or equipment. According to the cross-sectional view of the substrate shown in FIG. 1B, each of the sheets 10 having a small flaw is placed on a substrate by the bonding layer 1〇a, and then the cutting unit is cut and the sigma is cut. The substrate S cuts the substrate 1 1 to separate the wafers 1 from each other; wherein the thickness of the substrate 11 is 5 to 6 mils, and the material forming the substrate 11 can be a dielectric material or a metal, and the bonding layer He can be a glue or other fitting element. The surface of the substrate 11 can be divided into a plurality of crystallographic regions A, which can be strip-shaped, array-arranged or arranged according to test tools, and II16I2 5 201140664

各該晶片10係分別置於各該置晶HA上,而該置晶區A 之面積大於该單一晶片1 〇之尺寸,以利於切單作業。 接著,將該些置於該基板丨丨上之晶片1〇進行第二次 測試,以挑選出如第1C圖所示之有用的晶片結構丨,所述 之晶片結構1係為該晶片10設於該基板11上。 本發明藉由將薄晶片10設於較厚之基板11上,以令 晶片結構1之厚度H可達到後續製程所需的厚度,可避免 該晶片10因破裂而無法再利用,故本發明之晶片結“ 可以較便宜的價格繼續供應下游廠商,進而達到回收再利 用之目的。 另一方面,本發明復提供一種以回收之晶片製作半導 體封裝件之方法,係包括下列步驟: 如第2A圖所示,將複數根據前述測試方法取得之有 用的晶片結構i置於-承載件2G上,並電性連接該晶片 10與承載件20。於本實施例中’所述之承載件2〇係為電 路板,而該晶片H)係可藉由銲線21電性連接該電路板, 且泫些基板11藉由結合層20a以設於該承載件2〇上,又 該結合層20a係可為黏膠或其他貼合元件。 如第2B圖所示之剖面目,形成封裂夥體22於該 件20上,以包覆該晶片結構1。 —如第沉圖所示之剖面圖,係顯示沿第2B圖所示之士 割假想線κ進行切單’以得到複數半導體封裝件2。然而^ 應了解的是晶片的封裝件之種類$多,例如:導線年、’ 覆晶式、嵌埋式等,並不限於上述,特此述明。舉例:士、 111612 6 201140664 若以導線架作為承載件,則封裝膠體將可復包覆導線架的 内導腳,以完整保護晶片。 综上所述,本發明之自經回收之複數晶片測試並取得 供再利用之晶片的方法,藉由將小瑕疵之晶片設於基板 上,以增加整體結構之厚度而達到後續製程所需的厚度, 進而可繼續加工,有效達到回收再利用之目的,且符合環 保之需求。 ▲上述實施例係用以例示性t兒明本發明之原理及其功 效’而非用於限制本發明。4壬何熟習此項技藝之人士均可 在不違背本發明之精神及料下,對上述實施例進行修 改。因此本發明之權利保護範圍,應如後述之申請專利範 圍所列。 【圖式簡單說明】 利用I :21C圖係ί發明之自回收之複數晶片取得供, 部上視a曰·笫不忍圖’其中’第1Α圖係顯示晶圓的力 = 圖係顯示晶片置於基板後之剖面圖1 圖·員不經第二次測試後之晶片結構·以及 第2Α至2(:圖係顯示本發明之 之 體封裝件时法,其巾,帛2A 收之^製作+ _ 件之剖面圖;f 示晶片結構置於承載 係顯示切單㈣咖柄_;以及第况圖 【主要元件符號說明】 1 曰曰 片結構 晶片 111612 7 10 201140664 10a、20a 結合層 11 基板 2 半導體封裝件 20 承載件 21 銲線 22 封裝膠體 A 置晶區 H 厚度 S、K 假想線Each of the wafers 10 is placed on each of the crystallized HAs, and the area of the crystallographic regions A is larger than the size of the single wafer 1 to facilitate the singulation operation. Then, the wafers 1 on the substrate are subjected to a second test to select a useful wafer structure as shown in FIG. 1C, and the wafer structure 1 is the wafer 10. On the substrate 11. In the present invention, the thin wafer 10 is disposed on the thick substrate 11 so that the thickness H of the wafer structure 1 can reach the thickness required for the subsequent process, and the wafer 10 can be prevented from being reused due to cracking, so the present invention The wafer junction "can continue to be supplied to downstream manufacturers at a relatively low price, thereby achieving the purpose of recycling. On the other hand, the present invention provides a method for fabricating a semiconductor package from a recycled wafer, comprising the following steps: As shown, a plurality of useful wafer structures i obtained according to the foregoing test method are placed on the carrier 2G, and the wafer 10 and the carrier 20 are electrically connected. In the present embodiment, the carrier 2 is described. The circuit board is electrically connected to the circuit board by the bonding wire 21, and the substrate 11 is disposed on the carrier 2 by the bonding layer 20a, and the bonding layer 20a is An adhesive or other conforming element. As shown in Fig. 2B, a sealing body 22 is formed on the member 20 to cover the wafer structure 1. - a cross-sectional view as shown in the first sinking diagram, Shows the imaginary line along the line shown in Figure 2B The singulation is performed to obtain the plurality of semiconductor packages 2. However, it should be understood that there are many types of packages of the wafer, such as wire years, 'clad, embedded, etc., and are not limited to the above. Example: Shi, 111612 6 201140664 If the lead frame is used as the carrier, the encapsulant will cover the inner guide of the lead frame to completely protect the wafer. In summary, the self-recovered multi-chip of the present invention The method of testing and obtaining a wafer for reuse, by placing the wafer of the small crucible on the substrate, increasing the thickness of the overall structure to achieve the thickness required for the subsequent process, and further processing can be carried out, thereby effectively achieving the purpose of recycling. The above embodiments are intended to be illustrative of the principles and effects of the present invention, and are not intended to limit the invention. 4 Those who are familiar with the art may do not violate this The above embodiments are modified under the spirit of the invention. Therefore, the scope of protection of the present invention should be as listed in the patent application scope described later. [Simple description of the drawing] Using I: 21C According to the invention, the self-recovery of the plurality of wafers is obtained. The top view shows that the first picture shows the force of the wafer = the figure shows the profile of the wafer after the substrate is placed. After the second test, the wafer structure and the second to the second (the figure shows the body package of the present invention, the towel, the 帛2A, the y-piece, the y-piece section; f shows the wafer structure Placed on the load-bearing system to display the cut-off (4) coffee handle _; and the condition map [main component symbol description] 1 结构 film structure wafer 111612 7 10 201140664 10a, 20a bonding layer 11 substrate 2 semiconductor package 20 carrier 21 welding wire 22 Package colloid A crystal zone H thickness S, K imaginary line

Claims (1)

201140664 七、申請專利範圍: 1. 一種自回收之複數晶片取得供再利 , 包括: 疋日日片的方法,係 * 收集複數經第一次測試後捨棄之晶片; 將該些晶片放置於一基板上; 切割該基板,使各該晶片彼此分離;以及 將該些置於該基板上之晶片進行第 選出有用的晶片。 弟人H以挑 ♦ 2.如申請專利範圍第η所述之方法, 度係為1至3mU。 -中该曰曰片之厚 3.如申請專利範㈣i項所述之方法 度係為5i6mil。 、〒該基板之厚 4·如申請專利範㈣!項所述之方法,其中,形成 之材質係為介電材或金屬。 5.如申請專利範㈣】項所述之方法,其中, π申明專利範圍第1項所述 7由結合相設於該基板上 其中’該些晶片藉 7.—種以回收之晶片製作半導體雜件之方法,係包括: ^數根射請專職圍第丨項取得之設於該基 板上的晶片置於承載件上; 黾性連接該晶片與承載件; 形成封裝膠體,以包覆該晶片;以及 進仃切單,以得到複數半導體封裝件。 L 111612 9 201140664 8. 如申請專利範圍第7 度係為1至3mil。 項所述之方法,其中 9*如申請專利範㈣7項所述之方法,其中 由結合層以設於該承載件上。 10·如申請專利範圍帛7項所述之方法,其中 度係為5至6mi 1。 ,該晶片之厚 ’該些基板藉 ’該基板之厚 ⑴612201140664 VII. Scope of application for patents: 1. A self-recovering multi-chip obtained for re-profit, including: The method of the next day, the system* collects the wafers discarded after the first test; the wafers are placed in one On the substrate; cutting the substrate to separate the wafers from each other; and performing the selected useful wafer on the wafers placed on the substrate. The younger person H picks up ♦ 2. As described in the patent application scope η, the degree is 1 to 3 mU. - The thickness of the cymbal is 3. The method described in the patent application (4) i is 5i6mil. 〒The thickness of the substrate 4·If you apply for a patent (4)! The method of the invention, wherein the material formed is a dielectric material or a metal. 5. The method as claimed in claim 4, wherein the π-claimed patent range item 1 is formed by combining the phases on the substrate, wherein the wafers are made of the recovered wafer. The method of miscellaneous parts includes: ^ a number of shots, the wafers disposed on the substrate obtained by the full-scale 丨 丨 置于 置于 置于 置于 置于 置于 置于 置于 置于 置于 置于 置于 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片a wafer; and a dicing die to obtain a plurality of semiconductor packages. L 111612 9 201140664 8. The 7th degree of the patent application range is 1 to 3 mils. The method of claim 7, wherein the method of claim 4, wherein the bonding layer is provided on the carrier. 10. The method of claim 7, wherein the degree is 5 to 6 mi 1. , the thickness of the wafer 'the substrate borrows' the thickness of the substrate (1) 612
TW099114322A 2010-05-05 2010-05-05 Method for acquiring recycled chips and method for fabricating semiconductor package TW201140664A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW099114322A TW201140664A (en) 2010-05-05 2010-05-05 Method for acquiring recycled chips and method for fabricating semiconductor package
JP2011101540A JP5226828B2 (en) 2010-05-05 2011-04-28 Method for obtaining reusable chip from recovered chip and method for manufacturing semiconductor package

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