TW201138024A - Interfacial layers for electromigration resistance improvement in damascene interconnects - Google Patents

Interfacial layers for electromigration resistance improvement in damascene interconnects Download PDF

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TW201138024A
TW201138024A TW100101507A TW100101507A TW201138024A TW 201138024 A TW201138024 A TW 201138024A TW 100101507 A TW100101507 A TW 100101507A TW 100101507 A TW100101507 A TW 100101507A TW 201138024 A TW201138024 A TW 201138024A
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Taiwan
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layer
dielectric
copper
substrate
metal
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TW100101507A
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Chinese (zh)
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TWI612618B (en
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Ananda Banerji
George Andrew Antonelli
Jennifer O'loughlin
Mandyam Sriram
Schravendijk Bart Van
Seshasayee Varadarajan
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Novellus Systems Inc
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Priority claimed from US12/688,154 external-priority patent/US8268722B2/en
Priority claimed from US12/689,803 external-priority patent/US7858510B1/en
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Publication of TW201138024A publication Critical patent/TW201138024A/en
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Publication of TWI612618B publication Critical patent/TWI612618B/en

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    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Protective caps residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Protective caps are formed by depositing a first layer of aluminum-containing material over an exposed copper line by treating an oxide-free copper surface with an organoaluminum compound in an absence of plasma at a substrate temperature of at least about 350 DEG C. The formed aluminum-containing layer is passivated either partially or completely in a chemical conversion which forms Al-N, Al-O or both Al-O and Al-N bonds in the layer. Passivation is performed in some embodiments by contacting the substrate having an exposed first layer with an oxygen-containing reactant and/or nitrogen-containing reactant in the absence of plasma. Protective caps can be formed on substrates comprising exposed ULK dielectric. The aluminum-containing layer residing on the dielectric portion will typically spontaneously form non-conductive layer comprising Al-O bonds.

Description

201138024 六、發明說明： 【發明所屬之技術領域】 本發明係關於在部分製造之積體電路上形成材料層的方 法°特定而言’本發明係關於在銅線内形成保護蓋以便改 進鑲嵌互連件之電遷移性質的方法。 【先前技術】 鑲敌處理為一種用於在積體電路上形成金屬線之方法。 其涉及在介電層（層間介電質）中所形成之溝槽及介層孔中 形成嵌入金屬線。鑲嵌處理通常為較佳方法，因為其需要 比其他方法少之處理步驟且提供較高良率。其亦尤其良好 適合於諸如銅等不能容易被電漿蝕刻圖案化之金屬。 在典型之鑲嵌製程流程中，金屬沈積至經圖案化之介電 質上以填充介電層中所形成之介層孔及溝槽。所得金屬化 層通常直接形成於承載主動器件之層上，或形成於下伏 (lower-lying)金屬化層上。介電質擴散障壁材料之薄層（諸 如，碳化矽或氮化矽）沈積於鄰近之金屬化層之間，以防 止金屬擴散至介電質之大部分層中。在一些情況下，碳化 矽或氮化矽介電質擴散障壁層在層間介電質（ild)之圖案 化期間亦充當蝕刻終止層。 在典型的積體電路（1C)中， ’若干金屬化層彼此層疊地沈201138024 VI. Description of the Invention: [Technical Field] The present invention relates to a method of forming a material layer on a partially fabricated integrated circuit. In particular, the present invention relates to forming a protective cover in a copper wire to improve mosaic. A method of electromigration properties of a piece. [Prior Art] The enemies are processed as a method for forming metal lines on an integrated circuit. It involves forming an embedded metal line in the trenches and via holes formed in the dielectric layer (interlayer dielectric). Mosaic processing is often the preferred method because it requires fewer processing steps than other methods and provides higher yields. It is also particularly well suited for metals such as copper that cannot be easily patterned by plasma etching. In a typical damascene process, metal is deposited onto the patterned dielectric to fill the vias and trenches formed in the dielectric layer. The resulting metallization layer is typically formed directly on the layer carrying the active device or on the lower-lying metallization layer. A thin layer of dielectric diffusion barrier material, such as tantalum carbide or tantalum nitride, is deposited between adjacent metallization layers to prevent diffusion of the metal into most of the dielectric layer. In some cases, the tantalum carbide or tantalum nitride dielectric diffusion barrier layer also acts as an etch stop layer during the patterning of the interlayer dielectric (ild). In a typical integrated circuit (1C), 'several metallization layers are stacked one on another

而連接至下伏或上覆層之導電路徑。And connected to the conductive path of the underlying or overlying layer.

153514.doc 201138024 寸持續縮減而變得愈來愈明顯。當前，在9〇 11111技術節點 處以及在更先進節點處，非常需要可提供具有改進之使用 壽命及可靠性之互連件的互連件製造方法。 【發明内容】 在I c製造期間遇到的一個具有挑戰性的問題為電遷移故 障。當互連件所經歷之高電流密度導致金屬原子隨電流遷 移且因此導致在互連件内形成空隙時發生電遷移。最終， 空隙之形成可導致器件故障，稱為電遷移故障。在IC器件 之正在進行_之小型化期間，互連件尺寸減小，且互連件 經歷較大電流密度。因此，電遷移故障之可能性隨著此器 件小型化而增加。雖然銅具有比鋁大的電遷移電阻（甚至 在銅互連件中），但電遷移故障在45 nm技術節點處以及在 更先進節點處成為重大的可靠性問題。 本文提供能夠改進互連件之電遷移效能的駐留於金屬線 與介電質擴散障壁（或蝕刻終止）層之間的界面處之保護 蓋。亦描述形成此類蓋之方法。有利的是，所描述之保護 蓋可形成為駐留於金屬線之上部部分内處於其與介電質擴 散障壁層之界面處的非常薄的層，而不會顯著增加互連件 電阻。保護罩蓋層可包括（例如）互連件金屬（諸如銅）與摻 雜兀素（諸如硼、鋁、鈦等）之固溶體、合金或化合物。在 許多實施例中’選擇將與互連件金屬形成合金及/或將聚 集於era粒邊界處的摻雜元素為有利的，藉此減少互連件金 屬原子之遷移。 所提供之方法藉由在暴露之金屬線上沈積摻雜劑產生材 153514.doc 201138024 料（例如，含有 B、Τί Μ + _LL ,,·、 材料）的源層，將該源層之 上。以分轉化為鈍化層（例如，氮化物或氧化物），同時允 許摻雜劑產生源層之未改質部分保持與互連件金屬接觸， ::後允許來自源層之未改質部分的摻雜劑擴散至互連件 金屬中及/或與互連件金屬反應，而實現對保護蓋之厚声 的控制。P個實施例中，引人至互連件t之摻雜劑的量 又與互連件接觸而駐留的源層之未改質部分的厚度限制。 在其他實施例中，引人至互連件中之摻雜劑的量藉由控制 擴散及/或反應期間之溫度來控制。 有利的是’以此受控方式形成之薄保護蓋不會顯著增加 互連件之電阻，如當量高度反應性或易擴散之掺雜劑 (例如’ Si或Ge)沈積至互連件金屬上時通常無意發生的。 另卜如將把述，所提供之方法適合於由以極少選擇性或 零選擇J·生/尤積至暴露之金屬及介電質兩者上的摻雜劑產生 源層形成保護罩蓋層。應理解，此等方法亦可在含摻雜劑 之源層僅選擇性地沈積至金屬層上而不顯著沈積至介電質 上的彼等情況中使用。 根據一個態樣’提供一種形成半導體器件結構之方法β 在一個實施例中，該方法包括以下操作：（a)使具有暴露之 第一金屬層（例如’銅或銅合金）及暴露之介電層的基板與 包含棚或第二金屬（例如，Al、Hf、Ti、Co、Ta、Mo、 Ru、Sn、Sb等）之化合物接觸，以在介電質及第一金屬兩 者上沈積包含硼或第二金屬之源層；（b)對至少在第一金屬 之區上之源層的頂部部分進行改質以形成鈍化層，其中未 153514.doc 201138024 經改質源層之-部分保持與第—金屬層接觸；及⑷允許來 自未’.星改質源層之有效成分擴散至第一金屬中及/或與第 金屬反應，並在第一金屬層内形成保護蓋。 在一個實施例中，基板為含有内嵌於層間金屬介電層中 之暴露銅線的鑲嵌結構。在沈積源層之前，基板可視情況 預先清潔以自銅表面移除污染物（例如，氧化銅）。舉例而 5，可藉由將基板暴露於電漿中之還原氣體（例如，^或 NH3)而執行預先清潔。可接著藉由在某一溫度下使基板與 揮發性摻雜劑前驅體接觸而沈積含有摻雜劑源（有效成分） 的源層。通常（儘管並非必需），在無電漿放電的情況下用 熱方法執行源層之沈積。預先清潔及源層之沈積可在無真 空破壞的CVD裝置中執行（例如，在相同處理腔室中 在一個實施例中，藉由在無電漿放電的情況下在約2〇〇_ 4〇〇°c之間的腔室溫度下使基板與含有B2H6(或其他揮發性 之含硼前驅體）及惰性載氣之氣體混合物接觸而沈積含硼 源層。沈積腔室中之壓力維持在約0.5-10托的範圍内，且 氣體混合物中之濃度範圍在約0.5至2〇體積％之間。在 此些條件下，將含硼源層沈積至暴露之介電層上以及基板 之金屬部分上。發現源層含有B-H鍵且因此將稱為ΒΗχ 層。 在許多實施例中，歸因於金屬表面處之較高前驅體分解 速率’與其介電質部分相比，較大量之摻雜劑源材料沈積 於基板之金屬部分上。因此，在此等實施例中，沈積於金 屬部分上之源層的厚度大於沈積於介電質上之源層的厚 153514.doc 201138024 度。然而’對於許多含硼前驅體且對於含金屬前驅體而 言，金屬與介電質之間的完全沈積選擇性通常難以獲得。 有利的是’所描述之沈積方法不需要用於源層之沈積的絕 對金屬/介電質選擇性。 在一些實施例中，藉由在適合於引起前驅體分解及基板 上含有金屬之層之沈積的溫度及壓力下使基板與揮發性含 金屬前驅體（諸如，金屬齒化物、金屬氫化物、金屬羰基 合物或揮發性有機金屬化合物）接觸而沈積含金屬源層。 在許多情況下’使用如上文針對bhx層之沈積列舉的類似 溫度及壓力範圍β熟習此項技術者將理解如何針對不同類 型之金屬前驅體而最佳化沈積條件。 許多金屬適合作為用於形成保護蓋之摻雜劑。此等金屬 包括形成固溶體、合金或與互連件金屬之金屬間相的金 屬’以及能夠在互連件中在晶粒邊界處擴散及聚集的金 屬。舉例而言，A1、Hf、Ti、Co、Ta、Mo、RU、Sn及 Sb 可用作保護蓋之組分。亦可採用此等金屬彼此或與其他金 屬之合金及固溶體。用於含鋁源層之合適之揮發性前驅體 包括（但不限於）三曱基鋁、氫化二曱基鋁、三乙基鋁、三 異丁基銘及參（二乙胺基）铭。用於其他金屬之沈積的合適 之前驅體包括（但不限於）雙（環戊二烯）鈷、乙醢丙酮鈷 (Π)、肆（二甲胺基）姶、肆（二乙胺基）铪、肆（二甲胺基） 在目、肆（二甲胺基）鈦（TDMAT)、肆（二乙胺基）鈦（TDEAT)、 肆（乙基曱基胺基）鈦、雙（二乙胺基）雙（二異丙基胺基）鈦、 五（二甲胺基）钽、第三（丁基三亞胺基）（二乙胺基）鈕 153514.doc 201138024 (TBTDET)、五（二乙胺基）组、雙（乙基環戊二烯说二 甲胺基）録及四甲基錫。 如所提及，在沈積含有侧或金屬之源層之後，其頂部部 刀經改質Μ形成鈍化層，例如含有氮化物或氧化物之層， 而其底部部分保持未經改f且與互連件金屬接觸。在許多 實施例中，在源層在金屬上比在介電質上沈積至更大厚度 的it況下’改質操作將駐留於介電質上之源層的部分完全 轉化為含有具有低導電率之材料（例如，BN〆八叫等）的 鈍化層。執行此類改質以防止鄰近互連件之間的短路。此 外，駐留於金屬線上之源層的部分改質用以控制駐留於層 中的摻雜劑的量’且提供控制保護蓋之厚度並因此控制互 連件電阻率的途徑。 可使用許多製程來形成純化層。在—個實施例中藉由 在電漿放|中將基板暴露於含氣反應物而對源層進行改 質。舉例而言，可使用νη3、Ν2Η4、胺、Ν2及其混合物。 在一特定實例中’藉由在電聚中使基板與ν2_η3之混合 物接觸而對ΒΗΧ源層進行改f以形成含有ΒΝΧ之鈍化層: 2其他實施例中，藉由在電漿放電中將基板暴露於含氧化 合物（例如，02、Ν20或C〇2)而對源層（例如，含金屬源層） 進行改質，以形成含有氧化物（例如，氧化鋁、氧化鈦等） 之鈍化層。在其他實施例中，在電漿中以含有碳之反應物 對源層進行改質以形成含有碳化物或碳氫化合物（例如， BCX、CxHy專）之純化層。 經改質層之厚度可按需調整。藉由控制經改質層的厚 153514.doc 201138024 度’控制含有摻雜劑源之剩餘未經改質層的厚度，從而亦 產生對互連件内之保護蓋的厚度的控制。舉例而言，駐留 於金屬線上之源層厚度的約20-60%之間可經改質以形成鈍 化層’同時留下未經改質之含有摻雜劑的部分與金屬線接 觸。在一個實例中’駐留於金屬線上之源層具有約5〇_5〇〇 入之厚度。在源層厚度之約20-60%之間被轉化為鈍化層之 後’未經改質之源層的約20-400 A之間保持與金屬線接 觸。 接下來’在形成經改質層之後’允許來自未經改質之源 層之有效成分擴散至互連件金屬中及/或與互連件金屬反 應’並在互連件金屬之層内形成保護蓋。在一些實施例 中，在形成保護蓋之前，首先在源層内產生有效成分。取 決於有效成分之性質，多種條件可用於產生有效成分並促 進其擴散至互連件金屬中。在一些實施例中，將基板暴露 於高溫持續預定時間量促進在金屬互連件内形成保護蓋。 在其他實施例中，保護蓋之形成在容許有足夠時間用於摻 雜劑擴散之後在室溫下發生。 在些實施例中，在形成鈍化層之後，將蝕刻終止層或 ^電質擴散障壁層（例如，包含經摻雜或未經掺雜碳化石夕 或氮化矽之層）沈積至鈍化層上。在其他實施例中，鈍化 層本身可充當蝕刻終止層或介電質擴散障壁層，且不需要 獨立的银刻終止層。在後一實施例中，將金屬間介電質直 接沈積至鈍化層上。 在一些實施例中，在沈積介電質擴散障壁或姓刻終止層 153514.doc 201138024 之後執行藉由允許摻雜劑擴散至互連件金屬中及/或與互 連件金屬反應而進行的互連件金屬之摻雜。舉例而言，基 板可在蝕刻終止層（例如，碳化矽層）已經沈積之後經加熱 至至少約1 oo°c以促進形成保護蓋。 有利的是，在一些實施例中，在一個模組中在無真空破 壞的情況下依序執行整個蓋形成製程及擴散障壁（或蝕刻 終止）沈積製程。具有一個腔室内之多個台或具有多個腔 室之PECVD模組裝置為用於此沈積之合適裝置。值得注意 的疋，含金屬層及介電層兩者均可在一個PEcvd裝置中在 無真空破壞的情況下依序沈積。舉例而言，在一個實施例 中，該製程涉及沈積含金屬源層、將源層之頂部部分轉化 為鈍化層、允許有效成分在金屬互連件内形成保護蓋，以 及形成介電質擴散障壁或蝕刻終止層，其中所有操作均在 一個裝置中在無真空破壞的情況下執行。 使用此等方法形成之器件可具有改進的電遷移性質，且 亦可展現金屬/介電質擴散界面處之較大黏著力。 根據另一態樣，提供一種半導體器件。該半導體器件包 括介電質材料區及内嵌於該介電質材料中之銅或銅合金 區。該器件進一步包括包含ΒΝχ之層，該層安置於介電層 上且安置於銅或銅合金區上。該器件進一步包含銅或銅合 金區内之含硼蓋。 根據另一態樣，提供一種用於在部分製造之半導體器件 之金屬4分上或内形成保護蓋的裝置。該裝置包括：（約處 理腔室’該處理腔室具有用於引入反應物之入口 ；㈨晶圓 153514.doc 11 201138024 支撐件’該晶圓支撐件用於在保護蓋形成期間將晶圓固持 於適當位置；及（C)控制器，該控制器包含用於沈積保護蓋 之程式指令》該等指令包括用於以下操作之指令：⑴在金 屬之暴露部分上沈積包含棚或第二金屬之源層並在晶圓基 板上沈積介電質；（ii)對有效成分層之頂部部分進行改質 以形成鈍化層；及（iii)允許源層中之有效成分擴散至基板 上之金屬中及/或與該金屬反應並形成保護蓋。在一些實 施例中，該裝置為PECVD裝置。可在多台裝置之一個台處 依序執行所敍述之操作。在其他實施例中，可在該裝置之 第一台處執行一些操作，而可在不同台處執行其他操作。 一個台可經組態以用於在第一溫度下執行之製程，而另一 台可經組態以用於在不同溫度下執行之製程。舉例而言， 可在第一溫度下在多台裝置之一個台處執行源層之沈積， 而可在不同台處在不同溫度下執行源層之後續改質。基板 可在無真空破壞的情況下在台之間轉移。在其他實施例 中’可在多腔室裝置中類似地實施該製程，其中基板可在 不將基板暴露於周圍條件的情況下在腔室之間轉移。 在另一態樣中，提供一種在無氧化物銅表面上形成含鋁 保護蓋之方法。該方法之特徵可在於以下操作：（a)使具有 暴露之無氧化物銅或銅合金層及暴露之介電層的基板與包 含IS之化合物接觸，以在介電質及銅或銅合金層兩者上形 成包含鋁之第一層；（b)以化學方法對第一層之至少一部分 進行改質以形成包含銘之純化層；及（c)在鈍化層上沈積介 電層。在某些實施例中，操作（a)、及中之每一者在 153514.doc -12· 201138024 化學氣相沈積（CVD)裝置中執行。此外，在某些實施例 中，在（c)中沈積之介電層為蝕刻終止介電層。該蝕刻終止 介電層可例如為諸如氮化石夕或碳化石夕等經推雜或未經推雜 材料。在另一實施例中，在⑷中沈積之介電層$直接沈積 至鈍化層上之層間介電質（ILD)層。 在某些實施例中’該方法亦包括⑷之前的額外操作。特 定而言，基板表面經清潔以自銅或銅合金之表面完全移除 氧化銅。清潔技術之實例包括（1)直接電漿處理，（2)遠端 電聚處理，（3) UV處理，及⑷在包含n2、nh^H2中之至 少一者的氣體中之熱處理。 在以上描述之實施财，操作⑷可涉及在無電聚的情況 下在至少約35〇°C之基板溫度下（例如，至少約400°C下）使 基板與有機銘化合物接觸。作為一實例，有機鋁化合物為 三甲基鋁。 在某些實施例中，操作⑻涉及在不允許铭大量擴散至 銅層中的情況下實質上完全使駐留於銅或銅合金上之第一 層鈍化。或者，操作涉及在允許鋁部分擴散至銅層中的 情況下部分使駐留於銅或銅合金上之第—層鈍化。 在某些實施例中，在（b)中使該層鈍化包含形成包含ai_ N鍵之實質上固定的化合物。在特定實施例中純化涉及 用3氮》式劑處理基板’且該處理可例如為直接電漿處理、 遠端電聚處理、UV處理或熱處理。在更特定之實施例 中’該處理涉及在無電裂的情況下將基板暴露於含氣試 劑。在例如介電質為ULK介電質的情況下，此後—處理可 153514.doc 201138024 為適當的。 在另外其他實施例中，在（b)中使該層鈍化包含形成包 含A1-0鍵之實質上固定的化合物。此製程可涉及用含氧試 劑處理基板，且該處理可例如為以下中之—者：直接電浆 處理、遠端電漿處理、UV處理或熱處理。在特定實施例 中該處理涉及在無電漿的情況下使基板與含氧試劑接 觸。當例如介電質為ULK介電質時，此處理可為適當的。 含氧試劑之實例包括〇2、N2〇、c〇2及〇3。 本發明之另一態樣係關於用於形成半導體器件結構之裝 置，S亥裝置可包括以下特徵：（勾處理腔室，該處理腔室具 有用於引入氣態或揮發性之含金屬反應物的入口 ；（b)晶圓 支樓件’該晶圓支樓件用於在處理腔室中在晶圓基板上沈 積含金屬層期間將晶圓固持於適當位置；及（c)控制器，該 控制器包含程式指令。該等程式指令可包括用以執行以下 刼作的指令：⑴使具有暴露之無氧化物銅或銅合金層及暴 露之介電層的基板與含鋁反應物接觸，以在介電質及第一 金屬兩者上沈積包含鋁之第一層；及（ii)以化學方法對第 一層之至少一部分進行改質以形成包含鋁之鈍化層。 下文將參看相關聯之圖式更詳細地描述本發明之此等及 其他特徵及優點。 【實施方式】 引言及综述 隨著器件尺寸不斷減小，且互連件所經歷之電流密度不 斷增大，電遷移正成為1C製造中之重大可靠性問題。電遷 153514.doc • 14 · 201138024 為以電流遷移金屬原子且在互連件内形成空 今屬Γ;之形成可隨後導致器件故障。金屬原子之遷移在 :散障壁界面處以及沿著晶粒邊界特別顯著。當 月’ 9g⑽及45 nm技術節點處，需要用於改進電遷移效 能之方法。雖然可藉由將掺雜劑元素引人至互連件中來改 進電遷移一效能’但此類摻雜劑通常具有比互連件金屬(例 如’ cu)高的電阻率，且可顯著增加互連件電阻。因此， 對互連件金屬之^受控的摻雜可能導致具有*可接受高電 阻之互連件。 本文提供—種用於摻雜劑之受控引人之方法。該方法涉 及藉由將受控量之摻雜劑引入至互連件而在金屬互連件内 形成保遵蓋。因此’非常薄的保護蓋可形成於金屬線之上 部部分内，通常處於金屬與介電質擴散障壁（或蝕刻終止） 層之間的界面處。保護蓋較佳（但不—定）包括互連件金屬 與摻雜劑之固溶體、合金，或化合物。舉例而言，銅可用 B、A卜 Hf、Ti、Co、Ta、Mo、RU、Sn 或 Sb來摻雜。此等 摻雜劑亦可彼此組合使用，或與其他元素組合使用。一般 而言，可使用多種摻雜劑。能夠與互連件金屬形成固溶 體、合金及化合物的摻雜劑以及能夠在金屬/擴散障壁界 面處及在互連件内之晶粒邊界處累積的摻雜劑為尤其較佳 的。 雖然本文中所描述之保護蓋以及用於形成此類蓋之方法 對於改進互連件之電遷移效能而言為有利的，但對所描述 之器件以及製程之使用並不限於此特定應用。舉例而古， 153514.doc -15· 201138024 保護蓋可用以改進金屬線與介電質擴散障壁層或蝕刻終止 層之間的黏著，且用以防止互連件金屬在ic器件製造期間 氧化。 +將在銅雙鑲嵌處理之背景下說明在互連件中形成保護 蓋應理_纟文中所揭示之方法可用於其他處理方法中 (包括單鑲嵌處理）’且可應用於除銅之外的多種互連件金 屬。舉例而言’此等方法可應用於含鋁、金及銀之互連 件。 圖1A至圖1D中所呈現的為在雙鑲嵌製造製程之各個階 段處在半導體基板上創造之器件結構的橫截面圖。圖1E中 展不藉由雙鑲嵌製程創造之完成結構的橫截面圖。本申請 案中所使用之「半導體基板」* P艮於1C器件之半導體部 刀，而疋經廣泛定義為含半導體之基板。參看圖丨八，說明 用於雙鑲嵌製造之部分製造之1(]結構1〇〇的實例。如圖Μ 至圖ID中所說明之結構1〇〇為半導體基板之一部分，且在 二實施例中可直接駐留於含有主動器件（例如，電晶體） 之層上。在其他實施例中，其可直接駐留於金屬化層上， 或駐留於併入有導電材料之其他層（例如，含有記憶體電 容器之層）上。 圖1A中所說明之層1〇3為金屬間介電層，該金屬間介電 質可為二氧化矽，但更通常為低!^介電質材料。為了使金 屬間介電質堆疊之介電常數最小化，將具有小於約3 5、 較佳小於約3.0且常低於約2.8之k值的材料用作層間介電 質。此等材料包括（但不限於）熟習此項技術者已知之摻雜 153514.doc 201138024 雜^氧化#氧切含有有機物之低冰料及多孔之經摻 料。可例如藉由咖或藉由旋塗方法來沈 =料。層103可經_有線路徑(溝槽及介層孔)，在 分導電金屬擴散障壁⑼，隨後嵌入銅導 带1為銅或其他行料電材料提供半導體基板 之導電路徑，所以接近金屬線之下伏石夕器件及介電層必須 受：護以免受金屬離子(例如，Cu2+)影響，否則金屬離子 可&擴散或漂移至發或層間介電質中’且導致其性質降 級使用若干類型之金屬擴散障壁以便保護IC器件之介電 層。可將此等類型劃分為含有#分導電金屬之層（諸如， 1〇5)及介電質障壁層（將參看圖⑺對其進行進一步詳細描 述）。用於部分導電擴散障壁1〇5之合適材料包括諸如钽、 氮化鈕、鈦、氮化鈦等材料。通常藉由pvD或ald方法將 此等材料沈積於具有介層孔及溝槽之介電層上。 可藉由多種技術形成鋼導電路線丨〇7，該等技術包括 PVD、電鍍、無電沈積、cVD等。在一些實施中，形成銅 填充物之較佳方法包括藉由PVD沈積銅之薄晶種層，且隨 後藉由電鍵沈積塊體銅。由於在沈積銅時通常會有覆蓋層 (overburden)駐留於場效應區中’所以需要化學機械拋光 (CMP)操作來移除覆蓋層且獲得平坦化結構10〇。 接下來，參看圖1B，在已完成結構100之後，預先清潔 基板100之表面以移除污染物及金屬氧化物。在預先清潔 後，將含有有效成分之摻雜劑源層（含有硼或金屬之產生 摻雜劑之成分）沈積至銅線107上並沈積至介電質103上。 153514.doc •17· 201138024 接下來例如藉由對源層之氮化或氧化而將源層轉化為鈍化 層109。舉例而言，鈍化層可含有BNX、B〇x、Aio、Ti〇 X A 1 V·/ χ 等在；l電質區上將源層完全轉化為非導電鈍化層以防止 鄰近金屬線107之間的短路。源層之直接駐留於銅線1〇7上 之部分僅部分轉化為鈍化層，從而允許未經改質之源層之 刀保持與銅接觸。在允許來自源層之未經鈍化之部分 的摻雜劑擴散至銅中及/或與銅反應後，保護蓋108形成於 金屬線107之頂部部分内。可藉由控制沈積於源層中之材 料的量藉由在源層之部分純化期間控制改質之程度以及 藉由控制在摻雜劑之擴散及/或摻雜劑與銅之反應期間所 使用之條件來控制保護蓋之厚度。保護蓋可包括（例如）銅 與B Al、Ti等之固溶體或合金。在一些實施例中，藉由 控制用於促進摻雜劑自源層進行擴散之溫度及時間來控制 合金或固溶體中之摻雜劑的量。將在以下部分中詳細描述 保護蓋及純化層之組份。 在一些實施例中，鈍化層亦用作擴散障壁層。在其他實 施例中，獨立的擴散障壁（或蝕刻終止）層沈積於鈍化層之 頂部上。通常，此類擴散障壁層包括經摻雜或未經摻雜之 碳化碎或氮化碎。 如圖1B中所描繪，膜1〇9可包括單一鈍化層（例如，ΒΝχ 或入1〇3{層）’或由鄰近於銅線107之鈍化層以及駐留於鈍化 層上之上部介電質擴散障壁層（例如，經摻雜之碳化石夕層） 組成的雙層。將在後續部分中參看圖2Α至圖2C詳細描述 該兩個實施例。膜109將被稱作Cu/介電質界面膜或簡稱為 153514.doc -18- 201138024 界面膜」。 在界面膜包括獨立的介電質擴散障壁層之實施例中，通 常藉由PECVO方法將介電質擴散障壁層沈積於鈍化層之頂 部上。在一個實施例中，在不破壞真空的情況下在一個 PECVD裝置中執行鈍化層之沈積、保護蓋1〇8之形成及介 電質擴散障壁層之沈積》界面膜1〇9亦可在後續鑲嵌處理 期間用作钱刻終止件。 再次參看圖1B，將雙鑲嵌介電質結構之第一介電層111 沈積至膜109上。此後為藉由PECVD方法將蝕刻終止膜113 可選沈積於第一介電層U1上。介電層ln通常由低让介電 質材料（諸如，針對介電層丨〇3而列舉之介電質材料）構成。 應注意，層111及103不一定具有相同的組份。 如圖1C中所描，♦，製程繼續，其中將雙鑲嵌介電質結構 之第二介電層115以類似於第一介電層lu的方式沈積至蝕 刻終止膜113上。隨後為抗反射層（未圖示）及CMP終止膜 117之沈積。第二介電層115通常含有低k介電質材料，諸 如上文針對層1()3及U1而描述之介電質材料。終止膜 117用以在後續之CMp操作期間保護金屬間介電質（細)層 115之脆弱的介電質材料。通常，CMP終止層經受盥擴散 障壁及⑽j終止㈣9及113類似的整合要求，且可包括基 於碳化矽或氮化矽之材料。 土 如圖1D至1E中所描緣，雙鎮丧製程繼續，纟中在第一 及第二介電層中触刻介層孔ιΐ9及溝槽Η卜使用標準微影 技術來#刻®1D中所說明之圖案。可使用熟習此項技術者 153514.doc 19 201138024 眾所周知之溝槽優先或介層孔優先方法。 接下來’如®1E中所料’如上文所描述之此等新形成 之介層孔及溝槽可塗覆有金屬擴散障壁123，金屬擴散障 壁123可含有障壁材料，諸如組、氮化组、氮化欽，或有 效地阻止銅原子擴散至介電層中之其他材料。 在已沈積擴散障壁123之後，施加銅晶種層（通常藉由 PVD製程），以使得能夠隨後用銅嵌入對該等特徵進行電 填充。例如藉由電填充來沈積銅層，且在CMp操作中移除 沈積於場中之多餘金屬，其經執行以使得CMp於CMp終止 膜117處終止。圖1E展示完成之雙鑲嵌製程，其中銅導電 路線124及125嵌入至（未描繪之晶種層）障壁123上之介層孔 及溝槽表面上。圖1E說明三個互連件，其中已用受控之方 式摻雜銅線。 若需要進一步之處理，則在圖2E中所描繪之結構的頂部 上形成類似於膜109之界面膜及類似於蓋log之保護蓋，且 隨後沈積新的金屬化層。 現在將參看圖2A至圖2C詳細說明保護蓋108及界面層 109之結構及組份。 器件結構 參看圖2A，說明部分1(：結構之實例橫截面圖。在此器件 中’形成於層間介電質201中之介層孔及溝槽上襯有擴散 障壁材料203 ’且被填充有銅或銅合金2〇5 ^銅線205之頂 部部分包括薄保護蓋207，薄保護蓋207駐留於銅線205與 鈍化層209之間的界面處。鈍化層209駐留於ILD層201及保 153514.doc -20- 201138024 濩蓋207兩者上，且與該兩個層接觸。介電質擴散障壁或 蝕刻終止層2U駐留於鈍化層211之頂部上。雖然為了保持 清晰性而未對其進行展示，但另一 ILD層駐留於介電質擴 散障壁或蝕刻終止層211之頂部上。鈍化層2〇9及擴散障壁 (或蝕刻終止)層211-起構成界面膜(如參看圖1B由層109所 說明），界面膜駐留於金屬/ILD邊界處。 在一個實施例中，層介電層2〇1具有介於約^刪- 10,000 A之間的厚度。層2〇1可包括多種ILD材料諸如熟 習此項技術者已知之低乂及超低k介電質。舉例而言，可使 用換雜破之氧切，或具有小於約2.以的有機介電質材 料。銅線205可具有介於約.1()，_人之間的厚度銅線 2〇5之較佳不多於約1〇%、更佳不多於約以被保護蓋佔據 (如藉由層厚度量測應理解，在許多實施财，保護蓋 將具有分級之組份，其中摻雜劑之濃度在鈍化層界面處為 最大的。保護蓋之容許厚度將取決於摻雜劑之電阻率… 般而言，根據所描述之方法來形成保護蓋，使得介層孔之 電阻偏移小於約10%、較佳小於約5%，且更佳小於約 3%。電阻偏移被量測為不具有蓋之互連件的電阻對蛵加 蓋之互連件的電阻的差異。在―些實施例中，#由形成厚 度不超過5GG A ’且較佳不超過⑽A之保護蓋來實現容 之電阻偏移。 應理解，不同的摻雜劑可以不同方式在鋼互連件内擴 散’且可在不同程度上影響互連件電阻。因此，上文提供 之數值用作個實例，且並不意欲將結構限於所提及的厚 153514.doc 201138024 度參數。舉例而言，某些摻雜劑可擴散至銅互連件中以在 整個銅線上沈積而不會形成不同的蓋，或在晶粒邊界處累 積及/或在其他界面處累積’例如在具有擴散障壁2〇3之銅 層205之界面處累積。有利的是，所提供之方法允許以受 控之量引入此類摻雜劑，使得互連件電阻得以控制，即使 在此等情況下可能不準確地界定層厚度。 可在保護蓋中使用許多摻雜元素。優先使用與銅形成固 ;谷體、合金或化合物之彼等摻雜劑，且優先使用可在銅晶 粒邊界處累積以及在銅與其他層的界面處累積之摻雜劑。 具有相對低電阻率之材料（諸如金屬）常是較佳的。此外， 不容易在低溫下（例如在低於約100。〇之溫度下）擴散至銅中 之材料亦常為較佳的。合適摻雜劑之實例包括但不限於 B、A卜 Hf、Ti、Co、Ta、Mo、RU、Sn及 Sb。一般而言， 需要選定之摻雜劑具有揮發性前驅體，使得可藉由CVD方 法執行沈積。因此，具有揮發性氫化物、羰基合物、鹵化 物及有機金屬前驅體之金屬摻雜劑通常為較佳的。可在高 達450°C之溫度下及大於約丨托之壓力下以氣相引入之化合 物可為合適的前驅體。 在特定實施例中，保護蓋2〇7包含銅及硼，或銅及鋁， 或銅及鈦。在一些實施例中，摻雜劑彼此組合使用。舉例 而。，保濩蓋207可包括銅、鋁及鈦，或銅與摻雜劑之其 他i D在些實施例中，上文所描述之摻雜劑與用於形 成保護性自對準緩衝（PSAB)層之材料（例如，諸如^心“、 CuGex SlNx及SiCx等材料）組合使用。在名為心等人之發 153514.doc •22· 201138024 明人於2007年3月20曰申請之標題為「用於鑲嵌互連件之 保護性自對準緩衝層（Protective Self-aligned Buffer Layers for Damascene Interconnects)」的共同擁有的美國專利申 請案第11/726,363號中、在名為Chattopadhyay等人之發明 人於2007年2月20日申請之標題為「用於鑲嵌互連件之保 護性自對準緩衝層（Protective Self-aligned Buffer Layers for Damascene Interconnects)」的美國專利申請案第 11/709,293號中，以及在名為van Schravendijk等人之發明 人於2004年11月3日申請之標題為「藉由形成自對準緩衝 層來保護Cu鑲嵌互連件（pr〇tection of Cu Damascene Interconnects by Formation of a Self-aligned Buffer Layer)」的美國專利申請案第10/980,076號中詳細描述了 此類層’所有該等申請案均以全文引用的方式且出於任何 目的而併入本文中。 在一個實施例中，駐留於比〇層201之頂部上以及駐留於 保護蓋207之頂部上的鈍化層209具有介於約50-500 A之間 的厚度。鈍化層通常含有防止鄰近之互連件之間的短路之 非導電材料。鈍化層通常含有經改質之摻雜劑，例如，其 可含有摻雜劑（硼或金屬）之氮化物、氧化物、碳化物、硫 化物、砸化物、磷化物及砷化物。此外，鈍化層可含有碳 氫化合物CxHy °在一個實施例中，鈍化層含有ΒΝχ β bNx 層也可包括氫’且在一些實施例中可包括其他元素。在另 一實例中’鈍化層含有金屬氧化物，諸如ΑΚ)χ、Hf〇x、153514. Doc 201138024 inches continue to shrink and become more and more obvious. Currently, at the 9〇11111 technology node and at more advanced nodes, there is a great need for interconnect fabrication methods that provide interconnects with improved lifetime and reliability. SUMMARY OF THE INVENTION One challenging problem encountered during Ic fabrication is electromigration failure. Electromigration occurs when the high current density experienced by the interconnect causes the metal atoms to migrate with the current and thus cause voids to form within the interconnect. Eventually, the formation of voids can lead to device failure, known as electromigration failure. During the ongoing miniaturization of IC devices, interconnect sizes are reduced and interconnects experience large current densities. Therefore, the possibility of electromigration failure increases as the device is miniaturized. Although copper has greater electromigration resistance than aluminum (even in copper interconnects), electromigration failures are a significant reliability issue at the 45 nm technology node and at more advanced nodes. Provided herein are protective covers that reside at the interface between the metal line and the dielectric diffusion barrier (or etch stop) layer to improve the electromigration performance of the interconnect. Methods of forming such covers are also described. Advantageously, the described protective cover can be formed to reside in a very thin layer in the upper portion of the wire at its interface with the dielectric diffusion barrier layer without significantly increasing the interconnect resistance. The protective cap layer may comprise, for example, a solid solution, alloy or compound of interconnect metal (such as copper) and doped halogen (such as boron, aluminum, titanium, etc.). In many embodiments, it is advantageous to select doping elements that will alloy with the interconnect metal and/or concentrate at the boundaries of the elastomer particles, thereby reducing migration of the interconnect metal atoms. The method provided by depositing dopant material 153514 on the exposed metal line. Doc 201138024 The source layer of material (for example, containing B, Τί Μ + _LL , , ·, material), above the source layer. Sub-conversion into a passivation layer (eg, nitride or oxide) while allowing the dopant to produce an unmodified portion of the source layer that remains in contact with the interconnect metal, :: after allowing unmodified portions from the source layer The dopant diffuses into the interconnect metal and/or reacts with the interconnect metal to achieve a thick acoustic control of the protective cover. In the P embodiment, the amount of dopant introduced to the interconnect t is again limited by the thickness of the unmodified portion of the source layer that resides in contact with the interconnect. In other embodiments, the amount of dopant introduced into the interconnect is controlled by controlling the temperature during diffusion and/or during the reaction. Advantageously, the thin protective cover formed in this controlled manner does not significantly increase the resistance of the interconnect, such as equivalent highly reactive or easily diffusible dopants (eg, 'Si or Ge) deposited onto the interconnect metal. It usually happens unintentionally. As will be described, the method provided is suitable for forming a protective cap layer from a dopant-producing source layer with minimal or zero selectivity J/sum/extension to both exposed metal and dielectric. . It should be understood that such methods can also be used in situations where the source layer containing dopants is only selectively deposited onto the metal layer without significant deposition onto the dielectric. Providing a method of forming a semiconductor device structure according to an aspect β In one embodiment, the method includes the following operations: (a) exposing a first metal layer (eg, 'copper or copper alloy) and exposed dielectric The substrate of the layer is in contact with a compound comprising a shed or a second metal (eg, Al, Hf, Ti, Co, Ta, Mo, Ru, Sn, Sb, etc.) to deposit on both the dielectric and the first metal. a source layer of boron or a second metal; (b) modifying a top portion of the source layer on at least the region of the first metal to form a passivation layer, wherein 153514. Doc 201138024 The part of the modified source layer remains in contact with the first metal layer; and (4) is allowed to come from no. The active component of the star-modified source layer diffuses into and/or reacts with the first metal and forms a protective cap within the first metal layer. In one embodiment, the substrate is a damascene structure comprising exposed copper lines embedded in an interlevel metal dielectric layer. Prior to depositing the source layer, the substrate may be pre-cleaned to remove contaminants (e.g., copper oxide) from the copper surface. For example, pre-cleaning can be performed by exposing the substrate to a reducing gas (e.g., ^ or NH3) in the plasma. The source layer containing the dopant source (active ingredient) can then be deposited by contacting the substrate with a volatile dopant precursor at a temperature. Typically, although not necessarily, the deposition of the source layer is performed thermally without plasma discharge. Pre-cleaning and deposition of the source layer can be performed in a CVD apparatus without vacuum destruction (eg, in the same processing chamber, in one embodiment, by about 2 〇〇 4 在 in the absence of a plasma discharge) The substrate is contacted with a gas mixture containing B2H6 (or other volatile boron-containing precursor) and an inert carrier gas at a chamber temperature between °c to deposit a boron-containing source layer. The pressure in the deposition chamber is maintained at about 0. . Within the range of 5-10 Torr, and the concentration in the gas mixture is in the range of about 0. Between 5 and 2% by volume. Under these conditions, a boron-containing source layer is deposited onto the exposed dielectric layer and on the metal portion of the substrate. The source layer was found to contain a B-H bond and would therefore be referred to as a ruthenium layer. In many embodiments, a greater amount of dopant source material is deposited on the metal portion of the substrate due to the higher precursor decomposition rate at the metal surface than its dielectric portion. Thus, in these embodiments, the thickness of the source layer deposited on the metal portion is greater than the thickness of the source layer deposited on the dielectric 153514. Doc 201138024 degrees. However, for many boron-containing precursors and for metal-containing precursors, the complete deposition selectivity between the metal and the dielectric is often difficult to obtain. Advantageously, the described deposition method does not require absolute metal/dielectric selectivity for deposition of the source layer. In some embodiments, the substrate and the volatile metal-containing precursor (such as metal dentate, metal hydride, metal) are subjected to temperature and pressure suitable for causing decomposition of the precursor and deposition of a metal-containing layer on the substrate. The carbonyl-containing or volatile organometallic compound is contacted to deposit a metal-containing source layer. In many cases, using similar temperature and pressure ranges as listed above for the deposition of bhx layers, those skilled in the art will understand how to optimize deposition conditions for different types of metal precursors. Many metals are suitable as dopants for forming protective caps. Such metals include metals that form solid solutions, alloys or intermetallic phases with interconnect metals, and metals that are capable of diffusing and agglomerating at grain boundaries in the interconnect. For example, A1, Hf, Ti, Co, Ta, Mo, RU, Sn, and Sb can be used as components of the protective cover. Alloys and solid solutions of these metals or other metals may also be used. Suitable volatile precursors for use in the aluminum-containing source layer include, but are not limited to, tridecyl aluminum, hydrogenated bismuth aluminum, triethyl aluminum, triisobutyl, and ginseng (diethylamino). Suitable precursors for the deposition of other metals include, but are not limited to, bis(cyclopentadienyl)cobalt, acetoacetate cobalt (ruthenium), osmium (dimethylamino) ruthenium, osmium (diethylamino)铪, 肆 (dimethylamino) in the eyes, bismuth (dimethylamino) titanium (TDMAT), bismuth (diethylamino) titanium (TDEAT), bismuth (ethyl decylamino) titanium, double (two Ethylamino)bis(diisopropylamino)titanium, penta(dimethylamino)phosphonium, third (butyltriimido)(diethylamino) knob 153514. Doc 201138024 (TBTDET), pentad(diethylamino) group, bis(ethylcyclopentadiene dimethylamino) and tetramethyltin. As mentioned, after depositing the source layer containing the side or metal, the top portion of the knives is modified to form a passivation layer, such as a layer containing nitride or oxide, while the bottom portion remains unmodified and inter A piece of metal is in contact. In many embodiments, the reforming operation completely converts the portion of the source layer residing on the dielectric to contain a low conductivity in the case where the source layer is deposited on the metal to a greater thickness than the dielectric. The passivation layer of the material (for example, BN 〆 叫, etc.). Such modifications are performed to prevent short circuits between adjacent interconnects. In addition, the partial modification of the source layer residing on the metal lines serves to control the amount of dopant residing in the layer' and provides a means of controlling the thickness of the protective cover and thus controlling the interconnectivity of the interconnect. A number of processes can be used to form the purification layer. In one embodiment, the source layer is modified by exposing the substrate to a gas-containing reactant in a plasma discharge. For example, νη3, Ν2Η4, amine, oxime 2, and mixtures thereof can be used. In a specific example, the germanium source layer is modified to form a passivation layer containing germanium by contacting the substrate with a mixture of ν2_η3 in electropolymerization: 2 In other embodiments, the substrate is formed by plasma discharge. The source layer (eg, metal-containing source layer) is modified by exposure to an oxygenate (eg, 02, Ν20, or C〇2) to form a passivation layer containing an oxide (eg, alumina, titania, etc.) . In other embodiments, the source layer is modified with a reactant containing carbon in the plasma to form a purified layer containing carbides or hydrocarbons (e.g., BCX, CxHy). The thickness of the modified layer can be adjusted as needed. By controlling the thickness of the modified layer 153,514. Doc 201138024 degrees' controls the thickness of the remaining unmodified layer containing the dopant source, which also produces control over the thickness of the protective cover within the interconnect. For example, between about 20-60% of the thickness of the source layer residing on the metal line can be modified to form a passivation layer' while leaving the unmodified dopant-containing portion in contact with the metal line. In one example, the source layer residing on the metal line has a thickness of about 5 〇 5 inches. Approximately 20-400 Å of the unmodified source layer remains in contact with the metal line after being converted to a passivation layer between about 20-60% of the thickness of the source layer. Subsequent 'allowing the active component from the unmodified source layer to diffuse into and/or react with the interconnect metal' after forming the reformed layer' and form within the interconnect metal layer protection cap. In some embodiments, the active ingredient is first produced within the source layer prior to forming the protective cover. Depending on the nature of the active ingredient, a variety of conditions can be used to produce the active ingredient and promote its diffusion into the interconnect metal. In some embodiments, exposing the substrate to a high temperature for a predetermined amount of time facilitates forming a protective cover within the metal interconnect. In other embodiments, the formation of the protective cover occurs at room temperature after allowing sufficient time for the dopant to diffuse. In some embodiments, after forming the passivation layer, an etch stop layer or a dielectric diffusion barrier layer (eg, a layer comprising doped or undoped carbonized or lanthanum nitride) is deposited onto the passivation layer. . In other embodiments, the passivation layer itself can act as an etch stop layer or a dielectric diffusion barrier layer and does not require a separate silver gate stop layer. In the latter embodiment, an intermetal dielectric is deposited directly onto the passivation layer. In some embodiments, the deposited dielectric diffusion barrier or the surname termination layer 153514. Dop 201138024 then performs doping of the interconnect metal by allowing the dopant to diffuse into the interconnect metal and/or react with the interconnect metal. For example, the substrate can be heated to at least about 1 oo °C after the etch stop layer (e.g., the tantalum carbide layer) has been deposited to facilitate formation of the protective cover. Advantageously, in some embodiments, the entire lid formation process and diffusion barrier (or etch stop) deposition process are performed sequentially in a module without vacuum damage. A plurality of stages having a chamber or a PECVD module unit having a plurality of chambers is a suitable device for such deposition. It is worth noting that both the metal-containing layer and the dielectric layer can be deposited sequentially in a PEcvd device without vacuum damage. For example, in one embodiment, the process involves depositing a metal-containing source layer, converting a top portion of the source layer into a passivation layer, allowing the active component to form a protective cap within the metal interconnect, and forming a dielectric diffusion barrier. Or an etch stop layer in which all operations are performed in one device without vacuum damage. Devices formed using such methods can have improved electromigration properties and can also exhibit greater adhesion at the metal/dielectric diffusion interface. According to another aspect, a semiconductor device is provided. The semiconductor device includes a dielectric material region and a copper or copper alloy region embedded in the dielectric material. The device further includes a layer comprising germanium disposed on the dielectric layer and disposed on the copper or copper alloy region. The device further comprises a boron containing cap in the copper or copper alloy region. According to another aspect, an apparatus for forming a protective cover on or in a metal portion of a partially fabricated semiconductor device is provided. The apparatus comprises: (about a processing chamber) having a chamber for introducing a reactant; (9) a wafer 153514. Doc 11 201138024 Supports 'The wafer support is used to hold the wafer in place during formation of the protective cover; and (C) a controller containing program instructions for depositing a protective cover" Instructions for: (1) depositing a source layer comprising a shed or a second metal on a exposed portion of the metal and depositing a dielectric on the wafer substrate; (ii) modifying a top portion of the active component layer to form a passivation layer; and (iii) allowing the active component in the source layer to diffuse into and/or react with the metal on the substrate and form a protective cover. In some embodiments, the device is a PECVD device. The operations described can be performed sequentially at one of the multiple units. In other embodiments, some operations may be performed at the first station of the device, while other operations may be performed at different stations. One station can be configured for a process that is executed at a first temperature, and the other can be configured for a process that is performed at a different temperature. For example, deposition of the source layer can be performed at one of the plurality of devices at the first temperature, while subsequent modification of the source layer can be performed at different temperatures at different stations. The substrate can be transferred between the stages without vacuum damage. In other embodiments, the process can be similarly implemented in a multi-chamber device wherein the substrate can be transferred between the chambers without exposing the substrate to ambient conditions. In another aspect, a method of forming an aluminum-containing protective cover on an oxide-free copper surface is provided. The method can be characterized by the following operations: (a) contacting a substrate having an exposed oxide-free copper or copper alloy layer and an exposed dielectric layer with a compound comprising IS for dielectric and copper or copper alloy layers Forming a first layer comprising aluminum on both; (b) chemically modifying at least a portion of the first layer to form a purification layer comprising the inscription; and (c) depositing a dielectric layer on the passivation layer. In some embodiments, operations (a), and each of them are at 153,514. Doc -12· 201138024 Performed in chemical vapor deposition (CVD) equipment. Moreover, in some embodiments, the dielectric layer deposited in (c) is an etch stop dielectric layer. The etch stop dielectric layer can be, for example, a pulverized or undoped material such as a nitride or a carbonized stone. In another embodiment, the dielectric layer $ deposited in (4) is deposited directly onto the interlayer dielectric (ILD) layer on the passivation layer. In some embodiments, the method also includes additional operations prior to (4). Specifically, the surface of the substrate is cleaned to completely remove copper oxide from the surface of the copper or copper alloy. Examples of cleaning techniques include (1) direct plasma treatment, (2) remote electropolymerization, (3) UV treatment, and (4) heat treatment in a gas containing at least one of n2, nh^H2. In the practice described above, operation (4) may involve contacting the substrate with an organic compound at a substrate temperature of at least about 35 °C (e.g., at least about 400 °C) without electropolymerization. As an example, the organoaluminum compound is trimethylaluminum. In some embodiments, operation (8) involves substantially completely passivating the first layer residing on the copper or copper alloy without allowing a large amount of diffusion into the copper layer. Alternatively, the operation involves partially passivating the first layer residing on the copper or copper alloy while allowing the aluminum portion to diffuse into the copper layer. In certain embodiments, passivating the layer in (b) comprises forming a substantially immobilized compound comprising an ai_N bond. Purification in a particular embodiment involves treating the substrate with a 3 Nitrogen formulation and the treatment can be, for example, direct plasma treatment, remote electropolymerization, UV treatment or heat treatment. In a more specific embodiment, the treatment involves exposing the substrate to a gas-containing reagent without electrolysis. In the case where, for example, the dielectric is a ULK dielectric, the subsequent processing can be 153,514. Doc 201138024 is appropriate. In still other embodiments, passivating the layer in (b) comprises forming a substantially immobilized compound comprising an A1-0 bond. This process may involve treating the substrate with an oxygen-containing reagent, and the treatment may be, for example, the following: direct plasma treatment, remote plasma treatment, UV treatment, or heat treatment. In a particular embodiment the process involves contacting the substrate with an oxygen-containing reagent without plasma. This treatment may be suitable when, for example, the dielectric is a ULK dielectric. Examples of the oxygen-containing reagent include hydrazine 2, N2 hydrazine, c 〇 2, and hydrazine 3. Another aspect of the invention is directed to a device for forming a structure of a semiconductor device. The device can include the following features: (a check processing chamber having a metal-containing reactant for introducing a gaseous or volatile gas (b) a wafer fulcment member for holding the wafer in place during deposition of a metal-containing layer on the wafer substrate in the processing chamber; and (c) a controller, The controller includes program instructions. The program instructions can include instructions to: (1) contact a substrate having an exposed oxide-free copper or copper alloy layer and an exposed dielectric layer with an aluminum-containing reactant to Depositing a first layer comprising aluminum on both the dielectric and the first metal; and (ii) chemically modifying at least a portion of the first layer to form a passivation layer comprising aluminum. The drawings describe these and other features and advantages of the present invention in more detail. [Invention] Introduction and Overview As device dimensions continue to decrease and the current density experienced by interconnects continues to increase, electromigration is becoming 1C. Major reliability problems in making the electric move 153,514. Doc • 14 · 201138024 The formation of a metal atom by current and the formation of a void in the interconnect; the formation can subsequently lead to device failure. The migration of metal atoms is particularly pronounced at the interface of the barrier and along the boundaries of the grains. At the '9g(10) and 45 nm technology nodes of the month, methods for improving electromigration efficiency are needed. Although electromigration-efficiency can be improved by introducing dopant elements into the interconnects, such dopants typically have a higher resistivity than the interconnect metal (eg, 'cu) and can be significantly increased Interconnect resistance. Therefore, controlled doping of the interconnect metal may result in an interconnect having an acceptable high resistance. This document provides a controlled method for the introduction of dopants. The method involves forming a conformal cover within the metal interconnect by introducing a controlled amount of dopant to the interconnect. Thus a very thin protective cover can be formed in the upper portion of the metal line, typically at the interface between the metal and the dielectric diffusion barrier (or etch stop) layer. The protective cover preferably (but not necessarily) comprises a solid solution, alloy, or compound of interconnect metal and dopant. For example, copper may be doped with B, A, Hf, Ti, Co, Ta, Mo, RU, Sn or Sb. These dopants can also be used in combination with each other or in combination with other elements. In general, a variety of dopants can be used. Dopants capable of forming solid solutions, alloys and compounds with interconnect metals and dopants that can accumulate at the metal/diffusion barrier interface and at the grain boundaries within the interconnect are particularly preferred. While the protective covers described herein and the methods for forming such covers are advantageous for improving the electromigration performance of the interconnects, the use of the described devices and processes is not limited to this particular application. For example, ancient, 153,514. Doc -15· 201138024 Protective covers can be used to improve adhesion between the metal lines and the dielectric diffusion barrier layer or etch stop layer and to prevent oxidation of the interconnect metal during ic device fabrication. + will be described in the context of copper dual damascene processing to form a protective cover in the interconnect. The method disclosed in the text can be used in other processing methods (including single damascene processing) and can be applied to other than copper. A variety of interconnect metal. For example, these methods can be applied to interconnects containing aluminum, gold, and silver. Presented in Figures 1A through 1D are cross-sectional views of device structures created on a semiconductor substrate at various stages of a dual damascene fabrication process. A cross-sectional view of the completed structure created by the dual damascene process is shown in Figure 1E. The "semiconductor substrate" used in the present application is a semiconductor wafer of a 1C device, and is generally defined as a semiconductor-containing substrate. Referring to Figure VIII, an example of a 1(] structure 1 用于 for partial fabrication of dual damascene fabrication is illustrated. The structure 1 Μ illustrated in Figure 至 to Figure ID is part of a semiconductor substrate, and in the second embodiment The layer may reside directly on a layer containing an active device (eg, a transistor). In other embodiments, it may reside directly on the metallization layer or reside in other layers incorporating the conductive material (eg, containing memory) The layer 1 〇 3 illustrated in FIG. 1A is an inter-metal dielectric layer, and the inter-metal dielectric may be cerium oxide, but is more usually a low dielectric material. The dielectric constant of the intermetal dielectric stack is minimized and will have a thickness of less than about 35, preferably less than about 3. 0 and often less than about 2. A material having a k value of 8 is used as the interlayer dielectric. Such materials include, but are not limited to, those known to those skilled in the art to be doped 153,514. Doc 201138024 Miscellaneous ^ Oxidation # Oxygen cut low-alcohol containing organic matter and porous admixture. The material can be dried, for example, by coffee or by spin coating. The layer 103 can provide a conductive path of the semiconductor substrate via the _-wired path (trench and via hole) in the conductive metal diffusion barrier (9), and then the embedded copper conduction band 1 is copper or other conductive material, so that the metal line is close to the metal line. The underlying device and the dielectric layer must be protected from metal ions (eg, Cu2+), otherwise the metal ions can & diffuse or drift into the inter-layer dielectric and cause degradation of their properties using several types. A metal diffusion barrier protects the dielectric layer of the IC device. These types can be divided into layers containing # 分 conductive metals (such as 1 〇 5) and dielectric barrier layers (which will be described in further detail with reference to Figure (7)). Suitable materials for the partially conductive diffusion barrier 1〇5 include materials such as tantalum, nitride buttons, titanium, titanium nitride, and the like. These materials are typically deposited on a dielectric layer having vias and trenches by a pvD or ald method. The steel conductive path 丨〇7 can be formed by a variety of techniques including PVD, electroplating, electroless deposition, cVD, and the like. In some implementations, a preferred method of forming a copper fill comprises depositing a thin seed layer of copper by PVD and subsequently depositing bulk copper by electrical bonds. Since an overburden typically resides in the field effect region when depositing copper, a chemical mechanical polishing (CMP) operation is required to remove the cap layer and obtain a planarization structure 10〇. Next, referring to Fig. 1B, after the structure 100 has been completed, the surface of the substrate 100 is preliminarily cleaned to remove contaminants and metal oxides. After the pre-cleaning, a dopant source layer (a component containing boron or a metal-producing dopant) containing an active ingredient is deposited on the copper wire 107 and deposited on the dielectric material 103. 153514. Doc • 17· 201138024 Next, the source layer is converted into a passivation layer 109, for example by nitriding or oxidizing the source layer. For example, the passivation layer may contain BNX, B〇x, Aio, Ti〇XA 1 V·/χ, etc., and the source layer is completely converted into a non-conductive passivation layer to prevent the adjacent metal lines 107 from being interposed between the adjacent metal lines 107. Short circuit. The portion of the source layer directly residing on the copper wire 1〇7 is only partially converted into a passivation layer, thereby allowing the unmodified source layer blade to remain in contact with the copper. A protective cover 108 is formed in the top portion of the metal line 107 after allowing the dopant from the unpassivated portion of the source layer to diffuse into the copper and/or react with the copper. The amount of material deposited in the source layer can be controlled by controlling the extent of the modification during partial purification of the source layer and by controlling diffusion during dopant and/or reaction of dopant with copper. The conditions to control the thickness of the protective cover. The protective cover may include, for example, a solid solution or alloy of copper and B Al, Ti, or the like. In some embodiments, the amount of dopant in the alloy or solid solution is controlled by controlling the temperature and time used to promote diffusion of the dopant from the source layer. The components of the protective cap and the purification layer will be described in detail in the following sections. In some embodiments, the passivation layer also functions as a diffusion barrier layer. In other embodiments, a separate diffusion barrier (or etch stop) layer is deposited on top of the passivation layer. Typically, such diffusion barrier layers include carbonized or nitrided or doped or undoped. As depicted in FIG. 1B, the film 1〇9 may comprise a single passivation layer (eg, ΒΝχ or 1〇3{layer)' or a passivation layer adjacent to the copper line 107 and an upper dielectric residing on the passivation layer. A double layer composed of a diffusion barrier layer (for example, a doped carbonized stone layer). The two embodiments will be described in detail in the subsequent sections with reference to Figs. 2A to 2C. The film 109 will be referred to as a Cu/dielectric interface film or simply as 153514. Doc -18- 201138024 Interface film". In embodiments where the interface film comprises a separate dielectric diffusion barrier layer, a dielectric diffusion barrier layer is typically deposited on the top of the passivation layer by the PECVO method. In one embodiment, the deposition of the passivation layer, the formation of the protective cap 1 8 and the deposition of the dielectric diffusion barrier layer are performed in a PECVD apparatus without breaking the vacuum. Used as a money inscription during the mosaic process. Referring again to FIG. 1B, a first dielectric layer 111 of dual damascene dielectric structure is deposited onto film 109. Thereafter, the etch stop film 113 is optionally deposited on the first dielectric layer U1 by a PECVD method. Dielectric layer ln is typically constructed of a low dielectric material such as the dielectric material listed for dielectric layer 丨〇3. It should be noted that layers 111 and 103 do not necessarily have the same composition. As depicted in Figure 1C, the process continues with a second dielectric layer 115 of dual damascene dielectric structure deposited onto the etch stop film 113 in a manner similar to the first dielectric layer lu. This is followed by deposition of an anti-reflective layer (not shown) and a CMP stop film 117. The second dielectric layer 115 typically contains a low-k dielectric material, such as the dielectric materials described above for layers 1 () 3 and U1. The termination film 117 serves to protect the fragile dielectric material of the intermetal dielectric (fine) layer 115 during subsequent CMp operations. Typically, the CMP termination layer is subjected to similar diffusion requirements for the germanium diffusion barrier and (10)j termination (4) 9 and 113, and may include materials based on tantalum carbide or tantalum nitride. As shown in Figures 1D to 1E, the two-town mourning process continues. In the first and second dielectric layers, the etched interlayer holes ιΐ9 and the trenches are etched using standard lithography techniques. The pattern described in the article. Can use the familiar technology 153514. Doc 19 201138024 The well-known groove-first or via-first method. The newly formed via holes and trenches, as described above, as described in the <1>1E, may be coated with a metal diffusion barrier 123, which may contain barrier material such as groups, nitride groups Nitriding, or other materials that effectively prevent copper atoms from diffusing into the dielectric layer. After the diffusion barrier 123 has been deposited, a copper seed layer (usually by a PVD process) is applied to enable subsequent electrical filling of the features with copper embedding. The copper layer is deposited, for example, by electrical filling, and the excess metal deposited in the field is removed during CMp operation, which is performed such that CMp terminates at the CMp termination film 117. Figure 1E shows a completed dual damascene process in which copper conductive traces 124 and 125 are embedded on the via holes and trench surfaces on the barrier layer 123 (not depicted). Figure 1E illustrates three interconnects in which copper wires have been doped in a controlled manner. If further processing is required, an interface film similar to film 109 and a protective cover similar to the cover log are formed on top of the structure depicted in Figure 2E, and a new metallization layer is subsequently deposited. The structure and components of the protective cover 108 and the interface layer 109 will now be described in detail with reference to Figs. 2A through 2C. Device Structure Referring to FIG. 2A, a cross-sectional view of a portion 1 (the structure is illustrated. In this device, the via holes and trenches formed in the interlayer dielectric 201 are lined with a diffusion barrier material 203' and are filled with The top portion of the copper or copper alloy 2〇5^ copper wire 205 includes a thin protective cover 207 that resides at the interface between the copper wire 205 and the passivation layer 209. The passivation layer 209 resides in the ILD layer 201 and protects 153514 . Doc -20- 201138024 Both cover 207 are in contact with the two layers. A dielectric diffusion barrier or etch stop layer 2U resides on top of the passivation layer 211. While not shown for clarity, another ILD layer resides on top of the dielectric diffusion barrier or etch stop layer 211. The passivation layer 2〇9 and the diffusion barrier (or etch stop) layer 211 form an interface film (as illustrated by layer 109 in Fig. 1B), and the interface film resides at the metal/ILD boundary. In one embodiment, the layer dielectric layer 2〇1 has a thickness between about 10,000 Å and 10,000 Å. Layer 2 can include a variety of ILD materials such as low and ultra low k dielectrics known to those skilled in the art. For example, it is possible to use a modified oxygen cut, or have a diameter of less than about 2. Organic dielectric materials. Copper wire 205 can have a distance of about. 1 (), _ between the thickness of the copper wire 2 〇 5 is preferably no more than about 1%, more preferably no more than about to be occupied by the protective cover (as understood by layer thickness measurement, in many In practice, the protective cover will have a graded component in which the concentration of the dopant is greatest at the interface of the passivation layer. The allowable thickness of the protective cover will depend on the resistivity of the dopant... generally, as described The method is to form a protective cover such that the resistance of the via hole is offset by less than about 10%, preferably less than about 5%, and more preferably less than about 3%. The resistance offset is measured as the resistance of the interconnect without the cover. The difference in resistance of the capped interconnect. In some embodiments, # is formed by a protective cap that does not exceed 5GG A 'and preferably does not exceed (10) A. It should be understood that the difference is different. The dopants can diffuse in the steel interconnect in different ways' and can affect the interconnect resistance to varying degrees. Therefore, the values provided above are used as examples and are not intended to limit the structure to the mentioned Thick 153,514. Doc 201138024 degree parameter. For example, certain dopants may diffuse into the copper interconnect to deposit over the entire copper line without forming a different cap, or accumulating at grain boundaries and/or accumulating at other interfaces 'eg, The interface of the copper layer 205 of the diffusion barrier 2〇3 is accumulated. Advantageously, the method provided allows for the introduction of such dopants in a controlled amount such that the interconnect resistance is controlled, even though the layer thickness may not be accurately defined in such cases. Many doping elements can be used in the protective cover. It is preferred to use a dopant with copper to form solids, grains, alloys or compounds, and to preferentially use dopants which can accumulate at the copper grain boundaries and accumulate at the interface of copper with other layers. Materials having a relatively low electrical resistivity, such as metals, are often preferred. In addition, materials that do not readily diffuse into the copper at low temperatures (e.g., at temperatures below about 100 Torr) are often preferred. Examples of suitable dopants include, but are not limited to, B, A, Hf, Ti, Co, Ta, Mo, RU, Sn, and Sb. In general, the selected dopant is required to have a volatile precursor such that deposition can be performed by a CVD method. Therefore, metal dopants having volatile hydrides, carbonyl compounds, halogenated compounds, and organometallic precursors are generally preferred. The compound which can be introduced in the gas phase at a temperature of up to 450 ° C and a pressure greater than about 丨 can be a suitable precursor. In a particular embodiment, the protective cover 2〇7 comprises copper and boron, or copper and aluminum, or copper and titanium. In some embodiments, the dopants are used in combination with one another. For example. The cap 207 may comprise copper, aluminum, and titanium, or other od of copper and dopants. In some embodiments, the dopants described above are used to form a protective self-aligned buffer (PSAB). The material of the layer (for example, materials such as "heart", CuGex SlNx and SiCx) is used in combination. It is called 153514. Doc •22· 201138024 The co-owned US titled “Protective Self-aligned Buffer Layers for Damascene Interconnects”, filed March 20, 2007 Patent Application Serial No. 11/726,363, entitled "Protective Self-aligned Buffer for Mosaic Interconnects", filed on February 20, 2007, by the inventor of Chattopadhyay et al. U.S. Patent Application Serial No. 11/709,293, the entire disclosure of which is incorporated herein by reference in its entirety in its entire entire entire entire entire entire entire entire entire entire entire disclosure Such a layer is described in detail in U.S. Patent Application Serial No. 10/980,076, the entire disclosure of which is incorporated herein by reference. It is incorporated herein by reference in its entirety for all purposes. In one embodiment, the passivation layer 209, which resides on top of the germanium layer 201 and resides on top of the protective cap 207, has a thickness of between about 50 and 500 Å. The passivation layer typically contains a non-conductive material that prevents shorting between adjacent interconnects. The passivation layer typically contains a modified dopant, for example, which may contain nitrides, oxides, carbides, sulfides, tellurides, phosphides, and arsenides of dopants (boron or metal). Further, the passivation layer may contain a hydrocarbon CxHy °. In one embodiment, the passivation layer contains a ΒΝχ β bNx layer and may also include hydrogen 'and may include other elements in some embodiments. In another example, the passivation layer contains a metal oxide such as ruthenium, Hf〇x,

TiOx、CoOx、TaOx、Mo〇x、ru〇x、SnOjSbOx。 153514.doc •23· 201138024 如圖2A中所示’介電質擴散障壁或蝕刻終止層211駐留 於鈍化層之頂部上。在一個實施例中，層21丨具有介於約 50-500 A之間的厚度。習知地，曾將氮化矽及摻雜氮之碳 化矽（NDC)用於此應用。當前，具有比氮化矽低之介電常 數之材料常用作介電質擴散障壁。此等材料包括：富碳碳 化石夕材料’諸如Yu等人在2004年6月15日申請之共同讓渡 的美國專利申請案第10/869,474號中描述之富碳碳化矽材 料；Yu等人在2004年8月9曰申請之美國專利申請案第 10/91 5,11 7號以及Yu等人在2006年3月8日申請之美國專利 申請案第11/373,847號中所描述的摻雜硼之碳化石夕材料； 以及摻雜氧之碳化矽材料’例如Tang等人在2005年2月1 5 日發佈之美國專利第6,8 55，645號中描述的摻雜氧之碳化石夕 材料。在此段落中所提及的所有專利申請案均在此出於所 有目的並以全文引用的方式併入。在一些實施例中，層 211可含有若干子層，例如含有經摻雜及/或未經摻雜之碳 化石夕之子層，該等子層具有針對改進之擴散障壁及蝕刻終 止性質而調整之不同組份。舉例而言，障壁可包括未經摻 雜之碳化物的子層、摻雜氮之碳化物的子層及摻雜氧之碳 化物的子層的任何組合。該障壁可含有兩個子層、三個子 層或更多子層。在2004年6月15曰申請之美國專利申請案 第10/869,474號（2007年10月16日發佈之新專利第7,282,438 號）中呈現組合障壁層之實例，該申請案以全文引用的方 式併入本文中。一般而言，介電質擴散障壁層可包括經摻 雜或未經摻雜之碳化矽、氮化矽或碳氮化矽。 153514.doc •24· 201138024 在圖2A所說明之實施例中，層2〇9及211一起形成駐留於 兩個ILD層（頂部ild層未圖示）之間的界面層。 在某些實施例中，鈍化層209可用作擴散障壁或蝕刻終 止層，而不需要獨立的碳化矽或氮化矽層211。在圖⑼所 說明之此實施例中，駐留於兩個ILD層之間的界面層僅由 鈍化層209組成。舉例而言，某些金屬氧化物及金屬氮化 物可用作钱刻終止或擴散障壁層。 圖2C說明一實施例，其中摻雜劑或產生摻雜劑之化合物 的層208駐留於保護蓋207與鈍化層209之間，且與該兩個 層接觸。層208在銅線205上對準，且不在介電層2〇1上延 伸。層208可包括純摻雜劑或產生摻雜劑之化合物。舉例 而言’層208可包括ΒΗχ、A卜Ti、Ta、Hf、汕等。此層中 之金屬可為游離的或可與其他元素（諸如，H、c、N等）结 合。在一些實施例中，銅可向上擴散至層2〇8，從而與層 208中之摻雜劑形成合金、混合物或固溶體。在此等實施 例中，207/208雙層將用作保護蓋。一般而言，如本文中 所描述之保護蓋可在與周圍介電質2〇1相同之水平處完全 駐留於銅線内，或可包括駐留於周圍介電質2〇1之水平上 方的部分。 在一個特定實例中，器件具有如圖2Α中所示之結構，該 結構具有摻雜硼之保護蓋207及含有ΒΝΧ之鈍化層209 ^銅 線205駐留於具有約3,500 Α之厚度的ULK介電層（約2.5之 k)中。保護蓋207包括銅及硼，且具有約1〇〇 a之厚度。保 護蓋在其與鈍化層界接處駐留於銅線之頂部處。鈍化層具 153514.doc •25· 201138024 有約150 A之厚度，且包括3队。鈍化層亦可包括氫，且將 在實驗部分中被稱作⑺^^^層.擴散障壁層211可包括摻 雜氮之碳化矽、摻雜氧之碳化矽或未經摻雜之碳化矽。層 211具有100 Α至500 Α之厚度。 在另特疋貫例中’器件具有如圖2A中所示之結構，該 結構具有鈦保護蓋207及含有丁丨队之鈍化層2〇9。銅線2〇5 駐留於具有約3,500 A之厚度的ULK介電層（約2.5的k)中。 保》蔓蓋2 07包括銅及鈦，且具有約1〇〇 α之厚度。保護蓋在 其與鈍化層界接處駐留於鋼線之頂部處。鈍化層具有約 150 A之厚度，且包括。鈍化層亦可包括氫。擴散障 J層211可包括摻雜氮之碳化石夕、掺雜氧之碳化石夕或未經 摻雜之碳化矽。層211具有1〇〇人至5〇〇 A之厚度。 在另一特定實例中，器件具有如圖2八中所示之結構，該 結構具有摻雜鋁之保護蓋2〇7。銅線2〇5駐留於具有約 3,500 A之厚度的ULK介電層（約2.5的k)中。保護蓋207包 括鋼及鋁，且具有約1〇〇 A之厚度。保護蓋在其與鈍化層 界接處駐留於銅線之頂部處。鈍化層具有小於約1〇()人之 厚度，且基本上由Α1〇χ組成。擴散障壁層211具有約ι〇〇 A 至500 A之厚度，駐留成與Α1〇χ接觸，且可包括摻雜氮之 碳化矽、摻雜氧之碳化矽或未經摻雜之碳化矽。 用於形成保護罩蓋層之方法 藉由圖3Α中所示之製程流程圖來說明用於形成保護罩蓋 層之例示性方法。在圖4Α至圖4Ε中展示此製程之各個階 •^又處所獲4之器件結構的橫截面圖。雖然可在許多類型之 1535I4.doc -26- 201138024 裝置中實踐本文令所描述之方法，但在一些實施例中，電 漿增強型化學氣相沈積（PECVD)裝置為較佳的。在一些實 例中PECVD裝置能夠提供高頻（HF)及低頻（lf)電浆產 生源。 參看圖3A，製程藉由提供在介電質中具有銅線圖案之部 刀製造之半導體器件（如操作3〇1中所示）而開始。舉例而 s，可使用諸如圖4A中所示之器件的器件。該器件具有嵌 ^介電層401中之銅或銅合金層4〇5。薄的擴散障壁材料層 (含有例如Ta、TaNx、TiNx、RU、W)駐留於銅與介電質之 間的界面處》銅層及介電層暴露於基板表面處。 在操作303令視情況預先清潔基板，以自其表面移除污 染物。舉例而言，可藉由將基板暴露於電漿中之還原氣體 (例如’選自由處於電漿放電之H2、n2、NH3及其混合物組 成之群組的氣體）來預先清潔基板，以便自銅表面移除氧 化銅。在一些實施例中，以&電漿進行預先清潔已為器件 提供特定改進之特性。預先清潔期間之處理氣體亦可包括 載氣，諸如N2、He、Ar等。在一個實例中，在約2〇〇_ 400 C之溫度、約1.5-4托之壓力以及約4,〇〇〇-i〇,000 sccm 之Η2流動速率下在PECVD腔室中執行預先清潔。可含有 HF及LF成分之電漿經點燃且維持於每個3 00 mm晶圓200-1000 W之總功率下。在一些實施例中，較佳在預先清潔操 作期間使用處於0.1-1.5 W/cm2下之HF功率及處於0-0.8 W/cm2下之LF功率。在另一實例中，用nh3替代H2作為還 原氣體，且在約6,000至8，000 seem之範圍中的流動速率下 153514.doc -27· 201138024 流動至處理腔室中。n2載氣在約2,〇〇(M，_ sccm之流動 速率下流動至腔室中。預先清潔處理可持續若干秒，例如 介於約6-20秒之間。 在一些實施例中，較佳使用比直接電漿暴露更溫和的方 法來執行預先清潔。當銅線丧入可容易被直接電毁暴露損 壞之脆弱的ULK介電質中時，此等較溫和的方法尤其有 利。 在一些實施例中，藉由使用遠端電漿來執行對氧化銅之 完全或部分移除，該遠端電漿包含選自由h2、n2、NH3及 其混合物組成之群組的氣體。在此實施中，使用此等氣體 中之一者或一者以上（例如，H2與N2之混合物或WHS與乂之 混合物）以在實體上與固持晶圓基板之腔室分離的腔室中 形成電漿。接著將所形成電漿引導穿過遞送管線，到達離 子過濾器，離子過濾器耗盡離子之電漿，同時留下自由 基°將所得之富含自由基之處理氣體遞送穿過入口（例 如’鎮射頭），到達容納基板之腔室。富含自由基之處理 氣體（在一些實施例中’該氣體含有極少的離子物質或實 質上不含有離子物質）接觸基板表面，且根據需要部分地 或完全地移除氧化銅。因為直接電漿中所含有之高能離子 已牽涉到介電質損壞，所以使用缺乏離子之遠端電漿提供 進行預先清潔之溫和且有效的方式。在San Jose,TiOx, CoOx, TaOx, Mo〇x, ru〇x, SnOjSbOx. 153514.doc •23· 201138024 The dielectric diffusion barrier or etch stop layer 211 resides on top of the passivation layer as shown in FIG. 2A. In one embodiment, layer 21 has a thickness of between about 50 and 500 Å. Conventionally, tantalum nitride and nitrogen-doped niobium carbide (NDC) have been used for this application. Currently, materials having a lower dielectric constant than tantalum nitride are often used as dielectric diffusion barriers. The carbon-rich carbonized bismuth material described in U.S. Patent Application Serial No. 10/869,474, the entire disclosure of which is incorporated by reference in its entirety in Doping as described in U.S. Patent Application Serial No. 10/91, No. 11/A, filed on Jan. Boron-carbonized carbide material; and oxygen-doped carbonized ruthenium material, such as the carbon doped carbon fossil described in U.S. Patent No. 6,8,55,645, issued February 25, 2005. material. All patent applications referred to in this paragraph are hereby incorporated by reference in their entirety for all purposes. In some embodiments, layer 211 may contain several sub-layers, such as containing doped and/or undoped carbonized fossil layers, which are tailored for improved diffusion barrier and etch stop properties. Different components. For example, the barrier may comprise any combination of a sub-layer of undoped carbide, a sub-layer of nitrogen-doped carbide, and a sub-layer of oxygen-doped carbide. The barrier may contain two sub-layers, three sub-layers or more sub-layers. An example of a combined barrier layer is presented in U.S. Patent Application Serial No. 10/869,474, filed on Jun. Into this article. In general, the dielectric diffusion barrier layer may comprise doped or undoped tantalum carbide, tantalum nitride or tantalum carbonitride. 153514.doc •24· 201138024 In the embodiment illustrated in Figure 2A, layers 2〇9 and 211 together form an interfacial layer that resides between two ILD layers (top ild layers not shown). In some embodiments, passivation layer 209 can be used as a diffusion barrier or etch stop layer without the need for a separate tantalum carbide or tantalum nitride layer 211. In this embodiment illustrated in Figure (9), the interfacial layer residing between the two ILD layers consists only of the passivation layer 209. For example, certain metal oxides and metal nitrides can be used as a stop or diffusion barrier layer. Figure 2C illustrates an embodiment in which a layer of dopant or dopant-producing compound resides between and is in contact with the protective cap 207 and the passivation layer 209. Layer 208 is aligned on copper line 205 and does not extend over dielectric layer 2〇1. Layer 208 can include a pure dopant or a dopant-generating compound. For example, layer 208 can include germanium, A, Ti, Ta, Hf, germanium, and the like. The metal in this layer can be free or can be combined with other elements such as H, c, N, and the like. In some embodiments, copper may diffuse up to layer 2〇8 to form an alloy, mixture or solid solution with the dopant in layer 208. In these embodiments, the 207/208 double layer will be used as a protective cover. In general, the protective cover as described herein may reside entirely within the copper wire at the same level as the surrounding dielectric 2〇1, or may include a portion that resides above the level of the surrounding dielectric 2〇1. . In one particular example, the device has a structure as shown in FIG. 2A having a boron-doped protective cap 207 and a passivation layer 209 containing germanium. The copper wire 205 resides in a ULK dielectric having a thickness of about 3,500 Å. Layer (about 2.5 k). The protective cover 207 includes copper and boron and has a thickness of about 1 〇〇 a. The protective cover resides at the top of the copper wire at its interface with the passivation layer. Passivation layer 153514.doc •25· 201138024 has a thickness of about 150 A and includes 3 teams. The passivation layer may also include hydrogen and will be referred to as a (7) layer in the experimental section. The diffusion barrier layer 211 may include niobium-doped niobium carbide, oxygen-doped niobium carbide or undoped niobium carbide. Layer 211 has a thickness of from 100 500 to 500 。. In another embodiment, the device has a structure as shown in Fig. 2A having a titanium protective cover 207 and a passivation layer 2〇9 containing a butadiene team. The copper wire 2〇5 resides in a ULK dielectric layer (about k of about 2.5) having a thickness of about 3,500 Å. The vine cover 2 07 includes copper and titanium and has a thickness of about 1 〇〇 α. The protective cover resides at the top of the steel wire at its interface with the passivation layer. The passivation layer has a thickness of about 150 A and is included. The passivation layer may also include hydrogen. The diffusion barrier J layer 211 may include nitrogen-doped carbonized fossils, oxygen-doped carbonized fossils, or undoped niobium carbide. Layer 211 has a thickness of from 1 to 5 Å. In another specific example, the device has a structure as shown in Fig. 2, which has an aluminum-doped protective cover 2〇7. The copper wire 2〇5 resides in a ULK dielectric layer (about k of about 2.5) having a thickness of about 3,500 Å. The protective cover 207 includes steel and aluminum and has a thickness of about 1 〇〇A. The protective cover resides at the top of the copper wire at its interface with the passivation layer. The passivation layer has a thickness of less than about 1 Å () and consists essentially of Α1 。. The diffusion barrier layer 211 has a thickness of about ι 〇〇 A to 500 Å, resides in contact with Α 1 ,, and may include niobium-doped niobium carbide, oxygen-doped niobium carbide or undoped niobium carbide. Method for Forming a Protective Cover Layer An exemplary method for forming a protective cover layer is illustrated by the process flow diagram shown in Figure 3A. A cross-sectional view of the device structure obtained at each stage of the process is shown in FIGS. 4A to 4B. While the methods described herein can be practiced in many types of 1535I4.doc -26-201138024 devices, in some embodiments, plasma enhanced chemical vapor deposition (PECVD) devices are preferred. In some embodiments, PECVD devices are capable of providing high frequency (HF) and low frequency (lf) plasma generation sources. Referring to Figure 3A, the process begins by providing a semiconductor device fabricated as a blade having a copper pattern in a dielectric (as shown in Operation 3.1). For example, a device such as the one shown in Figure 4A can be used. The device has a copper or copper alloy layer 4〇5 embedded in a dielectric layer 401. A thin diffusion barrier material layer (containing, for example, Ta, TaNx, TiNx, RU, W) resides at the interface between the copper and the dielectric. The copper layer and the dielectric layer are exposed at the surface of the substrate. At operation 303, the substrate is pre-cleaned as appropriate to remove contaminants from its surface. For example, the substrate can be pre-cleaned by exposing the substrate to a reducing gas in the plasma (eg, selected from the group consisting of H2, n2, NH3, and mixtures thereof in the plasma discharge) to facilitate self-copper The surface is removed from copper oxide. In some embodiments, pre-cleaning with & plasma has provided the device with specific improved characteristics. The process gas during the pre-cleaning may also include a carrier gas such as N2, He, Ar, and the like. In one example, pre-cleaning is performed in a PECVD chamber at a temperature of about 2 〇〇 _ 400 C, a pressure of about 1.5-4 Torr, and a flow rate of about 4, 〇〇〇-i 〇 10,000 sccm. The plasma, which may contain HF and LF components, is ignited and maintained at a total power of 200-1000 W per 300 mm wafer. In some embodiments, HF power at 0.1-1.5 W/cm2 and LF power at 0-0.8 W/cm2 are preferably used during pre-cleaning operations. In another example, nh3 is used in place of H2 as the reducing gas and flows into the processing chamber at a flow rate in the range of about 6,000 to 8,000 seem 153514.doc -27·201138024. The n2 carrier gas flows into the chamber at a flow rate of about 2, 〇〇 (M, _ sccm. The pre-cleaning process can last for a few seconds, such as between about 6-20 seconds. In some embodiments, It is better to use a milder method than direct plasma exposure to perform pre-cleaning. These milder methods are especially advantageous when the copper wire is immersed in a fragile ULK dielectric that can be easily damaged by direct electrical damage. In an embodiment, the complete or partial removal of copper oxide is performed by using a remote plasma comprising a gas selected from the group consisting of h2, n2, NH3, and mixtures thereof. Using one or more of these gases (eg, a mixture of H2 and N2 or a mixture of WHS and ruthenium) to form a plasma physically formed in a chamber separate from the chamber holding the wafer substrate. The formed plasma is directed through a delivery line to an ion filter that depletes the plasma of ions while leaving free radicals to deliver the resulting free radical-rich process gas through the inlet (eg 'town Shot), arrive at the base The chamber. The free radical-rich process gas (in some embodiments, the gas contains little or no ionic species) contacts the surface of the substrate and partially or completely removes the copper oxide as needed. Because high-energy ions contained in direct plasma have been implicated in dielectric damage, the use of remote plasmas that lack ions provides a gentle and efficient way to perform pre-cleaning. In San Jose,

California 的 Novellus Systems所提供之 〇8111111&1^產品線中 有合適的實例遠端電漿系統。 在其他實施例中’藉由在存在還原氣體（例如，選自由 153514.doc •28- 201138024 H2 N2 NH3及其混合物組成之群組的氣體）的情況下使用 %卜（UV)辕射處理來執行對氧化銅之完全或部分移除。在 此實施中，此等氣體中之一者或一者以上（例如，^與沁 σ物或NH3與N2之混合物）接觸基板，同時以UV光照 射基板舉例而吕，諸如Β· Varadarajan等人在2009年11月 12曰申請之標題為「用於半導體處理中之〖恢復及表面清 潔之uv及還原處理（uv and Reducing f〇r κA suitable example of a remote plasma system is available in the 〇8111111&1^ product line offered by Novellus Systems of California. In other embodiments 'by using a %bu (UV) radiant treatment in the presence of a reducing gas (eg, a gas selected from the group consisting of 153514.doc • 28-201138024 H2 N2 NH3 and mixtures thereof) Perform a complete or partial removal of the copper oxide. In this embodiment, one or more of the gases (for example, a mixture with 沁σ or a mixture of NH3 and N2) are in contact with the substrate while irradiating the substrate with UV light, such as Β· Varadarajan et al. The title of the application filed on November 12, 2009 is "Using uv and Reducing f〇r κ for recovery and surface cleaning in semiconductor processing.

Recovery and surface Clean in Semiconductor Processing)」 的共同擁有的臨時專利中請案第61/26G，789號中描述了裝 置及製程條件，該中請案以全文引用的方式併人本文中， 以用於提供適合用於本文令所描述之實施例中的處理 之裝置及方法之細節的目的。所描述之uv處理可用於可 控地移除氧化銅，#中可藉由…暴露之持續時間、處理 氣體組份、|板溫度及其他條件來控制所移除氧化物之厚 度。 在-些實施例中’藉由在無電漿之環境中進行熱處理來 實現預先清潔。舉例而言，可在包含H2、N2、NH3或其混 合物之氣氛中將晶圓加熱至至少約200。〇之溫度並持續約 15至60秒。此減理可料部分氧域之料，且對於處 理含有脆弱之ULK介電質之基板而言尤其有利。 、 在完成預先清潔後，在操作3〇5中將含有摻雜劑之材料 的源層沈積至基板表面上。有利岐，含有摻雜劑之材 不需要選擇性地沈積至金屬表面上，且可沈積至介電質之 表面上及金屬上兩者。藉由在導致沈積含有摻雜劑(例 153514.doc -29· 201138024 如，含有硼或含有金屬）之源層的條件下使部分製造之器 件與含有摻雜劑之反應物（例如，與含有硼或含有金屬之 反應物）接觸來沈積源層。 在一個實施例中，在沒有電漿放電的情況下以熱的方式 沈積含有推雜劑之源層。舉例而言，揮發性前驅體（諸 如，揮發性氫化物、函化物、幾基合物或有機金屬化合 物）可在高溫下反應（例如，分解），以將含有摻雜劑之材料 層沈積於基板表面上。如熟習此項技術者將理解，可針對 每一特定前驅體調諧溫度範圍、基板暴露時間及其他沈積 條件。 在一個實施例中’ 用作前驅體以形成摻雜β之保護 蓋。在一個實例製程中，將連同一或多種額外載氣 (諸如N2、02、C〇2、He、NH3、Ar等）一起引入至處理腔 室中。在此實例中，Β2Ηδ之濃度介於約〇.5至約2〇%之範圍 中’且壓力介於約0.5托至約10托之範圍中β b2h6在不存 在電漿放電的情況下在約200_40(rc之間的腔室溫度下接 觸基板，從而導致將含硼層沈積於基板上。確定此層含有 B-H鍵，且將此層稱作BHj^。3札層用作擴散至銅線中並 形成保護蓋之B摻雜劑源。 在另一實例中，將揮發性含金屬之前驅體引入至腔室 中。有機金屬化合物、金屬氫化物、金屬鹵化物及金屬羰 基合物可用作合適的前驅體。舉例而言’可使用烷基取代 之金屬衍生物及環戊二烯基取代之金屬衍生物。前驅體在 尚溫下反應以在基板上形成含金屬源層。在一些實施例 153514.doc -30- 201138024 中，可使用類似於含B蓋之沈積中所使用之壓力及溫度範 圍的壓力及溫度範圍。一般而言，視前驅體之性質而定， 沈積條件經最佳化以沈積具有最佳品質的含金屬源層。舉 例而言，溫度範圍可經最佳化以有利於用於前驅體之特定 分解機制’且進而根據需要調諧含金屬源層之分解。熟習 此項技術者將理解如何最佳化沈積條件以及獲得具有經最 佳化組份的含金屬源層》 如曾提及’可將多種金屬用作摻雜劑。舉例而言，可用 A卜Hf、Ti、Co、Ta、Mo、Ru、Sn及Sb摻雜銅線。可使 用已知揮發性前驅體之其他金屬。適合於沈積含鋁源層之 前驅體之實例包括（但不限於）三曱基鋁、氫化二甲基鋁' 二乙基鋁、三異丁基鋁及參（二乙胺基）鋁。可用於沈積含 有其他金屬之源層的前驅體之實例包括（但不限於）雙（環戊 二烯）鈷、乙醯丙酮鈷（11)、肆（二甲胺基）铪、肆（二乙胺 基）铪、肆（二甲胺基）鉬、肆（二甲胺基）鈦（tdmat)、肆（二 乙胺基）鈦（TDEAT)、肆（乙基甲基胺基）鈦、雙（二乙胺基） 雙（二異丙基胺基）鈦、五（二甲胺基）鈕、第三（丁基三亞胺 基）（二乙胺基）鈕（TBTDET)、五（二乙胺基）鈕、雙（乙基環 戊二烯）釕、參（二甲胺基）銻及四甲基錫。 源層不一定需要含有純元素摻雜劑，而是可包括摻雜劑 與其他元素（例如，H、C、N等）之化合物。然而，可容易 自此二層產生摻雜劑，且一旦產生便能夠擴散至銅中及/ 或與銅反應°然而’在其他實施例中，源層可含有實質上 純的金屬或蝴。 153514.doc -31- 201138024 源層不需要專門選擇性地沈積於銅線之頂部上，而是可 沈積於介電層之頂部上及銅之頂部上兩者。然而，在許多 實施例中，實現銅與介電質之間的一定程度的選擇性，且 較厚之源層形成於銅線上，如圖4B中所說明，其中源層 408(其可為BHX層或含金屬層）在銅線408上具有比在介電 層401上厚的厚度。應理解，視特定前驅體及沈積條件而 定，可在將源層完全選擇性地沈積於銅線上至完全非選擇 性製程之範圍中實現廣泛多種選擇性，在完全非選擇性製 程中’在銅線及介電質兩者上將源層沈積至相等厚度。雖 然本文中所描述之方法可用於自選擇性地沈積源層及非選 擇性地沈積源層兩者中受控地引入捧雜劑，但本文中將該 等方法說明為將以部分選擇性沈積之層用作實例。此部分 選擇性之特徵在於’可在含硼及含許多金屬之源層兩者的 情況下觀察到，與沈積於介電質上之源層的厚度相比，沈 積於銅線上之源層具有較大厚度β在一些實施例中，駐留 於銅上之源層的厚度比駐留於介電質上之源層的厚度大約 10-500°/。之間。 再次參看圖3Α中所示之製程流程圖，當已在操作3〇5中 形成源層之後’在後續操作3〇7中，駐留於銅上之源層之 頂部部分經改質以形成鈍化層，而未經改質之源層之一部 分保持與銅層接觸》此藉由圖4C中所示之結構來說明，其 中僅源層408之一小部分保持未經改質且與銅線4〇5接觸， 而駐留於銅上之源層之頂部部分經轉化以形成鈍化層 4〇9。駐留於介電質上之源層之部分經完全轉化為鈍化材 153514.doc •32· 201138024 料°鈍化操作309用於兩個目的。首先，其幫助控制互連 件電阻，因為源層之部分鈍化限制了可用摻雜劑的量。較 佳地，鈍化層含有不容易自鈍化材料擴散至銅線中之材 料。舉例而言’硼經轉化為氮化硼；鋁經轉化為氧化鋁 專。雖然游離的蝴及紹能夠擴散至銅線中，但當經轉化為 氮化物及氧化物時，此等材料被捕集於鈍化層内，且不能 進入銅線並增加其電阻率，因為源層之頂部部分經改質為 純化層’所以藉由保持與銅線接觸之源層的未經改質部分 的厚度來確定引入至銅線中之摻雜劑的量。視需要被引入 至線中之摻雜劑的量而定，可將較大或較少量之源層轉化 為鈍化層。舉例而言，最初沈積之源層的厚度可在約5〇_ 500 Α之間的範圍令，該源層之約2〇·6〇%可被轉化為鈍化 層。 在源層含有沈積於銅及介電質兩者上之導電材料的彼等 貫施例中亦需要鈍化。在此等實施例中，鈍化將導電材料 (例如，金屬）轉化成很少導電性或不具有導電性之材料， 藉此防止鄰近銅線之間的短路。舉例而言，可在介電質上 將駐留於介電質上之部分導電性ΒΗΧ源層完全轉化成含有 基本上不導電的ΒΗΧ之鈍化層。類似地，可將含有鋁之源 層轉化成不導電的氧化鋁。 許多化合物（諸如氮化物、氧化物、硫化物、硒化物、 碲化物、磷化物及碳化物）為用於鈍化層之合適材料。在 此等化合物中，氮化物及氧化物在許多實施例中為較佳 的。 153514.doc •33· 201138024 可藉由使含有摻雜劑之源層與適當之試劑接觸而形成純 化層，該適當之試劑能夠將源層材料改質為鈍化材料。雖 然在-些f施例巾可用熱的方式執行此改f (不使用電 漿），但通常較佳在電㈣電中對源層進行改f。舉例而 言，可藉由在電毁中使基板與含氮之反應物（諸如N2、 NH3、N2H4、胺等）接觸來執行氮化。可藉由在電衆中接觸 引入之含氧反應物（諸如02、C02、N20等）而以類似方式形 成氧化物。可藉由分別使基板暴露於含有所需元素之反應 物（例如 H2S、HaSe、H，Te、PH,、ru、t „ rt2ie CxHy)而以類似方式形成 硫化物、硒化物、碲化物、磷化物及碳化物。 在一些實施例中，後處理涉及直接電漿處理。舉例而 言，可用在選自由HrNrNH3及其混合物組成之群組的 處理氣體中所形成之電漿來處理具有暴露之源層的基板。 在一些實施例中，在電漿中用Ha來處理具有源層之基板。 氫電漿處理可用以自前驅體層中移除殘餘有機基，並形成 末端金屬-Η鍵。在其他實例中，在電漿中用^與乂之混合 物或在電漿中用ΝΗ3對基板進行後處理，結果是移除了有 機基並形成金屬-Ν鍵。在一些實施例中可使用其他氮化 劑，諸如Ν2Η4及胺。 在後處理的情況下，有時候需要使用比直接電漿處理更 溫和的處理方法。舉例而言，在一些實施例中，可使用在 選自由Η2、Ν2、ΝΗ3及其混合物組成之群組的氣體中所形 成之遠端電漿來處理基板。如前所述，在實體上與容納基 板之腔室分離之腔室中產生遠端電漿，並消耗掉該遠端電 153514.doc •34· 201138024 漿中之離子物質，然後將其遞送至基板，此降低介電質受 損的概率。此係因為遠端電漿中含有之自由基的損害性2 常低於高能量離子。可藉由遠端電漿來實現金屬_H及金 屬-N鍵之形成’以及自層中移除有機基。 此外，可使用先前以引用的方式併入的美國臨時申請案 第61/260,789號中描述之方法，藉由在選自由％、％、 NH3及其混合物組成之群組的處理氣體中之uv輻射來執行 溫和的後處理。可使用此uv處理來形成金屬·Η及金屬_N 鍵，並且自前驅體層中移除有機取代基。 在一些貫知例中，藉由在不含電漿的環境中進行熱處理 來實現後處理。舉例而言，可在包含札、、NH3或其混 合物的氣氛中將晶圓加熱至至少約3〇〇至35〇。〇的溫度。此 熱處理對於處理含有脆弱的ULK介電質之基板尤其有利。 在一些實施例中，藉由在不含電漿的環境中在室溫下或 在高溫下用反應物處理源層而執行後處理。舉例而言，在 一些實施例中（例如，對於含八丨或含Ti之層），藉由在不含 電漿的環境中用含氧之反應物（例如02、H2〇、N2〇)處理 基板來形成含有金屬·氧鍵之鈍化層。 當在ILD層中使用ULK介電質（其為特別容易受損的多孔 及有機介電質）時，遠端電漿後處理、熱後處理&uv後處 理尤其有利》 雖然在許多實施例中氮化後處理為較佳的，但在—些實 施例中可使用其他類型之後處理。 舉例而言’可藉由在具有或不具有電漿的情況下使具有 I53514.doc -35- 201138024 暴露之前驅體層的基板接觸含氧氣體（諸如〇2、c〇2、 等)來實施用以形成金屬_〇鍵之氧化後處理。在其他實施 例中，例如藉由在電漿中用碳氫化合物處理源層而在後處 理步驟中形成金屬.C鍵。可藉由在具有或不具有電浆的情 況下使基板暴露於含有所需元素之反應物（分別為例如 H2S、H2Se、H2Te、ph3)而在後處理步驟中形成金屬& 金屬-Se、金屬-Te及金屬邛鍵。對於此等類型之後處理可 使用直接電漿及遠端電漿兩者。 再次參看圖4C，可看出，鈍化層4〇9(含有例如ΒΝχ、 Α10χ、ΤιΟχ等）駐留於介電層4〇1上及銅層4〇5上。含有未 改質之摻雜劑源的薄層408駐留於銅線與鈍化材料層之 間。 在形成鈍化層之後，在操作3〇9中，允許來自未經改質 之源層的有效成分（摻雜劑）擴散至銅中且/或與銅反應，並 在銅層内形成保護蓋。此在圖4C所示之結構中由箭頭說 明。圖4D中展示了所得結構，其中已在銅線之上部部分中 形成了保護蓋407。在此實例中，來自源層408之捧雜劑已 完全遷移至銅線中。在其他實施例中，一部分摻雜劑可保 留於源層内。而在其他實施例中，在銅擴散至未經改質之 源層中的同時，摻雜劑可擴散至銅層中。在後兩種情況 下’保護蓋可駐留於最初呈現之銅線（如圖2C中說明）内以 及其頂部上。 保護蓋之形成可在各種條件下發生，該條件可取決於駐 留於未經改質之源層中之特定摻雜劑源。在一些實施例 153514.doc •36· 201138024 中’駐留於源層内之含摻雜劑之材料可能不容易擴散至銅 中，與銅反應。在此等實施例中，可藉由例如使基板暴露 於高溫而首先產生摻雜劑。在其他實施例中，亦藉由加熱 基板來促進摻雜劑之擴散及/或反應。在一些實施例中， 可藉由控制使基板暴露於高溫之時間及暴露本身之溫度來 控制保護蓋的厚度。在一些實施例中，藉由將基板加教至 至少約1〇〇。(：之溫度持續預定時間段（例如，約〇25至⑹分 鐘）來促進形成保護蓋。 在形成保護蓋後’即刻在操作311中沈積捧雜之或未推 雜之碳化矽層。圖4E中展示所得結構。可看出，在銅線上 及介電質區上之鈍化層409頂部上沈積碳化矽層41卜碳化 矽層充當蝕刻終止件或介電質擴散障壁層，且通常沈積至 約HHMOO A的厚度。可例如藉由在電漿放電中使基板暴 露於切之及含碳 < 前驅體而#由CVD(較佳藉由pEcvD) 沈積碳化碎層。舉例而言，可料垸、燒基㈣及碳氣化 合物用作前驅體。當沈積摻雜之碳切時，另外將含換雜 劑之前驅體引入至處理腔室中。舉例而言，可在沈積含氧 之碳化碎期間添加C02、〇2或_，可添加㈣以沈積推 雜有硼之碳化矽，可添加\%及A以沈積摻雜有氮之碳化 石夕等。在其他實施例中，在鈍化層之頂部上沈積經推雜的 或未經摻雜的氮化矽以充當蝕刻終止件或擴散障壁層。在 —些實施例卜在高於形成罩蓋層（包括形成源層及鈍化） 時使用之溫度的溫度下執行介電質擴散障壁層的沈積。舉 例而言，在一些實施例中，在350〇c以下之溫度下（例如， 153514.doc •37- 201138024 在約200°C至350°C下）實施保護蓋的形成，而在至少約 350°C(例如，375°C至450。〇之溫度下執行擴散障壁沈積。 應注意，在一些情況下，介電質擴散障壁或蝕刻終止層 之沈積為可選的，因為鈍化層本身可能具有充當擴散障壁 或蝕刻終止件之適當性質。舉例而言，含有特定金屬氧化 物之鈍化層可充當擴散障壁層，從而無需沈積獨立的碳化 石夕層。 圖3中描繪之製程前進至後續操作313，在操作313中沈 積層間介電質（諸如二氧化石夕、有機石夕玻璃、多孔有機介 電質等）。將介電質沈積至擴散障壁或蝕刻終止層上（例如 沈積至碳化矽層上），或直接沈積至鈍化層上（若鈍化材料 具有充當擴散障壁之適當性質）。可藉由PECVD或藉由旋 塗方法來沈積介電質，且通常將其沈積至約3〇〇〇至1〇〇〇〇 A的厚度《接著，如圖1(：至1£中描繪，可進一步接著鑲嵌 製程。 應瞭解，圖3所示之流程圖所說明之製程僅為例示性 的’且可實施對此製程之各種修改。舉例而言，可用不同 的次序來執行圖3所示之製程之各個操作。具體而言，可 在處理期間之不同時間執行將有效成分（摻雜劑）引入至銅 層中。在一些實施例中，可在已沈積蝕刻終止件或擴散障 壁層之後起始摻雜劑之產生及擴散。在一些實施例中，在 已形成ILD層之後在後處理中促進摻雜劑之擴散。通常， 藉由將基板加熱至至少約100〇c的溫度來執行此操作。在 其他實施例中，有效成分（摻雜劑）可擴散至銅中且/或與鋼 153514.doc -38- 201138024 反應，然後使源層鈍化。在此實施例中，可藉由控制未經 改質之源層與銅接觸的時間及/或藉由控制製程溫度來控 制引入之摻雜劑的量。 在一些實施例中，藉由以下方式修改圖3 A中說明之製 程.使駐留於銅線上之源層完全而非部分地鈍化，以便實 質上防止摻雜劑元素擴散至鋼線中。此修改在一些情況下 為有利的，因為歸因於摻雜劑擴散之互連件電阻增加可得 以最小化，同時仍然能實現改進之電遷移效能。 圖3B所示之製程流程圖說明該製程之另一實施例。此製 程使用用冑溫方式將含銘之源層沈積於不含氧化物之銅表 面上。在操作301中該製程藉由提供具有介電質中之銅線 圖案的部分製造之半導體器件而開始。舉例而言，可使用 諸如圖4A所示之基板的基板。在一些實施例中，銅線嵌入 於ULK ;丨電質（諸如介電常數為2 8及以下的多孔有機介電 質)層中。在圖3B中描述之實施例中，提供不含氧化物之 銅表面以防止氧化銅與有機鋁前驅體之間的反應非常重 要。甚至氧化銅之薄層將改變鋁沈積之機制，從而導致氧 化铭的形h在圖3B中描述之實施财，此類直接在銅表 面上形成氧化鋁為不合需要的。 在操作303中，$ 了移除氧化銅，預先清潔基板。用自 銅表面上完全移除氧化銅的方式來控制預清潔。此可藉由 選擇適當的預清潔持續時間及製程條件來實現。如上文參 看圖A所述可藉由直接電漿處理、遠端電漿處理、 處理或熱處理來執行預清潔。當使用脆弱的ULK介電質 153514.doc •39· 201138024 時’在一些實施例中使用在不存在直接電漿的情況下之預 處理。 在獲得不含氧化物之銅層之後，在至少約35〇。〇之基板 溫度（諸如至少約40(TC )下使部分製造之器件與有機鋁反應 物接觸’以形成含鋁之層’如操作305中所示。值得注意 的是’在較低溫度下，含鋁層在不含氧化物之銅表面上的 沈積速率不夠。可使用各種有機鋁反應物，其中在一些實 施例中二坑銘特別是三甲基銘為較佳的。合適的反應物之 貫例包括選自由三甲基鋁、氩化二甲基鋁、三乙基鋁、三 異丁基紹及參（二乙胺基）銘組成之群組的前驅體。在不存 在電漿的情況下，反應物接觸CVD腔室中之基板，且反應 物通常在暴露之介電質及銅表面兩者上形成含銘的層。可 例如藉由控制反應物流動速率及基板溫度來控制層的厚 度。沈積於介電質上之層通常在沈積後即刻自發氧化以形 成含有A1-0鍵之不導電層（由於介電質中存在氧化物質 在含銘之層未在介電質上完全氧化之彼等情況下，在後處 理步驟中對該層進行改質，其將介電質上之所有導電材料 轉化成不導電形式以防止互連件之間的短路。無論沈積於 介電質上之含鋁的層是否在沈積後立即自發氧化，均可使 用後處理步驟將駐留於銅上之含鋁之層的至少一部分轉化 成固疋化合物，該固定化合物在一些實施例中可能不導 電。 操作307提供兩個後處理選項。在第一實施例中，僅對 駐留於銅上之含鋁之層的頂部部分進行改質以形成鈍化 153514.doc -40· 201138024 層’其中未經改質之層的一部分保持與銅層接觸，其中在 操作309中允許來自未經改質部分之鋁擴散至銅中。在替 代實施例中’對駐留於銅上之整個含鋁之層進行改質以形 成固定化合物，從而實質上防止鋁擴散至銅線中。因為將 過量之鋁擴散至銅中會導致互連件電阻不當增加，且因為 在銅上形成薄的固定蓋（例如’含有A1-0或ai_n鍵之蓋）改 進與介電質的黏著，所以在一些實施例中，較佳最小化或 完全避免鋁擴散。 如參看圖3A所述，可使用各種後處理方法，包括在高溫 或室溫下之直接電漿處理、遠端電漿處理' UV處理及熱 (不含電漿）處理。 在一個實施例中，使用不含電漿之氧化處理（在室溫或 高溫下）以在銅表面上形成含有A1-0鍵之層。舉例而言， 可在不存在電漿的情況下使具有含鋁層之基板（在有機鋁 反應物處理之後）與含氧之反應物（諸如〇2、〇3、N2〇、h20 或C〇2)接觸’以形成固定之含有A1_0之材料。 在另一實施例中，使用不含電漿之氮化處理（在室溫或 高溫下）以在銅表面上形成含有A1-N鍵的層《舉例而言， 可在不存在電漿的情況下使具有含鋁之層之基板（在有機 銘反應物處理之後）與含氧反應物（諸如氨或聯氨）接觸。 當基板含有機械上脆弱的ULK介電質時，不含電漿之後 處理（包括UV及熱處理）尤其較佳，因為不含電漿之後處理 導致的介電質損害最小。 在後處理之後，該製程在操作311及3 13中以介電質擴散 153514.doc -41 · 201138024 障J層沈積及㈣介電質沈積結束，肖等操作如參看圖3A 所述而執行。 上过·方法自b夠長：供具有可控電阻且具有改進之電遷移特 眭之互連件。藉由此等方法形成之保護罩蓋層之厚度可在 :勺ίο A至ι〇,〇〇〇 A的範圍内變化。特別有利的《，此等方 法提供對在約10人至100入範圍内特別是在1〇 A至6〇 A範 圍内的罩蓋層厚度的控制。厚度介於約ίο A至6〇 A之罩蓋 膜可提供具有小於1%且小於3%之特別小的電阻偏移的互 連件，此目前是1C工業中所要求的。 裝置 一般而言，保護蓋之形成可在任何類型之裝置中執行， 該裝置允許引入揮發性前驅體，且經組態以提供對反應條 件（例如，腔室溫度、前驅體流動速率、暴露時間等）之控 制°通常較佳在不使基板暴露於周圍環境的情況下執行操 作301至311 ’以便防止對基板之無意氧化及污染。在一個 實施例中，在一個模組中依序執行操作301至311，而不破 壞真空。在一些實施例中，在一個CVD(較佳PECVD)裝置 中執行操作301至311，該裝置具有位於一個腔室内之多個 台’或具有多個腔室。可自Inc of San Jose，CA，Novellus Systems，Inc購得之VECT0Rtm PECVD裝置為合適裝置之 實例。 例示性裝置將包括一或多個腔室或「反應器」（有時包 括多個台），該等腔室或反應器容納一或多個晶圓且適合 於進行晶圓處理。每一腔室可容納一或多個晶圓以進行處 J535I4.doc • 42- 201138024 理。該一或多個腔室將晶圓維持於所界定位置中（在該位 置内運動或不運動，例如旋轉、振動或其他攪動在一 個實施例中，在製程期間在反應器内將正經歷源層及蝕刻 終止層沈積之晶圓自一個台轉移至另一個台。當正在處理 中時，藉由台座、晶圓夾及/或其他晶圓固持裝置將每一 晶圓固持於合適位置。對於要加熱晶圓之特定操作，該裝 置可包括加熱器，諸如加熱板。在本發明之較佳實施例 中，可使用PECVD系統。在更較佳之實施例中，pEcVD 系統包括LF RF電源。 圖5提供描繪經配置以用於實施本發明之各種反應器組 件的簡單方塊圖《如圖所示，反應器500包括處理腔室 524，處理腔室524封閉反應器之其他組件且用以容納由電 容器型系統產生之電漿，該電容器型系統包括結合接地加 熱器塊520工作之鎮射頭514。高頻RF產生器5 02及低頻rf 產生器504連接至匹配網路506，該匹配網路506又連接至 簇射頭514。 在反應器内’晶圓台座518支撐基板516。該台座通常包 括夾、叉或起模頂桿’用以在沈積反應期間或沈積反應之 間固持及轉移基板。該夾可為靜電夾、機械夾或可用於工 業及/或研究中之各種其他類型之夾。 處理氣體經由入口 512引入。多個源氣體管線510連接至 歧管508。氣體可預先混合或不預先混合。使用適當之閥 控及質量流量控制機制來確保在該製程之預清潔、源層之 形成、鈍化層之形成及摻雜階段期間遞送正確的氣體。在 153514.doc •43- 201138024 以液體形式遞送化學前驅體的情況下，使用液流控制機 制。接著，在液體到達沈積腔室之前，在加熱至高於液體 之蒸發點的歧管中輸送液體期間，使液體蒸發並與其他處 理氣體混合。 處理氣體經由出口 522自腔室500退出。真空泵526(例 如’一級或二極機械乾泵及/或渦輪分子泵）通常將處理氣 體抽出，並藉由封閉迴路控制流量限制器件（諸如節流閥 或擺閥）在反應器内維持合適低的壓力。 在該等實施例中之一者中，可使用多台裝置來形成罩蓋 層及擴散障壁。該多台反應器允許在一個腔室環境中同時 執行不同製程，藉此提高晶圓處理之效率。圖6中描繪此 裝置之一個實例。展示了俯視圖之示意圖。裝置腔室6〇1 包含四個台603至609及兩個承載室（進入承載室619及退出 承載室617)。在其他實施例中，可將單個承載室用於晶圓 之進入及退出兩者。一般而言，在多台裝置之單個腔室内 可存在任何數目個台。台6〇3用於基板晶圓之裝載及卸 載。台603至609可具有相同或不同的功能。舉例而言― 些台可專用於形成罩蓋層，而其他台可用於沈積介電質擴 散障壁膜。此外，一些台可專用於氧化銅還原。 在該等實施例中之一者中，個別台可在相異之製程條件 下操作，且可實質上彼此隔離。舉例而言，一個台可在一 個概度狀態下操作，而另__台可在不同之溫度狀態下操 作。 、 在一個實施例中，預清潔操作、源層之沈積及鈍化層之 153514.doc 201138024 :成：一個較佳溫度狀態下執行，且在多台裝置之一個台 、:在"'實施例中，介電質擴散障壁之沈積可能需 要不同的：度狀態，且可在不同的台中進行。在一些實施 幻中在單台或多台裝置之-個台中執行整個罩蓋製程， 〇括預處理、源層之形成、鈍化及含摻雜劑之蓋的形成。 在一些實施财，亦可在與罩蓋操作相同的台處執行介電 質擴散障壁層之沈積。在—些情況下，可使用進入承載室 619來預清潔或以其他方式預處理晶圓。此可能涉及藉由 例如化學還原進行之氧化物移除。 在一個實例中，台603可專用於預清潔及形成罩蓋層（由 前驅體層及鈍化層）。台6G3可在約則。c至彻。〇之溫度範 圍處操作，此在-些實施例巾對於罩蓋及預清潔操作兩者 均為較佳的。可在約35(rc至4〇〇它之溫度範圍下在台 605、607及609中進行介電質擴散障壁材料（諸如碳化矽）之 沈積，根據一些碳化矽沈積製程，該溫度範圍為較佳的製 程溫度。 有利的是，在一些實施例中，預清潔、源層之沈積、鈍 化及摻雜劑之引入可能需要類似條件，且可在一個台6〇3 處執行。 根據上述實施例，台603為預清潔台及保護蓋形成台。 台605、607及609可全部用於介電質擴散障壁層之沈積。 使用分度板（indexing Plate)611將基板抬離台座，並在下一 處理台處準確地定位基板。在台603處裝載晶圓基板且在 此處使晶圓基板經受任何處理（例如，預清潔及罩蓋，包 153514.doc -45- 201138024 括前驅體層沈積及純化）之後’將晶圓基板分度至台605， 在此處執行罩蓋（包括源層沈積及鈍化）及/或介電質沈積。 接著將晶圓移動至台607，在台607處開始或繼續擴散障壁 介電質的沈積。進一步將基板分度至台609,在台609處執 行對障壁介電質的進一步沈積，且接著將基板分度至台 603 ’在台603處將基板卸載，且在模組中裝上新的晶圓。 在正常挺作期間’獨立的基板佔據每一台，且每當重複製 程時’將基板移動至新的台。因此，具有四個台603、 605、607及609之裝置允許同時處理四個晶圓，其中至少 一個台執行不同於在其他台執行之製程的製程。或者，四 個晶圓可在全部四個台處經受相同操作，而不使某些台專 用於特定層之沈積。 現在將提供台之間製程序列之幾個具體實例。在第一實 例中，進入承載室執行預處理（例如，氧化銅之還原）。接 著，裝置之第一台（例如，台603或依序配置之多個第一台） 形成罩蓋層（藉由例如暴露於前驅體，諸如TMA) ^接著， 第二台（例如，圖6中之台6〇5)執行後處理，諸如鈍化（例 如，如本文中所述暴露於氮、氨及/或氫接著，裝置中 之其餘台（例如，台607及609)執行擴散障壁形成。 在另一實例中’第一台（例如，台6〇3)執行預處理第 二台（例如，台605或一系列順序台）執行罩蓋層之形成及後 處理（例如鈍化）兩者，且其餘之台執行介電質擴散障壁層 沈積。在又一實例中，第一台執行預處理、罩蓋層沈積及 後處理。其餘之台執行擴散障壁形成。 153514.doc •46· 201138024 可藉由控制器單元613來控制製程停侔 .^ Λ 件及製程流程本 身，控制器單元613包含用於監視、維捭 、*得及/或調整特定製 程變量（諸如HF及LF功率、氣體流動速率及時間、溫度、 壓力等等）的程式指令。舉例而言，可包 匕栝私夂用於源層 沈積及鈍化之硼烷及氨之流動速率的指令。該等指令可浐 定用以執行根據上述方法之操作的所有參數。舉^二言，曰 指令可包括用於預清潔、源層沈積、鈍化層之形成將摻 雜劑引人至鋼線中及介電錢散障壁沈積的參數。控制器 可包含用於不同裝置台之不同或相同指令，因而允許裝置 ***立地或同步操作。 圖7中說明多台裝置之另一實例。多台裝置7〇1包括駐留 於三個獨立處理腔室717、719及72丨中之六個台7〇3、 705、707、7〇9、711及713，其中兩個台駐留於每一腔室 中。鄰近於腔室717、719及721之含有機器人之腔室715提 供用於將晶圓裝載至台中及自台中卸載晶圓的機制。控制 器723提供用於操作多台裝置川的指令…個腔室内之個 別台可彼此隔離，且可進行相同或不同操作。在一個實施 例中，同時將兩個晶圓轉移至駐留於一個腔室72〗中之台 703及705，且使其同時經歷相同操作，包括預清潔、源層 沈積、鈍化層之形成及銅摻雜。在完成此製程之後，將該 兩個晶圓自腔室721移除，且同時引入至駐留於腔室7〇9中 的台707及709。在此腔室中，同時沈積擴散障壁材料層。 接著將該等晶圓自腔室71 9移除，且引入至駐留於腔室717 中之台711及713 ’在台711及713中接著進行進一步處理。 153514.doc •47· 201138024 在一些實施例中，可用在不同腔室中執行之不同子製程 (例如，源層沈積、鈍化、摻雜劑擴散）在多腔室裝置中執 行保護罩盖層的形成。 存在多種可在多台卫具中實施罩蓋製程之方式諸如圖 6及圖7所示的彼等方式…般而言，所描述之製程容易整 合至鎮嵌流程中’不需㈣基板進行消耗大量資源之處 置’且可在與介電質擴散障壁沈積相同的裝置中執行。此 外，經由對摻雜劑之受控釋放而進行的電阻控制尤其有 利。所描述之方法亦可用於形成具有銅與介電質擴散障壁 之間的改進之黏著的互連件。 現在將藉由具體實例來說明所描述方法之若干實施例。 實驗實例 將參考實驗實例來說明具有摻雜有硼之保護蓋以及含有 棚及氮之鈍化層的銅互連件的製造。 在所描述之實例中，藉由電漿預清潔操作來開始該製 程。在CMP操作之後獲得具有在超低k介電質（k=2 5 ; 5,000 A厚）中之銅線之暴露圖案的部分製造之半導體器 件，且將其置放於PECVD VECTORtm裝置之處理腔室中。 在四台裝置之一個台處執行整個罩蓋製程。首先，將基板 預加熱至350°C，且在4,000 seem之流動速率下將h2引入至 處理腔室中。使Hz在4托之壓力下自處理時間之〇秒流動至 30秒。在處理時間之3〇秒處，點燃HF RF電衆，且在1.23 W/cm2之功率下一直保持至處理時間之45秒。在用％電漿 預清潔基板之後’切斷H2流及電漿功率，並將b2h6以與氬 153514.doc -48· 201138024 的混合物之形式引入至處理腔室中。混合物中b2h6之濃度 為約5體積％，且將該混合物以約3600 seem之流動速率連 同以2400 seem流動速率引入之N2—起引入。使氣體自處 理時間之45秒流動至85秒，在此期間在基板上沈積含有 BHX之源層。在約350°C之溫度下且在約2.3托之壓力下執 行沈積。估計沈積於銅頂部上之源層的厚度為約215 A， 而估計沈積於介電質頂部上之源層的厚度為約159 A。在 已沈積了源BHX層之後’使棚院流停止，且使層純化以形 成（BNH)X。鈍化係在處理時間之85秒與90秒之間執行，且 涉及將NH3以約7000 seem之流動速率連同2800 seem之流 動速率下的N2—起引入。點燃具有功率位準為〇.8〇 w/cm2 的HF組分及功率位準為〇·37 W/cm2的LF組分之電漿，並將 電漿自90秒維持至96秒。在約350C之溫度下及約2.3托之 壓力下執行鈍化。估計駐留於介電質上之BHX層之整個厚 度轉變為（BNH)X，且駐留於銅上之源層的約25%之厚度轉 變為（BNH)X。稍後，藉由FT IR光譜學來分析（BNH)X層。 在IR光 s普上觀察到在 3430 cm·1 (υΝ_Η)、2560 cm·1 (υΒ_Η)及 1375 cm 1 (υβ-Ν)下之蜂值。 允許硼擴散至銅線中以形成摻雜有硼之罩蓋層。應瞭 解，硼擴散可在已使源層之頂部部分氮化（鈍化）之前及之 後發生。估計駐留於銅線内之摻雜有硼之蓋的厚度為约25 Α至 75 A 〇 在350°C之溫度下在單個台中執行整個罩蓋製程。隨 後，在350°C下在電漿中使用四曱基矽烷、氨及氮作為處 153514.doc -49· 201138024 理氣體在PECVD裝置之三個不同台中在基板上沈積 SixCyNz擴散障壁層（約500 Α)β在三個台中之每一者中沈 積碳化物層厚度之三分之一。 使用四點彎曲黏著測試來量測具有及不具有含硼之蓋的The apparatus and process conditions are described in the co-pending provisional patent of the Recovery and Surface Clean in Semiconductor Processing, pp. 61/26G, 789, which is hereby incorporated by reference in its entirety for use in The purpose of providing details of the apparatus and methods suitable for use in the processes described in the examples herein is provided. The described uv treatment can be used to controllably remove copper oxide, and the thickness of the removed oxide can be controlled by the duration of exposure, the composition of the gas, the temperature of the plate, and other conditions. In some embodiments, pre-cleaning is achieved by heat treatment in a plasma-free environment. For example, the wafer can be heated to at least about 200 in an atmosphere comprising H2, N2, NH3, or a mixture thereof. The temperature of the crucible lasts for about 15 to 60 seconds. This reduction may be part of the oxygen field and is particularly advantageous for processing substrates containing a weak ULK dielectric. After the pre-cleaning is completed, a source layer of the dopant-containing material is deposited onto the surface of the substrate in operation 3〇5. Advantageously, the dopant-containing material does not need to be selectively deposited onto the metal surface and can be deposited onto both the surface of the dielectric and the metal. By partially depositing a device with a dopant-containing reactant (eg, and containing) under conditions that result in deposition of a source layer containing a dopant (eg, 153514.doc -29. 201138024, for example, containing boron or containing a metal) Boron or a metal containing reactant is contacted to deposit the source layer. In one embodiment, the source layer containing the dopant is thermally deposited without plasma discharge. For example, a volatile precursor such as a volatile hydride, a complex, a few complexes, or an organometallic compound can be reacted (eg, decomposed) at elevated temperatures to deposit a layer of material containing the dopant On the surface of the substrate. As will be appreciated by those skilled in the art, temperature ranges, substrate exposure times, and other deposition conditions can be tuned for each particular precursor. In one embodiment, ' is used as a precursor to form a protective cover that is doped with beta. In one example process, one or more additional carrier gases (such as N2, 02, C〇2, He, NH3, Ar, etc.) are introduced together into the processing chamber. In this example, the concentration of Β2Ηδ is in the range of about 〇.5 to about 2〇% and the pressure is in the range of about 0.5 Torr to about 10 Torr. β b2h6 is in the absence of a plasma discharge. 200_40 (contacting the substrate at a chamber temperature between rc, resulting in deposition of a boron-containing layer on the substrate. It is determined that this layer contains a BH bond, and this layer is referred to as BHj^. 3 layer is used for diffusion into the copper wire And forming a B-dopant source for the protective cover. In another example, a volatile metal-containing precursor is introduced into the chamber. Organometallic compounds, metal hydrides, metal halides, and metal carbonyls can be used. Suitable precursors. For example, 'a metal-substituted metal derivative and a cyclopentadienyl-substituted metal derivative can be used. The precursor reacts at a temperature to form a metal-containing source layer on the substrate. In some implementations In Example 153514.doc -30- 201138024, pressure and temperature ranges similar to those used in the deposition of B-containing coatings can be used. In general, depending on the nature of the precursor, the deposition conditions are optimal. To deposit the best quality metal For example, the temperature range can be optimized to facilitate a particular decomposition mechanism for the precursor' and then to tune the decomposition of the metal-containing source layer as needed. Those skilled in the art will understand how to optimize the deposition conditions. And obtaining a metal-containing source layer having an optimized composition. As mentioned above, a plurality of metals can be used as a dopant. For example, Ab Hf, Ti, Co, Ta, Mo, Ru, Sn can be used. And Sb doped copper wire. Other metals of known volatile precursors may be used. Examples of precursors suitable for depositing an aluminum source layer include, but are not limited to, tridecyl aluminum, hydrogenated dimethyl aluminum' Base aluminum, triisobutyl aluminum and ginseng (diethylamino) aluminum. Examples of precursors that can be used to deposit source layers containing other metals include, but are not limited to, bis(cyclopentadienyl)cobalt, acetamidineacetone Cobalt (11), hydrazine (dimethylamino) hydrazine, hydrazine (diethylamino) hydrazine, hydrazine (dimethylamino) molybdenum, hydrazine (dimethylamino) titanium (tdmat), hydrazine (diethylamine) Titanium (TDEAT), bismuth (ethylmethylamino) titanium, bis(diethylamino) bis(diisopropylamino) Titanium, penta(dimethylamino) knob, third (butyltriimido) (diethylamino) knob (TBTDET), penta(diethylamino) knob, bis(ethylcyclopentadienyl) anthracene , ginseng (dimethylamino) ruthenium and tetramethyl tin. The source layer does not necessarily need to contain a pure element dopant, but may include a compound of a dopant with other elements (for example, H, C, N, etc.). However, dopants can be readily produced from the two layers and, once produced, can diffuse into and/or react with copper. However, in other embodiments, the source layer can contain substantially pure metals or butterflies. .doc -31- 201138024 The source layer does not need to be specifically deposited on top of the copper wire, but can be deposited on top of the dielectric layer and on top of the copper. However, in many embodiments, a certain degree of selectivity between copper and dielectric is achieved, and a thicker source layer is formed on the copper line, as illustrated in Figure 4B, where source layer 408 (which may be BHX) The layer or metal containing layer has a thicker thickness on the copper line 408 than on the dielectric layer 401. It will be appreciated that depending on the particular precursor and deposition conditions, a wide variety of selectivities can be achieved in the fully selective deposition of the source layer on the copper wire to a completely non-selective process, in a completely non-selective process. The source layer is deposited to an equal thickness on both the copper wire and the dielectric. Although the methods described herein can be used to control the introduction of dopants in both the selective deposition of the source layer and the non-selective deposition of the source layer, the methods herein are described as being to be partially selectively deposited. The layers are used as examples. This partial selectivity is characterized by 'observable in the case of both boron-containing and source layers containing many metals, the source layer deposited on the copper line has a thickness compared to the thickness of the source layer deposited on the dielectric Larger Thickness β In some embodiments, the thickness of the source layer residing on the copper is about 10-500°/thicker than the thickness of the source layer residing on the dielectric. between. Referring again to the process flow diagram shown in FIG. 3A, after the source layer has been formed in operation 3〇5, in the subsequent operation 3〇7, the top portion of the source layer residing on the copper is modified to form a passivation layer. And a portion of the source layer that has not been modified remains in contact with the copper layer. This is illustrated by the structure shown in FIG. 4C, in which only a small portion of the source layer 408 remains unmodified and is copper-plated. 5 contact, while the top portion of the source layer residing on the copper is transformed to form a passivation layer 4〇9. The portion of the source layer residing on the dielectric is completely converted to passivation material. 153514.doc •32· 201138024 The material passivation operation 309 is used for two purposes. First, it helps control the interconnect resistance because partial passivation of the source layer limits the amount of dopant available. Preferably, the passivation layer contains a material that does not readily diffuse from the passivation material into the copper wire. For example, boron is converted to boron nitride; aluminum is converted to alumina. Although the free butterfly can diffuse into the copper wire, when converted into nitrides and oxides, these materials are trapped in the passivation layer and cannot enter the copper wire and increase its resistivity because the source layer The top portion is modified to a purification layer' so the amount of dopant introduced into the copper wire is determined by maintaining the thickness of the unmodified portion of the source layer in contact with the copper wire. A larger or smaller amount of the source layer can be converted to a passivation layer depending on the amount of dopant introduced into the line as needed. For example, the thickness of the initially deposited source layer can range from about 5 Å to about 500 Å, and about 2 〇 6 % of the source layer can be converted to a passivation layer. Passivation is also required in the embodiment where the source layer contains a conductive material deposited on both copper and dielectric. In such embodiments, passivation converts a conductive material (e.g., metal) into a material that is less conductive or non-conductive, thereby preventing short circuits between adjacent copper lines. For example, a portion of the conductive germanium source layer residing on the dielectric can be completely converted to a passivation layer containing substantially non-conductive germanium on the dielectric. Similarly, a source layer containing aluminum can be converted to a non-conductive alumina. Many compounds, such as nitrides, oxides, sulfides, selenides, tellurides, phosphides, and carbides, are suitable materials for the passivation layer. Among such compounds, nitrides and oxides are preferred in many embodiments. 153514.doc •33· 201138024 A source layer can be modified to a passivating material by contacting the source layer containing the dopant with a suitable reagent to form a purified layer. Although it is possible to perform this modification in a thermal manner (without using plasma), it is generally preferred to modify the source layer in electrical (four) power. For example, nitriding can be performed by contacting the substrate with a nitrogen-containing reactant (such as N2, NH3, N2H4, amine, etc.) in electrical destruction. The oxide can be formed in a similar manner by contacting an oxygen-containing reactant (such as 02, C02, N20, etc.) introduced in the electricity. Sulfide, selenide, telluride, phosphorus can be formed in a similar manner by exposing the substrate to a reactant containing the desired element, such as H2S, HaSe, H, Te, PH, ru, t rt2ie CxHy, respectively. And in some embodiments, the post-treatment involves direct plasma treatment. For example, the plasma formed in the treatment gas selected from the group consisting of HrNrNH3 and mixtures thereof can be used to treat the source with exposure. The substrate of the layer. In some embodiments, the substrate having the source layer is treated with Ha in the plasma. Hydrogen plasma treatment can be used to remove residual organic groups from the precursor layer and form terminal metal-Η bonds. In an example, the substrate is post-treated with a mixture of ruthenium and ruthenium in the plasma or with ruthenium 3 in the plasma, with the result that the organic group is removed and a metal-ruthenium bond is formed. In some embodiments, other nitridation may be used. Agents such as Ν2Η4 and amines. In the case of post-treatment, it is sometimes necessary to use a milder treatment than direct plasma treatment. For example, in some embodiments, it may be selected from the group consisting of Η2, Ν2, ΝΗ3 and The distal plasma formed in the gas of the group consisting of the mixture processes the substrate. As previously described, the distal plasma is physically generated in a chamber separate from the chamber housing the substrate, and the far side is consumed 153514.doc •34· 201138024 The ionic species in the slurry is then delivered to the substrate, which reduces the probability of dielectric damage. This is because the damage of the free radicals contained in the far-end plasma is often low. For high-energy ions, metal_H and metal-N bond formation can be achieved by remote plasma and organic groups can be removed from the layer. In addition, US interim applications previously incorporated by reference can be used. The method described in No. 61/260,789, which performs a mild post-treatment by uv radiation in a process gas selected from the group consisting of %, %, NH3, and mixtures thereof. This uv treatment can be used to form a metal. Η and metal _N bond, and remove organic substituents from the precursor layer. In some examples, post-treatment is achieved by heat treatment in a plasma-free environment. For example, it can be included , NH3 or a mixture of gases The wafer is heated to a temperature of at least about 3 Torr to 35 Torr. This heat treatment is particularly advantageous for processing substrates containing a weak ULK dielectric. In some embodiments, by in a plasma-free environment The post treatment is carried out by treating the source layer with the reactants at room temperature or at elevated temperature. For example, in some embodiments (for example, for a layer containing tantalum or Ti), by not containing a plasma The substrate is treated with an oxygen-containing reactant (eg, 02, H 2 〇, N 2 〇) to form a passivation layer containing a metal-oxygen bond. When a ULK dielectric is used in the ILD layer (which is particularly susceptible to damage) Far-end plasma post-treatment, thermal post-treatment & uv post-treatment are particularly advantageous when porous and organic dielectrics are used. Although nitriding treatment is preferred in many embodiments, in some embodiments Use other types after processing. For example, 'the substrate can be exposed to an oxygen-containing gas (such as 〇2, c〇2, etc.) by having the substrate of the precursor layer exposed to I53514.doc-35-201138024 with or without plasma. To form a post-oxidation treatment of the metal _ 〇 bond. In other embodiments, the metal.C bond is formed in a post-treatment step, such as by treating the source layer with a hydrocarbon in the plasma. Metal & Metal-Se can be formed in a post-treatment step by exposing the substrate to a reactant containing the desired element (with, for example, H2S, H2Se, H2Te, ph3, respectively) with or without plasma. Metal-Te and metal bismuth bonds. Both direct plasma and remote plasma can be used for these types of post processing. Referring again to FIG. 4C, it can be seen that the passivation layer 4〇9 (containing, for example, ruthenium, iridium 10 χ, ΤιΟχ, etc.) resides on the dielectric layer 4〇1 and on the copper layer 4〇5. A thin layer 408 containing an unmodified dopant source resides between the copper line and the passivation material layer. After the formation of the passivation layer, in operation 3〇9, the active ingredient (dopant) from the unmodified source layer is allowed to diffuse into the copper and/or react with copper, and a protective cap is formed in the copper layer. This is illustrated by the arrows in the structure shown in Fig. 4C. The resulting structure is illustrated in Figure 4D in which a protective cover 407 has been formed in the upper portion of the copper wire. In this example, the dopant from source layer 408 has completely migrated into the copper wire. In other embodiments, a portion of the dopant can be retained within the source layer. In other embodiments, the dopant may diffuse into the copper layer while the copper diffuses into the unmodified source layer. In the latter two cases, the protective cover can reside in the initially presented copper wire (as illustrated in Figure 2C) and on top of it. The formation of the protective cover can occur under a variety of conditions, which can depend on the particular dopant source remaining in the unmodified source layer. In some embodiments 153514.doc • 36· 201138024, dopant-containing materials residing in the source layer may not readily diffuse into the copper and react with the copper. In such embodiments, the dopant can be first produced by, for example, exposing the substrate to elevated temperatures. In other embodiments, diffusion and/or reaction of the dopant is also facilitated by heating the substrate. In some embodiments, the thickness of the protective cover can be controlled by controlling the time at which the substrate is exposed to high temperatures and the temperature of the exposed itself. In some embodiments, the substrate is taught to be at least about 1 Torr. (The temperature of the: is continued for a predetermined period of time (for example, about 25 to (6) minutes) to promote the formation of the protective cover. Immediately after the formation of the protective cover, a layer of carbonized germanium is deposited or undoped in operation 311. Figure 4E The resulting structure is shown. It can be seen that a tantalum carbide layer 41 is deposited on top of the passivation layer 409 on the copper line and the dielectric region. The tantalum carbide layer acts as an etch stop or dielectric diffusion barrier layer and is typically deposited to about The thickness of HHMOO A. The substrate can be exposed to carbon and carbon, for example, by plasma discharge. <Precursor# The carbonized fracture layer is deposited by CVD (preferably by pEcvD). For example, ruthenium, ruthenium (IV) and carbon gas compounds can be used as precursors. When the doped carbon is deposited, the precursor containing the dopant is additionally introduced into the processing chamber. For example, CO 2 , 〇 2 or _ may be added during the deposition of oxygen-containing carbonization ash, (4) may be added to deposit lanthanum carbide doped with boron, and \% and A may be added to deposit carbon-doped carbonized fossils. Wait. In other embodiments, the doped or undoped tantalum nitride is deposited on top of the passivation layer to act as an etch stop or diffusion barrier layer. The deposition of the dielectric diffusion barrier layer is performed at temperatures above the temperatures used to form the cap layer (including forming the source layer and passivating). For example, in some embodiments, the formation of the protective cover is performed at a temperature below 350 〇c (eg, 153514.doc • 37-201138024 at about 200 ° C to 350 ° C), while at least about 350 °C (for example, 375 ° C to 450 ° diffusion temperature barrier deposition is performed. It should be noted that in some cases, the deposition of dielectric diffusion barrier or etch stop layer is optional because the passivation layer itself may have Appropriate properties that act as a diffusion barrier or etch stop. For example, a passivation layer containing a particular metal oxide can act as a diffusion barrier layer, thereby eliminating the need to deposit a separate layer of carbonized carbide. The process depicted in FIG. 3 proceeds to subsequent operations 313. An interlayer dielectric (such as a dioxide dioxide, an organic glass, a porous organic dielectric, etc.) is deposited in operation 313. The dielectric is deposited onto a diffusion barrier or an etch stop layer (eg, deposited onto a tantalum carbide layer) Top), or deposited directly onto the passivation layer (if the passivation material has the appropriate properties to act as a diffusion barrier). The dielectric can be deposited by PECVD or by spin coating, and is typically deposited A thickness of about 3 〇〇〇 to 1 〇〇〇〇 A. Next, as depicted in Figure 1 (: to 1 £, the process can be further embedded. It should be understood that the process illustrated in the flow chart shown in Figure 3 is only Various modifications to this process can be implemented and can be performed, for example, the various operations of the process illustrated in Figure 3 can be performed in a different order. In particular, the active ingredients can be performed at different times during processing ( The dopant) is introduced into the copper layer. In some embodiments, the generation and diffusion of the dopant can be initiated after the etch stop or diffusion barrier layer has been deposited. In some embodiments, after the ILD layer has been formed Promoting diffusion of the dopant during post processing. Typically, this operation is performed by heating the substrate to a temperature of at least about 100 〇 C. In other embodiments, the active ingredient (dopant) can diffuse into the copper and / or react with steel 153514.doc -38 - 201138024, and then passivate the source layer. In this embodiment, by controlling the time of contact of the unmodified source layer with copper and / or by controlling the process temperature The amount of dopant introduced is controlled. In some embodiments, the process illustrated in Figure 3A is modified in such a manner that the source layer residing on the copper wire is completely but not partially passivated to substantially prevent diffusion of dopant elements into the steel wire. This is advantageous in some cases because the increase in interconnect resistance due to dopant diffusion can be minimized while still achieving improved electromigration performance. The process flow diagram shown in Figure 3B illustrates another process In one embodiment, the process uses a germanium source layer deposited on the copper-free surface of the oxide by a temperature-dependent method. In operation 301, the process is fabricated by providing a portion having a copper line pattern in the dielectric. Starting with a semiconductor device, for example, a substrate such as the substrate shown in Fig. 4A can be used. In some embodiments, the copper wire is embedded in a layer of ULK; germanium (such as a porous organic dielectric having a dielectric constant of 28 and below). In the embodiment depicted in Figure 3B, it is important to provide an oxide-free copper surface to prevent the reaction between copper oxide and the organoaluminum precursor. Even a thin layer of copper oxide will alter the mechanism of aluminum deposition, resulting in the oxidation of the shape h described in Figure 3B, which is undesirable for forming aluminum oxide directly on the copper surface. In operation 303, the copper oxide is removed, and the substrate is cleaned in advance. Pre-cleaning is controlled by completely removing copper oxide from the copper surface. This can be achieved by selecting the appropriate pre-cleaning duration and process conditions. Pre-cleaning can be performed by direct plasma treatment, remote plasma treatment, treatment or heat treatment as described above with reference to Figure A. When a fragile ULK dielectric 153514.doc • 39· 201138024 is used, a pretreatment in the absence of direct plasma is used in some embodiments. After obtaining an oxide-free copper layer, it is at least about 35 Torr. The substrate temperature of the crucible, such as at least about 40 (TC), causes the partially fabricated device to contact the organoaluminum reactant to form an aluminum-containing layer as shown in operation 305. It is worth noting that at lower temperatures, The deposition rate of the aluminum-containing layer on the surface of the oxide-free copper is insufficient. Various organoaluminum reactants can be used, of which in some embodiments it is preferred that the two pits, especially trimethyl, are preferred. The example includes a precursor selected from the group consisting of trimethylaluminum, dimethylaluminum hydride, triethylaluminum, triisobutyl sulphate, and succinyl (diethylamino). In the absence of plasma In the case where the reactants contact the substrate in the CVD chamber, and the reactants typically form a layer containing the imprint on both the exposed dielectric and the copper surface. The layer can be controlled, for example, by controlling the reactant flow rate and substrate temperature. The thickness deposited on the dielectric is usually spontaneously oxidized immediately after deposition to form a non-conductive layer containing A1-0 bonds (due to the presence of oxidized species in the dielectric, the layer containing the inscription is not completely dielectric) In the case of oxidation, in the post-processing step The layer is modified to convert all of the conductive material on the dielectric into a non-conducting form to prevent short circuits between the interconnects, whether or not the aluminum-containing layer deposited on the dielectric is deposited immediately after deposition. Spontaneous oxidation, a post-treatment step can be used to convert at least a portion of the aluminum-containing layer residing on the copper to a solid chelating compound, which in some embodiments may be non-conductive. Operation 307 provides two post-treatment options. In the first embodiment, only the top portion of the aluminum-containing layer residing on the copper is modified to form passivation 153514.doc -40·201138024 layer 'where a portion of the unmodified layer remains in contact with the copper layer, Wherein aluminum from the unmodified portion is allowed to diffuse into the copper in operation 309. In an alternative embodiment, the entire aluminum-containing layer residing on the copper is modified to form a fixed compound to substantially prevent aluminum diffusion. Into the copper wire, because the diffusion of excess aluminum into the copper will result in an improper increase in the resistance of the interconnect, and because the formation of a thin fixed cover on the copper (such as 'cover with A1-0 or ai_n key) is improved. Adhesion to the dielectric, so in some embodiments, it is preferred to minimize or completely avoid aluminum diffusion. As described with reference to Figure 3A, various post-treatment methods can be used, including direct plasma treatment at elevated temperatures or room temperature. , remote plasma treatment 'UV treatment and heat (without plasma) treatment. In one embodiment, the plasma-free oxidation treatment (at room temperature or high temperature) is used to form A1- on the copper surface. A layer of 0. For example, a substrate having an aluminum-containing layer (after treatment with an organoaluminum reactant) and an oxygen-containing reactant (such as 〇2, 〇3, N2〇) can be used in the absence of plasma. , h20 or C〇2) contact 'to form a fixed material containing A1_0. In another embodiment, a plasma-free treatment (at room temperature or elevated temperature) is used to form A1 on the copper surface. Layer of -N bond "For example, a substrate having an aluminum-containing layer (after treatment with an organic reactant) can be contacted with an oxygen-containing reactant (such as ammonia or hydrazine) in the absence of plasma. When the substrate contains a mechanically fragile ULK dielectric, post-plasma-free processing (including UV and heat treatment) is especially preferred because dielectric damage caused by post-treatment without plasma is minimal. After the post-treatment, the process is completed in operations 311 and 3 13 by dielectric diffusion 153514.doc -41 · 201138024 barrier J deposition and (iv) dielectric deposition, and operations such as described with reference to Figure 3A. The method has been long enough for an interconnect with a controllable resistance and improved electromigration characteristics. The thickness of the protective cover layer formed by such methods can vary within the range of scoop ίο A to ι〇, 〇〇〇 A. Particularly advantageous, these methods provide control over the thickness of the cover layer in the range of about 10 to 100 inches, particularly in the range of 1 A to 6 A. A cover film having a thickness of between about 0.25 A and about 6 A provides an interconnect having a particularly small resistance offset of less than 1% and less than 3%, which is currently required in the 1C industry. Devices In general, the formation of a protective cover can be performed in any type of device that allows the introduction of a volatile precursor and is configured to provide reaction conditions (eg, chamber temperature, precursor flow rate, exposure time) Control of the etc. is generally preferred to perform operations 301 through 311 ' without exposing the substrate to the surrounding environment in order to prevent unintentional oxidation and contamination of the substrate. In one embodiment, operations 301 through 311 are performed sequentially in a module without breaking the vacuum. In some embodiments, operations 301 through 311 are performed in a CVD (preferred PECVD) apparatus having a plurality of stages within a chamber or having a plurality of chambers. A VECT0Rtm PECVD apparatus available from Inc. of San Jose, CA, Novellus Systems, Inc. is an example of a suitable apparatus. An exemplary device will include one or more chambers or "reactors" (sometimes including a plurality of stages) that house one or more wafers and are suitable for wafer processing. Each chamber can hold one or more wafers for processing. J535I4.doc • 42- 201138024. The one or more chambers maintain the wafer in a defined position (with or without motion within the position, such as rotation, vibration, or other agitation. In one embodiment, the source will be experienced within the reactor during the process Layer and etch stop layer deposited wafers are transferred from one station to another. Each wafer is held in place by pedestals, wafer holders, and/or other wafer holding devices while in process. To heat the particular operation of the wafer, the apparatus can include a heater, such as a heater plate. In a preferred embodiment of the invention, a PECVD system can be used. In a more preferred embodiment, the pEcVD system includes a LF RF power source. 5 provides a simplified block diagram depicting various reactor components configured for use in practicing the present invention. As shown, reactor 500 includes a processing chamber 524 that encloses other components of the reactor and is configured to accommodate A capacitor-type system produces a plasma that includes a town head 514 that operates in conjunction with a ground heater block 520. A high frequency RF generator 502 and a low frequency rf generator 504 are coupled to the matching network 5 06, the matching network 506 is in turn coupled to the showerhead 514. Within the reactor, the wafer pedestal 518 supports the substrate 516. The pedestal typically includes a clip, fork or die ejector for use during deposition or deposition reactions. The substrate is held and transferred. The clip can be an electrostatic clip, a mechanical clip, or various other types of clips that can be used in industry and/or research. Process gases are introduced via inlet 512. A plurality of source gas lines 510 are coupled to manifold 508. The gas may or may not be pre-mixed. Appropriate valve control and mass flow control mechanisms are used to ensure proper gas delivery during pre-cleaning of the process, formation of source layers, formation of passivation layers, and doping stages. .doc •43- 201138024 In the case of a chemical precursor delivered in liquid form, a flow control mechanism is used. Next, before the liquid reaches the deposition chamber, during transport of the liquid to a manifold that is heated above the evaporation point of the liquid, The liquid evaporates and mixes with other process gases. The process gas exits from chamber 500 via outlet 522. Vacuum pump 526 (eg, a primary or secondary mechanical dry pump and/or The wheel molecular pump) typically draws process gas and maintains a suitably low pressure within the reactor by a closed loop controlled flow limiting device, such as a throttle or a pendulum valve. In one of these embodiments, Multiple devices are used to form the cap layer and the diffusion barrier. The multiple reactors allow different processes to be performed simultaneously in a single chamber environment, thereby increasing the efficiency of wafer processing. An example of such a device is depicted in Figure 6. A schematic view of the top view. The device chamber 6〇1 includes four stages 603 to 609 and two load carrying chambers (into the carrying chamber 619 and exiting the carrying chamber 617). In other embodiments, a single carrying chamber can be used for the wafer. Both enter and exit. In general, there can be any number of stations in a single chamber of multiple devices. Table 6〇3 is used for loading and unloading of substrate wafers. Stages 603 through 609 can have the same or different functions. For example, some of the stages can be dedicated to forming a cap layer, while others can be used to deposit a dielectric diffusion barrier film. In addition, some stations can be dedicated to copper oxide reduction. In one of these embodiments, the individual stations can operate under different process conditions and can be substantially isolated from one another. For example, one station can operate in a single state, while another station can operate at different temperatures. In one embodiment, the pre-cleaning operation, the deposition of the source layer, and the passivation layer are performed 153514.doc 201138024: in a preferred temperature state, and in one of the plurality of devices, in the "' embodiment The deposition of dielectric diffusion barriers may require different degrees of state and may be performed in different stages. In some implementations, the entire cap process is performed in a single or multiple devices, including pre-treatment, formation of source layers, passivation, and formation of a cap containing a dopant. In some implementations, deposition of a dielectric diffusion barrier layer may also be performed at the same station as the cover operation. In some cases, the entry carrier chamber 619 can be used to pre-clean or otherwise pre-treat the wafer. This may involve oxide removal by, for example, chemical reduction. In one example, stage 603 can be dedicated to pre-cleaning and forming a cap layer (by a precursor layer and a passivation layer). Taiwan 6G3 is available at the appointment. c to the end. Operating in the temperature range of the crucible, it is preferred in some embodiments for both the cover and the pre-cleaning operation. The deposition of a dielectric diffusion barrier material (such as tantalum carbide) may be performed in stages 605, 607, and 609 at a temperature range of about 35 (rc to 4 Torr), which may be based on some tantalum carbide deposition processes. Optimum Process Temperature. Advantageously, in some embodiments, pre-cleaning, deposition of source layers, passivation, and introduction of dopants may require similar conditions and may be performed at one station 6〇3. The stage 603 is a pre-cleaning stage and a protective cover forming stage. The stages 605, 607 and 609 can all be used for the deposition of the dielectric diffusion barrier layer. The indexing plate 611 is used to lift the substrate off the pedestal and next The substrate is accurately positioned at the processing station. The wafer substrate is loaded at stage 603 where the wafer substrate is subjected to any processing (eg, pre-cleaning and capping, package 153514.doc -45-201138024 including precursor layer deposition and purification) Afterwards, the wafer substrate is indexed to stage 605 where the cover (including source layer deposition and passivation) and/or dielectric deposition is performed. The wafer is then moved to stage 607, starting at stage 607 or Continue to spread the barrier Qualitative deposition. Further indexing the substrate to stage 609, performing further deposition of the barrier dielectric at stage 609, and then indexing the substrate to stage 603' unloads the substrate at stage 603, and in the module Install a new wafer. During the normal setup, 'a separate substrate occupies each unit, and every time the re-copying process' moves the substrate to a new station. Therefore, there are four stations 603, 605, 607 and 609. The device allows four wafers to be processed simultaneously, at least one of which performs a different process than the one performed at the other station. Alternatively, four wafers can be subjected to the same operation at all four stations without having certain stations dedicated to Deposition of a particular layer. Several specific examples of inter-stage programming will now be provided. In a first example, a pre-treatment (e.g., reduction of copper oxide) is performed into the load compartment. Next, the first station of the apparatus (eg, The stage 603 or a plurality of first stations configured in sequence) form a cover layer (by, for example, being exposed to a precursor such as TMA). Next, the second stage (for example, the stage 6〇5 in FIG. 6) performs post-processing. , such as passivation (for example, such as Exposure to nitrogen, ammonia, and/or hydrogen as described herein, and the remaining stations in the apparatus (eg, stages 607 and 609) perform diffusion barrier formation. In another example, the first station (eg, station 6〇3) performs The second pre-processing (eg, stage 605 or series of sequential stages) performs both the formation of the cap layer and the post-treatment (eg, passivation), and the remaining stages perform dielectric diffusion barrier layer deposition. In yet another example The first stage performs pre-treatment, cap layer deposition and post-treatment. The remaining stages perform diffusion barrier formation. 153514.doc •46· 201138024 The controller unit 613 can be used to control the process stoppage. ^ Λ Parts and process flow In its entirety, controller unit 613 includes program instructions for monitoring, maintaining, and/or adjusting specific process variables such as HF and LF power, gas flow rate and time, temperature, pressure, and the like. For example, instructions for the flow rate of borane and ammonia used for source layer deposition and passivation can be included. These instructions determine all of the parameters used to perform the operations in accordance with the methods described above. In other words, the 指令 command may include parameters for pre-cleaning, source layer deposition, formation of a passivation layer, introduction of the dopant into the steel wire, and deposition of the dielectric barrier. The controller can include different or identical instructions for different sets of stations, thus allowing the set to operate independently or synchronously. Another example of a plurality of devices is illustrated in FIG. The plurality of devices 7〇1 includes six stations 7〇3, 705, 707, 7〇9, 711 and 713 residing in three independent processing chambers 717, 719 and 72, wherein two stations reside in each In the chamber. A robot-containing chamber 715 adjacent to chambers 717, 719, and 721 provides a mechanism for loading wafers into and out of the stage. The controller 723 provides instructions for operating a plurality of devices. Each of the chambers can be isolated from each other and can perform the same or different operations. In one embodiment, two wafers are simultaneously transferred to stations 703 and 705 residing in one chamber 72 and subjected to the same operation simultaneously, including pre-cleaning, source layer deposition, passivation layer formation, and copper. Doping. After completing this process, the two wafers are removed from chamber 721 and simultaneously introduced to stations 707 and 709 residing in chamber 7〇9. In this chamber, a layer of diffusion barrier material is simultaneously deposited. The wafers are then removed from chamber 7199 and introduced into stations 711 and 713' residing in chamber 717 for further processing in stages 711 and 713. 153514.doc •47· 201138024 In some embodiments, the protective cap layer can be performed in a multi-chamber device using different sub-processes (eg, source layer deposition, passivation, dopant diffusion) performed in different chambers form. There are a variety of ways in which the cover process can be implemented in multiple fixtures, such as those shown in Figures 6 and 7. In general, the described process is easily integrated into the town-in-the-loop process without the need for (four) substrates for consumption. The disposal of a large amount of resources' can be performed in the same device as the dielectric diffusion barrier deposition. In addition, resistance control via controlled release of dopants is particularly advantageous. The described method can also be used to form interconnects having improved adhesion between copper and dielectric diffusion barriers. Several embodiments of the described method will now be illustrated by way of specific examples. Experimental Example The manufacture of a copper interconnect having a protective cover doped with boron and a passivation layer containing a shed and nitrogen will be described with reference to experimental examples. In the depicted example, the process is initiated by a plasma pre-cleaning operation. A partially fabricated semiconductor device having an exposed pattern of copper lines in an ultra low k dielectric (k = 2 5 ; 5,000 A thick) is obtained after the CMP operation and placed in a processing chamber of a PECVD VECTORtm device in. The entire cover process is performed at one of the four units. First, the substrate was preheated to 350 ° C and h2 was introduced into the processing chamber at a flow rate of 4,000 seem. The Hz was allowed to flow from the leap second of the treatment time to 30 seconds under a pressure of 4 Torr. The HF RF power was ignited at 3 sec. of the processing time and held at a power of 1.23 W/cm2 until 45 seconds of processing time. After pre-cleaning the substrate with % plasma, the H2 stream and plasma power were turned off and b2h6 was introduced into the processing chamber as a mixture with argon 153514.doc -48·201138024. The concentration of b2h6 in the mixture was about 5% by volume, and the mixture was introduced at a flow rate of about 3600 seem in conjunction with N2 introduced at a flow rate of 2400 seem. The gas was allowed to flow for 45 seconds from the treatment time to 85 seconds during which the source layer containing BHX was deposited on the substrate. The deposition was carried out at a temperature of about 350 ° C and at a pressure of about 2.3 Torr. The thickness of the source layer deposited on top of the copper is estimated to be about 215 A, while the thickness of the source layer deposited on top of the dielectric is estimated to be about 159 A. The shed stream is stopped after the source BHX layer has been deposited, and the layer is purified to form (BNH)X. Passivation is performed between 85 seconds and 90 seconds of processing time and involves introducing NH3 at a flow rate of about 7000 seem along with N2 at a flow rate of 2800 seem. The HF component having a power level of 〇8 〇 w/cm 2 and a MF component having a power level of 〇·37 W/cm 2 were ignited, and the plasma was maintained from 90 seconds to 96 seconds. Passivation was carried out at a temperature of about 350 C and a pressure of about 2.3 Torr. It is estimated that the entire thickness of the BHX layer residing on the dielectric is converted to (BNH)X, and about 25% of the thickness of the source layer residing on the copper is converted to (BNH)X. Later, the (BNH) X layer was analyzed by FT IR spectroscopy. The bee values at 3430 cm·1 (υΝ_Η), 2560 cm·1 (υΒ_Η), and 1375 cm 1 (υβ-Ν) were observed on the IR light. Boron is allowed to diffuse into the copper wire to form a cap layer doped with boron. It should be understood that boron diffusion can occur before and after the top portion of the source layer has been nitrided (passivated). It is estimated that the boron-doped lid residing in the copper wire has a thickness of about 25 Α to 75 A. The entire cap process is performed in a single stage at a temperature of 350 °C. Subsequently, using a tetradecyl decane, ammonia and nitrogen as a 153514.doc -49·201138024 chemistry gas at 350 ° C in a plasma deposition of a SixCyNz diffusion barrier layer on the substrate in three different stages of the PECVD apparatus (about 500 Α) β deposits one third of the thickness of the carbide layer in each of the three stages. Use a four-point bending adhesion test to measure with and without a boron-containing cover

Cu (5’〇〇〇 A)-SixCyNz (500 Α)失層之黏著能量。與對於不 具有摻雜有B的蓋的習知夾層結構獲得之僅15 3 J/m2之黏 著此·量相比，在藉由上述方法獲得之夾層中觀察到μ.4 &quot;m2之較高黏著能量。已知改進之黏著通常與改進之電遷 移效能有關。 亦針對含有摻雜有硼之保護蓋及（BNH)χ鈍化層之結構量 測洩漏電流及飽和電容。觀察到此等參數實質上不受所描 述之罩蓋程序影響。 雖然為了清晰起見省略了各種細節，但可實施各種替代 設計方案。因此，當前之實例應被視為說明性的而非限制 性的，且本發明不限於本文中給出之細節，而是可在所附 申凊專利範圍之範嗜内加以修改。 【圖式簡單說明】 圖lA-縣*在鋼雙鑲嵌製造製程期間創造之器件 之橫截面圖； ° 圖2A-2C展示說明保護蓋之部分製造之器件結構的橫截 面圖； 程：3A呈現根據一些實施例之蓋形成製程之—實例製程流 圖3B呈現根據-些實施例之蓋形成製程之另—實例製程 153514.doc •50· 201138024 流程圖； 圖4A-4E展示根據〆些實施例之在罩蓋層形成期間創造 之器件結構的橫截面圖； 圖5為根據本發明之一些實施例的能夠使用可用於形成 罩蓋層之低頻（LF)及高頻（HF)射頻電漿源之PECVD裝置的 示意表示； 圖6為根據本發明之一些實施例的適合於形成罩蓋層之 多台裝置之一個實例的示意表示；及 圖7為根據本發明之一些實施例的適合於形成罩蓋層之 多台裝置之另一實例的示意表示。 【主要元件符號說明】 100 1C結構 103 介電層 105 部分導電金屬擴散障壁 107 銅導電路線/金屬線 108 保護蓋 109 鈍化層/界面膜/界面層 111 第一介電層 113 #刻終止膜 115 第二介電層 117 CMP終止膜 119 介層孔 121 溝槽 123 金屬擴散障壁 153514.doc •51- 201138024 124 銅導電路線 125 銅導電路線 201 層間介電質/1] 203 擴散障壁材料 205 銅或銅合金/命 207 薄保護蓋 208 層 209 鈍化層 211 擴散障壁層 401 介電層 405 銅層 407 保護蓋 408 源層 409 鈍化層 411 碳化矽層 500 反應器 502 高頻RF產生器 504 低頻RF產生器 506 匹配網路 508 歧管 510 源氣體管線 512 入口 514 簇射頭 516 基板 ·52· 153514.doc 201138024 518 晶圓台座 520 接地加熱器塊 522 出口 524 處理腔室 526 真空泵 601 裝置腔室 603 台 605 台 607 台 609 台 611 分度板 613 控制器單元 617 退出承載室 619 進入承載室 701 多台裝置 703 台 705 台 707 台 709 台 711 台 713 台 715 腔室 717 腔室 719 腔室 153514.doc -53- 201138024 721 723 腔室 控制器 153514.doc -54-Cu (5'〇〇〇 A)-SixCyNz (500 Α) lost adhesion energy. Compared with the adhesion of only 15 3 J/m2 obtained for a conventional sandwich structure without a cap doped with B, a comparison of μ.4 &quot;m2 is observed in the interlayer obtained by the above method. High adhesion energy. Improved adhesion is known to be associated with improved electromigration performance. The leakage current and saturation capacitance are also measured for structures containing a boron-doped protective cap and a (BNH) germanium passivation layer. It is observed that these parameters are substantially unaffected by the described capping procedure. Although various details have been omitted for clarity, various alternative designs can be implemented. Therefore, the present examples are to be considered as illustrative and not restrictive, and the invention is not limited to the details given herein, but may be modified within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1A-Cross-sectional view of a device created during a steel dual damascene manufacturing process; ° Figure 2A-2C shows a cross-sectional view of a device structure partially fabricated by a protective cover; </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; A cross-sectional view of a device structure created during formation of a cap layer; FIG. 5 is a low frequency (LF) and high frequency (HF) radio frequency plasma source that can be used to form a cap layer in accordance with some embodiments of the present invention. Figure 6 is a schematic representation of one example of a plurality of devices suitable for forming a cap layer in accordance with some embodiments of the present invention; and Figure 7 is suitable for formation in accordance with some embodiments of the present invention. A schematic representation of another example of multiple devices of the cover layer. [Main component symbol description] 100 1C structure 103 dielectric layer 105 partial conductive metal diffusion barrier 107 copper conductive route / metal line 108 protective cover 109 passivation layer / interface film / interface layer 111 first dielectric layer 113 #刻止膜膜115 Second dielectric layer 117 CMP termination film 119 via hole 121 trench 123 metal diffusion barrier 153514.doc • 51- 201138024 124 copper conductive route 125 copper conductive route 201 interlayer dielectric / 1] 203 diffusion barrier material 205 copper or Copper Alloy/Life 207 Thin Protective Cover 208 Layer 209 Passivation Layer 211 Diffusion Barrier Layer 401 Dielectric Layer 405 Copper Layer 407 Protective Cover 408 Source Layer 409 Passivation Layer 411 Tantalum Carbide Layer 500 Reactor 502 High Frequency RF Generator 504 Low Frequency RF Generation 506 matching network 508 manifold 510 source gas line 512 inlet 514 shower head 516 substrate · 52 · 153514.doc 201138024 518 wafer pedestal 520 grounding heater block 522 outlet 524 processing chamber 526 vacuum pump 601 device chamber 603 605 units 607 units 609 units 611 index boards 613 controller unit 617 exits the load compartment 619 into the load compartment 701 Multiple devices 703 705 707 709 711 713 715 chamber 717 chamber 719 chamber 153514.doc -53- 201138024 721 723 chamber controller 153514.doc -54-

Claims (1)

201138024 七、申請專利範圍： 1. 一種用於形成一半導體器件結構之方法，該方法包含： (a) 在至少約350°C之一基板溫度下使具有一暴露之無 氧化物的銅或銅合金區及—暴露之介電質區的一基板與 一包含鋁之化合物接觸，以在該介電質及該銅或銅合金 層兩者上形成一包含鋁之第一層； (b) 以化學方法對該第一層之至少一部分進行改質以形 成一包含鋁之鈍化層；及 0)在該鈍化層上沈積一介電層。 2. 如請求項1之方法，其中在（a)之前，清潔該基板表面以 自銅或銅合金之表面完全移除氧化銅。 3. 如靖求項2之方法，其中該清潔選自由以下各項組成之 群組：直接電襞處理、遠端電漿處理、uv處理，以及在 包含N2、NH3及Η2中之至少一者的氣體中之熱處理。 4. 如請求項1之方法，其中（a)包含在無電漿的情況下使該 基板與一有機鋁化合物接觸。 5. 如請求項4之方法，其中（a)包含在至少約4〇〇〇c之一基板 溫度下使該基板與一有機鋁化合物接觸。 6. 如請求項2之方法，其中該有機鋁化合物為三甲基鋁。 7. 如請求項1之方法’其中（b)包含在不允許鋁大量擴散至 該銅中的情況下使駐留於該銅或銅合金上之該第一層實 質上完全鈍化。 8. 如凊求項1之方法，其中（b)包含在允許鋁部分擴散至該 鋼中的情況下使駐留於該銅或銅合金上之該第一層部分 153514.doc 201138024 鈍化。 9. 10, 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 如4求項1之方法’其中在（b)中形成該純化層包含形成 一包含A1-N鍵之實質上固定的化合物。 如請求項9之方法’其中⑻包含用一含氮試劑處理該基 板其中該處理選自由以下各項組成之群組：直接電漿 處理、遠端電漿處理、。乂處理及熱處理。 如凊求項10之方法，其中(b)包含在無電漿的情況下用一 含氮試劑處理該基板。 如請求項11之方法，其中該介電質為一ULK介電質。 如凊求項1之方法’其中在(b)中形成該鈍化層包含形成 一包含A1-0鍵之實質上固定的化合物。 如請求項13之方法，其中(b)包含用一含氧試劑處理該基 板其中該處理選自由以下各項組成之群組：直接電漿 處理、遠端電漿處理、uv處理及熱處理。 如》月求項13之方法’其中⑻包含在無電漿的情況下使該 基板與一含氧試劑接觸。 如》青求項15之方法，其中該介電質為―介電質。 如請求項13之方法，其中⑻包含用選自由〇2、N2〇、 及〇3組成之群組的一含氧試劑來處理該基板。 如叫求項1之方法，其中在一化學氣相沈積（CVD)裝置中 執行（a)、（b)及（c)。 如凊求項1之方法，其中在⑷中沈積之該介電層為一蝕 刻終止介電層。 如凊求項19之方法’其中該蝕刻終止介電層包含選自由 153514.doc 201138024 氮化矽及碳化矽組成之群組的經摻雜或未經摻雜材料。 21.如請求項丨之方法，其中在（c)中沈積之該介電層為直接 沈積至該鈍化層上之一層間介電質（ILD)，。 • 22· —種用於形成一半導體器件結構之裝置，該裝置包含： (a) —處理腔室，該處理腔室具有一用於引入氣態或揮 發性之含金屬反應物的入口； (b) 圓支稽'件’該晶圓支撐件用於在該處理腔室中 在晶圓基板上沈積一含金屬層期間將該晶圓固持於者 位置；及 胃 (c) 一控制器，該控制器包含用於以下操作之程式指 令： (i)處理一具有暴露之銅或銅合金及暴露之介電質的 基板’以自該暴露之銅或銅合金移除氧化物； (Π)在至少約350°C之一基板溫度下使具有一暴露之 無氧化物的銅或銅合金區及一暴露之介電質區的該基板 與一含鋁反應物接觸，以在該介電質及該第一金屬兩者 上形成一包含鋁之第一層；及 (iii)以化學方法對該第一層之至少一部分進行改質 - 以形成一包含铭之純化層。 23.如請求項22之裝置，其中該控制器程式指令（ii)指定在無 電漿的情況下使該基板與該含鋁反應物接觸。 153514.doc201138024 VII. Patent Application Range: 1. A method for forming a semiconductor device structure, the method comprising: (a) rendering an exposed oxide-free copper or copper at a substrate temperature of at least about 350 °C An alloy region and a substrate of the exposed dielectric region are in contact with a compound comprising aluminum to form a first layer comprising aluminum on both the dielectric and the copper or copper alloy layer; (b) Chemically modifying at least a portion of the first layer to form a passivation layer comprising aluminum; and 0) depositing a dielectric layer on the passivation layer. 2. The method of claim 1, wherein prior to (a), cleaning the surface of the substrate to completely remove copper oxide from the surface of the copper or copper alloy. 3. The method of claim 2, wherein the cleaning is selected from the group consisting of direct electrolysis treatment, remote plasma treatment, uv treatment, and at least one of including N2, NH3, and Η2 Heat treatment in the gas. 4. The method of claim 1, wherein (a) comprises contacting the substrate with an organoaluminum compound without plasma. 5. The method of claim 4, wherein (a) comprises contacting the substrate with an organoaluminum compound at a substrate temperature of at least about 4 〇〇〇c. 6. The method of claim 2, wherein the organoaluminum compound is trimethylaluminum. 7. The method of claim 1 wherein (b) comprises substantially completely passivating the first layer residing on the copper or copper alloy without allowing a large amount of aluminum to diffuse into the copper. 8. The method of claim 1, wherein (b) comprises passivating the first layer portion 153514.doc 201138024 residing on the copper or copper alloy while allowing the aluminum portion to diffuse into the steel. 9. 10, 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. The method of claim 1 wherein the formation of the purification layer in (b) comprises forming an A1-N-containing bond A substantially fixed compound. The method of claim 9 wherein (8) comprises treating the substrate with a nitrogen-containing reagent, wherein the treatment is selected from the group consisting of direct plasma treatment, remote plasma treatment, .乂 treatment and heat treatment. The method of claim 10, wherein (b) comprises treating the substrate with a nitrogen-containing reagent without plasma. The method of claim 11, wherein the dielectric is a ULK dielectric. The method of claim 1 wherein the forming the passivation layer in (b) comprises forming a substantially immobilized compound comprising an A1-0 bond. The method of claim 13, wherein (b) comprises treating the substrate with an oxygen-containing reagent, wherein the treatment is selected from the group consisting of direct plasma treatment, remote plasma treatment, uv treatment, and heat treatment. For example, the method of the above-mentioned item 13 wherein (8) comprises contacting the substrate with an oxygen-containing reagent in the absence of plasma. The method of claim 15, wherein the dielectric is a dielectric. The method of claim 13, wherein (8) comprises treating the substrate with an oxygen-containing reagent selected from the group consisting of 〇2, N2〇, and 〇3. The method of claim 1, wherein (a), (b) and (c) are performed in a chemical vapor deposition (CVD) apparatus. The method of claim 1, wherein the dielectric layer deposited in (4) is an etch stop dielectric layer. The method of claim 19 wherein the etch stop dielectric layer comprises a doped or undoped material selected from the group consisting of 153514.doc 201138024 tantalum nitride and tantalum carbide. 21. The method of claim 1, wherein the dielectric layer deposited in (c) is an inter-layer dielectric (ILD) deposited directly onto the passivation layer. • A device for forming a semiconductor device structure, the device comprising: (a) a processing chamber having an inlet for introducing a gaseous or volatile metal-containing reactant; a wafer support member for holding the wafer in a position during deposition of a metal containing layer on the wafer substrate in the processing chamber; and a stomach (c) a controller, the controller The controller includes program instructions for: (i) processing a substrate having exposed copper or copper alloy and exposed dielectric to remove oxides from the exposed copper or copper alloy; Contacting the substrate with an exposed oxide-free copper or copper alloy region and an exposed dielectric region with an aluminum-containing reactant at a substrate temperature of at least about 350 ° C for contacting the dielectric and Forming a first layer comprising aluminum on both of the first metal; and (iii) chemically modifying at least a portion of the first layer to form a purification layer comprising the inscription. 23. The device of claim 22, wherein the controller program instruction (ii) specifies contacting the substrate with the aluminum-containing reactant without plasma. 153514.doc
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