201133351 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體製造’特別是有關於半導體製 造的晶片認證方法。 【先前技術】 隨著客戶需求的不斷改變，積體電路(ic)設計（或製造） 公司與客戶間的往來日益頻繁，晶片認證的重要性也與日 倶增。晶片認證(die identification)用以確保晶片能夠正確 且安全地在1C設計（製造）公司和客戶間被傳送。 目前已經有數種習知的技術方案可用於晶片認證。第 1圖是習知之晶片認證方法的流程圖。如第1圖所示，這 種習知方法是用於晶圓的最終測試(Final Test，FT)階段， 本方法首先產生隨機的亂數(random number)，然後將產生 的亂數以一次性寫入(one-time program，0TP)的方式寫入 晶片，以進行晶片認證的後續流程。然而，這種方法僅確 保相鄰的兩個亂數不重複，所以僅能確保相鄰的兩個晶片 是不同的。 第2圖是另一種習知之晶片認證方法的流程圖。如第 2圖所示，這種方法也是用於最終測試階段，首先，本方 法由客戶提供驗證設備，而該驗證設備產生唯一碼，然後 將產生的唯一碼以一次性寫入的方式寫入晶片，以進行晶 片認證的後續流程。除了客戶本身之外，他人對客戶提供 的驗證設備一無所悉（如產生唯一碼的方法），所以這種方 法又稱為『黑盒子式』技術方案(Black Box Solution))。然 0810-A34563TWF AU2009059 4 201133351 而黑盒子式技術方案僅能使用單一機台進行量產，無法使 用多台機台進行大量量產，因此生產週期聘間（cycle time) 增加。此外，因為需要外的驗證設備，這種方法也會增 加生產的成本。 因此，需要一種低成本的晶片認證方法其能夠產生 不重覆且安全的密碼（code)以進行晶片認證。 【發明内容】 ' φ 本發明之一實施例提供一種產生晶片認證碼之方 法，包括：提取第一晶片所屬的第一晶圓批次號碼；提取 第一晶片於第一晶圓的第一晶片座標；以及根據第一晶片 所屬第一晶圓批次號碼和第一晶片座標產生第一唯一碼。 本發明之另一實施例提供一種晶片認證方法，包括： 產生第一晶片的第一唯一碼，其中第一唯一碼係由第一晶 片所屬的第一晶圓批次號碼和第一晶片於第一晶圓的第一 晶片座標組合而得；將第一唯一碼寫入第一晶片；根據第 • 一唯一碼，對第一晶片進行晶片認證，其中，當已寫入上 述第一晶片的第一唯一碼符合寫入前的第一唯一碼，則通 過認證；反之當已寫入上述第一.晶片的第一唯一碼不符合 寫入前的第一唯一碼，則不會通過認證。 本發明另一實施例提供一種晶片認證系統，用於前段 測試，包括：自動化參數測試裝置、序號產生裝置、加密 裝置，以及驗證裝置。自動化參數測試裝置，用以進行複 數晶片的分類測試。序號產生裝置，用以產生晶片之第一 晶片的第一序號。加密裝置，用以將第一序號加密為第一 0810-A34563TWF AH2009059 5 201133351 唯一碼。驗證裝置，用以根據第一唯一碼，對第一晶片進 行晶片認證。 本發明另一實施例提供一種採用計算機程序執行晶 片認證的方法，包括：使用自動化參數測試裝置進行複數 晶片的分類測試；使用序號產生裝置分別產生上述晶片之 第一晶片的第一序號；以及使用驗證裝置根據第一序號， 對第一晶片進行晶片認證。 【實施方式】 為了讓本發明上述和其他目的更清晰易懂，特列舉較 佳實施例，搭配所附圖示，作詳細說明如下： 第3A圖為本發明一實施例之晶片認證方法的流程 圖。在本實施例中，晶片認證方法始於步驟S30a，其中進 行複數晶片的分類測試，用以根據既定的分類標準將晶片 加以分類。在一實施例中，分類測試包括直流測試(如電性 連續性測試、開（短）路電流和漏電流測試），以及/或數位和 類比功能測試，但不以此為限。為了讓1C製造公司、1C 設計公司和客戶能夠持續地追蹤使用的晶片及其功能，所 以本實施例之晶片認證方法是用於晶圓的前段測試階段。 在其他實施例中，本發明的晶片認證方法亦可用於晶圓的 最終測試階段。在晶片的分類測試後，流程接著前進至步 驟S31 a，用以產生第一晶片的第一唯一碼unicode_# 1。步 驟S31a詳述如下。 第4圖為說明第3A圖之步驟S311a的示意圖，其用 以詳細說明本實施例產生第一唯一碼的方法。第4圖顯示 0810-A34563TWF AH2009059 6 201133351 一個晶圓40，晶圓40具有已分類測試的複數晶片，其中 每一個晶片會以一個二位碼數字（binary number)來代表其 分類測試的結果，例如Bin 1、Bin 9或Bin 10。舉例而言， Bin 1表示晶片是通過的（pass/good) ’而Bin 7和Bin 9分 別表示沒有通過漏電流測試和沒有通過開（短）路電流測試 的’所以標示為Bin 7和Bin 9的晶片是未通過的 (fail/bad)。由晶圓40總結出的二位碼數字可顯示出分類測 試的結果，如在分類測試的特定項目中有多少晶片是（未） • 通過的。當全數晶片均完成分類測試後，便可以得知晶圓 40的良率，在本實施例中，晶圓40的良率(yield)為86.23 ; 此外’晶圓40的晶圓批次號碼(Lot ID)為。 在本實施例中，第一晶片40a的第一序號serial_# 1係 根據第一晶片40a所屬的晶圓批次號碼和第一晶片40a的 晶片座標而決定。舉例而言’第一晶片40a的第一序號 serial_#l係將第一晶片40a所屬的第一晶圓批次號碼 W卯Μ㈨i和第一晶片40a的第一晶片座標（〇8,07)組合而 • 得。以數學式表示如下： serial—#1=62801800 JQSQ7 在本實施例中，第一晶圓批次號碼和第一晶片座標分 別為9位元和4位元的數字，且第一晶圓批次號碼和第一 晶片座標分別作為最大有效位元組（m〇st significant bytes，MSB)和最小有效位元組（ieast signmcant bytes， LSB)。 在其他實施例中，第一晶圓批次號碼和第一晶片座標 分別能夠是其他位元值（如8位元和6位元）的數字，且第 0810-A34563TWF_Ali2009059 201133351 一晶圓批次號碼和第一晶片座標分別作為最小有效位元組 和最大有效位元組。 接著流程前進至步驟S312a，其中將第一序號加密為 第一唯一碼。在本實施例中，第一序號serial_# 1藉由資料 加密標準（Data Encryption Standard，DES)方式而被加密為 第一唯一碼unicode_#l，但並非以此為限；其它的密碼技 術，例如 3DES(Triple DES)、AES(Advanced DES)或 RSA(Rivest-Shamir_Adleman Encryption)等密碼技術亦可 用於本實施例。步驟S312a詳述如下。 參考第5圖，其係用以說明本實施例之序號加解密流 程的示意圖。如第5圖所示，1C設計（製造）公司將第一序 號serial_# 1以DES方式加密為第一唯一碼unicode_# 1。具 體而言，DES密碼技術藉由5位元的加密金錄(Encryption key)將13位元的明文(Plain text)(即第一序號serial__#l)加 密成為13位元的秘文（Cipher text)(即第一唯一碼 unique_#l ’ 且在此實施例中 unique_#l 等同 unicode_#l)， 其中留下8位元作同位檢查(parity check)。接著，藉由5 位元的解密金鑰(Decryption key)將經過DES加密的第一唯 一碼unicode_#l解密成為原先的第一序號Serial_# 1。DES 加密的步驟對應於步驟S312a，而DES解密的步驟對應於 步驟S34c(於第6圖詳述）。在其他實施例中，第一序號 serialJ1能夠擴充至64位元，且加密金鑰和解密金鑰均為 54位元，而留下8位元作為同位檢查。由於DES密碼技術 的特性’所以在本實施例中，加密金錄和解密金鑰是相同 的’並且由1C設計公司所指派。藉此方式，本發明能夠確 0810-A34563TWF_AH2009059 8 201133351 保晶片的序號的安全性。在其他實施例中，由於使用不同 的密碼技術（如RSA密碼技術），加密金鑰和解密金錄是不 同且/或由客戶指派的。 在本實施例中，第一晶片40a和第二晶片40b屬於相 同的晶圓.40 ’所以兩者的晶圓批次號瑪相同（均為 <52洲7洲07)，但兩者的晶片座標不同。由於第一晶片40a 的晶片座標與其他晶片的晶片座標不同5所以第一晶片40a 的第一序號serial_#l與其他晶片的第一序號不同，第一唯 參 一碼unicode_# 1與其他晶片的第一唯一碼因而不同。在其 他實施例中，第一晶片40a和第二晶片40b分別屬於不同 的晶.圓’由於兩者的晶圓批次5虎碼不同’所.以兩者的弟'~~ 序號和第一唯一碼不同。藉此方式，本發明能夠確保任意 兩個晶片的序號不重複。 接著流程前進至步驟S33a，用以將第一唯一碼寫入第 -一晶片。在本實施例中，第一唯·'—碼unicode_# 1是以OTP 方式寫入第一晶片40a。在其他實施例中，第一唯一碼 春 unique_#l是以RSA方式寫入第一晶片40a。 接著流程前進至步驟S34a，用以根據第一唯一碼進行 晶片認證。在本實施例中，其中判斷已寫入第一晶片40a 的第一唯一碼unicode_# 1’是否符合寫入前的第一唯一碼 unicode_#l，具體而言，當已寫入第一晶片40a的第一唯一 碼unicode_#l’符合寫入前的第一唯一碼unicode_#l時，第 一晶片40a通過認證；反之當已寫入第一晶片40a的第一 唯一碼unicode_#l’不符合寫入前的第一唯一碼unicode_#l 時，第一晶片40a不會通過認證。在其他實施例中，第一 0810-A34563TWT AH2009059 9 201133351 = j,接著由ic攻計（製造）公司被傳送到客戶端以進行 最終測試’請參考稍後第6圖的說明。 要/意的疋，根據對安全性的不同需求，在晶片認證 =程序中’將第—序號serial_#l加解密的步驟（步驟S312a) 疋可任選的。具體而言，請參考帛3b圖，帛圖的各個 步驟類似於第3A圖的相應步驟，不再贅述。然而，第3B 圖中並不包括第一唯_碼unic〇de—W的加密步驟(例如第 3A圖的步驟S312a)，因此也不需要相應的解密步驟(例如 第6圖的步驟S34c)。舉例而言，當客戶認為晶片的安全性 等級点夠被降低時，其可以在產生第一序號抓㈤一 #1之 後’直接將第一序號serial_#1當作第一唯一碼unic〇de_#1 寫入第一晶片40a，而不進行第一序號serial_#1的加密步 驟；並且在最終測試的階段，便不需要進行相應的解密步 驟。藉由這種方式，能夠使安全性等級較低的晶片能夠快 速地送交客戶端，以減少生產週期。 接著，進入晶片認證的最終測試階段。如第6圖所示， 在步驟S35a’當客戶需要對第一晶片40a進行晶片認證 時，以OTP方式讀出已寫入第—晶片40a的第一唯一碼 Unicode #1 ° 接著流程前進至步驟S35b，其中藉由一解密金錄 (Decryption key)，將從第一晶片40a讀出的第一唯一碼 unicode_#l’解密為第二序號seriai_#2。如前述，在本實施 例中’加密金錄和解密金錄是相同的，並且由1C設計公司 所指派。 接著流程前進至步驟S35c，用以判斷第二序號 0810-A34563TWF一Α1Ϊ2009059 】〇 201133351 serial_#2是否符合第一序號serial_#；[。若第二序號serial_#2 符合第一序號serial一#1，則進入步驟S35d ;若第二序號 serial_#2不符合第一序號serial—#卜則進入步驟S35e，判 定此第一晶片認證失敗。為了簡化說明，本文並未對DES 和OTP的密碼技術進行詳細說明，如有需要，可以參考密 碼學相關書籍。 第7圖為本發明一實施例之晶片認證系統的示意圖。 第7圖顯示一個晶片認證系統7 0，包括自動化參數測試系 • 統71、序號產生裝置72、加密裝置73，以及驗證裝置74。 在其他實施例中，本發明的晶片認證系統70亦可用於晶圓 的最終測試階段。 自動化參數測試系統(automated test system)71輕接於 序號產生裝置72。自動化參數測試系統71是一種自動化 測試系統’用以執行複數晶片的分類測試，例如直流測試 (如電性連續性測試、開（短）路電流和漏電流測試），以及/ 或數位和類比功能測試，但不以此為限。自動化參數測試 _ 系統71包括探針卡介面（pr〇be card interface)、晶圓定位裝 置(wafer positioning device)、參數測試裝置(parameter test device)和/或作為伺服器的計算機，但並非以此為限。 在自動化參數測試系統71完成複數晶片的分類測試 後，序號產生裝置72產生第一晶片40a的第一序號 serial_#l。在本實施例中，第一晶片40a的第一序號 serial_#l係根據第一晶片40a所屬的晶圓批次號碼和第一 晶片40a的晶片座標而決定。舉例而言，第一晶片40a的 第一序號serial_#l係將第一晶片40a所屬的晶圓批次號碼 0810-A34563TWF AH2009059 11 201133351 和第一晶片40a的晶片座標組合而得，如步驟S31 la所述。 加密裝置73耦接於序號產生裝置72和驗證裝置74 間，用以將第一序號serial_#l加密為第一唯一碼。具體而 言，加密裝置73以DES方式將第一晶片40a的第一序號 serial_# 1加密為第一唯一碼unicode_# 1，如步驟S312a所 述。 驗證裝置74的密碼寫入暨判斷裝置74a以OTP方式 將第一唯一碼unicode_#l寫入第一晶片40a，並且判斷已 寫入第一晶片40a的第一唯一碼是否符合寫入前的第一唯 一碼unicode_#l，如步驟S34a所述。 當需要對第一晶片40a進行晶片認證時，密碼讀出裝 置74b以OTP方式讀出已寫入第一晶片40a的第一唯一碼 unicode_#l。要注意的是，在第7圖中，雖然密碼讀出裝 置74b與密碼寫入暨判斷裝置7.4a是位於同一處；然而， 密碼讀出裝置74b可位於別處。換言之，在本實施例中， 密碼寫入暨判斷裝置74a是位於1C設計（製造）公司之處， 而密碼讀出裝置74b是位於客戶之處，但並非以此為限。 具體而言，當客戶取得第一晶片40a且需要對其進行晶片 認證時，客戶使用密碼讀出裝置74b，以OTP方式讀出已 寫入第一晶片40a的第一唯一碼unicode_#l，如步驟S34a 所述。 解密暨判斷裝置74c耦接於密碼讀出裝置74b，並藉 由一解密金鑰，將從第一晶片40a讀出的第一唯一碼 imicode_#l解密為第二序號serial_#2，並且判斷第二序號 serial_#2是否符合第一序號serial_#l，如步驟S34c和S34d 0810-A34563TWF AIi2009059 12 201133351 所述。類似於密碼讀出裝置74b，在本實施例中，解密裝 置74c也是位於客戶端，但並非以此為限。 以下說明本發明之晶片認證方法的另一實施例。不同 於前述晶月認證方法的實施例，本實施例係取得每一晶片 的序號以進行後續的晶片認證。在本實施例中，晶片認證 方法包括對複數晶片的分類測試，其中根據既定的分類標 準將晶片加以分類，如步驟S30a和S30b所述。接著，取 得每一晶片的序號，如步驟S311a所述。然後，將每一晶 • 片的序號加密為唯一碼，如步驟S312a所述。在本實施例 中，序號藉由資料加密標準(DES)方式而被加密為唯一碼， 如步驟S312a所述，但並非以此為限，其它的密碼技術， 例如3DES、AES或RSA等亦可用於本實施例。接著，將 這些唯一碼寫入對應之晶片中。在本實施例中，唯一碼是 以OTP方式（或RSA方式等）寫入晶片，如步驟S33a所述。 接著流程前進至步驟S34a，其中根據這些唯一碼進行 晶片認證。在本實施例中，其中判斷每一晶片的唯一碼是 • 否符合每一晶片在寫入前的唯一碼。在其他實施例中，每 一晶片接著由1C設計（製造）公司被傳送到客戶端以進行最 終測試’請蒼考第6圖。 如第6圖所示，最終測試始於步驟S35a，當客戶需要 對每一晶片進行晶片認證時，以OTP方式讀出已寫入每一 晶片的唯一碼。 接著流程前進至步驟S35b，用以藉由一解密金鑰，將 從每一晶片讀:出的唯一碼解密為對應的序號。如前述，在 本實施例中，加密金鑰和解密金鑰是相同的，並且由1C設 0810-A34563TWF AU2009059 13 201133351 計公司所指派。 接著流程前進至步驟S35c，用以判斷解密後之對應的 序號是否符合每一晶片之加密前的序號。若解密後之對應 的序號符合每一晶片之加密前的序號，則進入步驟S35d ; 若解密後之對應的序號是否符合每一晶片之加密前的序 號，則進入步驟S35e，判定此晶片認證失敗。 由於第一序號是根據第一晶片所屬的晶圓批次號碼 和第一晶片於第一晶圓的第一晶片座標而決定，所以第一 序號是唯一的（unique)。由於第一序號由DES密碼技術所 保護，所以能夠確保加密後之第一序號的安全性。此外， 本發明的晶片認證系統能夠設置在許多機台中，以進行大 規模量產，進而減少生產週期時間。 雖然本發明已由較佳實施例揭露如上，但並非用以限 制本發明。在不脫離本發明精神和範疇的前提下，本領域 熟習技藝者當能作些許更動。換言之，本發明所列舉之實 施例雖然僅包括一個晶圓上的一個晶片（如晶圓40上的第 一晶片40a)，但本領域熟習技藝者當能將其推廣應用至相 同（或不同）晶圓上的複數晶片。此外，本發明應用不限於 特定兩實體間（例如本發明實施例之1C設計（製造)與客戶 間），其他可能需要進行晶片認證的產品（例如憑證管理機 構(certificate authority，CA)所使用的認證卡或1C卡、行 動電話、數位機上盒(set-top box，STB))，當視其需要實施 本發明。上述步驟的組合能夠以多種組合依序或同時地完 成，並且沒有任何特定步驟係關鍵和/或必須的。並且’關 於實施例所描述的特徵和說明能夠其他實施例所描述的特 0810-A34563TWF Α1Ϊ2009059 14 201133351 徵和說明互相結合。因此，本發明的範疇涵括上述變型。 【圖式簡單說明】 本發明可藉由上述實施方式並搭配所附圖示而被較 佳地理解； 第1圖是習知之晶片認證方法的流程圖； 第2圖是另一種習知之晶片認證方法的流程圖； 第3A圖為本發明一實施例之晶片認證方法的流程 • 圖，其中包括加密的步驟； 第3B圖為本發明一實施例之晶片認證方法的流程 圖，其中不包括加密的步驟； 第4圖為第3A圖與第3B圖之步驟S31a和S31b的示 意圖，其用以說明本發明一實施例產生第一唯一碼的方法； 第5圖為一示意圖，用以說明本發明一實施例之第一 序號的加解密流程； 第6圖為本發明一實施例之晶片認證方法的流程圖， • 用以說明本發明晶片認證方法在最終測試時的詳細步驟； 第7圖為本發明一實施例之晶片認證系統的示意圖。 【主要元件符號說明】 70〜晶片認證糸統； 71〜自動化參數測試系統； 72〜序號產生裝置； 73〜加密裝置； 74〜驗證裝置； 0810-A34563TWF AH2009059 15 201133351 74a〜密碼寫入暨判斷裝置； 74b〜密碼讀出裝置； 74c〜解密暨判斷裝置； .40〜晶圓， 40a〜第一晶片； 40b〜第二晶片；： serial_#l〜第一序號； unicode_#l~第一唯一碼； serial_#2〜第二序號； unique—# 1 ~ 第一·唯一石馬0 0810-A34563TWF ΑΠ2009059 16201133351 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to semiconductor manufacturing, particularly to wafer authentication methods related to semiconductor fabrication. [Prior Art] As the needs of customers continue to change, the integration of integrated circuit (ic) design (or manufacturing) companies with customers has become increasingly frequent, and the importance of wafer certification has also increased. Die identification is used to ensure that the wafer is properly and safely transferred between the 1C design (manufacturing) company and the customer. There are several conventional technical solutions available for wafer certification. Figure 1 is a flow chart of a conventional wafer authentication method. As shown in Fig. 1, this conventional method is used in the final test (Final Test, FT) stage of the wafer. The method first generates a random random number, and then the generated random number is once Write to the wafer in a one-time program (0TP) for subsequent processing of wafer authentication. However, this method only ensures that the two adjacent random numbers are not repeated, so only the two adjacent wafers are guaranteed to be different. Figure 2 is a flow chart of another conventional wafer authentication method. As shown in Figure 2, this method is also used in the final test phase. First, the method provides the verification device by the client, and the verification device generates a unique code, and then writes the generated unique code in a write-once manner. Wafer for subsequent processing of wafer certification. In addition to the customer itself, others have no knowledge of the verification device provided by the customer (such as the method of generating a unique code), so this method is also known as the "Black Box Solution". However, the black box type technology solution can only be mass-produced using a single machine, and it is not possible to use a large number of machines for mass production, so the cycle time of the production cycle is increased. In addition, this approach also increases the cost of production because of the need for external verification equipment. Therefore, there is a need for a low cost wafer authentication method that is capable of producing non-repeating and secure passwords for wafer authentication. SUMMARY OF THE INVENTION An embodiment of the present invention provides a method for generating a wafer authentication code, including: extracting a first wafer batch number to which the first wafer belongs; and extracting a first wafer on the first wafer of the first wafer a coordinate; and generating a first unique code based on the first wafer lot number and the first wafer coordinate to which the first wafer belongs. Another embodiment of the present invention provides a wafer authentication method, including: generating a first unique code of a first wafer, wherein the first unique code is the first wafer batch number and the first wafer to which the first wafer belongs a first wafer coordinate of a wafer is combined; writing a first unique code to the first wafer; performing wafer authentication on the first wafer according to the first unique code, wherein when the first wafer is written If the unique code conforms to the first unique code before writing, the authentication is passed; otherwise, when the first unique code that has been written into the first chip does not meet the first unique code before the writing, the authentication will not pass. Another embodiment of the present invention provides a wafer authentication system for use in a front-end test, including: an automated parameter testing device, a serial number generating device, an encryption device, and a verification device. Automated parameter testing device for classification testing of complex wafers. A serial number generating device for generating a first serial number of the first wafer of the wafer. The encryption device is configured to encrypt the first serial number into the first 0810-A34563TWF AH2009059 5 201133351 unique code. And a verification device for performing wafer authentication on the first wafer according to the first unique code. Another embodiment of the present invention provides a method for performing wafer authentication using a computer program, comprising: performing a classification test of a plurality of wafers using an automated parameter testing device; generating a first serial number of the first wafer of the wafer by using a serial number generating device; and using The verification device performs wafer authentication on the first wafer according to the first serial number. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to make the above and other objects of the present invention more comprehensible, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 3A is a flowchart of a wafer authentication method according to an embodiment of the present invention. Figure. In the present embodiment, the wafer authentication method begins in step S30a, in which a classification test of a plurality of wafers is performed to classify wafers according to a predetermined classification standard. In one embodiment, the classification test includes DC tests (e.g., electrical continuity tests, open (short) current and leakage current tests), and/or digital and analog function tests, but is not limited thereto. In order to allow 1C manufacturing companies, 1C design companies, and customers to continuously track the wafers used and their functions, the wafer authentication method of this embodiment is for the front-end testing phase of the wafer. In other embodiments, the wafer authentication method of the present invention can also be used in the final testing phase of a wafer. After the classification test of the wafer, the flow then proceeds to step S31a to generate a first unique code unicode_#1 of the first wafer. Step S31a is described in detail below. Fig. 4 is a view for explaining step S311a of Fig. 3A for explaining in detail a method of generating the first unique code in the present embodiment. Figure 4 shows 0810-A34563TWF AH2009059 6 201133351 A wafer 40 having a plurality of wafers that have been classified for testing, each of which will represent the results of its classification test with a binary number, for example Bin 1, Bin 9 or Bin 10. For example, Bin 1 indicates that the wafer is pass/good' and Bin 7 and Bin 9 indicate that the leakage current test has not passed and the open (short) current test has not passed, so the labels are Bin 7 and Bin 9. The wafer is fail (fail/bad). The two-digit code number summarized by wafer 40 can show the results of the classification test, such as how many wafers in the particular item of the classification test are (not) • passed. After all the wafers have been classified and tested, the yield of the wafer 40 can be known. In this embodiment, the yield of the wafer 40 is 86.23; in addition, the wafer lot number of the wafer 40 ( Lot ID) is. In the present embodiment, the first serial number serial_# 1 of the first wafer 40a is determined based on the wafer lot number to which the first wafer 40a belongs and the wafer coordinates of the first wafer 40a. For example, the first serial number serial_#1 of the first wafer 40a combines the first wafer lot number W卯Μ(9)i to which the first wafer 40a belongs and the first wafer coordinate (〇8, 07) of the first wafer 40a. And • got it. The mathematical expression is as follows: serial—#1=62801800 JQSQ7 In this embodiment, the first wafer lot number and the first wafer coordinate are 9-bit and 4-bit numbers, respectively, and the first wafer batch The number and the first wafer coordinate are respectively regarded as the most significant byte (MSB) and the least significant byte (LSB). In other embodiments, the first wafer lot number and the first wafer coordinate can be numbers of other bit values (eg, 8-bit and 6-bit), respectively, and the 0810-A34563TWF_Ali2009059 201133351 wafer number And the first wafer coordinate as the least significant byte and the most significant byte respectively. The flow then proceeds to step S312a, in which the first serial number is encrypted as the first unique code. In this embodiment, the first serial number serial_#1 is encrypted by the Data Encryption Standard (DES) method to be the first unique code unicode_#l, but not limited thereto; other cryptographic techniques, for example, Cryptographic techniques such as 3DES (Triple DES), AES (Advanced DES) or RSA (Rivest-Shamir_Adleman Encryption) can also be used in this embodiment. Step S312a is described in detail below. Referring to Fig. 5, there is shown a schematic diagram for explaining the sequence number encryption and decryption process of this embodiment. As shown in Fig. 5, the 1C design (manufacturing) company encrypts the first serial number serial_#1 into the first unique code unicode_#1 in the DES mode. Specifically, the DES cryptography encrypts a 13-bit plain text (ie, the first serial number serial__#1) into a 13-bit secret (Cipher text) by a 5-bit Encryption key. (ie, the first unique code unique_#l ' and in this embodiment unique_#l is equivalent to unicode_#l), where 8 bits are left for parity check. Next, the DES-encrypted first unique code unicode_#1 is decrypted into the original first serial number Serial_#1 by a 5-bit decryption key. The step of DES encryption corresponds to step S312a, and the step of DES decryption corresponds to step S34c (detailed in Fig. 6). In other embodiments, the first serial number serialJ1 can be expanded to 64 bits, and both the encryption key and the decryption key are 54 bits, leaving 8 bits as a parity check. Due to the nature of the DES cryptography technique, in this embodiment, the cryptographic record and the decryption key are the same 'and assigned by the 1C Design Company. In this way, the present invention can confirm the security of the serial number of the wafer of 0810-A34563TWF_AH2009059 8 201133351. In other embodiments, the encryption key and the decryption record are different and/or assigned by the client due to the use of different cryptographic techniques (e.g., RSA cryptography). In this embodiment, the first wafer 40a and the second wafer 40b belong to the same wafer .40 'so the wafer lot numbers of the two are the same (both < 52 continents 7 continent 07), but both The wafer coordinates are different. Since the wafer coordinates of the first wafer 40a are different from the wafer coordinates of the other wafers, the first serial number serial_#1 of the first wafer 40a is different from the first serial number of the other wafers, and the first unique code unicode_#1 and other wafers The first unique code is thus different. In other embodiments, the first wafer 40a and the second wafer 40b belong to different crystals. The circle 'because the wafer batches of the two are different from each other', the two brothers'~~ serial number and first The unique code is different. In this way, the present invention can ensure that the serial numbers of any two wafers are not repeated. The flow then proceeds to step S33a for writing the first unique code to the first wafer. In the present embodiment, the first code unicode_# 1 is written in the OTP manner to the first wafer 40a. In other embodiments, the first unique code spring unique_#1 is written to the first wafer 40a in an RSA manner. The flow then proceeds to step S34a for wafer authentication based on the first unique code. In this embodiment, it is judged whether the first unique code unicode_#1' written to the first wafer 40a conforms to the first unique code unicode_#1 before writing, specifically, when the first wafer 40a has been written. When the first unique code unicode_#l' conforms to the first unique code unicode_#1 before writing, the first wafer 40a passes the authentication; otherwise, when the first unique code unicode_#l' that has been written to the first wafer 40a does not match When the first unique code unicode_#1 before writing is written, the first wafer 40a does not pass the authentication. In other embodiments, the first 0810-A34563TWT AH2009059 9 201133351 = j, followed by the ic attack (manufacturing) company is transmitted to the client for final testing' Please refer to the description of Figure 6 later. If necessary, the step of encrypting and decrypting the first serial number serial_#1 (step S312a) in the wafer authentication = program is optional according to the different requirements for security. Specifically, please refer to Figure 3b. The steps in the figure are similar to the corresponding steps in Figure 3A, and will not be described again. However, the encryption step of the first unique code unic〇de-W is not included in Fig. 3B (e.g., step S312a of Fig. 3A), and accordingly a corresponding decryption step (e.g., step S34c of Fig. 6) is not required. For example, when the customer thinks that the security level of the wafer is enough to be reduced, it can directly treat the first serial number serial_#1 as the first unique code unic〇de_# after generating the first serial number (five) one #1. 1 is written to the first wafer 40a without the encryption step of the first serial number serial_#1; and at the final test stage, the corresponding decryption step is not required. In this way, a wafer with a lower security level can be quickly delivered to the client to reduce the production cycle. Next, enter the final test phase of wafer certification. As shown in FIG. 6, when the client needs to perform wafer authentication on the first wafer 40a in step S35a', the first unique code Unicode #1 ° written to the first wafer 40a is read in the OTP manner, and then the flow proceeds to the step. S35b, wherein the first unique code unicode_#l' read from the first wafer 40a is decrypted into a second serial number seriai_#2 by a decryption key. As described above, in the present embodiment, the 'encrypted gold record and the decrypted gold record are the same, and are assigned by the 1C design company. Then the flow proceeds to step S35c to determine whether the second serial number 0810-A34563TWF Α1Ϊ2009059 〇 201133351 serial_#2 meets the first serial number serial_#; [. If the second serial number serial_#2 meets the first serial number one #1, the process proceeds to step S35d; if the second serial number serial_#2 does not comply with the first serial number serial_#, the process proceeds to step S35e, and the first chip authentication failure is determined. In order to simplify the description, this article does not elaborate on the cryptography techniques of DES and OTP. If necessary, you can refer to the books related to cryptography. Figure 7 is a schematic diagram of a wafer authentication system in accordance with an embodiment of the present invention. Figure 7 shows a wafer authentication system 70 comprising an automated parameter testing system 71, a serial number generating device 72, an encryption device 73, and a verification device 74. In other embodiments, the wafer authentication system 70 of the present invention can also be used in the final testing phase of a wafer. The automated test system 71 is lightly coupled to the serial number generating means 72. The automated parametric test system 71 is an automated test system 'used to perform classification testing of complex wafers, such as DC tests (eg, electrical continuity tests, open (short) current and leakage current tests), and/or digital and analog functions. Test, but not limited to this. Automated Parametric Test _ System 71 includes a pr〇be card interface, a wafer positioning device, a parameter test device, and/or a computer as a server, but not Limited. After the automated parameter testing system 71 completes the classification test of the plurality of wafers, the serial number generating means 72 generates the first serial number serial_#1 of the first wafer 40a. In the present embodiment, the first serial number serial_#1 of the first wafer 40a is determined based on the wafer lot number to which the first wafer 40a belongs and the wafer coordinates of the first wafer 40a. For example, the first serial number serial_#1 of the first wafer 40a is obtained by combining the wafer lot number 0810-A34563TWF AH2009059 11 201133351 to which the first wafer 40a belongs and the wafer coordinates of the first wafer 40a, as in step S31 la Said. The encryption device 73 is coupled between the serial number generating device 72 and the verification device 74 for encrypting the first serial number serial_#1 into the first unique code. Specifically, the encrypting means 73 encrypts the first serial number serial_# 1 of the first wafer 40a into the first unique code unicode_#1 in the DES mode as described in step S312a. The password writing and judging means 74a of the verification means 74 writes the first unique code unicode_#1 to the first wafer 40a in the OTP manner, and judges whether or not the first unique code written in the first wafer 40a conforms to the first before writing. A unique code unicode_#l, as described in step S34a. When wafer authentication is required for the first wafer 40a, the password reading device 74b reads out the first unique code unicode_#1 written to the first wafer 40a in an OTP manner. It is to be noted that, in Fig. 7, although the password reading means 74b is located at the same place as the password writing/judging means 7.4a; however, the password reading means 74b may be located elsewhere. In other words, in the present embodiment, the password writing and judging device 74a is located at the 1C design (manufacturing) company, and the password reading device 74b is located at the customer, but not limited thereto. Specifically, when the client obtains the first wafer 40a and needs to perform wafer authentication thereon, the client uses the password reading device 74b to read the first unique code unicode_#1 that has been written into the first wafer 40a in an OTP manner, such as Step S34a is described. The decryption and judging device 74c is coupled to the password reading device 74b, and decrypts the first unique code imicode_#1 read from the first wafer 40a into a second serial number serial_#2 by a decryption key, and judges Whether the two serial number serial_#2 meets the first serial number serial_#l, as described in steps S34c and S34d 0810-A34563TWF AIi2009059 12 201133351. Similar to the password reading device 74b, in the present embodiment, the decrypting device 74c is also located at the client, but is not limited thereto. Another embodiment of the wafer authentication method of the present invention will be described below. Different from the embodiments of the aforementioned crystal moon authentication method, this embodiment obtains the serial number of each wafer for subsequent wafer authentication. In the present embodiment, the wafer authentication method includes a classification test of a plurality of wafers in which wafers are classified according to a predetermined classification standard, as described in steps S30a and S30b. Next, the serial number of each wafer is obtained as described in step S311a. Then, the serial number of each chip is encrypted as a unique code as described in step S312a. In this embodiment, the serial number is encrypted into a unique code by the Data Encryption Standard (DES) method, as described in step S312a, but not limited thereto, and other cryptographic technologies, such as 3DES, AES, or RSA, may also be used. In this embodiment. These unique codes are then written to the corresponding wafer. In the present embodiment, the unique code is written to the wafer in an OTP mode (or RSA mode, etc.) as described in step S33a. The flow then proceeds to step S34a, where wafer authentication is performed based on these unique codes. In this embodiment, it is judged whether the unique code of each wafer is • whether or not the unique code of each wafer before writing is matched. In other embodiments, each wafer is then transferred by the 1C design (manufacturing) company to the client for final testing. As shown in Fig. 6, the final test starts in step S35a, and when the customer needs to perform wafer authentication for each wafer, the unique code written to each wafer is read in OTP mode. The flow then proceeds to step S35b for decrypting the unique code read from each wafer into a corresponding serial number by means of a decryption key. As described above, in the present embodiment, the encryption key and the decryption key are the same, and are assigned by 1C. The flow then proceeds to step S35c to determine whether the corresponding serial number after decryption matches the serial number before encryption of each chip. If the corresponding serial number after decryption meets the pre-encryption serial number of each chip, the process proceeds to step S35d; if the corresponding serial number after decryption meets the pre-encryption serial number of each chip, the process proceeds to step S35e, and the chip authentication failure is determined. . Since the first serial number is determined based on the wafer lot number to which the first wafer belongs and the first wafer coordinate of the first wafer on the first wafer, the first serial number is unique. Since the first serial number is protected by the DES cryptographic technique, the security of the encrypted first serial number can be ensured. In addition, the wafer authentication system of the present invention can be installed in many machines for mass production, thereby reducing production cycle time. Although the invention has been disclosed above by the preferred embodiments, it is not intended to limit the invention. Those skilled in the art will be able to make some changes without departing from the spirit and scope of the invention. In other words, although the embodiment of the present invention includes only one wafer on one wafer (such as the first wafer 40a on the wafer 40), those skilled in the art can apply it to the same (or different). A plurality of wafers on a wafer. Moreover, the application of the present invention is not limited to a specific two entities (for example, 1C design (manufacturing) and customers in the embodiment of the present invention), and other products that may require wafer authentication (such as a certificate authority (CA)). Authentication card or 1C card, mobile phone, set-top box (STB), when it is necessary to implement the present invention. Combinations of the above steps can be performed sequentially or simultaneously in various combinations, and no particular steps are critical and/or necessary. And the features and descriptions described in the embodiments can be combined with the descriptions of the special 0810-A34563TWF Α1Ϊ2009059 14 201133351 described in the other embodiments. Accordingly, the scope of the invention encompasses the above variations. BRIEF DESCRIPTION OF THE DRAWINGS The present invention can be better understood by the above embodiments and with the accompanying drawings; FIG. 1 is a flow chart of a conventional wafer authentication method; and FIG. 2 is another conventional wafer authentication. FIG. 3A is a flow chart of a wafer authentication method according to an embodiment of the present invention, including a step of encrypting; FIG. 3B is a flowchart of a wafer authentication method according to an embodiment of the present invention, which does not include encryption. 4 is a schematic diagram of steps S31a and S31b of FIG. 3A and FIG. 3B for explaining a method for generating a first unique code according to an embodiment of the present invention; FIG. 5 is a schematic diagram for explaining the present invention; FIG. 6 is a flowchart of a wafer authentication method according to an embodiment of the present invention, and FIG. 6 is a flowchart for explaining a wafer authentication method of the present invention in a final test; FIG. A schematic diagram of a wafer authentication system in accordance with an embodiment of the present invention. [Main component symbol description] 70~chip authentication system; 71~automatic parameter test system; 72~ serial number generating device; 73~encrypting device; 74~verifying device; 0810-A34563TWF AH2009059 15 201133351 74a~password writing and judging device 74b~password reading device; 74c~decryption and judging device; .40~ wafer, 40a~first wafer; 40b~second wafer;: serial_#l~first serial number; unicode_#l~first unique code ; serial_#2~second serial number; unique—# 1 ~ first·only stone horse 0 0810-A34563TWF ΑΠ2009059 16