201131721 六、發明說明： 【發明所屬之技術領域】 此專利申請案大體上係關於積體電路（ic)封裝技術且特 定言之（但無限制之意）係關於用於1C封裝之引線框及其之 製造方法。 - 此申請案主張2009年4月3曰申請之美國臨時申請案第 61/166,547號及2009年7月17曰申請之臨時申請案第 61/226,361號之權利，其等以引用的方式併入本文中。 【先前技術】 1C封裝係製造IC裝置所包括之最終階段其中一階段。在 1C封裝期間，將一或多個IC晶片安裝於一封裝基板上將 其（等）連接至電觸點，且接著以包括諸如環氧樹脂或聚矽 氧模製化合物之電絕緣體之包封（encapsulati〇n)材料塗 覆。接著可將該所得IC封裝安裝於一印刷電路板（pCB)上 及/或連接至其他電氣組件。 通常，1C封裝可包含電觸點而不是外部引線，其中該等 電觸點係、由包封材料覆蓋於頂部且暴露於該職裝之底 Z ’所α其等可連接至位於該IC封裝下之電氣組件。通 . *使用金屬引線框架形成該1C封裝之部分可比使用一 層壓板或層壓帶材料更具成本效益，此係因為(例如)可使 用諸如銅、錄或其他金屬或金屬合金之更具成本效益材料 之故^且使用此等材料可允許採用更具成本效益之製造程 序諸如印模或餘刻而不是多步層壓程序。 【發明内容】 151426.doc 201131721 此申請案所揭示之各種實施例企圖將部分㈣刻及選擇 性鑛敷之引線框架用於具有高密度接觸 :電路(IC)封裝。上述發明内容不意圓代表本發明之:積 實施例或各態樣。 可 【實施方式】 當結合隨_式時，藉由參考下文實施方式可獲得本發 明之各種實施例之更完整的理解。 參考該等隨_式’現在將更充分地描述本發明之各種 實施例。然而本發明可以許多不同形式具體實施且不應視 為限制本文所闞述之該等實施例；而是提㈣等實施例使 得此揭示内容將為詳盡及完整，且將充分傳達本發明之範 疇至熟悉此項技術者》 現在參考圖1A至圊1E，其等顯示在一製造程序之各不 同階段處一 1C封裝之一實施例的橫截面側視圖。出於描述 目的，已描述相對於一單一 1(：封裝之製造程序，但是，如 下文將更詳細地描述，該製造程序之步驟可被應用於設置 於一引線框架條上之一些或所有複數個裝置區域。現在參 考圖1A’該程序以諸如具有大體上平頂面及平底面之一金 屬條之一未經蝕刻之引線框架i 00開始。通常，一製造商 會收到用於一 1C封裝之設計準則，舉例而言諸如待安裝於 該引線框架之一 1C晶片之大小及待設置於該引線框架之一 頂面上之接合區域之數量。該設計準則亦可包含待設置於 該引線框架之一底面上之接觸區域之大小及位置。該等接 觸區域之間之距離或間距可視將安裝該1C封裝之電氣組件 151426.doc 201131721 (舉例而言諸如一 PCB)之最小需求而定。在圖iB中，該引 線框架100之一頂面係經部分蝕刻，以產生界定於其上之 金屬跡線U2之凹口 126。在所示之實施例中，已將一金屬 鍍層施加於設置於該等金屬跡線122之一頂面上之接合區 域118及設置於該等金屬跡線122之一底面上之接觸區域 106 »可藉由施加可黏合或可焊材料於該等金屬跡線丨22， 其例如諸如銀（Ag)、金（Au)、銅（Cu)或其他可黏合材料之 鐘敷或包層金屬’來形成該等接合區域U8及接觸區域1〇6 之金屬鍍層。在各種實施例中，可在諸如一製造工廠之一 第一位置處完成該引線框架100之頂面之蚀刻，且可在舉 例而言諸如該製造工廠之一不同區域或一不同製造工廠之 一第一位置70成剩餘步驟。在此等實施例中，藉由部分触 刻該引線框架100，比起若全部蝕刻該引線框架1〇〇 ,該等 金屬跡線122係更穩定且更不可能移動。 在圖1 c中，已利用例如環氧樹脂之黏著材料j丨〇將一 ic 晶片104固定至該引線框架1〇〇β在將該…晶片安裝於該引 線框架100後，可將該1C晶片例如經由導線接合丨〗4電耦合 至設置於晶粒附著區域外之該等接合區域。在圖1D中已 施加一包封化合物108(如陰影區域顯示）以包封該10:晶片 104及該等導線接合114 〇舲冰，y 4 +上，，人 4此外，该包封化合物1 08亦已填 充該等凹口 126，包含設詈於兮 3 °又直於5亥1c晶片104下之該等凹口201131721 VI. Description of the Invention: [Technical Field of the Invention] This patent application is generally related to integrated circuit (ic) packaging technology and specifically (but not limiting) relates to lead frames for 1C packages and Its manufacturing method. - This application claims the benefit of U.S. Provisional Application No. 61/166,547, filed on Apr. 3, 2009, and the Provisional Application No. 61/226,361, filed on Jan. 17, 2009, which is hereby incorporated by reference. In this article. [Prior Art] The 1C package is one of the final stages of the manufacturing of the IC device. During the 1C package, one or more IC chips are mounted on a package substrate to connect them to the electrical contacts, and then encapsulated with an electrical insulator including a compound such as an epoxy or polyoxymethylene molding compound. (encapsulati〇n) material coating. The resulting IC package can then be mounted on a printed circuit board (pCB) and/or connected to other electrical components. In general, a 1C package may include electrical contacts instead of external leads, wherein the electrical contacts are covered by an encapsulating material to the top and exposed to the bottom of the job, and may be connected to the IC package. The electrical components underneath. It is more cost effective to form a portion of the 1C package using a metal lead frame than to use a laminate or laminate tape material because, for example, it is more cost effective to use, for example, copper, recording or other metals or metal alloys. The material and the use of such materials may allow for more cost effective manufacturing procedures such as stamping or casting rather than multi-step lamination. SUMMARY OF THE INVENTION Various embodiments disclosed in this application attempt to use a partially (four) engraved and selectively deposited lead frame for use with high density contacts: circuit (IC) packages. The above summary of the invention is not intended to represent the invention or the embodiments. [Embodiment] A more complete understanding of various embodiments of the present invention can be obtained by referring to the following embodiments. Various embodiments of the present invention will now be described more fully with reference to the appended claims. However, the present invention may be embodied in many different forms and should not be construed as being limited to the details of the embodiments described herein. The embodiments of the present invention are intended to be exhaustive and complete, and to fully convey the scope of the invention. The present technology now refers to Figures 1A through 1E, which show cross-sectional side views of one embodiment of a 1C package at various stages of a manufacturing process. For the purposes of this description, a manufacturing procedure has been described with respect to a single 1 (: package, but as will be described in more detail below, the steps of the manufacturing process can be applied to some or all of the plurals placed on a lead frame strip Device area. Referring now to Figure 1A', the program begins with an unetched lead frame i 00 such as one of a substantially flat top and a flat bottom metal strip. Typically, a manufacturer will receive a 1C package. a design criterion, such as, for example, the size of a 1C wafer to be mounted on the lead frame and the number of bonding regions to be disposed on a top surface of the lead frame. The design criteria may also include a lead frame to be disposed on the lead frame. The size and location of the contact area on one of the bottom surfaces. The distance or spacing between the contact areas may depend on the minimum requirements of the electrical component 151426.doc 201131721 (for example, a PCB) to which the 1C package is mounted. In Figure iB, one of the top surfaces of the leadframe 100 is partially etched to create a recess 126 defining a metal trace U2 thereon. In the illustrated embodiment, A metal plating is applied to the bonding region 118 disposed on one of the top surfaces of the metal traces 122 and the contact region 106 disposed on a bottom surface of the metal traces 122. by applying a bondable or solderable material Forming the bonding regions U8 and the contact regions 1 with the metal traces 22, such as, for example, silver (Ag), gold (Au), copper (Cu), or other alloying or cladding metal. Metal plating of 〇 6. In various embodiments, the top surface of the leadframe 100 may be etched at a first location such as a manufacturing facility, and may be, for example, in a different region of the manufacturing facility or The first position of one of the different manufacturing plants is 70% of the remaining steps. In these embodiments, by partially engraving the lead frame 100, the metal traces 122 are compared to if the lead frame 1 is completely etched. More stable and less likely to move. In Fig. 1c, an ic wafer 104 has been secured to the lead frame by using an adhesive material such as an epoxy resin, and the wafer is mounted on the lead frame. After 100, the 1C wafer can be, for example Electrically coupled to the bonding regions disposed outside the die attach regions by wire bonds. An encapsulation compound 108 (shown as shaded regions) has been applied in FIG. 1D to encapsulate the 10: wafer 104 and such Wire bonding 114 〇舲 ice, y 4 + upper, human 4 In addition, the encapsulating compound 108 has also filled the notches 126, including the 詈 3 ° and the 5 1 1c wafer 104 Notch
126。在圖1£中，已回蝕該引線框架100之-底面。在各; 實施例中，該底面之賴可包含對應於形成於該引線㈣ 議之-頂面之料凹口_該引線框架⑽之部分H 151426.doc 201131721 完全蝕穿該引線框架100，藉此將該等金屬跡線122相互電 隔離使得該引線框架1〇〇之剩餘部分經由金屬跡線122電耦 合該等接合區域118至該等接觸區域1〇6。在一些實施例 中’該回蝕可包含暴露該包封化合物108之部分之一底 面。在各種實施例中’該回蝕可包含蝕刻一些該等金屬跡 線122之蝕刻部分122a。如所示之實施例可見，該等接合 區域118係自該等接觸區域1〇6橫向遠端設置使得沒有與該 引線框架100之該頂面垂直的線與一接合區域及一接觸區 域二者相交。在各種實施例中，該等金屬跡線122可經建 構以提供自該接合區域118至設置於該1C晶片104下方之橫 向遠端设置之接觸區域106之一電氣通道或路由。在一些 實施例中’可將一保護塗層129施加於該引線框架100與包 封化合物108之各種下表面。 現在參考圖2 A至圖2B，顯示一部分經蝕刻之引線框架 200之一實施例之各種態樣。圖2A係在一 IC晶片被安裝於 其上前之一部分經蝕刻之引線框架2〇〇之一俯視圖。圖2B 係對應於圖2A之細節A之該引線框架200之一部分之一橫 截面侧視圖。顯示該引線框架200具有複數個以一預定圖 案蝕刻入其之一頂面以界定複數個金屬跡線222(如陰影部 分顯示）之上部的凹口 226(如未畫陰影部分顯示）。在所示 之實施例中，各金屬跡線222具有設置於其之一末端之一 接合區域218及設置於其之一相反末端之一接觸區域2〇6。 雖然在該實施例圖示中僅該頂面被蝕刻，出於描述目的， 已將該引線框架200之一底面上將設置該等接觸區域2〇6之 151426.doc 201131721 位置顯不為未畫陰影正方形。在圖⑶中，圖2A之細節A之 杈截面側視圖顯示在該等凹口 226蝕刻入引線框架2〇〇之頂 面以界疋該等金屬跡線222之上部後的該引線框架2〇〇。 現在參考圖3A至圖3B，顯示用於一 1(：封裝製造程序之 一部分經蝕刻之引線框架3〇〇之一實施例之一俯視圖及一 仰視圖。在圖3A中，出於描述目的，顯示一 IC晶片3〇4之 一略圖。在此實施例中，接合區域318(如實線正方形顯示） 之一外排係直接設置於對應接觸區域（如虛線正方形顯示） 上。此外，顯示接合區域318之一内排自對應接觸區域3〇6 橫向遠端地設置且經由金屬跡線322電耦合至該等接觸區 域 306。 現在參考圖3B，可見該引線框架3〇〇之一仰視圖。在所 不之實施例中，該引線框架3〇〇之底面可設置該等接觸區 域306之位置顯示為實線正方形。在一些實施例中，在蝕 刻前可施加金屬鍍層於該等接觸區域3〇6。出於描述目 的’已顯示該等金屬跡線322為陰影部分。在一些實施例 中，該等接觸區域306以彼此相距之至少一最小距離間 隔’舉例而言諸如PCB設計規格所要求之最小距離。在所 不之實施例中，圍繞於該引線框架300周邊之各接合區域 318(如虛線正方形顯示）係直接設置於一對應接觸區域3〇6 上且因此此等接合區域3 18必須亦以彼此相距之至少該最 小距離間隔。然而’因為該等金屬跡線322電耦合接合區 域318之内排以自對應接觸區域306橫向遠端地設置，所以 該等接合區域3 1 8可以小於該等PCB設計規格要求之該最 151426.doc 201131721 小距離間隔，而仍允許該等接觸區域3 〇6以彼此相距之至 少該最小距離間隔。 現在參考圖4A，顯示一部分經蝕刻且選擇性鍍敷之引線 框架400之一實施例之一俯視圖。出於描述目的，可安裝 一 1C晶片404之位置之輪廟係顯示為虛線。在此實施例 中，藉由蝕除該引線框架400之一頂面之部分形成凹口 426 以界定其上設置有接合區域418之金屬跡線422之上部。在 此實施例中，該引線框架400之底面上設置該等接觸區域 406之位置係顯示為斷圓。如下文將更詳細地描述，接合 區域418之所有外排係直接設置於對應接觸區域4〇6上，而 接合區域418内排之至少一部分並非直接設置於對應接觸 區域406上，允許接合區域418之内排更緊密相隔。 現在參考圖4B，顯示圖4A之細節A與細節B之俯視圖及 側視圖。在細節A中，已將凹口 426蝕刻入引線框架400之 一頂面以界定耦合在該引線框架4〇〇之頂面上之接合區域 41 8至該引線框架4〇〇之一底面上將設置該等接觸區域4〇6 之位置之金屬跡線422之上部。此外，已以（例如）一金屬鍍 層選擇性鍍敷該引線框架400之該等頂面與底面。如所示 之實施例可見，該等接合區域418與該等接觸區域4〇6大體 上具有相同寬度。因為該等接合區域418係直接設置於該 等接觸區域406上，該等接合區域418之間距必須等於該等 接觸區域406之間距，其係受將安裝該1(：封裝之pcB之最 小要求約束。 現在參考細節B，提供顯示在兩個正下方具有接觸區域 151426.doc 201131721 406之接合區域41 8之間***接合區域418之俯視圖及側視 圖。在所示之實施例中’該等接合區域418係設置於該引 線框架400之一頂面上且顯示為長方形及該引線框架4〇〇之 一底面上將設置該等接觸區域4〇6之位置顯示為圓形。在 細節B所示之實施例中，該等接合區域418之寬度相對於細 節A所示之該等接合區域具有減小的寬度。由於該等接觸 區域（未顯示）之一者係自中間接合區域418之正下方橫向遠 端地設置，該等全部接合區域418的寬度可小於該等接觸 區域406的寬度，因此允許該等接合區域418比該等接觸區 域406更緊密設置。 現在參考圖5，顯示具有圍繞在一引線框架5〇〇周邊之接 合區域518之一外排及具有設置於將安裝一IC晶片5〇4之區 域下之接觸區域506之接合區域518之一内排之該引線框架 5 00之一貫施例的一俯視圖。在此實施例中，設置該等接 合區域518之内排之該等金屬跡線522之末端具有大於耦合 該等接合區域518至對應接觸區域5〇6之其餘金屬跡線522 之一寬度。舉例而言，在不同實施例中，該等金屬跡線 522可具有約5.5密耳之一間距，其中一寬度約15密耳且彼 此間隔約4密耳。在各種實施例中，該等接合區域$丨8可具 有約5.5密耳之一間距，其中一寬度約2·5密耳且彼此間隔 約3密耳。在各種實施例中，該等接觸區域5〇6之最小間距 係由將安裝該1C封裝之PCB之需要決定。在各種實施例 中，該等接觸區域506可具有約6密耳之一直徑及157密耳 之一間距，7_9密耳之一直徑及197密耳之一間距或98密 151426.doc 201131721 耳之一直徑及25.6密耳之一間距。 現在參考圖6A至圖6C，顯示一部分經蝕刻之引線框架 600之各種實施例之俯視圖。在圖6A中，顯示一引線框架 600之一實施例，該引線框架6〇〇具有部分界定於其可安裝 一 IC Ba片604之至少一部分的頂面上之一晶粒附著襯墊 (DAP)602。在所示之實施例中，將安裝該IC晶片6〇4之區 域（該晶粒附著區域）包含該DAP 602與該等金屬跡線622之 部为之一者。在各種實施例中，該Dap 602可提供尤其係 用於該1C晶片604之增強的熱消散及/或結構支撐。在圖6B 所示之實施例中，金屬跡線622a係電耦合至該DAP 602(例 如）以提供用於該1C晶片604之一電接地。在一些實施例 中’一或多個通道可形成於該DAP 602中以促進該包封材 料流入其他隔離的或難以到達的地方。 現在參考圖6C，顯示可用於一 ic封裝之一部分經截刻之 引線框架6 0 0之一俯視圖。在所示之實施例中，顯示一 ic 晶片604可安裝之位置。如所見，在此實施例中該IC晶片 604係小於圖6A及圖6B中之該等1C晶片604，顯示利用金 屬跡線允許該等接觸區域之至少一部分自對應接合區域遠 端地設置’藉此增加可用於1C晶片及引線框架之一給定大 小組合之I/O連接的數量。如從所示之實施例可見，利用 該引線框架600上之金屬跡線以自該等接合區域遠端地設 置該等接觸區域可經建構以提供複數排接合區域及複數排 接觸區域。在各種實施例中，可將三或四排接合區域部分 蝕刻入該引線框架中且對應於五個或更多個接觸區域之金 151426.doc _ 10· 201131721 屬鍍層可設置於該引線框架之一底面上。舉例而言，一 5x5毫米的引線框架可經建構以提供超過1〇〇個ι/〇連接。 如所示之實施例中可見，各種實施例可利用向外選路及向 内選路之一組合。 現在參考圖7,其顯示—IC封裝製造程序7〇〇之一實施例 之一流程圖。言玄程序於將一部分經触刻之引隸架之設計 準則提供給一製造商之步驟7〇2開始。在各種實施例中， 可透過一客戶訂單接收及/或可由製造商開發該設計準則 之至4分。該设計準則可包含有關一最終丨匸封裝之資 訊及/或可包含僅有關一部分經蝕刻之引線框架之資訊。 舉例而3，1¾設計準則彳包含一所希望之引線框架的長 度 '寬度及高度、待安裝於該引線框架上之ic晶片的大 J接。區域的數量、接合區域的位置、接觸區域的數 量、接觸區域的位置及/或其他設計準則。在步驟7〇4，向 一第一位置提供一未經蝕刻之金屬條（舉例而言諸如一銅 金屬條）之。在步驟706,利用任意數目的蝕刻程序部分蝕 刻該金屬條之一頂面’以產生界定其上設置有接合區域之 金屬跡線之上部之凹σ的圖帛。該等凹口的圖案可如設計 準财可能提供般對應於耗合料接合區域至該等接觸區 域之位置所需之金屬跡線。在—些實施例中，㈣刻可為 一半蝕刻，使得形成於該引線框架中之該等凹口於其間延 伸半。舉例而言，在一4密耳引線框架中，該半餘刻將 為-2密耳钱刻。在各種實施例中，該引線框架可於 h於+。舉例而言，在一些實施例令，該 I51426.doc •11 · 201131721 部分蝕刻可為至約3密耳+/_〇.5密耳之一深度。在該頂面經 部分钱刻後’該引線框架之該頂面及底面之一或二者可藉 由舉例而言諸如鍍敷該等接合區域及/或將設置該等接觸 區域之位置而選擇性地鍍敷。該等接合區域之金屬鍍層可 藉由施加一可黏合材料於該等金屬跡線而形成。在各種實 施例中，可在該金屬鍍敷之後施行一表面黏合性增強處理 (AE處理」），舉例而言，諸如，粗糙化及/或清潔該表 面以增加黏合性。 在步驟708，該部分經蝕刻之引線框架可自該第一位董 運送至帛一位置。纟各種實施W中，該部分經触％ 線框架在運送期間為該等金屬跡線提供穩定性。舉例雨 言’在-些實施例中，該第一位置可為適合蝕刻該引線相 架之β亥頂面之一製造工廠之一部分且該第二位置可為適名 完成該1C封裝程序之該製造工廠之相同或不同部分。在_ 一貫鉍例巾該第—位置可為一第一製造工廠且該第二伯 置可為一第二製造工廠。在-些實施例中，該第一位置可 為-第-製造工廠且該第二位置可為一客戶的位置或其他 位置在步驟710，將一 IC晶片安裝於該部分經姓刻之引 線框架上。其次，在步驟712將該1C晶片導線接合至該部 分經㈣之引線框架後，在步驟714包封該Κ晶片。該程 序以在步驟716該金屬條之—底面之回#結束。 現在參考圖8，顯示可用於，裝製造程序之(例如) 該類型之一金屬條_。該金屬條_包含設置於其上之複 數個裝置區域8CU。在—些實施例中，該金屬條綱可為銅 151426.doc -12· 201131721 或其他金屬或金屬合金且可具有5密耳、大於5密耳或小於 5密耳之-厚度。在不同實施财，該等裝置區域斯之大 小可變化且在-金屬條_上之裝置區域8〇ι之數量亦可變 化舉例而σ在些實施例中，在一金屬條8〇〇上之裝 置區域801之數量可為從小於1〇〇至大於1〇〇〇之任意數量。 在一 1C製造程序期間 ，可將一或多個1C晶片附著至各裝置 區域801且以一包封化合物包封。在各種實施例中，該等 1C晶片可經由導線接合電耦合至該裝置區域肋丨或直接電 耦合至一覆晶構造中。該IC製造程序亦可包含相互單一化 该等裝置區域801以形成可經建構以安裝於諸如一 pcB之 一外部裝置之複數個1C封裝。當將該等IC封裝安裝於一 PCB上時’該等1C晶片可經由設置於該等1(：封裝之一底面 上之接觸區域電搞合至該PC B。 雖然已在該等隨附圖式中繪示且在上述實施方式中描述 该方法之各種實施例及本發明之係統，應理解本發明不限 於所揭示之實施例，但是可在不脫離如本文闡述之本發明 之精神下做一些重新整理、修改及取代。 【圖式簡單說明】 圖1A至圖1E圖解說明在一製造程序之各種不同階段處 一無引線1C封裝之一實施例的態樣； 圖2 A至圖2B係頂面上形成複數個金屬跡線之一金屬引 線框架之一實施例的兩個視圖； 圖3A至圖3B係具有兩排接合區域及多排接觸區域之一 引線框架之一實施例的一俯視圖及一仰視圖； 151426.doc •13- 201131721 圖4A至圖4B圖解說明一部分經蝕刻及選擇性鍍敷之引 線框架之一實施例的各種態樣； 圖5顯示具有耦合接合區域至接觸區域之複數個金屬跡 線之一部分經蝕刻之引線框架的一例示性實施例； 圖6A至圖6C圖解說明用於一無引線ic封裝之一部分經 蝕刻之引線框架之各種實施例的俯視圖； 圖7係用於製造一部分經蝕刻之引線框架之一程序之一 實施例的一流程圖；及 圖8圖解說明用於形成複數個部分經蝕刻之引線框架之 一引線框架條的一實施例。 【主要元件符號說明】 100 未經钱刻之金屬框架 104 1C晶片 106 接觸區域 108 包封化合物 108a 钱刻部分 110 黏著材料 114 導線結合 118 接合區域 122 金屬跡線 122a 金屬跡線之蚀刻部分 126 凹口 129 保護塗層 200 部分經蝕刻之引線框架 151426.doc -14· 201131721 206 218 222 226 300 304 306 318 322 400 404 406 418 422 426 500 504 506 518 522 600 602 604 接觸區域 接合區域 金屬跡線 凹口 部分經蝕刻之引線框架 1C晶片 接觸區域 接合區域 金屬跡線 部分經蝕刻且選擇性鍍敷之引線框架 1C晶片 接觸區域 接合區域 金屬跡線 凹口 引線框架 1C晶片 接觸區域 接合區域 金屬跡線 部分經蝕刻之引線框架 晶粒附著襯墊（DAP) 1C晶片 金屬跡線 151426.doc 15· 622 201131721 622a 金屬跡線 700 1C封裝製造程序 800 金屬條 801 裝置區域 151426.doc -16-126. In Fig. 1, the bottom surface of the lead frame 100 has been etched back. In the embodiment, the bottom surface may comprise a recess corresponding to the top surface of the lead (four) - the portion of the lead frame (10) H 151426.doc 201131721 completely etches through the lead frame 100, This electrically isolates the metal traces 122 from each other such that the remainder of the leadframe 1 is electrically coupled via the metal traces 122 to the contact regions 118 to the contact regions 1〇6. In some embodiments, the etch back can include exposing one of the portions of the encapsulating compound 108. In various embodiments, the etch back can include etching some of the etched portions 122a of the metal traces 122. As can be seen in the illustrated embodiment, the joint regions 118 are disposed laterally distal from the contact regions 1〇6 such that there are no lines perpendicular to the top surface of the lead frame 100 and a joint region and a contact region. intersect. In various embodiments, the metal traces 122 can be configured to provide an electrical path or route from the bond region 118 to a laterally disposed contact region 106 disposed below the 1C wafer 104. In some embodiments, a protective coating 129 can be applied to the various lower surfaces of the leadframe 100 and the encapsulating compound 108. Referring now to Figures 2A through 2B, various aspects of an embodiment of a portion of an etched leadframe 200 are shown. Figure 2A is a top plan view of a portion of the lead frame 2 etched before an IC wafer is mounted thereon. Figure 2B is a cross-sectional side view of a portion of the lead frame 200 corresponding to detail A of Figure 2A. The leadframe 200 is shown having a plurality of notches 226 (shown as unshaded portions) that are etched into a top surface of a predetermined pattern to define an upper portion of a plurality of metal traces 222 (as shown by the shaded portions). In the illustrated embodiment, each metal trace 222 has a bond region 218 disposed at one of its ends and a contact region 2〇6 disposed at one of its opposite ends. Although only the top surface is etched in the embodiment of the embodiment, for the purpose of description, the 151426.doc 201131721 position on the bottom surface of one of the lead frames 200 on which the contact areas 2 〇 6 are to be placed is not drawn. Shaded squares. In Figure (3), a cross-sectional side view of detail A of Figure 2A shows the lead frame 2 after the notches 226 are etched into the top surface of the leadframe 2 to define the upper portions of the metal traces 222. Hey. Referring now to Figures 3A-3B, there is shown a top view and a bottom view of one embodiment of a lead frame 3 for etching a portion of a package fabrication process. In Figure 3A, for purposes of description, An outline of an IC chip 3〇4 is shown. In this embodiment, one of the lands 318 (as shown by the solid square display) is disposed directly on the corresponding contact area (as indicated by the dashed square). In addition, the joint area is displayed. One of the inner rows of 318 is disposed laterally distally from the corresponding contact area 3〇6 and is electrically coupled to the contact areas 306 via metal traces 322. Referring now to Figure 3B, one of the lead frames 3'''''''''''' In the embodiment, the bottom surface of the lead frame 3 is disposed such that the positions of the contact regions 306 are displayed as solid squares. In some embodiments, a metal plating layer may be applied to the contact regions before etching. 6. The metal traces 322 have been shown as shaded portions for purposes of description. In some embodiments, the contact regions 306 are spaced apart from each other by at least a minimum distance 'for example, such as P The minimum distance required by the CB design specification. In the embodiment, the respective bonding regions 318 (shown by dashed squares) surrounding the periphery of the lead frame 300 are directly disposed on a corresponding contact region 3〇6 and thus The equal bonding regions 3 18 must also be spaced apart from each other by at least the minimum distance. However, because the inner rows of the metal traces 322 electrically coupled to the bonding regions 318 are disposed laterally distally from the corresponding contact regions 306, the bonding The region 3 1 8 may be smaller than the minimum distance of the most 151426.doc 201131721 of the PCB design specifications, while still allowing the contact regions 3 〇 6 to be spaced apart from each other by at least the minimum distance. Referring now to Figure 4A, a portion is shown A top view of one embodiment of an etched and selectively plated leadframe 400. For purposes of description, a wheel temple that can mount a 1C wafer 404 is shown as a dashed line. In this embodiment, by etching A portion of the top surface of one of the lead frames 400 forms a recess 426 to define an upper portion of the metal trace 422 on which the joint region 418 is disposed. In this embodiment, the lead The locations on the bottom surface of the wire frame 400 where the contact regions 406 are disposed are shown as broken. As will be described in more detail below, all of the efflux of the bond regions 418 are disposed directly on the corresponding contact regions 4〇6, and the joint regions At least a portion of the inner row of 418 is not disposed directly on the corresponding contact area 406, allowing the inner rows of the joint regions 418 to be more closely spaced. Referring now to Figure 4B, a top view and a side view of detail A and detail B of Figure 4A are shown. The recess 426 has been etched into the top surface of one of the lead frames 400 to define a bonding region 418 coupled to the top surface of the lead frame 4 to one of the bottom surfaces of the lead frame 4 The upper portion of the metal trace 422 at the location of the contact area 4〇6. Additionally, the top and bottom surfaces of the leadframe 400 have been selectively plated, for example, with a metal coating. As can be seen in the illustrated embodiment, the joint regions 418 have substantially the same width as the contact regions 4〇6. Because the joint regions 418 are disposed directly on the contact regions 406, the distance between the joint regions 418 must be equal to the distance between the contact regions 406, which is subject to the minimum requirement that the 1 (: packaged pcB) will be installed. Referring now to detail B, there is provided a top view and a side view showing the insertion of the joint region 418 between the two joint regions 418 with the contact regions 151426.doc 201131721 406 directly below. In the illustrated embodiment, the joint regions The 418 is disposed on a top surface of the lead frame 400 and is displayed as a rectangle and a position on the bottom surface of the lead frame 4 on which the contact regions 4〇6 are disposed is displayed as a circle. In an embodiment, the width of the joint regions 418 has a reduced width relative to the joint regions shown in detail A. Since one of the contact regions (not shown) is laterally below the intermediate joint region 418, Remotely disposed, the width of the total joint regions 418 can be less than the width of the contact regions 406, thus allowing the joint regions 418 to be more closely disposed than the contact regions 406. Referring to FIG. 5, there is shown an outer row having a bonding region 518 surrounding a periphery of a lead frame 5 and having one of the bonding regions 518 disposed in a contact region 506 under the region where an IC wafer 5〇4 is to be mounted. A top view of a consistent embodiment of the leadframe 500. In this embodiment, the ends of the metal traces 522 that are disposed within the inner regions of the bond regions 518 have greater than the coupling of the bond regions 518 to corresponding contacts. One of the remaining metal traces 522 of the region 5〇6. For example, in various embodiments, the metal traces 522 can have a pitch of about 5.5 mils, wherein a width of about 15 mils and spaced apart from each other About 4 mils. In various embodiments, the joint regions $丨8 can have a pitch of about 5.5 mils, wherein one width is about 2.5 mils and spaced apart from each other by about 3 mils. In various embodiments The minimum spacing of the contact regions 〇6 is determined by the need to mount the PCB of the 1C package. In various embodiments, the contact regions 506 can have a diameter of about 6 mils and one of 157 mils. Spacing, 7_9 mil one diameter and 197 mils One pitch or 98 151 426.doc 201131721 One of the ear diameters and one of the 25.6 mil pitches. Referring now to Figures 6A-6C, a top view of various embodiments of a portion of the etched leadframe 600 is shown. In Figure 6A, a In one embodiment of a lead frame 600, the lead frame 6A has a die attach pad (DAP) 602 partially defined on a top surface on which at least a portion of an IC Ba sheet 604 can be mounted. In the embodiment, the region (the die attach region) on which the IC chip 6〇4 is mounted includes one of the DAP 602 and the portions of the metal traces 622. In various embodiments, the Dap 602 can provide enhanced thermal dissipation and/or structural support, particularly for the 1C wafer 604. In the embodiment illustrated in Figure 6B, metal traces 622a are electrically coupled to the DAP 602 (e.g., for example) to provide electrical grounding for one of the 1C wafers 604. In some embodiments, one or more channels may be formed in the DAP 602 to facilitate the flow of the encapsulating material into other isolated or hard to reach locations. Referring now to Figure 6C, there is shown a top plan view of a lead frame 600 that can be used for cutting a portion of an ic package. In the illustrated embodiment, the location at which an ic wafer 604 can be mounted is displayed. As can be seen, in this embodiment the IC die 604 is smaller than the 1C wafers 604 of Figures 6A and 6B, showing that the use of metal traces allows at least a portion of the contact areas to be remotely located from the corresponding joint area. This increase can be used for the number of I/O connections of a given size combination of one of the 1C wafer and the lead frame. As can be seen from the illustrated embodiment, the use of metal traces on the leadframe 600 to provide the contact regions distally from the bonding regions can be configured to provide a plurality of rows of bonding regions and a plurality of rows of contact regions. In various embodiments, three or four rows of bonding regions may be partially etched into the lead frame and gold corresponding to five or more contact regions 151426.doc _ 10· 201131721 galvanic coating may be disposed on the lead frame On the bottom surface. For example, a 5 x 5 mm lead frame can be constructed to provide more than 1 ι/〇 connection. As can be seen in the illustrated embodiment, various embodiments can utilize a combination of one of an outward routing and an inward routing. Referring now to Figure 7, there is shown a flow diagram of one of the embodiments of the IC package fabrication process. The vocabulary program begins with the step 7〇2 of providing a part of the design rule of the etched lead frame to a manufacturer. In various embodiments, the design criteria may be received by a customer order and/or may be developed by the manufacturer to a score of four. The design criteria may include information about a final package and/or may include information about only a portion of the etched lead frame. For example, the 3,13⁄4 design guidelines include the length 'width and height of a desired lead frame, and the large J junction of the ic wafer to be mounted on the lead frame. The number of zones, the location of the joint zone, the number of contact zones, the location of the contact zone, and/or other design criteria. In step 7〇4, an unetched metal strip (for example, a copper metal strip) is provided to a first location. At step 706, one of the top faces of the metal strip is partially etched using any number of etch procedures to produce a pattern of recesses σ defining the upper portion of the metal trace on which the bond regions are disposed. The pattern of the notches may provide metal traces as desired for designing the location of the material-bonding region to the contact regions. In some embodiments, (iv) may be half etched such that the notches formed in the lead frame extend halfway therebetween. For example, in a 4 mil lead frame, the half-detail will be -2 mils. In various embodiments, the lead frame can be at h +. For example, in some embodiments, the I51426.doc •11 · 201131721 partial etch may be one depth to about 3 mils + / _ 5 5 mils. After the top surface is partially engraved, one or both of the top and bottom surfaces of the lead frame may be selected by, for example, plating the joint regions and/or the locations at which the contact regions are to be disposed. Sexually plated. The metallization of the bonding regions can be formed by applying an adhesive material to the metal traces. In various embodiments, a surface adhesion enhancement treatment (AE treatment) may be applied after the metal plating, such as, for example, roughening and/or cleaning the surface to increase adhesion. At step 708, the partially etched lead frame can be transported from the first position to the first position. In various implementations, the portion provides stability to the metal traces during transport via the contact % line frame. For example, in some embodiments, the first location may be a portion of a manufacturing plant suitable for etching the beta top surface of the lead photo frame and the second location may be a suitable name to complete the 1C packaging process. The same or different parts of the manufacturing plant. The first location may be a first manufacturing facility and the second location may be a second manufacturing facility. In some embodiments, the first location may be a - manufacturing plant and the second location may be a customer location or other location. In step 710, an IC chip is mounted to the portion of the lead frame. on. Next, after bonding the 1C wafer wire to the lead frame of the portion (4) in step 712, the germanium wafer is encapsulated in step 714. The process ends with the back of the metal strip at step 716. Referring now to Figure 8, there is shown, for example, one of the metal strips of this type that can be used to mount a manufacturing process. The metal strip_ contains a plurality of device areas 8CU disposed thereon. In some embodiments, the metal strip can be copper 151426.doc -12. 201131721 or other metal or metal alloy and can have a thickness of 5 mils, greater than 5 mils, or less than 5 mils. In different implementations, the size of the device regions may vary and the number of device regions 8〇 on the metal strip may also vary. σ, in some embodiments, on a metal strip 8〇〇 The number of device regions 801 can be any number from less than 1 〇〇 to greater than 1 。. One or more 1C wafers may be attached to each device region 801 and encapsulated with an encapsulating compound during a 1C fabrication process. In various embodiments, the 1C wafers can be electrically coupled to the device region ribs via wire bonds or directly electrically coupled to a flip chip configuration. The IC fabrication process can also include singulating the device regions 801 with each other to form a plurality of 1C packages that can be configured to be mounted to an external device such as a pcB. When the IC packages are mounted on a PCB, the 1C wafers can be electrically coupled to the PC B via contact areas disposed on one of the bottom surfaces of the package. Although already in the drawings The various embodiments of the method and the system of the present invention are illustrated in the above-described embodiments, and it is to be understood that the invention is not limited to the disclosed embodiments, but may be made without departing from the spirit of the invention as set forth herein. Some rearrangements, modifications, and substitutions. [Schematic Description of the Drawings] Figures 1A-1E illustrate aspects of an embodiment of a leadless 1C package at various stages of a fabrication process; Figure 2A through Figure 2B Two views of one embodiment of a metal lead frame forming one of a plurality of metal traces on the top surface; FIGS. 3A-3B are top views of one embodiment of a lead frame having one of two rows of bonding regions and a plurality of rows of contact regions And a bottom view; 151426.doc • 13-201131721 FIGS. 4A-4B illustrate various aspects of one embodiment of a portion of an etched and selectively plated lead frame; FIG. 5 shows a coupled bond region to a contact region An exemplary embodiment of a partially etched leadframe of a plurality of metal traces; FIGS. 6A-6C illustrate top views of various embodiments of a partially etched leadframe for a leadless ic package; FIG. A flow diagram of one embodiment of a process for fabricating a portion of an etched leadframe; and Figure 8 illustrates an embodiment of a leadframe strip for forming a plurality of partially etched leadframes. DESCRIPTION OF SYMBOLS 100 Unetched metal frame 104 1C wafer 106 Contact area 108 Encapsulation compound 108a Engraved portion 110 Adhesive material 114 Wire bond 118 Bonding area 122 Metal trace 122a Metal trace etching portion 126 Notch 129 Protection Coating 200 partially etched lead frame 151426.doc -14·201131721 206 218 222 226 300 304 306 318 322 400 404 406 418 422 426 500 504 506 518 522 600 602 604 Contact area joint area metal trace notch portion Etched lead frame 1C wafer contact area bonding area metal trace portion etched and selective Laminated lead frame 1C wafer contact area bonding area metal trace recessed lead frame 1C wafer contact area bonding area metal trace portion etched lead frame die attach pad (DAP) 1C wafer metal trace 151426.doc 15· 622 201131721 622a Metal Trace 700 1C Package Manufacturing Procedure 800 Metal Strip 801 Device Area 151426.doc -16-