TW201131712A - Flip chip package structure with heat dissipation enhancement and its application - Google Patents
Flip chip package structure with heat dissipation enhancement and its application Download PDFInfo
- Publication number
- TW201131712A TW201131712A TW099107271A TW99107271A TW201131712A TW 201131712 A TW201131712 A TW 201131712A TW 099107271 A TW099107271 A TW 099107271A TW 99107271 A TW99107271 A TW 99107271A TW 201131712 A TW201131712 A TW 201131712A
- Authority
- TW
- Taiwan
- Prior art keywords
- lead frame
- chip package
- package structure
- flip chip
- wafer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
201131712 六、發明說明: 【發明所屬之技術領域】 本發明係有關一種覆晶(flip-chip)封裝結構,特別是關於- 種散熱型覆晶封裝結構。 【先前技術】 覆晶封裝也稱為「倒晶封裝」,是晶片封裝技術的一種。 此封裝技術有別於過糾晶料裝主要在於,以往是將晶片貼 附在墊片(chippad)上’再用打線法(wire b〇nding)將晶片與基板 上的連結點連接’而覆晶封裝是將晶片的連接點成長凸塊 _nP),然後將晶片翻轉_過來使凸塊與基板上的連結點直 接連結。覆晶封裝可以達職職干擾、電錄、最低連接電 路損耗及有效率的散熱途彳^應用於微細間距(fme沖⑻、高 頻或輸入輸_〇)腳數很乡時,覆晶技術就可以展現其優點。 未來電子產品持續朝向輕薄短小、高速、高腳數發展,以 導線架為基_傳朗裝將漸不翻,其顧範圍也將偈限於 低階/低單_產心在絲覆晶封裝展娜上,依缺會 朝^腳數、細間距的目標前進。因此,需要有散熱能力較高 的霜晶封裝结爐。 L發明内容】 之一’在於提出一種散熱型覆晶封裝結構。 根據本發明,-種散熱型覆晶封魏構包含具有引腳的導 線架,具有凸塊及晶背金屬的⑼置於該導線架下方該凸塊 201131712 在該晶片的上表面與該引腳電性連接’該晶背金屬在該晶片的 下表面’以及包覆該晶>|及該導雜的封轉體裸露出該曰 背金屬。 以曰曰 【實施方式】 圖1係本發明所使用的晶片結構,晶片1〇的連接點有凸 塊12供電性連接外部電路。除了凸塊12之外晶片⑺的背 面貼附-晶背金屬14,用以將晶片1Q的熱能往外部傳導。 圖2係本發明的第一實施例,其包含具有多個引腳162的 導線架16,以及封裝膠體18包覆凸塊12、晶片1〇之部分區 域以及導線架16之部份區域不需要像習知的覆晶封 裝被翻轉,而是直接倒置於導線架10下,引腳162和凸塊12 形成電性連接’但是還是與習知的覆晶封裝一樣具有低訊號干 擾、電性佳、最低連接電路損耗及有效率的散熱途徑等優點。 晶背金屬14裸露於封裝膠體18外,使晶片1〇直接向外部環 境散熱,因此具有更好的散熱效果。在此實施例中,導線架 16之引腳162僅部分被封裝膠體18包覆,另部分形成外引腳。 圖3係本發明的第二實施例。與圖2的實施例相同,晶片 10倒置於導線架16下,引腳162和凸塊u形成電性連接, 晶背金屬14裸露於封裝膠體外,但是此實施例之導線架 16完全被封裝膠體2〇包覆,因此無外引腳延伸到封裝膠體2〇 外,只有裸露出引腳162之部分下表面164。 圖4係圖2的實施例的應用示意圖。將圖2的覆晶封裝置 於電路板22上’晶片10透過凸塊12及引腳162與電路板22 m 4 201131712 之金屬24電性連接,晶背金屬14熱接觸電路板22上之導熱 材料26。可以將晶背金屬η焊接導熱材料%, 佈在二者之間。晶片丨。在工作期間,其產生二= 14傳遞到導熱材料26上,因此可以使晶片1〇於穩定的工作 溫度下。在其他實施例+ ’電路板22上之_材料%可直接 使用電路板22之金屬24。 以上對於本發明之較佳實施例所作的敘述係為闡明之目 的,而無意限定本發明精確地為所揭露的形式,基於以上的教 導或從本發明的實施例學習而作修改或變化是可能的,實施例 係為解說本發明的原理以及讓熟習該項技術者以各種實施例 利用本發明在實際朗上而選擇及敘述,本發_技術思想企 圖由以下的申請專利範圍及其均等來決定。 【圖式簡單說明】 圖1係本發明所使用的晶片結構; 圖2係本發明的第一實施例; 圖3係本發明的第二實施例;以及 圖4係圖2的實施例的應用示意圖。 【主要元件符號說明】 10晶片 12 .凸塊 14 晶背金屬 、 16導線架 201131712 162引腳 164引腳之下表面 18 封裝膠體 20 封裝膠體 22 電路板 .24 金屬 26 導熱材料
Claims (1)
- 201131712 七、申請專利範圍: 1. -種散熱魏覆晶封觀構人 具有引腳的導線架; 3 具有凸塊及晶背金屬的晶 片的上表面糊輪邮塊在該晶 面;以及 禪該Β日彦金屬在該晶片的下表 片及該導線架㈣_體 接觸到外部電路板上的導熱材料。稞露出m屬’使其可 2·如請求項1之覆晶封裝結構 ° 導線架之部細以及响==膠體咖凸塊、該 腳。 邛刀區域,露出該導線架之引 3.如請求項2之覆晶封裝結構,复中 部分下表面。 、封裝膠體係露出該引腳之 4. 一種如請求項1之覆晶封裝結構的應用, 金屬電性連接該引腳,以及導熱材料熱接 包含電路板,其上有 觸該晶背金屬。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW099107271A TW201131712A (en) | 2010-03-12 | 2010-03-12 | Flip chip package structure with heat dissipation enhancement and its application |
US13/043,782 US8659128B2 (en) | 2010-03-12 | 2011-03-09 | Flip chip package structure with heat dissipation enhancement and its application |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW099107271A TW201131712A (en) | 2010-03-12 | 2010-03-12 | Flip chip package structure with heat dissipation enhancement and its application |
Publications (1)
Publication Number | Publication Date |
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TW201131712A true TW201131712A (en) | 2011-09-16 |
Family
ID=44559165
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW099107271A TW201131712A (en) | 2010-03-12 | 2010-03-12 | Flip chip package structure with heat dissipation enhancement and its application |
Country Status (2)
Country | Link |
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US (1) | US8659128B2 (zh) |
TW (1) | TW201131712A (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI557813B (zh) * | 2015-07-02 | 2016-11-11 | 萬國半導體(開曼)股份有限公司 | 超薄芯片的雙面暴露封裝結構及其製造方法 |
TWI625833B (zh) * | 2016-02-25 | 2018-06-01 | 台達電子工業股份有限公司 | 封裝結構 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9437528B1 (en) | 2015-09-22 | 2016-09-06 | Alpha And Omega Semiconductor (Cayman) Ltd. | Dual-side exposed semiconductor package with ultra-thin die and manufacturing method thereof |
TWI657554B (zh) | 2015-09-30 | 2019-04-21 | 台達電子工業股份有限公司 | 封裝結構 |
DE102019120886A1 (de) * | 2019-08-02 | 2021-02-04 | Infineon Technologies Ag | Halbleitergehäuse mit einem Hohlraum in seinem Gehäusekörper |
US11955456B2 (en) * | 2021-06-30 | 2024-04-09 | Texas Instruments Incorporated | Flip chip packaged devices with thermal pad |
US20230059142A1 (en) * | 2021-08-17 | 2023-02-23 | Texas Instruments Incorporated | Flip chip packaged devices with thermal interposer |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6657311B1 (en) | 2002-05-16 | 2003-12-02 | Texas Instruments Incorporated | Heat dissipating flip-chip ball grid array |
SG142321A1 (en) * | 2008-04-24 | 2009-11-26 | Micron Technology Inc | Pre-encapsulated cavity interposer |
JP5542364B2 (ja) | 2008-04-25 | 2014-07-09 | 株式会社半導体エネルギー研究所 | 薄膜トランジスタの作製方法 |
-
2010
- 2010-03-12 TW TW099107271A patent/TW201131712A/zh unknown
-
2011
- 2011-03-09 US US13/043,782 patent/US8659128B2/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI557813B (zh) * | 2015-07-02 | 2016-11-11 | 萬國半導體(開曼)股份有限公司 | 超薄芯片的雙面暴露封裝結構及其製造方法 |
TWI625833B (zh) * | 2016-02-25 | 2018-06-01 | 台達電子工業股份有限公司 | 封裝結構 |
Also Published As
Publication number | Publication date |
---|---|
US8659128B2 (en) | 2014-02-25 |
US20110221047A1 (en) | 2011-09-15 |
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