TW201128345A - Timing adjusting module, two line transmission system and timing adjusting method - Google Patents

Abstract

The present discloses a timing adjusting module for adjusting timing and clock signals corresponding to a plurality of chips, respectively. The timing adjusting module includes a timing storage unit for storing the timing and clock signals corresponding to the plurality of chips, and a timing adjusting unit coupled to the timing storage unit for adjusting the timing and clock signals corresponding to the plurality of chips, storing the adjusted timing and clock signals into the timing storage unit, and outputting information of timing and clock signals corresponding to a chip among the plurality of chips when receiving an pointer signal of the chip.

Description

201128345 六、發明說明： 【發明所屬之技術領域】 本發明係指-種時序調整模組、二線傳輸系統及時序調榮方 法’尤指-種可分卿整複數個晶片之時序及時脈的時序調整模 組、一線傳輸系統及時序調整方法。 【先前技術】 匯流排係主裝置（maste〇與從魏置（I)之間溝通的工 具’用來進行資料、時脈、位址傳輪，分為序列式及並列式雨種。 其中，序列匯流排係將複數個資料於同_條資料線上依序傳輸(一個 時間點-個位元），而非像並列-樣由數條線一次傳輸數個位元，因 =比並舰流排節省較多針腳。在序顺流射統中，主裝置（或 攸屬a置）利肖介面電路輸出單端邏輯訊號，而從屬裝置（或主 裝置）根據邏解位_接收資料為何。其中，㈣周邊介面⑽i P eral lnterfaee ’卿及内部整合電路匯流排（I祕 C刪tBUS ’ I2C)騎見的序列式匯流排系統。 ☆舉例來說’請參考第j圖，第！圖係習知使用内部整合電路匯 流排之-系統K)之示意圖。系統1〇包含有一主裝置腳、一時脈 ’次（iock hue) CLK、-資料線（她jine) DATA及從屬裝置似」 〜SLA_N°主裝置_包含有一程式搬及一驅動單元⑽。其尹， 主裝置】〇〇另包含尹央處理器（CPU)、記憶體等，而從屬裝置SjLA j 201128345 〜SLA_N另包含有晶片chip_l〜Chip_N、記憶體等，分別用來實 現主裝置100及從屬裝置SLA_1〜SLA_N的功能，而不限於此。此 外，從屬裝置SLA_1〜SLA_N分別對應於從屬位址AddJ〜 Add_N，作為位址的指標。程式1〇2包含有相對應於從屬裝置SLAj 〜SLA_N的應用程式apPJ〜APP_N，分別用來產生控制訊號 C〇n_l〜Con—N，以控制從屬裝置SlAji〜sla—N。驅動單元1〇4 耦接於程式102，用來根據内部整合電路匯流排標準的時序及時 φ脈’透柄脈、線CLK及資料線DATA，分別將控制訊號c〇nl 〜c〇nN 依所對應的從屬位址Add—i〜Add_N傳輸至從屬裝置化八」〜 SLA—N。其巾，内部整合電龍流排標準係設定即時脈（咖⑻為 1〇〇千赫兹（KHz)、保持時間（h〇ldingtime)為15〇奈秒（仍）及 建立時間（setup time)為250奈秒。 誶細來說’請參考第2圖，第2圖為第i圖中時脈線⑽及資 4線DATA之波形示意圖。在理想狀態下，當時脈線CLK於高準 裝置SLAJ〜SLA_N可進行資料操取，因此當時脈線 二於低準位時，㈣線_可變動為下-個位摘值。外而， 於韻裝置SLAJ〜SLA—N中晶片的元件會產生邏輯延細gic :==料=中各元件傳輸時恤延遲，所以當時脈線 不應立㈣二T ㈣維持於正確準位—段時間，而 行資獅f 供從屬裝置SLA 1〜SLA N進 丁貝^ ^ W賴為，㈣外，於時脈線 為4位（即從屬裝置SLA」〜SLA_N可進行資料触）前， 201128345 資料線DATA中的資料需先達到穩態一段時間，以供從屬裝置 SLA—1〜SLA一N進行資料擷取，此段時間定義為一建立時間τ_^。 然而，使用内部整合電路匯流排標準的時序及時脈進行傳輸， 由於序及時脈係g]定的’因此在使社較缺乏彈性。舉例來說， 因應各晶片的需求’其晶片的保持時間及建立時間未必能配合内部 整合電路匯流排標準的15〇奈秒及25〇奈秒。 智知技術提出一 一種一線傳輸的技術，其與内部整合電路 匯流排的差別在於其時序非限定於⑼奈秒，即各晶片所使用的時 序（即保持時間及建立時間等）會有所不同。在此情況下，主裝置 上的内部整合電路匯流排硬體控制器或利用輸入/輸出接腳⑽ pms)她之軟體控繼無法與使料同時相晶片_。如此一 ，’由於内部整合電路匯流排硬體控制器通常無法調整其時序（如 rjrm7and8seriesplatfom) j ^bf 輸出接腳雛讀體㈣器㈣序，使其符合 訂下一個通用的時序。 而水以 ςτΔ , ^ 不同晶片的時序互斥，如從屬^ 一中晶片的最大保持時間為 片最小雜_ * 子間為300奈秒，而從屬褒置SLA 2 t 最J保持時間為400奈秒，造成無法找到一 - 由於對輸入/輸出針腳模擬 T此. 來達成，因此-旦遇到中_制轉時序的控婦、利用約 遇到中斷ame卿tM麵财縣搶佔（恤 201128345 P__)功趣鳩統下’可能細其它具有較高優先順序的 工作奪取控卿。如此-來’針對較敏感的保持時間，就有可能拉 大其時間。另外，為了節省電源消耗，部分微處理器㈤啊·謹） 利用二線傳輸與主機溝通時，會降低鱗脈，而無法接受内部整合 電路匯流排標準100千赫茲的時脈。 因此，習知技術在面對不同晶片組合時，必須調整出不同的通 用時序，非常耗費時間’而且有可能根本無法找到可以通用的時序； 對於不需用到漏千赫兹的裝置，亦無法減少其時脈，造成不必要 的電源消耗。有鑑於此，習知技術實有改進之必要。 【發明内容】 因此，本發明之主要目的即在於提供—種可分別調整複數個晶 片之時序及時脈的時序罐難、二線傳齡統及時序調整方法。 本發明揭露-種時序調整模組，用於分別調整複數個晶片之時 序及時脈。該時序調整模組包含有—時序儲存單元，用來儲存該複 數個晶>1所分卿應之時序及雜；以及—時序調整單元，耗接於 該時序儲存單元，用_整該複數個“所分別對應之時序及時脈 並儲存於該時序儲存單元，且於接_對應於該複數個晶片之一晶 片的一指標訊號時，輸出該晶片所對應之時序及時脈之資訊。 本發明另揭露-種二線傳輸系統，包含有複數個I置，包含有 201128345 複數個阳片，複數個應用程式，對應於該複數個裝置；一驅動單元， 透過一時脈線及一資料線耦接於該複數個裝置，用來於接收到該複 數個應用程式之-應用程式所傳送的—控制訊號時，輸出該應用程 式所對應之的-指標城，並根據該；所對應之時序及時 脈，傳送該控制訊號至該晶片所屬之裝置；以及一時序調整模組，、 執接於該驅動單元’祕分別調㈣複數個晶片之時序及時脈。該 時序調整模組包含有_時序齡單元，峰儲存織數個晶片所^ 別對應之時序及時脈；以及-時序調整單元，祕於辦序儲存 元，用來罐紐數個晶丨所分麟應之鱗及時脈麵存於該時 序儲存單元，且於接收到該應用程式所對應該晶⑽指標訊號時了 輪出該晶片所對應之時序及時脈之資訊至該驅動單元。 -本發明另揭露-種時序調整方法，用於一二線傳輸系統中，該 -線傳輸纽包含有複數個晶# ’辦糊整方法包含有調整該複 數個晶片所分麟應之時序及時脈；儲存職數個晶片齡麟應 之吩序及時脈；以及於接收到對應於該複數個晶片之—晶片的一指 標訊號時，輸出該晶片所對應之時序及時脈之資訊。 【實施方式】 立請參考第3圖’第3圖為本發明實施例一二線傳輸系統％之示 思圖。二線傳輸系、统30包含有一主裝置3〇〇、一時脈、線（d〇ck —) CLK、一資料線（dataline) DATA及從屬裝置SLAJ〜SLA__N。主 袈置300包含有一程式302、一驅動單元3〇4及一時序調整模組 201128345 306 ’其中，主裝置另包含中央處理器⑽⑴、記憶體等，而 攸屬裝置SLA—1〜SLA—N另包含有晶片Chip—、記憶體 等刀別用來貝現主裝置3〇〇及從屬裝置sla—^〜见IN的功能， 而不限於此此外，k屬裝置SLA—i〜SLA_N分別對應於從屬位址 Add_l Add—N ’作為位址的指標^程式孤包含有相對應於從屬 裝置SLA—1〜SLA-N的應用程式APP—1〜APP—N，分別用來產生 控制訊號Con_l〜c〇n N，以押制從眉奘罟ςΤ λ -Μ衩制從屬裝置SLA__1〜SLA_N。驅動 鲁單元304麵接於程式3〇2，其可以係一軟體控制器，用來於接收到 相對應於應用財APP—卜継—N之一應用程式妍―χ所產生的 控制訊號Con_x時’輸出應用程式聊—χ所對應之晶片chip—x的 從屬位址Add—x至時序調整模組3〇6，以取得Chip—X所對應之時序 及時脈之資訊’並根據晶片Chip_x所對應之時序及時脈，傳送控制 訊號Con—X至晶片Chip_x所屬之從屬裝置SLA—X。時序調整模組 306包含有-時序儲存單元3〇8及一時序調整單元·。時序儲存單 鲁兀删用來儲存晶月Chip—!〜chip_N所分別對應之時序及時脈。 時序調整單元31〇_辦序赫單元，用_整晶# (㈣」〜201128345 VI. Description of the Invention: [Technical Field of the Invention] The present invention refers to a timing adjustment module, a two-line transmission system, and a timing adjustment method, which are particularly useful for timing and time-sharing of a plurality of chips. Timing adjustment module, first-line transmission system and timing adjustment method. [Prior Art] The bus master device (a tool for communication between the masse and the slave (I) is used for data, clock, and address transmission, and is divided into serial and side-by-side rain. The sequence bus system transmits multiple data in sequence on the same data line (one time point - one bit), instead of juxtaposed - like several lines transmitted by several lines at a time, because of the ratio of the ship The row saves more pins. In the sequential flow system, the master device (or the slave device) outputs the single-ended logic signal, and the slave device (or the master device) receives the data according to the logic bit_. Among them, (4) Peripheral interface (10) i P eral lnterfaee 'Qing and internal integrated circuit bus (I secret C deleted tBUS 'I2C) riding the serial bus system. ☆ For example, please refer to the j chart, the first! A schematic diagram of the use of an internal integrated circuit bus-system K) is known. The system 1 includes a master device, a clock, an iphone hue CLK, a data line (her jine) DATA, and a slave device. The SLA_N° master device includes a program and a drive unit (10). The yin, the main device 〇〇 further includes a Yinyang processor (CPU), a memory, etc., and the slave devices SjLA j 201128345 ～ SLA_N further include a chip chip_l~Chip_N, a memory, etc., respectively, for implementing the main device 100 and The functions of the slave devices SLA_1 to SLA_N are not limited thereto. Further, the slave devices SLA_1 to SLA_N correspond to the slave addresses AddJ to Add_N, respectively, as indices of the address. The program 1〇2 includes application programs apPJ~APP_N corresponding to the slave devices SLAj~SLA_N for generating control signals C〇n_l~Con-N, respectively, to control the slave devices SlAji~sla-N. The driving unit 1〇4 is coupled to the program 102, and is configured to control the signals c〇nl~c〇nN according to the timing of the internal integrated circuit bus bar standard in time, the pulse path, the line CLK and the data line DATA. The corresponding slave addresses Add_i~Add_N are transferred to the slave device eight"~SLA-N. Its towel, the internal integrated electric dragon flow standard system sets the instant pulse (coffee (8) is 1 〇〇 kHz (KHz), hold time (h〇ldingtime) is 15 〇 nanosecond (still) and setup time is set 250 nanoseconds. 谇In detail, please refer to Figure 2, Figure 2 is a waveform diagram of the clock line (10) and the 4-line DATA in the i-th picture. Under ideal conditions, the pulse line CLK is at the Micro-level device SLAJ. ~SLA_N can be used for data manipulation. Therefore, when the pulse line is at the low level, the (4) line _ can be changed to the next-bit value. In addition, the components of the chip in the SNAJ~SLA-N will generate logic. Delayed gic :==Material = The delay of the shirts in the transmission of each component, so the pulse should not be established at the time (4) 2 T (4) maintained at the correct level - the time, while the lion f is for the slave device SLA 1~SLA N Dingbei ^ ^ W Laiwei, (4) outside, before the time line is 4 (ie slave device SLA) ~ SLA_N can be touched), the data in the data line DATA of 201128345 must first reach steady state for a period of time The slave devices SLA-1 to SLA-N perform data acquisition, and this period of time is defined as a setup time τ_^. The timing and time-sharing of the integrated circuit bus standard is transmitted. Because of the orderly and timely pulse system, the company is less flexible. For example, depending on the requirements of each chip, the holding time and setup time of the chip may not be able to With 15 ns nanoseconds and 25 〇 nanoseconds of the internal integrated circuit bus standard. Zhizhi technology proposes a one-line transmission technology, which differs from the internal integrated circuit bus in that its timing is not limited to (9) nanoseconds. The timing used by each chip (ie, hold time and setup time, etc.) will vary. In this case, the internal integrated circuit on the master device is connected to the hardware controller or using the input/output pin (10) pms) The software control can not be simultaneously phased with the material. As a result, the internal integrated circuit bus hardware controller can usually not adjust its timing (such as rjrm7and8seriesplatfom) j ^bf output pin read body (four) device (four) sequence, so that it meets the next general timing. The water is mutually exclusive with the timing of 晶片τΔ, ^ different wafers. For example, the maximum holding time of the wafer in the subordinate is one of the minimum miscellaneous _ * between 300 nanoseconds, and the maximum holding time of the subordinate SLA 2 t is 400 nanometers. Seconds, caused by the inability to find one - due to the input / output pin simulation T this. To reach, so - encountered the mid- _ system rotation of the control of the woman, the use of the encounter encountered interrupt ame Qing tM face Caixian preemption (shirt 201128345 P__ Under the fun-filled system, it is possible to take advantage of other high-priority jobs to seize the control. So-to's for a more sensitive hold time, it is possible to increase its time. In addition, in order to save power consumption, some microprocessors (five) ah.) When using the two-wire transmission to communicate with the host, the scale will be reduced, and the internal integrated circuit busbar standard 100 kHz clock will not be accepted. Therefore, the conventional technology must adjust different common timings in the face of different chip combinations, which is very time consuming and may not find a universal timing at all; it cannot be reduced for devices that do not need to use a kilohertz. Its clock causes unnecessary power consumption. In view of this, the prior art has been improved. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a timing tank difficulty, a second-line ageing system, and a timing adjustment method for separately adjusting the timing and time of a plurality of wafers. The invention discloses a timing adjustment module for separately adjusting the timing and time of a plurality of chips. The timing adjustment module includes a timing storage unit for storing timings and impurities of the plurality of crystals, and a timing adjustment unit, which is consumed by the timing storage unit, and uses the _ integer The respective timings and clocks are stored in the timing storage unit, and when the information signal corresponding to one of the plurality of wafers is connected, the information corresponding to the timing and time pulse corresponding to the wafer is output. A second-line transmission system includes a plurality of I-positions, including a plurality of 201128345 plurality of positive images, a plurality of applications corresponding to the plurality of devices, and a driving unit coupled through a clock line and a data line And the plurality of devices are configured to, when receiving the control signal transmitted by the application of the plurality of applications, output the indicator city corresponding to the application, and according to the timing and time corresponding to the application; And transmitting the control signal to the device to which the chip belongs; and a timing adjustment module, which is connected to the driving unit to secretly adjust (4) the timing and time of the plurality of chips. The sequence adjustment module includes a chronological age unit, the peak stores a number of wafers corresponding to the timing and time pulse; and - the timing adjustment unit, the secret storage unit, used to count the number of wafers The scale and the pulse face are stored in the timing storage unit, and when the application receives the indicator signal corresponding to the crystal (10), the information corresponding to the timing and time of the wafer is rotated to the driving unit. Exposing a timing adjustment method for a two-wire transmission system, the line transmission button includes a plurality of crystals, and the method includes: adjusting a timing and a pulse of the plurality of wafers; A plurality of wafer ages are ordered and timed; and when an indicator signal corresponding to the plurality of wafers is received, the timing and time information corresponding to the wafer is output. [Embodiment] Please refer to 3 is a schematic diagram of a second-line transmission system according to an embodiment of the present invention. The second-line transmission system 30 includes a main device 3〇〇, a clock, and a line (d〇ck —) CLK. Data line DAT A and slave devices SLAJ~SLA__N. The main device 300 includes a program 302, a driving unit 3〇4, and a timing adjustment module 201128345 306 'where the main device further includes a central processing unit (10) (1), a memory, etc. The devices SLA-1 to SLA-N further include a chip Chip, a memory, and the like for the function of the main device 3 and the slave device sla-^~IN, and are not limited thereto. SLA_i~SLA_N respectively correspond to the subordinate address Add_l Add_N ' as an index of the address ^ program orphans corresponding to the application devices APP-1 to APP-N corresponding to the slave devices SLA-1 to SLA-N, respectively It is used to generate the control signals Con_l~c〇n N to control the slave devices SLA__1~SLA_N from the eyebrows λ-Μ衩. The driver unit 304 is connected to the program 3〇2, which can be a software controller for receiving the control signal Con_x generated by the application application 継 N N 'Output application chat-χ corresponds to the slave chip address of the chip chip-x Add-x to the timing adjustment module 3〇6, to obtain the information of the timing and time pulse corresponding to the Chip-X' and corresponding to the chip Chip_x The timing and timing of the transmission control signal Con_X to the slave device SLA_X to which the chip Chip_x belongs. The timing adjustment module 306 includes a timing storage unit 〇8 and a timing adjustment unit. The timing storage list is used to store the timing and time pulse corresponding to the crystal moon Chip-!~chip_N. Timing adjustment unit 31 〇 _ ordering unit, using _ 晶晶# ((4) ”~

Chip—Ν所分別對應之時序及時脈並儲存於時序儲存單元細，且於 接收到應用程式APP_X所對應晶片Chip—χ的從屬位址Ad(x時， 輸出晶片Chip—X所對應之時序及時脈之資訊至驅動單元3(w。如此 一來，藉由使用不同時序及時脈傳送不同晶片ChipJ〜Chip—N的 控制訊號CGn_l〜Con__N，二線傳齡統3〇不但可以省去找出一個 通用時序所需的資源，同時可以使用較省電的時脈進行傳輸。 201128345 簡單來說’二線傳輪系 僂給系铋川极^ U^、白知系統10相異之處在於二線 調咖獅铸輕單元310Chip-Ν corresponds to the timing and time-sharing and is stored in the timing storage unit, and when receiving the slave address Ad of the chip Chip_ corresponding to the application APP_X (x, the output chip Chip-X corresponds to the timing in time) The information of the pulse is sent to the driving unit 3 (w. Thus, by using different timings and clocks to transmit the control signals CGn_l~Con__N of different chips ChipJ~Chip-N, the second-line ageing system can not only find one. The resources required for general-purpose timing can be transmitted at the same time with the power-saving clock. 201128345 Simply speaking, the 'two-line transmission system is given to the 铋川极^ U^, and the Baizhi system 10 is different in the second line.调咖狮铸轻单位310

Chin 1-Ph· 一斤刀別對應之時序及時脈，進而將晶片 -〜1P—所分別對應之時序及時脈 Add」〜Add + 貝l刀刊以從屬位址 〇〇 ~ ”、、 ‘儲存於時序儲存單元308。在此情況下，舍 驅動單兀304接收到控制訊號— _ 田 至時序T ^㈣傅如屬位址Add_x 休_組306，以獲得晶片啊―χ所對應 訊，並根據晶片Chip χ所料痛々〇士 e 斤物脈之貝Chin 1-Ph· A pound of knife does not correspond to the timing and time pulse, and then the wafer - ~ 1P - corresponding to the timing and time pulse Add" ~ Add + shell l knife to the subordinate address 〇〇 ~ ”, 'storage In the timing storage unit 308. In this case, the switch driver unit 304 receives the control signal _ field to the timing T ^ (four) Fu as the address Add_x Hugh _ group 306, to obtain the wafer χ χ 对应 对应, and According to the chip Chip, the pain of the gentleman

至” rh. P-X所對應之時序及時脈’傳送控制訊號C〇n X h曰片ChlP—X所屬之從射置SLA—X。如此一來，不-貧源找出一個通用昧皮_. 个而耗費 寺序，同時可以使用較省電的時脈進行傳輸。 可歸納為一流裎40，如 詳細來說，二線傳輸系統3〇之運作 第4圖所示，包含以下步驟： 步驟402 :間始。To "Rh. PX corresponds to the timing and time pulse" transmission control signal C〇n X h C ChlP-X belongs to the SLA-X from the shot. So, do not - poor source to find a universal suede _. It consumes the temple sequence and can be transmitted using a more power-saving clock. It can be summarized as a first-class 裎40. For details, the operation of the second-line transmission system is shown in Figure 4, which includes the following steps: Step 402 : Beginning.

步驟404 .應用程式Αρρ—Χ傳送控制訊號c〇m驅動單元 3〇4 〇 至日才序調整模組Step 404. The application Αρρ-Χ transmits the control signal c〇m drive unit 3〇4 〇 to the day order adjustment module

X 步驟406 :驅動單幻04傳送從屬位址Add 306 步驟4〇8 :，序調整模組3〇6依從雜址-ο判斷時序儲存 早tl 308中是否存有晶片Chip—乂所對應之時序及時 脈之資訊。若是，則進行步驟420 ;若否，則進行步 驟 410。 步驟410 :時序調整模組306預設晶片Chip一X的—保持時間 10 201128345X Step 406: Driving the Single Magic 04 Transfer Slave Address Add 306 Step 4〇8: The sequence adjustment module 3〇6 follows the stray address-o to determine whether the timing of the chip Chip-乂 is stored in the early t1 308. Timely information. If yes, proceed to step 420; if no, proceed to step 410. Step 410: The timing adjustment module 306 presets the chip Chip-X-hold time 10 201128345

TjioW為150奈秒、一時脈F—d〇ck為動千赫兹。 -中建立時間T—set視為時脈低準位周期（cl〇ck bwcycle)減去保持時間T_>〇ld。 步驟412 :判斷時脈㈣淡是否低於—50千_。若是，進行 步驟422 ;若否，則進行步驟414。 步驟414 :判斷建立時間W是否低於MO奈秒。若是，將時 脈F一clock減少1〇千赫茲後進行步驟412 ;若否， • 則進行步驟416。 步驟416 .根據保持時間T—h〇ld及時脈F—也成傳送一調整訊 號Adj至晶片chip_x ’並判斷是否收到晶片chip_x 所回傳之一確認碼（Ackn〇wiedgement，ACK)ACK， 若是，則進行步驟418 ;若否，將建立時間T_set增 加100奈秒後進行步驟414。其中，增加建立時間 T_set可視為減少建立時間T_set。 • 步-418 :將保持時間T_hold及時脈F_clock設為晶片Chip_x 所對應之時序及時脈，並與從屬位址Add_x儲存於 時序儲存單元308中。 步驟420 :驅動單元3〇4根據晶片chip_x所對應之時序及時 脈，傳輸控制訊號Con_x至晶片Chip_x所屬之從屬 裝置SLA_x。 步驟422 :結束。 流程40詳細說明二線傳輸系統3〇在測試並儲存各晶片所對應 11 201128345 守序及日视的資訊的操作流程 用時序，同時可以使用較省_ 士 ·她作，不需找出一個通 曰曰片所能運作的最小保持時間，使得軟進步付到各 間。值得注意的是，流程40僅為本發明卜，、有車父大的緩衝時 精神她彳物存⑷觸紅啦主要 知式欲傳紐制訊號時，使 $ § ''於應用 輪，凡依此概念衍生之系統，皆屬= 時脈進行傳 程中時序^^恤的預設值來進行輕，而調整過 寸序及¥脈调整的幅度亦可改變，只要 =:序:時脈的資訊即可。再者，流程”二^ 際^可在附smrr時序及時脈進行調整並储存，實 谓裝置-接上即進行晶片之時序糾脈調整並儲存， 4可名去_是否有儲存“之時序鱗脈㈣訊的步驟。 —根據本發明之精神，流㈣可更進—步歸納為—流㈣，如 弟5圖所不，包含以下步驟： 步驟500 :開始。TjioW is 150 nanoseconds, and one clock F-d〇ck is moving kilohertz. - The medium setup time T-set is regarded as the clock low level period (cl〇ck bwcycle) minus the hold time T_>〇ld. Step 412: Determine whether the clock (four) is lighter than -50 thousand _. If yes, proceed to step 422; if no, proceed to step 414. Step 414: Determine whether the establishment time W is lower than MO nanoseconds. If yes, step 412 is performed by reducing the clock F clock by 1 kHz; if not, then proceeding to step 416. Step 416. According to the hold time T-h〇ld, the pulse F-also transmits an adjustment signal Adj to the chip chip_x' and determines whether a confirmation code (Ackn〇wiedgement, ACK) ACK is returned from the chip chip_x, if Then, step 418 is performed; if not, the setup time T_set is increased by 100 nanoseconds and then step 414 is performed. Among them, increasing the setup time T_set can be regarded as reducing the setup time T_set. • Step-418: Set the hold time T_hold and the pulse F_clock to the timing and time corresponding to the chip Chip_x, and store it in the timing storage unit 308 with the slave address Add_x. Step 420: The driving unit 〇4 transmits the control signal Con_x to the slave device SLA_x to which the chip Chip_x belongs according to the timing and time corresponding to the chip chip_x. Step 422: End. The process 40 details the timing of the operation flow of the second-line transmission system 3 in testing and storing the information of the 11 201128345 sequence and the daily view of each wafer, and can be used by the province _ 士············· The minimum hold time that the cymbal can operate allows soft progress to be paid to each. It is worth noting that the process 40 is only the present invention, and the spirit of the car's father is buffered when she saves the object (4) touches the red. The main knowledge is that when the message is transmitted, the $ § '' is applied to the application wheel. The system derived from this concept is = the default value of the timing ^^ shirt in the time of the transmission, and the amplitude of the adjusted order and the pulse adjustment can also be changed, as long as =: sequence: clock Information can be. In addition, the process "two ^ ^ ^ can be adjusted and stored in the smrr timing and pulse, the actual device - connected to the wafer timing correction and storage, 4 can be named _ whether there is a storage of "time scales The steps of the pulse (four). - In accordance with the spirit of the present invention, stream (4) can be further advanced into a stream (four), as shown in Figure 5, including the following steps: Step 500: Start.

步驟502 ·輕㉟$ ChipJ〜啊―崎分騎應之時序及時脈。 步驟504.錯存晶片Chip—j〜chip_N所分別對應之時序及時脈。 步驟5〇6於接收到對應於晶片ChiP_l〜Chip一N之晶片Chip—X 的從屬位址Add—X時’輸出晶片Chip—X所對應之時 序及時脈之資訊。 >^驟8驅動單元304根據晶片Qiip_x所對應之時序及時 201128345 脈’傳輸控制訊號con_x 步驟510:結束。 - 關 於流程％可參考上述制，在此不再贅述 在W技射’面對不同晶片組合時，必須調整出不同的通用 二’非常耗費時間，而且無法減少其時脈，造成不必要的電源消 ^ ° ^較之下’本發明彻不同時序及時脈傳送不同晶片的控制訊 來，.不但不需找出—個通科序，同時可以使用較省電 制::有::輸:更可以利用最小保持時間進行傳輸，使得軟體控 钔。0具有車父大的緩衝時間。 電的t所述，本發明不需找出—個通用時序，同時可以使用較省 Μ進仃傳輸’更可赠軟體控制雜持時間具有較大的緩衝。 以上所述僅為本發明之較佳實施例，凡依本發明申 所做之均等變倾修飾，皆麵本發明之涵蓋範圍。 耗圍 【圖式簡單說明】 21圖係習知使用内部整合電路匯流排之H示 第2圖為第i圖中時脈線及資料線之波形示意圖。〜 第3圖為本發明實施例—二線傳輸系統之示意圖。 第4圖為本發明實施例之一流程之示意圖。 13 201128345 第5圖為本發明實施例之一流程之示意圖。 【主要元件符號說明】 10 系統 100、300 主裝置 102 、 302 程式 104 、 304 驅動單元 30 二線傳輸糸統 306 時序調整模組 308 時序儲存單元 310 時序調整單元 40、50 流程 402〜422、500〜510 步驟 CLK 時脈線 DATA 資料線 SLA—1 〜SLA_N 從屬裝置 Add_l 〜Add_N 從屬位址 Chip— 1 〜Chip_N 晶片 APP—1 〜APP_N 應用程式 Con_l 〜Con—N 控制訊號 T_hold 保持時間 T_set 建立時間 F clock 時脈 14Step 502 · Light 35$ ChipJ~ ah-Saki-Kan rides the timing and timeliness. Step 504. The timing and time pulse corresponding to the chip-J~chip_N are respectively stored. Step 5〇6 outputs the information of the timing and time corresponding to the chip Chip_X when receiving the slave address Add_X corresponding to the chip Chip_X of the chips ChiP_1 to Chip-N. > Step 8 driving unit 304 according to the timing corresponding to the chip Qiip_x in time 201128345 pulse 'transmission control signal con_x step 510: end. - For the process %, please refer to the above system. It is not mentioned here that in the case of W technology, when facing different chip combinations, it is necessary to adjust different common two's very time-consuming, and it is impossible to reduce the clock and cause unnecessary power supply.消 ^ ° ^ lower than 'the invention of different timings and timely transmission of different wafer control signals, not only need not find out - a general order, at the same time can use more power-saving system:: have:: lose: more The minimum hold time can be used for transmission, so that the software is controlled. 0 has a buffer time of the car father. According to the electrical t, the present invention does not need to find a common timing, and can use the more advanced transmission to transmit the software to control the hybrid time with a larger buffer. The above description is only the preferred embodiment of the present invention, and the equivalent modifications of the present invention are within the scope of the present invention. Consumption (simplified diagram) 21 diagram is known to use the internal integrated circuit bus H shown in Figure 2 is the waveform diagram of the clock line and data line in the i-th figure. ~ Figure 3 is a schematic diagram of a second-line transmission system according to an embodiment of the present invention. Figure 4 is a schematic diagram of a flow of an embodiment of the present invention. 13 201128345 FIG. 5 is a schematic diagram of a flow of an embodiment of the present invention. [Main component symbol description] 10 System 100, 300 Main device 102, 302 Program 104, 304 Drive unit 30 Second-line transmission system 306 Timing adjustment module 308 Timing storage unit 310 Timing adjustment unit 40, 50 Flow 402~422, 500 ~510 Step CLK Clock Line DATA Data Line SLA-1~SLA_N Slave Address Add_l~Add_N Slave Address Chip-1~Chip_N Chip APP-1~APP_N Application Con_l~Con-N Control Signal T_hold Hold Time T_set Setup Time F Clock clock 14

Claims (1)

201128345 七、申請專利範圍： ’種時序織歡，贿分職整複數個 包含有： 曰曰 片之時序及時脈， 別對應之時序及 時序儲存單70，絲儲存該複數個晶片所分 時脈；以及 日==^接_物椒，物整該複數個 9刀1U應之時序及時脈並儲存於該時序儲存單元， 收到對應於該複數個晶片之一晶片的一指標訊號 夺’輸出該晶片所對應之時序及時脈之資訊。 2. • 求項1所述之時序調整模組，其中該時序調整單元調整該 複數個曰曰片所分別對應之時序及時脈係根據一時序及一時脈傳 送°周整°孔號1帛—晶片，並於收到該第-晶片所回傳之-CAeknowle(igement ’ ACK)時，將該第一晶片所對應之 時序及時脈儲存於該時序儲存單元。 4.如请求項3所述之時序調整模組，其巾該時序包含有___保持時 間（holdingtime)及一建立時間（setuptime)。 15 201128345 5. ^ M 4所述之時糊整模組，其巾該保持時間及 預設值分聰轉_隐電路（_德㈣_ = 規格的150奈秒㈤及謂千赫兹（KHz)。 6·如請求項5所述之時序調整模組，其中於未收到該第-晶片所 回傳之輕碼時，增加該保持時間的長度，並根據該保持時間 及5玄時脈傳送該調整訊號至該第—晶片。 7. 2請求項6所述之時序調整模組，其中於該建立時間小於—第_ -預設值時’減少該時脈的頻率且調整該保持時間為該預設 值，並根據該保持時間及該時脈傳送該調整訊號至該第一晶片。 8·如請求項7所述之時序調整模組，其中該第一預設值為符合内 部整合電路規格的250奈秒。 9· 種-一線傳輸糸統，包含有： 複數個裝置，包含有複數個晶片； 聋數個應用程式’用來產生複數個控制訊號，以控制該相對應 複數個裝置； ~ 一驅動單元，耦接於該複數個應用程式並透過一時脈線（d〇ck line)及一資料線（dataline)耦接於該複數個裝置，用來 於接收到相對應該複數個應用程式之一應用裎式的一控制 訊號時，輸出該應用程式所對應之一晶片的—指標訊號， 16 201128345 並根據該晶片所對應之時序及時脈，傳送該控制訊號至該 晶片所屬之裝置；以及 一時序調麵組，雛_驅解元，崎分綱整該複數個 晶片之時序及時脈，包含有： 時序儲存單元，用來儲存該複數個晶片所分別對應之時 序及時脈；以及 -時序調整單元’触於鱗序儲存單元，絲調整該複 數，晶片所分別對應之時序及時脈並儲存於該時序儲 存單元，且於接收到該應用程式所對應該晶片的指標 讯遽時’輸出該晶騎應之時序及時脈之資訊至該 驅動單元。 如明求項9所述之二線傳輸系統，其中該驅動單元係—軟體。 U.如請求項9所述之二線傳輸系統，其中該指標訊號係-對庫於 遠晶片的從屬位址（slaveaddrcss)。 9所述之二線傳輸系統，其中該時序調整單元調整該 、,阳片所”別對應之時序及時脈雜據—時序及一時脈傳 訊號至-第—晶片，並於收到該第—晶片所回傳之一 時:及I rledgement，ACK)時’將該第一晶片所對應之 時序及時脈儲存於鱗序儲存單元。 17 201128345 13.如請求項12所述之二線傳輸系統，其_該時序包含有—保待聍 間（holdmg time)及一建立時間（_ρ iime)。 卞 I4·如請求項I3所述之二線傳輸系統’其中該保持時間及該時脈 預設值分別為符合内部整合電路（imer_integ論杨她，斤） 規格的150奈秒（ns)及1〇〇千赫茲（jQjz)。 15.如請求項Μ所述之二線傳輸系統，其中於未收到該第一晶片所 回傳之確認碼時’增加該保持時間的長度，並根據該保持時間· 及該時脈傳送該調整訊號至該第一晶片。 16·如請求項15所述之二線傳輸魏，其中於該建立時間小於一第 一預設值時，減少該時脈的頻率且調整該保持時間為該預設 值’亚根據該保持時間及該時脈傳送該調整訊號至該晶片。 Π.如請求項16所述之二線傳輪系統，其中該第一預設值為符合内# 部整合電路規格的250奈秒。 18. 一種時序輕方法，用於—二線傳輸系統中， 包含有複數個晶片，該時序調整方法包含有： 該二線傳輸系統 調整該複數個晶片所分別對應之時序及時脈； 儲存該複數個晶片所分別對應之時序及時脈； 於接收到對應於該複數個晶 片之一晶片的一指標訊號時 18 201128345 輸出該晶片所對應之時序及時脈之資訊；以及 驅動單元根據該晶片所對應之時序及時脈，進行一控制 訊號的傳輸。 19.如凊求項1S所述之時序調整方法，其中該指標訊號係一對應於 該晶片之從屬位址（slave address )。 籲2〇.如响求項I8所述之時序調整方法，其中調整該複數個晶片所分 別對應之時序及時脈包含有； 根據-時序及-時脈傳送—調整訊號至―第—晶片；以及 於收到該第-晶片所轉之—確認碼（AeknGwledgement， ACK)時’儲存該第—晶片所對應之時序及時脈。 21·如請求項2〇所述之時序調整方法，其中該時序包含有-保持時 • 間（h〇1dingtlme)及—建立日HHsetuptime)。 22.如請求項21所述之時序調整方法，其中該保持時間及該時脈的 予員設值分別為符合内部整合電路（inter s㈣d circuit，如 規格的150奈秒（ns)及100千赫兹（KHz)。 23.如請求項22所述之時序調整方法，其中於未收到該第一晶片所 回傳之確認碼時，增加該簡時_長度，絲據該保持時間 及該時脈傳送該調整訊號至該第_晶片。 19 201128345 24. 如請求項23所述之時序調整方法，其中於該建立時間小於一第 一預設值時，減少該時脈的頻率且調整該保持時間為該預設 值，並根據該保持時間及該時脈傳送該調整訊號至該第一晶片。 25. 如請求項24所述之時序調整方法，其中該第一預設值為符合内 部整合電路規格的250奈秒。 八、圖式· 20201128345 VII. The scope of application for patents: 'A kind of time series weaving, bribes and divisions include a series of time series and time series, and the corresponding timing and time series storage list 70, the silk stores the clocks of the plurality of wafers. And day ==^ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Information about the timing and timing of the wafer. 2. The timing adjustment module of claim 1, wherein the timing adjustment unit adjusts the timing and time-cord of the plurality of cymbals respectively according to a timing and a clock transmission. The chip, and receiving the CAEKnowle (igement ' ACK) returned by the first chip, stores the timing and time corresponding to the first chip in the timing storage unit. 4. The timing adjustment module of claim 3, wherein the timing includes a ___holding time and a setup time. 15 201128345 5. ^ At the time of M 4, the paste module has its holding time and preset value. The hidden circuit (_de (four)_ = 150 nanoseconds (five) and the kilohertz (KHz). The timing adjustment module of claim 5, wherein the length of the hold time is increased when the light code returned by the first chip is not received, and the time is transmitted according to the hold time and the 5th clock Adjusting the signal to the first wafer. 7. The timing adjustment module of claim 6, wherein when the settling time is less than - the first predetermined value, the frequency of the clock is decreased and the holding time is adjusted. a preset value, and transmitting the adjustment signal to the first chip according to the hold time and the clock. 8. The timing adjustment module according to claim 7, wherein the first preset value conforms to an internal integrated circuit specification 250 nanoseconds. 9. The first-line transmission system includes: a plurality of devices including a plurality of chips; and a plurality of applications 'for generating a plurality of control signals to control the corresponding plurality of devices; ~ a driving unit coupled to the plurality of applications and And a plurality of devices coupled to the plurality of devices for outputting the control signal when a control signal corresponding to one of the plurality of applications is received through the d〇ck line and the data line The program corresponds to one of the wafer-index signals, 16 201128345 and transmits the control signal to the device to which the wafer belongs according to the timing and time corresponding to the chip; and a timing adjustment group, the young_dissolving element, the Aligning the timing and time of the plurality of chips, comprising: a timing storage unit for storing timing and time corresponding to the plurality of chips; and - the timing adjustment unit is adapted to the scale storage unit, and adjusting the plurality The corresponding timing and time of the chip are stored in the timing storage unit, and when the indicator information corresponding to the chip is received by the application, the information of the timing and time of the crystal ride is output to the driving unit. The second-line transmission system of claim 9, wherein the driving unit is a software. U. The second-line transmission system of claim 9, wherein the finger The signal system is a slave address of the remote chip (slaveaddrcss). The second-line transmission system described in the above, wherein the timing adjustment unit adjusts the timing, time and pulse of the positive film, and the timing and time. The pulse signal is transmitted to the first-order wafer and the time-series corresponding to the first wafer is stored in the scale storage unit when receiving one of the first wafers: and I rledgement (ACK). 201128345 13. The second-line transmission system of claim 12, wherein the timing includes a holdmg time and a settling time (_ρ iime).卞I4· The second-line transmission system as described in claim I3, wherein the hold time and the preset value of the clock are 150 nanoseconds (ns) and 1 respectively in accordance with the internal integrated circuit (imer_integ on Yang she, kg) specifications 〇〇 kHz (jQjz). 15. The second-line transmission system of claim 1, wherein the length of the hold time is increased when the confirmation code returned by the first chip is not received, and the time is transmitted according to the hold time and the clock Adjust the signal to the first wafer. The second-line transmission Wei as claimed in claim 15, wherein when the settling time is less than a first preset value, the frequency of the clock is decreased and the hold time is adjusted to be the preset value, according to the hold time. And the clock transmits the adjustment signal to the chip. The two-wire transmission system of claim 16, wherein the first preset value is 250 nanoseconds in accordance with the specifications of the internal integrated circuit. 18. A timing method for use in a two-wire transmission system, comprising a plurality of wafers, the timing adjustment method comprising: the two-wire transmission system adjusting timing, time and pulse corresponding to the plurality of wafers; storing the plurality Each of the wafers corresponds to a timing and time pulse; when receiving an index signal corresponding to one of the plurality of wafers, 18 201128345 outputs the timing and time information corresponding to the wafer; and the driving unit corresponds to the wafer The timing and timing are used to transmit a control signal. 19. The timing adjustment method of claim 1, wherein the indicator signal corresponds to a slave address of the chip. The method of timing adjustment according to the item I8, wherein adjusting the timing and time corresponding to the plurality of chips respectively comprises: adjusting the signal to the first chip according to the - timing and - clock transmission; When receiving the confirmation code (AeknGwledgement, ACK) transferred by the first wafer, the timing and time corresponding to the first wafer are stored. 21. The timing adjustment method as claimed in claim 2, wherein the timing includes -holding time (h〇1dingtlme) and - establishing day HHsetuptime). 22. The timing adjustment method of claim 21, wherein the hold time and the set value of the clock are respectively conformed to an internal integrated circuit (inter s (d) d circuit, such as 150 nanoseconds (ns) and 100 kHz of the specification (KHz) 23. The timing adjustment method of claim 22, wherein the chronological length is increased when the acknowledgment code returned by the first chip is not received, and the retention time and the clock are The timing adjustment method according to claim 23, wherein when the settling time is less than a first preset value, the frequency of the clock is decreased and the hold time is adjusted. For the preset value, and transmitting the adjustment signal to the first chip according to the hold time and the clock. 25. The timing adjustment method of claim 24, wherein the first preset value is consistent with an internal integrated circuit 250 nanoseconds of the specification. Eight, schema · 20