TW201126742A - High-efficiency amorphous silicon photovoltaic devices - Google Patents

High-efficiency amorphous silicon photovoltaic devices Download PDF

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TW201126742A
TW201126742A TW099131791A TW99131791A TW201126742A TW 201126742 A TW201126742 A TW 201126742A TW 099131791 A TW099131791 A TW 099131791A TW 99131791 A TW99131791 A TW 99131791A TW 201126742 A TW201126742 A TW 201126742A
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layer
glass
substrate
lpcvd
deposited
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TW099131791A
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Daniel Borrello
Evelyne-Sauvain Vallat
Julien Bailat
Ulrich Kroll
Johannes Meier
Stefano Benagli
Miguel Marmelo
Giovanni Monteduro
Jochen Hoetzel
Jerome Steinhauser
Castens Lucie
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Oerlikon Solar Ag
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Abstract

A method for manufacturing an amorphous silicon p-i-n solar cell is disclosed. The cell comprises an anti-reflection coating and doped LPCVD ZnO front and back contacts, wherein the doped LPCVD ZnO front and back contacts are polycrystalline films constituted of large grains whose extremities appear at the growing surface as pyramids. The method comprises depositing said front contact by means of LPCVD; depositing the silicon layers of said p-i-n solar cell by means of plasma enhanced chemical vapor deposition; depositing said back contact by means of LPCVD; providing said anti-reflection coating. The amorphous silicon p-i-n solar cell can achieve a stabilized efficiency of 10.09%.

Description

201126742 六、發明說明： 【發明所屬之技術領域】 本發明係關於以矽為基礎的薄膜太陽能電池（thin film solar cell)與模組及其製造。本發明係關於針對薄 膜、以矽為基礎的太陽能電池或模組之製程的改善。更詳 而言之’本發明係關於非晶體的薄膜太陽能電池及其製造。 【先前技術】 光伏打裝置（photovoltaic device)、光電轉換裝置 (photoelectric conversion device)或太陽能電池係轉換 光的裝置，尤其是將太陽光轉換成為直流（DC)電力。由於 薄膜太陽能電池允許使用玻璃、玻璃陶瓷（glass ceramic)、 或其他堅硬的或可彎曲的基板作為基底材料（基板），而非 晶體的或多晶矽，故以低成本量產薄膜太陽能電池相當受 到關注。該太陽能電池結構（亦即，負責或具有光伏打效應 之層序列）係沉積於薄層中。此沉積可發生於大氣或真空條 件下。沉積技術係本領域中所廣為熟知者，如PVD、CVD、 PECVD、APCVD、…所有上述技術皆正為半導體製程·中所使 用。 太陽能電池的轉換效率係太陽能電池效能的常見測 量，且係由輸出功率密度（=開路電壓Voc、填充因子 (fill-factor)FF及電流密度Jsc之乘積）與輸入功率密度 之比率所決定。 薄膜太陽能電池一般而言包含第一電極、一個或多個 半導體薄膜p-i-n或n-i-p接面、以及第二電極，上述各 94994 4 201126742 者係依序地堆疊於基板上。P~i-n接面或薄膜光電轉換單 元之各者自包含爽於經正摻雜（d〇ped)或p_ ； 型層與經負摻雜（neSatively doped)或n-型層之間的純 - 質（intrinsic)層或卜型層。該純質的半導體層佔據該薄 膜p-i-n接面的大部分厚度。光電轉換主要發生在此卜型 層；因此，該純質的半導體層亦稱為主動（active)或吸收 體層（absorber layer)。 取決於該i-型層之結晶性（crystallinity)，太陽能 電池或光電（轉換）裝置區分為非晶體的（a_Si)或微晶體的 (// c-Si)太1¼能電池’不受限於鄰近的p_型與n_型層之结 晶性種類。於本技術領域中，該微晶體層係習知技術，於 非晶體的基材（matrix)中包括至少15%拉曼結晶性（Raman crystallinity)之微晶體微晶（microcrystal 1 ine crystallite)。 該p-i-n接面中經摻雜的層經常亦稱作為視窗層 (window layer)。由於該經摻雜的p/n層所吸收的光會因 為該主動層（active layer)而消失，故期望有高度透明的 視窗層，以得到高電流密度（Jsc)。再者，該等視窗層有助 於在構成該太陽能電池之半導體接面中建立電場，有助於 收集經光產生的電荷載體並且得到高Voc與FF數值。除此 之外’為了得到良好的FF數值’該前方透明導電性氧化物 (TC0)與該視窗層之間的接點應該為具有低電阻的歐姆接 點。於本領域中，由於微晶矽的視窗層的較佳光學特性（吸 收較少）’使得微晶矽的視窗層已較非晶體的視窗層更受青 94994 201126742 昧。 第9圖所示之先前技術顯示基本的、簡單的光伏打電 池40’該光伏打電池4〇包括透明基板41 (例如：具有透明 導電性氧化物層（TC0)42沉積於其上之玻璃）。該層亦稱作 前方接點，並且作為用於該光伏打元件之第一電極。基板 41與前方接點42的結合亦為習知的蓋板（superstrate)。 下一層43係作為主動光伏打層，並且包括形成p_i_n接面 的三個“次層（sub-iayer)” 。該層43包括氫化的微晶 體、奈米結晶或非晶石夕或上述各者之結合。次層44(鄰近 TC0刖方接點42)係經正摻雜者，該鄰近的次層45係純質 者，且該最後的次層46係經負摻雜者。於替代實施例中， 上述層序列p-i-n可轉換為n-i-p，接著層44係經識別為 η-層，層45依然是純質的，層46作為p-層。 最終，該電池包含背面接點層47(亦稱為背面接點） 以及反射層48，該背面接點層47可由氧化鋅、氧化錫或 ΙΤ0所製成。又或者’可實現金屬化的背面接點，該背面 接點可結合背面反射體48與背面接點47之物理特性。為 了說明起見，箭頭係指出照射光。 一般而言，可了解到當光（例如：太陽輻射）照射於光 電裝置上時，該i-層中產生電洞對。來自經產生的電洞對 之電洞係朝向該P型區，而電子係朝向該η型區。該等接 點一般而言係直接或間接與該ρ型與η型區接觸。只要光 持續產生電洞對，則電流將流經連接這些接點之外部電路。 【發明内容】 94994 6 201126742 _ 本發明之一實施態樣為一種用於製造非晶矽p-i-n太 陽能電池之方法，該電池包括抗反射塗佈以及經摻雜的 w LPCVD ZnO前方與背面接點，其中，該經摻雜的LPCVD ZnO : 前方與背面接點係由大型粒狀物所構成之多晶膜，該大型 ' 粒狀物的末端如同角錐出現於生長表面，該方法包括：藉 由LPCVD沉積該前方接點；藉由電漿辅助化學氣相沉積來 沉積該p-i-n太陽能電池之矽層；藉由LPCVD沉積該背面 接點，以及設置該抗反射塗佈。 本發明之另一實施態樣為一種非晶矽P_i_n太陽能電 池，包括抗反射塗佈、珍層之p_i_n接面、及經摻雜的lpcvd ZnO前方與背面接點，其中，該經摻雜的LpcvD Zn〇前方 與背面接點係由大型粒狀物所構成之多晶膜，該大型粒狀 物的末如同角雜出現於生長表面 【實施方式】 I· 一般 工業用 KAI-M R&D /5 aa201126742 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to tantalum-based thin film solar cells and modules and their manufacture. The present invention relates to improvements in the processing of thin film, germanium-based solar cells or modules. More specifically, the present invention relates to amorphous thin film solar cells and their manufacture. [Prior Art] A photovoltaic device, a photoelectric conversion device, or a device for converting light by a solar cell, in particular, converting sunlight into direct current (DC) power. Since thin film solar cells allow the use of glass, glass ceramics, or other hard or bendable substrates as the substrate material (substrate) instead of crystalline or polycrystalline germanium, the production of thin film solar cells at low cost is of considerable concern. . The solar cell structure (i.e., the sequence of layers responsible for or having a photovoltaic effect) is deposited in a thin layer. This deposition can occur under atmospheric or vacuum conditions. Deposition techniques are well known in the art, such as PVD, CVD, PECVD, APCVD, ... all of which are being used in semiconductor processes. The conversion efficiency of a solar cell is a common measure of solar cell performance and is determined by the ratio of output power density (= product of open circuit voltage Voc, fill-factor FF, and current density Jsc) to input power density. A thin film solar cell generally comprises a first electrode, one or more semiconductor thin films p-i-n or n-i-p junctions, and a second electrode, each of which is sequentially stacked on a substrate. Each of the P~in junction or the thin film photoelectric conversion unit is self-contained with a purely doped (d〇ped) or p_; type layer and a neatly doped or n-type layer - An intrinsic layer or a layer. The pure semiconductor layer occupies most of the thickness of the p-i-n junction of the film. Photoelectric conversion occurs mainly in this type of layer; therefore, the pure semiconductor layer is also referred to as an active or absorber layer. Depending on the crystallinity of the i-type layer, the solar cell or photoelectric (conversion) device is classified as amorphous (a_Si) or microcrystalline (//c-Si) too 11⁄4 can be 'unlimited' The crystalline species of the adjacent p_type and n_type layers. In the art, the microcrystalline layer is a conventional technique for including microcrystal 1 ine crystallite of at least 15% Raman crystallinity in an amorphous matrix. The doped layer in the p-i-n junction is often also referred to as the window layer. Since the light absorbed by the doped p/n layer disappears due to the active layer, a highly transparent window layer is desired to achieve a high current density (Jsc). Moreover, the window layers facilitate the creation of an electric field in the semiconductor junctions that make up the solar cell, aid in the collection of photogenerated charge carriers and result in high Voc and FF values. In addition to this, in order to obtain a good FF value, the contact between the front transparent conductive oxide (TC0) and the window layer should be an ohmic contact having a low resistance. In the art, the window layer of the microcrystalline germanium is more susceptible to the greener window layer due to the better optical properties (less absorption) of the window layer of the microcrystalline germanium. 94994 201126742 昧. The prior art shown in Figure 9 shows a basic, simple photovoltaic cell 40' comprising a transparent substrate 41 (e.g., glass having a transparent conductive oxide layer (TC0) 42 deposited thereon) . This layer is also referred to as the front contact and serves as the first electrode for the photovoltaic element. The combination of the substrate 41 and the front contact 42 is also a conventional superstrate. The next layer 43 acts as an active photovoltaic layer and includes three "sub-iayeres" that form the p_i_n junction. This layer 43 comprises hydrogenated microcrystals, nanocrystals or amorphous stones or a combination of the above. Sublayer 44 (adjacent to TC0 square junction 42) is a positive dopant, the adjacent sublayer 45 is pure, and the last sublayer 46 is a negative dopant. In an alternative embodiment, the layer sequence p-i-n can be converted to n-i-p, followed by layer 44 as the η-layer, layer 45 as pure, and layer 46 as the p-layer. Finally, the battery includes a back contact layer 47 (also referred to as a back contact) and a reflective layer 48 which may be made of zinc oxide, tin oxide or tantalum. Alternatively, or a metallized back contact, the back contact can combine the physical characteristics of the back reflector 48 and the back contact 47. For the sake of explanation, the arrows indicate the illumination light. In general, it can be appreciated that when light (e.g., solar radiation) is incident on the photovoltaic device, a pair of holes are created in the i-layer. The hole from the resulting pair of holes faces the P-type region, and the electrons face the n-type region. These contacts are generally in direct or indirect contact with the p-type and n-type regions. As long as the light continues to create a pair of holes, current will flow through the external circuitry that connects these contacts. SUMMARY OF THE INVENTION 94994 6 201126742 _ One embodiment of the present invention is a method for fabricating an amorphous germanium pin solar cell comprising antireflective coating and doped w LPCVD ZnO front and back contacts, Wherein the doped LPCVD ZnO: the front and back contacts are polycrystalline films composed of large granular particles, and the ends of the large 'granules appear as pyramids on the growth surface, the method includes: by LPCVD Depositing the front contact; depositing a tantalum layer of the pin solar cell by plasma assisted chemical vapor deposition; depositing the back contact by LPCVD, and providing the anti-reflective coating. Another embodiment of the present invention is an amorphous germanium P_i_n solar cell comprising an anti-reflective coating, a p_i_n junction of a rare layer, and a front and back contact of the doped lpcvd ZnO, wherein the doped The front and back joints of LpcvD Zn〇 are polycrystalline films composed of large granular materials, and the ends of the large granular materials appear on the growth surface as the corners are mixed. [Embodiment] I·General industrial KAI-M R&D /5 aa

仙反應器所製備之LPCVD-ZnO TCO J 之高效非晶矽裴置 本專利申。月案之此—般部分實質上係取自2刪年9 月W向美國專利商標局提出申請序號61/244,236之美 == 案。下文中提出對於沉積於經摻雜的 LPCVD-ZnO上之高效能非a ^ 外日日石夕P-i-n太陽能電池所使用之 最佳化1-層厚度之研究。 a ^ . 此種最佳化的動作已經於明顯相 薄的非晶體卜層厚度達 ^則優異且穩定的效率。具有紀錄交 率（record efficiencv、1n Λ y)l0· 09%(於1平方公分上）之吸收j 7 94994 201126742 的單一接面a-Si:H電池係由NREL所獨立確認。於一表中，High-efficiency amorphous device of LPCVD-ZnO TCO J prepared by the reactor. The general part of the monthly case is essentially taken from the date of September 2, and the US Patent and Trademark Office filed the application for the number 61/244,236. A study of optimized 1-layer thickness for use in high performance non-a ^ outer day shi shi P-i-n solar cells deposited on doped LPCVD-ZnO is presented below. a ^ . This optimized action has been excellent in the thickness of the apparently thin amorphous layer and is stable and stable. A single junction a-Si:H battery with a record rate (record efficiencv, 1n Λ y) 10·09% (on 1 cm 2 ) absorption j 7 94994 201126742 was independently confirmed by NREL. In a table,

Oerlikon Solar-Lab Neuchatel 與 NREL 實驗室對於相同 裝置所作的測量結果於兩種特性之間顯現出極低的偏差。 為了 a-Si : Η電池所研發的製程係應用於製備迷你模組 (10X10平方公分）。於JRC之ESTI實驗室，對這些吸收光 迷你模組所作的測量已經確認了 9. 2%的模纽孔徑效率。 可從下文中的節II至IV進一步了解本發明某些態樣 之細節。 I. 1介紹 在朝向達成市電同價（grid parity)的方向上，以非 晶石夕與微晶串疊型技術為基礎的薄膜太陽能模組對於縮減 製造成本具有很大的潛力。對於兩種技術而言，梦薄膜可 沉積於單一腔室電漿輔助化學氣相沉積（PECVD)反應器（類 似Oerlikon Solar KAI系統）中。先前的研究已經證明當 引進特殊的p-i介面處理[1，2]時，該KAI反應器可產生高 品質的非晶碎p- i —η電池。 同時，藉由適當地降低該a-Si : Η吸收體層厚度，能 夠正面地影響該等模組之製造成本與光吸收能力。為此目 的’採用粗縫的TC0以加強該裝置内的光捕捉。該TC0内 所增加的光-散射造成該電池中數個-摺疊的光路徑 (several - fold path of light)，並因此能夠採用厚度較 薄的吸收體層。此外，由於//c-Si:H之光學吸收較a-Si:H 之光學吸收差，故對於微晶串疊型裝置而言，該前方tc〇 之光-散射特性甚至更為重要。 94994 8 201126742 TC0薄膜特性（如高傳輸、高導電性、優異的光-散射 能力（可見光與近紅外線範圍））、以及適合薄膜均勻生長的 . 表面形態係高效能矽薄膜裝置所必需的。藉由低壓化學氣 * 相沉積（LPCVD)所製造之摻雜硼的氧化鋅（boron-doped ' zinc oxide)經證實由於其傑出的光-散射能力，因此能夠 產生優異的薄膜矽太陽能電池[3]。當以量產規模生產時， LPCVD-ZnO亦為低成本的TC0。基於這些原因，已經決定研 發用於沉積1. 4m2的大面積LPCVD-ZnO層之製程與.生產設 備[4 ]。 本專利申請案提出於單一接面a-Si:H電池以及具有 所有LPCVD-ZnO前方與背面電極之迷你模組上所達到之結 果。 1.2實驗結果 所提出的p-i-n a-Si :H電池係沉積於R&D單一腔室 KAI-M系統中（52 x 41 cm2的基板尺寸）。在各個電池經過 之後’在原地使用電漿製程（in_situ plasma pr〇cess)# /月理該ΚΑΙ電漿箱反應器（piasmab〇x react〇r) 0 先前的研究證明能夠利用40.68MHz的激發頻率來沉 積品質優異的非晶石夕i-層（以3.35 A/s的速率）[5, 6, 7]。 於此新的研究中，該i-層的沉積速率係1.75 A /s。 ▲各個電池與迷你模組皆具有内部製備的LPCVD-ZnO作 為前=與背面接點，後者結合白反射體（WR)[8]。該等ZnO 層的"L積參數係經最佳化，以得到有效率的光一散射、高透 明度及導電性。如同玻璃蓋板，我們採用厚度1mm之Schott 9 94994 201126742 硼矽玻璃33。該等LPCVD-ZnO層的光學特性係利用裝配有 積分球（integrating sphere)之 Perkin Elmer lambda 950 光譜儀進行測量。 為求仔細描述特性，所有的電池皆係藉由雷射圖案化 而構建為經良好定義之1平方公分之面積。尺寸1〇 x 1〇 平方公分的迷你模組係藉由對於單石串聯連接 (monolithic series connection)的節段（segment)施加雷 射刻劃（laser scribing)而實現。 該等電池的I (V)特性係於25。C的溫度以及AM 1. 5照 度（Wacom WXS-155S-L2雙電源模擬器）下進行測量。紀錄 電池（record cell)與迷你模組的ι(ν)特性係由該 National Renewable Laboratory (NREL) ' Golden (USA) 以及JRC之ESTI實驗室、ispra (Italy)分別獨立地進行 測量。 光吸收試驗係於以下條件下進行：一個太陽照明強度 (功率達MW之硫磺燈）、5(rc、於1000h期間以及於開路電 壓下。為了將溫度維持於5〇。〇，光吸收測試下的樣本係置 放於冷卻平台上。先前由該JRCiESTI實驗室所測量的非 晶體p-i-n迷你模組（10><10平方公分）之仏數值係作為將 該樣本平台上之光強度設定至1000W/m2之參考。再者，光 均勻度係經決定為優於土5〇<。 該冷卻平台係由熱傳導墊片（therm〇_c〇nductive pad) 所覆蓋，能夠確保受測試的樣本具有良好的熱接觸 (thermal contact)。為了決定該平台上各個區域之溫度， 94994 10 201126742 係採用於其頂部貼附有PtlOO感測器之a-Si : Η電池樣本 (5x5平方公分）。於該感測器與該電池之間，係採用熱傳 導（thermo-conductive paste)貼片以確保良好的熱接觸。 : 於底部（背面側（陰影侧））上，一些樣本亦包含感測器。經 * 試驗發現，兩個感測器（頂部與底部）之間的溫度差係小於 1°C。最終，視所測量到之溫度而定，該冷卻平台係經區分 於不同的區域中。區分出具有50°C± 2°C的理想範圍，並 將其用於本發明所描述之光吸收試驗。 在將該等樣本（本發明所考量者）置放於該光吸收平 台之理想區域上之後，PtlOO感測器係貼附於其上，且再 度控制該溫度。接著開始進行光吸收試驗。為了確認於該 光吸收試驗期間各種條件皆保持不變，於不同時期控制該 光強度與溫度。具體而言，於該光吸收的初始段、中間段 以及末段皆小心翼翼地驗證這些參數。於迷你模組之光吸 收試驗期間，係採用用於確認該溫度之類似之周嚴程序。 再者，發現到溫度於50°C標準數值附近有± 2°C的變化。 1.3結果 1.3. 1 LPCVD-ZnO 作為前方 TC0The measurements made by Oerlikon Solar-Lab Neuchatel and NREL Laboratories for the same device show very low deviations between the two characteristics. For the a-Si: Η battery research and development process is used to prepare mini modules (10X10 square centimeters). At JRC's ESTI laboratory, measurements of these light-absorbing mini-modules have confirmed 9.2% of the mold aperture efficiency. Further details of some aspects of the invention can be found in Sections II through IV below. I. 1 Introduction Thin-film solar modules based on non-crystallographic and microcrystalline tandem technology have great potential for reducing manufacturing costs in the direction of achieving grid parity. For both technologies, the dream film can be deposited in a single chamber plasma assisted chemical vapor deposition (PECVD) reactor (similar to the Oerlikon Solar KAI system). Previous studies have shown that when a special p-i interface treatment [1, 2] is introduced, the KAI reactor can produce a high quality amorphous shredded p-i-n battery. At the same time, by appropriately reducing the thickness of the a-Si: Η absorber layer, the manufacturing cost and light absorbing ability of the modules can be positively affected. For this purpose, the TC0 is used to enhance the light trapping within the device. The increased light-scattering within the TC0 results in a single-fold path of light in the cell, and thus a thinner absorber layer can be used. In addition, since the optical absorption of //c-Si:H is inferior to the optical absorption of a-Si:H, the light-scattering characteristic of the front tc〇 is even more important for the microcrystalline tandem device. 94994 8 201126742 TC0 film properties (such as high transmission, high conductivity, excellent light-scattering ability (visible and near-infrared range)), and suitable for uniform film growth. Surface morphology is required for high-performance thin film devices. Boron-doped 'zinc oxide produced by low pressure chemical gas phase deposition (LPCVD) has been proven to produce excellent thin film tantalum solar cells due to its excellent light-scattering ability [3] ]. LPCVD-ZnO is also a low cost TC0 when produced on a mass production scale. For these reasons, it has been decided to develop a process and a production facility for depositing a large area LPCVD-ZnO layer of 1.4 m2 [4]. This patent application is presented on a single junction a-Si:H cell and a mini-module with front and back electrodes of all LPCVD-ZnO. 1.2 Experimental results The proposed p-i-n a-Si :H battery was deposited in a R&D single chamber KAI-M system (52 x 41 cm2 substrate size). In the in-situ use of the plasma process (in_situ plasma pr〇cess) # / 理 ΚΑΙ ΚΑΙ ΚΑΙ ΚΑΙ 〇 〇 0 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 先前 ΚΑΙ ΚΑΙ ΚΑΙ ΚΑΙ 先前 先前 ΚΑΙ ΚΑΙ ΚΑΙ To deposit an amorphous austenitic i-layer (at a rate of 3.35 A/s) [5, 6, 7]. In this new study, the deposition rate of the i-layer was 1.75 A / s. ▲ Each battery and mini module has an internally prepared LPCVD-ZnO as the front = back contact, which combines with a white reflector (WR) [8]. The "L product parameters of these ZnO layers are optimized for efficient light-scattering, high transparency, and electrical conductivity. Like the glass cover, we use Schott 9 94994 201126742 borosilicate glass 33 with a thickness of 1 mm. The optical properties of the LPCVD-ZnO layers were measured using a Perkin Elmer lambda 950 spectrometer equipped with an integrating sphere. In order to describe the characteristics carefully, all batteries are constructed by laser patterning to a well-defined area of 1 square centimeter. A mini module of size 1 〇 x 1 平方 square centimeter is realized by applying laser scribing to a segment of a monolithic series connection. The I (V) characteristics of these batteries are at 25. Measurements were made at temperature of C and AM 1. 5 illuminance (Wacom WXS-155S-L2 dual power simulator). The ι(ν) characteristics of the record cell and the mini-module were measured independently by the National Renewable Laboratory (NREL) 'Gold (USA) and the ESRC's ESTI laboratory, ispra (Italy). The light absorption test was carried out under the following conditions: a solar illumination intensity (sulfur lamp with a power of MW), 5 (rc, during 1000 h, and at an open circuit voltage. In order to maintain the temperature at 5 〇. 〇, under light absorption test The sample is placed on a cooling platform. The value of the amorphous pin mini module (10 >< 10 cm ^ 2 ) previously measured by the JRCIESTI laboratory is used as the light intensity on the sample platform to 1000 W. /m2 reference. Furthermore, the light uniformity is determined to be better than the soil. The cooling platform is covered by a thermoconductive gasket (therm〇_c〇nductive pad) to ensure that the sample under test has Good thermal contact. In order to determine the temperature of each area on the platform, 94994 10 201126742 is based on a-Si: Η battery sample (5x5 cm2) with PtlOO sensor attached to the top. A thermo-conductive paste patch is used between the sensor and the battery to ensure good thermal contact. : On the bottom (back side (shaded side)), some samples also contain sensors. The test found that the temperature difference between the two sensors (top and bottom) is less than 1 ° C. Finally, depending on the measured temperature, the cooling platform is differentiated into different areas. a desired range of 50 ° C ± 2 ° C and used in the light absorption test described in the present invention. After placing the samples (the subject of the present invention) on the desired area of the light absorbing platform, The PtlOO sensor is attached to it and the temperature is controlled again. Then the light absorption test is started. In order to confirm that the various conditions remain unchanged during the light absorption test, the light intensity and temperature are controlled at different times. In the initial, intermediate and final sections of the light absorption, these parameters are carefully verified. During the light absorption test of the mini-module, a similarly strict procedure for confirming the temperature is used. It was found that the temperature was ± 2 ° C around the standard value of 50 ° C. 1.3 Results 1.3.1 LPCVD-ZnO as the front TC0

相較於先前於EU PVSEC所提出的研究[7]中所使用之 層，本發明所提出之ZnO層（亦即，類型A與類型B)係經 過修改。具體而言，對於類型A而言，於600奈米時的霧 度因子（haze factor)係自20%降低至12%，但是對於ZnO 類型B而言，霧度因子則猛然增加至70%。然而，到目前 為止，僅ZnO類型A係用於製備迷你模組。兩種類型的ZnO 11 94994 201126742 皆為由大型粒狀物所構成之多晶膜，該大型粒狀物的末端 如同角錐出現於生長表面（如第1圖所示）。此類隨著生長 的粗糖表面紋理係如同第2圖所繪示之擴散透射一般擴散 該光。此效應造成光有效地散射進入該;ε夕裝置[9]。 關於使用高霧度LPCVD-ZnO作為前方接點的習知缺 點在於薄膜矽裝置的最佳化係更為敏感且困難的。但是， 能夠提供這些類型ZnO層、能夠證明該前方ZnO類型B之 尚九數值潛力亦包含於我們的研究之中。 1.3.2非晶矽電池 第3圖與第4圖分別顯示先前由〇erlikonSolar~Lab 心11(±針61於2008[7]所得到之非晶體丨-層厚度系列以及 於2009所得到之新系列。重要的是，指出應用於2009電 池製備中的一些改變：該i-層的沉積速率係自3. 35A/s 降低至1. 75A/s、採用增加該短路電流密度 (short-circuit current density)的新方法（無抗反射、 AR、塗佈）、以及輕微地降低該ZnO前方接點之霧度。 以速率3. 35A/s與1· 75A/s所沉積且厚度為1微米 之a-Si : Η層之光學特性係經位於布拉格之捷克科學院之 物理研究所所測量。留意到，降低該i-層的沉積速率並未 伴隨有光學特性的變化，如同通常單獨修改矽烷稀釋所期 望者。同時考量到i-層具有1. 73電子伏特之光學能隙 (Tauc’ s)[5]。對於達到具有高短路電流密度之a_si : jj 電池而言’這是一個重要的特徵’如同高效能（在光吸收之 後）微晶裝置之設計中所期望者。 94994 12 201126742 ' 藉由比較第3圖與第4圖主要所觀察到的係該人數值 的明顯增加。這是對於4〇〇至800奈米波長範圍中之光強 - 度損失的最小化之密集研究所得到之結果。留意到，Tsc數 * 值的增加並未降低該電池祝數值與I數值。另一個觀察 到的係新研發的製程之初始與穩定開路電壓（&數值）的 輕微增加。僅參照第4圖，可能可推斷出作為該卜層厚度 之函數之最大效率尚未達到；將進一步研究厚度更薄的 層，如180奈米。 從這個研究中所學習到的基本原則係將LPCVD_Zn〇前 方與背面接點用於a-Si : Η單一接面太陽能電池，即便以 薄1-層（180奈米）亦能夠提供非常高的穩定/sc數值 (16mA/cm2)以及良好的〜數值與FF數值。優異的光捕捉、 厚度薄的p-1-ri層以及高品質的卜層係達到高效能裝置的 關鍵因素。 有了以薄1-層製備高效能電池的經驗，下一步係研究 具有氣體玻璃-基板介面之市售抗反射（AR)塗佈之裝置。此 外，我們已經開發了内部寬頻帶AR。 考直到對於具有AR之電池進行試驗，亦對新類型的 LPCVD-ZnO進行測試（Zn〇類型B，於_奈米具有7〇%之霧 度）。就類型A ZnO所製備的電池而言，選擇厚度18〇奈米 之i-層，而就類型BZnO所製備之電池而言，選定25〇奈 米之吸收體層。如第5圖所示’於類型B Zn〇上，我們測 量到10. 03%的最高紀錄吸收光電池效率。 第5圖所不之具有最高紀錄的電池係送至臓l， 94994 201126742The ZnO layers (i.e., Type A and Type B) proposed by the present invention have been modified as compared to the layers previously used in the study [7] proposed by EU PVSEC. Specifically, for type A, the haze factor at 600 nm was reduced from 20% to 12%, but for ZnO type B, the haze factor suddenly increased to 70%. However, up to now, only ZnO type A has been used to prepare mini-modules. Both types of ZnO 11 94994 201126742 are polycrystalline films composed of large granules whose ends appear as pyramids on the growth surface (as shown in Figure 1). This type of coarse sugar surface texture grows as the diffuse transmission as depicted in Figure 2 diffuses the light. This effect causes light to effectively scatter into the; 夕 装置 device [9]. A conventional disadvantage with the use of high haze LPCVD-ZnO as the front contact is that the optimization of the film tantalum device is more sensitive and difficult. However, the ability to provide these types of ZnO layers and to demonstrate the potential of the front ZnO type B is also included in our research. 1.3.2 Amorphous Tantalum Batteries Figures 3 and 4 show the previous series of amorphous germanium-layer thicknesses obtained by 〇erlikonSolar~Lab Heart 11 (±Ne 61 in 2008 [7] and new in 2009). Series. It is important to point out some changes in the preparation of the 2009 battery: the deposition rate of the i-layer is reduced from 3.35 A/s to 1.75 A/s, and the short-circuit current is increased. Density) new method (no anti-reflection, AR, coating), and slightly reduce the haze of the ZnO front contact. Deposited at a rate of 3.35A / s and 1. 75A / s and a thickness of 1 micron a-Si: The optical properties of the ruthenium layer are measured by the Institute of Physics of the Czech Academy of Sciences in Prague. It is noted that reducing the deposition rate of the i-layer is not accompanied by changes in optical properties, as is usually done by modifying the decane dilution separately. Expectant. At the same time, the i-layer has an optical energy gap of 1.73 eV (Tauc's) [5]. This is an important feature for a_si:jj cells with high short-circuit current density. As high performance (after light absorption) in the design of the microcrystalline device Expectant. 94994 12 201126742 ' A significant increase in the value of this person is observed by comparing the main figures in Figures 3 and 4. This is for the intensity-degree loss in the wavelength range from 4 〇〇 to 800 nm. The result of minimizing the intensive study. Note that the increase in the Tsc number* value does not reduce the battery value and the I value. Another observed initial and stable open circuit voltage for the newly developed process (& A slight increase. With reference to Figure 4, it may be inferred that the maximum efficiency as a function of the thickness of the layer has not been reached; a thinner layer, such as 180 nm, will be further studied. The basic principle is to use LPCVD_Zn〇 front and back contacts for a-Si: Η single junction solar cells, providing very high stability/sc values (16mA/cm2) even in thin 1-layer (180 nm) And good ~ value and FF value. Excellent light capture, thin p-1-ri layer and high quality layer to achieve the key factor of high-performance device. With a thin 1-layer preparation of high-performance battery Experience, the next step A commercially available anti-reflective (AR) coating device with a gas glass-substrate interface has been studied. In addition, we have developed an internal wideband AR. It is not tested for batteries with AR, but also for new types of LPCVD-ZnO. Test (Zn〇 type B, having a haze of 7〇% in _ nanometer). For a battery prepared by type A ZnO, an i-layer having a thickness of 18 Å is selected, and a battery prepared for the type BZnO is used. For this purpose, an absorber layer of 25 nanometers is selected. As shown in Fig. 5, on the type B Zn〇, we measured a maximum record of 10.03% to absorb the efficiency of the photovoltaic cell. The battery with the highest record in Figure 5 is sent to 臓l, 94994 201126742

Golden, CO(USA)，而其單獨特性之結果係顯示於第6圖 中。確認有10. 09%之相當高且穩定的效率。非晶矽單一接 面電池第一次達到超過10%障礙之效率。就發明人所知， 第6圖中所示之電池代表非晶矽p-i_n電池的新世界紀 錄。相較於先前的最高紀錄（β = 9. 47%，由IMT，Neuchatel 所得到[9, 10])，本發明得到了 〇. 6%的絕對顯著的改善。 這樣的冠軍電池證明了 〇C 〇erlikon LPCVD-ZnO(前方 與背面接點）結合沉積於單一腔室KAITM反應器中的非晶矽 係非常成熟且具有南效率的技術。 於第7圖中，如第6圖所示之電池之絕對EQE係由經 正規化（normalized)成17. 284mA/cm2之ΑΜ1. 5短路電流密 度之NREL之QE測量（來自NREL之I(V)特性）所計算得到。 留意到，於非晶矽之吸收範圍内，各處皆具有很高的絕對 EQE特性。此結果係於對形成該電池之所有層與介面進行 密集最佳化之後達到。尤其是，本發明所提出之LPCVD-ZnO 的優異光-散射、高品質及標準能隙i-層（沉積於該ΚΑΙ反 應器中）係用於獲得如此高的絕對EQE的重要因素。 於表1中’顯示R&D Solar-Lab NeucMtel中所製備 的不同的最高紀錄電池的回顧。具體而言，表1對於首先 於Oerlikon Solar-Lab Neuchatel進行測量的以及稍後（9 天内）於NREL進行測量的I (V)電池參數之間進行比較。值 得留意的是’能夠以經分析的兩種不同類型ZnO(亦即，類 型A與類型B)達到非常高的效率（超過1〇%):見表1所示 之電池3497、3473以及3470。 14 94994 201126742 如表1所示，本發明之AMI. 5 I-V特性與NREL的測 量相當一致。本發明想要強調的是本發明之AM15校正係 基於ESTI(Ispra)’該ESTI(Ispra)似乎與NREL相當匹配。 所能留意到的最明顯偏差係在於樣本3297與3470所使用 的電池面積的測定。如表1所示，這個最終事實會造成所 決定的效率發生變化。 樣本 AR I sc [mA] Voc [mV] FF[%] 效率 [%] 面積 [cm2] Zn(J 類型-ΰ，p-i(250nm)-n 電池 3328 Oerlikon Com. 18.070 878 65.68 9.93 1.05 3328 NREL Com. 18.110 875.6 65.91 9.94 1.051 3497 Oerlikon Oerl. 18. 040 879 66. 39 10.03 1.05 3497 NREL Oerl. 18.098 876.7 66.58 10.09 1.047 ZnO 類型-A，D-i(180nmVn 雷池 3473 Oerlikon Oerl. 17.310 885 68.61 10.01 1.05 3473 NREL Oerl. 17. 480 883.8 68.33 10.06 1.049 3297 Oerlikon No 16. 680 881 67.65 9.47 1.05 3297 NREL No 16.708 878.2 67. 57 9.55 1.038 3470 Oerlikon Cora. 17.290 882 68.15 9.90 1.05 3470 NREL Com. 17. 360 885.6 67.85 10.06 1.036 表 1 :回顧由 Oerlikon Solar-Lab Neuchatel 所製備並測 量以及特性由NREL所獨立描述之最高紀錄電池。所有的電 池皆沉積於R&D ΚΑΙ M PECVD系統中，具有LPCVD-ZnO前 方與背面接點，並且於開路電壓條件、5(TC、一個太陽照 明等條件下持續吸收光達1〇〇〇小時。有鑑於電池3328與 3470塗佈有市售的AR塗佈，故電池3497與3473上鋪設 有本發明所提供之内部AR(〇erl.)。 1.3. 3非晶矽迷你模級 15 94994 201126742 於尺寸1平方公分之電池上實驗所得到的發現係轉換 成最佳化LPCVD-ZnO上之迷你模組。對於該迷你模組而 言，係選擇於ZnO類型A上更為成熟的技術。考量以下三 種i-層厚度：180、215、及250奈米。在光吸收（如同第2 節所描述之條件）之後，效率最佳的迷你模組係經送至於 JRC於Ispra之ESTI實驗室測量其獨立特性（最佳結果係 顯示於第8圖）。模組孔徑面積（module aperture area) 同樣係由ESTI所決定。9. 2%之穩定模組孔徑效率係得到證 實（如第2節所描述，於〇erlikon Solar-Lab完成光吸收 後）。當最南紀錄電池結果（表1 : NREL)與最高紀錄迷你模 組（第8圖：ESTI)相比較時，經計算得到〇· 86%的效率損 失（絕對的）。此數值係合理的，且本發明之最高紀錄電池 結果因此進一步得到確認。 1.4歸納與結論 當採用經適當推雜的LPCVD-ZnO電極時，對非晶發 p-i-n太陽能電池之i-層厚度進行最佳化之成果已經顯示 出可利用薄i-層（180奈米）得到高/sc數值以及效率水準。 /儿積於該KAI系統中的兩品質石夕層以及該内部經摻雜 的LPCVD-ZnO之優異特性已經證實為達到高效率水準的重 要因素。内部ZnO顯現出高傳輸、高導電性、優異的光— 散射能力、以及適合生長高品質a-Si: η薄膜之表面形態。 於1平方公分上可達到10. 09%的穩定的最高紀錄電池 效率（由NREL所獨立確認）。這種結果提供了我們目前所知 對於a-Si : Η單一接面木陽能電池經確認的最高穩定電池 94994 16 201126742 _ 效率。相較於先前同樣由NREL所確認的最佳電池 (t?=9. 47%J. Meier et al., IMT, Neuchatel [9, 10]) . 而言’本發明於D上明顯得到了 0. 62%的絕對改善。此外， ' 另外兩個電池顯現出10. 06%的效率（NREL)。 *· _ 為電池所開發的製程經轉換至迷你模組之製備 (10x10平方公分）。JRC於Ispra之ESTI實驗室對這些吸 收光迷你模組之測量顯示出9. 2%的孔徑面積效率 (aperture area efficiency)。這樣穩定的高模組效率係 與該NREL電池效率測量有關。 本發明指出迷你模組的·結果證明最高紀錄電池可經 長:升至用於咼效月b之模組。下一個階段，〇eri α〇η Solar 將專注於提升至尺寸1.4平方公尺的工業用基板。 結果顯不出Oerlikon Solar的技術用於製造高效能 非晶石夕與微晶串疊型模組之高度潛力。 II.用於改善電性特性之表面處理 用於製造效能經改善之光伏打裝置之方法 本專利申凊案的這個部分係實質上取自2〇〇9年9月 18曰向美國專利商標局提出申請序號61/243,646之美國 臨時申睛案，而其係有關於改善用於薄膜、以石夕為基礎的 太陽忐電池或模組之製程。更詳而言之，本專利申請案係 關於用於薄膜石夕太陽能電池中所謂視窗層（wind〇w la㈣ 的製程以及用於此類太陽能電池的層結構。尤其，本專利 申凊案係關於用於太陽能電池結構申電極層的表面處理， 該電極層包括透明的導電性氧化物（TC〇)。 94994 17 201126742 π. 1先前技術的缺點 該等視窗（ρ/η-型）層一般而言係由非晶石夕或微晶石夕 (亦稱作奈米結晶（nanocrystalline))或者兩者之任何混 合物以及兩者與氧、碳、鍺、及類似材料之合金所製成。 由於該p/n-型層有高度缺陷（不規則），故經光產生的電洞 對（electron-hole pair)重新結合的機率很高；因此，並 未提供該裝置之光電流（photocurrent)，但是卻造成吸收 的損失（absorption loss)。基於這個理由，摻雜層之厚度 應該被最小化，以便縮減這種光學損失。然而，當經摻雜 層之厚度縮減太多時’填充因子與開路電廢的數值會明顯 下降。 U·歸納 於本說明書中建議，在生長用於薄膜矽層堆疊之視窗 層之前’應該實施短暫的表面處理，以分別製備非常薄的、 連續的或不連續的晶核層（1111〇1631：丨〇1113761')或1'00表 面。已經顯示出此類處理能夠改善稍後所介紹的電池之電 性特性。 實施方式 一般而言，再次參考第9圖，薄膜光伏打裝置光伏打 電池40包括基板41 (較佳的情況是，透明的玻璃基板，通 吊具有0. 4匪至5mm之厚度，較佳的情況是，2mm至4mm)、 導電性氧化物42(作為該基板41上之接點）、一個或多個 半導體層43至46(在曝露於光之後立即產生電荷分離）、 以及第二導電性接點47。 18 94994 201126742 本說明書中所提出的表面處理包括設置具有TC〇接點 層42於其上之基板41、以介於〇至8〇%間之濃度以氣態提 供SiH4、flz及視需要為摻雜氣體（例如：三甲硼[烷]、二硼 燒等等）m佳的濃度為0至，用於沉積接續的 次層44= P-型摻雜的視窗層。 在以下範例中，在P-層之前，實施有如表2中所示之 參數的該表面處理增加該太陽能電池之效率達2. 〇9%(表 3)’於電流密度中達到此增益之一半（見於第1〇圖中邱幻。 ------ SiH4 (seem) Hz (seem) TMB/Hz (seem) CH4 (seem) p /^c-Si：H 62 1800 3.3 0 P a-SiC:H 50 98 58 95 -J 表面處sE ~~62" 「1800 「0 0 P /^c-Si-H LP^SiCrH_ 06 1800 3. 3 0 50 —98 58 95 表3 時間Golden, CO (USA), and the results of its individual characteristics are shown in Figure 6. It is confirmed that there is a relatively high and stable efficiency of 10.09%. For the first time, an amorphous tantalum single-junction cell achieved an efficiency of more than 10% of the barrier. As far as the inventors are aware, the battery shown in Fig. 6 represents a new world record of an amorphous 矽p-i_n battery. Compared to the previous highest record (β = 9.47%, obtained by IMT, Neuchatel [9, 10]), the present invention yielded an absolutely significant improvement of 6%.6%. Such a champion battery demonstrates that 〇C 〇erlikon LPCVD-ZnO (front and back contacts) combines the very mature and south-efficient technology of amorphous lanthanum deposited in a single chamber KAITM reactor. In Fig. 7, the absolute EQE of the battery as shown in Fig. 6 is measured by a QE of NREL which is normalized to 17.284 mA/cm2 and 1.5 short circuit current density (I of N from NREL) ) Characteristic) is calculated. It is noted that there is a high absolute EQE characteristic throughout the absorption range of the amorphous germanium. This result is achieved after intensive optimization of all layers and interfaces forming the cell. In particular, the excellent light-scattering, high quality and standard energy gap i-layers (deposited in the ruthenium reactor) of the LPCVD-ZnO proposed by the present invention are important factors for obtaining such a high absolute EQE. A review of the different top-recorded cells prepared in R&D Solar-Lab NeucMtel is shown in Table 1. Specifically, Table 1 compares the I (V) battery parameters measured first in Oerlikon Solar-Lab Neuchatel and measured later in NREL (9 days). It is worth noting that the two different types of ZnO (i.e., type A and type B) that have been analyzed achieve very high efficiencies (over 1%): see batteries 3497, 3473, and 3470 shown in Table 1. 14 94994 201126742 As shown in Table 1, the AMI. 5 I-V characteristics of the present invention are quite consistent with the measurement of NREL. The present invention is intended to emphasize that the AM15 correction of the present invention is based on ESTI (Ispra)' which appears to be quite compatible with NREL. The most obvious deviation that can be noted is the measurement of the cell area used in samples 3297 and 3470. As shown in Table 1, this final fact will cause the determined efficiency to change. Sample AR I sc [mA] Voc [mV] FF [%] Efficiency [%] Area [cm2] Zn (J type - ΰ, pi (250 nm) - n Battery 3328 Oerlikon Com. 18.070 878 65.68 9.93 1.05 3328 NREL Com. 18.110 875.6 65.91 9.94 1.051 3497 Oerlikon Oerl. 18. 040 879 66. 39 10.03 1.05 3497 NREL Oerl. 18.098 876.7 66.58 10.09 1.047 ZnO Type-A, Di (180nmVn Thunder Pool 3473 Oerlikon Oerl. 17.310 885 68.61 10.01 1.05 3473 NREL Oerl. 17 480 883.8 68.33 10.06 1.049 3297 Oerlikon No 16. 680 881 67.65 9.47 1.05 3297 NREL No 16.708 878.2 67. 57 9.55 1.038 3470 Oerlikon Cora. 17.290 882 68.15 9.90 1.05 3470 NREL Com. 17. 360 885.6 67.85 10.06 1.036 Table 1: Review The highest record battery prepared and measured by Oerlikon Solar-Lab Neuchatel and characterized by NREL. All batteries are deposited in the R&D ΚΑΙ M PECVD system with LPCVD-ZnO front and back contacts and open circuit Under the condition of voltage, 5 (TC, one solar illumination, etc., the light is continuously absorbed for 1 hour. In view of the commercially available AR coating of the battery 3328 and 3470, The internal AR (〇erl.) provided by the present invention is laid on the pools 3497 and 3473. 1.3. 3 amorphous 矽 mini mold grade 15 94994 201126742 The discovery obtained on the battery of 1 cm square size is converted into the best The mini-module on LPCVD-ZnO. For this mini-module, it is a more mature technology selected for ZnO type A. Consider the following three i-layer thicknesses: 180, 215, and 250 nm. After absorption (as described in Section 2), the most efficient mini-modules were sent to JRC's ESTI laboratory in Ispra to measure their individual characteristics (best results are shown in Figure 8). The module aperture area is also determined by ESTI. 9. The 2% stability module aperture efficiency is verified (as described in Section 2, after errikon Solar-Lab completes light absorption). When the southernest recorded battery result (Table 1: NREL) is compared with the highest record minimodel (Figure 8: ESTI), an efficiency loss of 86% (absolute) is calculated. This value is reasonable and the highest recorded battery results of the present invention are therefore further confirmed. 1.4 Summary and conclusions When using properly littered LPCVD-ZnO electrodes, the results of optimizing the i-layer thickness of amorphous hairpin solar cells have been shown to be obtainable using thin i-layers (180 nm). High / sc values and efficiency levels. The superior properties of the two-quality stellite layer in the KAI system and the internal doped LPCVD-ZnO have proven to be important factors in achieving high efficiency levels. The internal ZnO exhibits high transport, high electrical conductivity, excellent light-scattering ability, and surface morphology suitable for growing high-quality a-Si: η thin films. A stable maximum record battery efficiency of 10.09% at 1 square centimeter (independently confirmed by NREL). This result provides what we currently know for a-Si: 最高 single junction Muyang energy battery confirmed the highest stable battery 94994 16 201126742 _ efficiency. Compared to the best battery previously confirmed by NREL (t? = 9.47% J. Meier et al., IMT, Neuchatel [9, 10]). In terms of 'the invention is clearly 0 on D 62% absolute improvement. In addition, 'the other two batteries showed 10.06% efficiency (NREL). *· _ The process developed for the battery was converted to a mini module (10x10 cm2). The measurement of these absorption light mini-modules by the JRC's ESTI laboratory in Ispra showed 9.2% aperture area efficiency. This stable high module efficiency is related to the NREL battery efficiency measurement. The present invention indicates that the result of the mini-module proves that the highest recorded battery can be extended: to the module for the effective month b. In the next phase, 〇eri α〇η Solar will focus on upgrading to an industrial substrate measuring 1.4 square meters. The results show that Oerlikon Solar's technology is used to create high-performance amorphous Aussie and microcrystalline tandem modules. II. Surface treatment for improving electrical properties. Method for manufacturing photovoltaic devices with improved performance. This part of the patent application is substantially from September 18, 2009 to the US Patent and Trademark Office. The US temporary application for the application of the serial number 61/243,646 is proposed, and the process for improving the solar cell or module for the film and the Shi Xi-based is proposed. More specifically, the present patent application relates to a process for a so-called window layer (window w la (four) in a thin film solar cell and a layer structure for such a solar cell. In particular, this patent application is related to For surface treatment of a solar cell structure application electrode layer, the electrode layer comprises a transparent conductive oxide (TC〇). 94994 17 201126742 π. 1 Disadvantages of the prior art, such window (ρ/η-type) layers are generally It is made of amorphous or microcrystalline (also known as nanocrystalline) or any mixture of the two and alloys of both with oxygen, carbon, germanium, and the like. The p/n-type layer is highly defective (irregular), so the probability of recombination of the electron-hole pair by light is high; therefore, the photocurrent of the device is not provided, but It causes absorption loss. For this reason, the thickness of the doped layer should be minimized in order to reduce this optical loss. However, when the thickness of the doped layer is reduced too much, the 'fill factor' The value of the road waste will be significantly reduced. U. It is suggested in this specification that a short surface treatment should be performed before the growth of the window layer for the stacking of the film layers to prepare very thin, continuous or discontinuous, respectively. The nucleation layer (1111〇1631:丨〇1113761') or the 1'00 surface. It has been shown that such a treatment can improve the electrical characteristics of the battery described later. Embodiments Referring again to Figure 9 again The thin film photovoltaic device photovoltaic cell 40 includes a substrate 41 (preferably, a transparent glass substrate having a thickness of 0.4 to 5 mm, preferably 2 mm to 4 mm), and conductive oxidation. The object 42 (as a junction on the substrate 41), one or more semiconductor layers 43 to 46 (which generates charge separation immediately after exposure to light), and a second conductive contact 47. 18 94994 201126742 The proposed surface treatment includes disposing a substrate 41 having a TC 〇 contact layer 42 thereon, providing SiH4, flz in a gaseous state at a concentration of between 〇 and 8〇%, and optionally a doping gas (for example, trimethylboron [ Alkane Burning, etc.) m is preferably at a concentration of 0 to deposit a successive sub-layer 44 = P-type doped window layer. In the following example, before the P-layer, parameters as shown in Table 2 are implemented. The surface treatment increases the efficiency of the solar cell by 2. 〇9% (Table 3)' to achieve one-half of this gain in current density (see Qiu Ying in Figure 1) ------ SiH4 (seem) Hz (seem) TMB/Hz (seem) CH4 (seem) p /^c-Si:H 62 1800 3.3 0 P a-SiC:H 50 98 58 95 -J Surface sE ~~62" "1800 "0 0 P /^c-Si-H LP^SiCrH_ 06 1800 3. 3 0 50 —98 58 95 Table 3 Time

1----- Jsc QE Voc FF 00~ 70. 67 ΤοΓδό- ------- (mA/cm2) (mV) 效率 16. 81 903. 03^ 'θΤΤΤοο' _____«) 16. 98 10. 73 10. 95 1. 02 0.88 0. lmo 兩個步驟所組成（表 2 對於標準p-層之範例而言，由 的上部）： 1 · P M c - S i: Η -以適用於微晶矽材料的條件沉積p _層 2· Pa~SiC:H-沉積非晶矽與碳之合金之p_型摻雜^ 94994 19 201126742 所提出的矽層堆疊經表面處理，該表面處理包括三個 步驟（表2的下部）： 1. 表面處理：將該TC0層42短暫曝露（5秒）於具p /zc 條件而無摻雜氣體之電漿下。該電漿條件係選定為與接下 來步驟2之條件相同，但無任何摻雜物氣體。 2. p/z c-Si :H-於用於微晶體材料之條件下沉積p-層 達65秒 3. pa-SiC:H-沉積非晶矽與碳之合金之p-型摻雜層 表3顯示單一接面非晶體太陽能電池的絕對值“標準 P”與本發明的“表面處理+標準P層”以及相對增益。 表2中所述之範例係展示結果，但並非限定。處理溫 度可於150與280°C之間變動，而不會偏離本發明之主旨。 可成功地採用介於13. 56MHz與82MHz(13. 56MHz之譜波） 間的頻率。對於該沉積製程而言，S i H4、H2、及摻雜物（如 果有的話）CH4、TMB、PH3之間的比例係恰當的，且可輕易 地從表2推導出來。應用於該製程室之功率將影響到所想 要之沉積速率，但是亦將影響到該層之結晶性以及其穩定 度。由於此範例中的電池之尺寸為1 cm2，故可由表2輕易 地推導出每平方公分（cm2)的個別功率密度。 本發明之製程應理解為用於在TC0表面上沉積經摻雜 的矽層之製程，包括以第一組製程參數實施第一電漿處理 製程步驟，接著以本質上相同的（第一）組製程參數但包含 摻雜物氣體或前驅物（precursor)來實施第二電漿沉積製 程步驟。舉例而言，p-#c層係以介於0. 1%至10%之間的 20 94994 201126742 -石夕烧濃度比（SiH4/H2)進行沉積，較佳的情況是，介於1% 至5%之間並具有摻雜物濃度比（摻雜物/石夕烧）介於0.01% ；至㈤車乂佳的情況是，介於〇. 05%至〇· 5%之間具有10 -mW/cm2至1 W/cm2之功率密度’較佳的情況是，介於5〇 mW/cm2 至300mW/cm之間並具有壓力介於〇. 5至12此紅之間。第 -製程步驟相關於第—加上第二製程步驟的持續時間之時 間比例應該介於5至20%之間及/或（以絕對數值而言）介於 3至15秒之間’較佳的情況是，介於5至1〇秒之間。上 述參數典型上係用於KAI-MPECVD反應器，該KAI-MPECVD 反應器操作於40MHz並具有大約3〇〇〇 cm2的電極表面。 此製程可擴及KAI 1200或類似的工業用反應器，如 同市售來自Oerlikon Solar的反應器。該TCO(ZnO)層可 沉積於習知為TC0 1200 (亦來自Oerlik〇n s〇lar)之系統 上。 本發明之方法可以有利的方式應用於所有類型的薄 膜矽光伏打層堆疊上，其中，經摻雜的視窗層必須被沉積 於TC0前方接點上。該矽光伏打層堆疊可為單一接面非晶 體的、串疊型接面微晶的、串疊型接面非晶體的、或者類 似結構的。 in. DART-擴散的抗反射處理 用於藉由改善載體基板來製造光伏打裝置之方法 本專利申請案的這個部分係實質上取自2009年9月 18日向美國專利商標局提出申請序號61/243, 689之美國 臨時申請案，而其係有關於改善用於薄臈、以矽為基礎的 94994 21 201126742 太陽此電池或模組之製程。更詳而言之，本專利申請案係 關於用於薄膜矽太陽能電池之基板或蓋板（superstrate) 的處理製程。 III. 1先前技術之缺點 所屬技術領域中持續對於改善電池效率並同時降低 製造成本這方面投入心力。此平衡相當難以維持。 為了改善光伏打（PV)裴置之電性轉換效率，應該於該 彡動矽層内盡可能吸收最多的照射光（impinging light)。 這個部分係藉由1)最小化反射比損失（reflectance 1〇ss) 以及2)於該光伏打主動；g夕層附近引入光—散射光學介面 (light-scattering optical interface)所達到。 於該蓋板p-i-n組構中產生光強度損失uight intensity loss)的第一光學介面係氣體/玻璃介面49.(第9 阖）。為了避免典型上由於此介面的光反射所造成的4%損 失，已知有兩種主要技術：抗反射薄膜塗佈（ARC)或者抗反 射蝕刻（化學式、電漿式或機械式）。 為了於光學介面得到光_散射，通常使用粗链的介面， A部分為TCO/Si介面，於第g圖中係位於參考點42(前方 接點）與44以及46與47(背面接點）之間。然而，強烈的 光-散射需要非常粗糙的TC〇，這使得後續之密集的矽生長 以及雷射圖案化該裝置變得更加困難。 因此，想藉由使用具有紋理的玻璃（textured giasses) 來引進粗糙的氣體/玻璃及/或粗糙的玻璃/TC0介面。然 而，使用初始具有紋理的玻璃係相當昂貴的，且於基本的 22 94994 201126742 雷射圖案化，，製程步驟會產生問題。 典型上’以p_i—n形式沉積於平坦的經AR塗佈的玻 • 璃上之薄獏矽太陽能電池接腳會顯現出3至4%的光電流增 加二從而直接增進電池效率。然而，市面上所販售用於可 ’ 見光-近紅外線（visible_near IR)範圍（寬頻）内之介電 从—塗佈的成本相當高。因此’經AR塗佈的麵特別用於 高效率（最高記錄）電池之製造。 就作者本身所知，用於產生抗反射玻璃之第二種已知 技術（亦即抗反射钱刻）到現在為止仍未使用於薄膜太陽 月b電池的製&上。這很讓人驚對，因為進一步姓刻該玻璃 月&夠額外地於該第一氣體/玻璃介面造成光_散射。然而， 由於對於沉積於初始具有紋理的玻璃之電池進行雷射構建 有額外的困難度，所以此效應可能尚未彰顯。確實，自玻 璃-側進入該裝置之圖案化雷射光束同樣會經歷此光—散射 效應，且因此，用於被定義之材料脫落（materiai ablation) 所需之集中強度（focused intensity)會有部分損失。如此 一來’更難以於光-散射玻璃上雷射刻劃電池與模組。當單 石串聯連接（monolithic series connection)係薄膜矽光 伏打之關鍵元件時，相較於習知以晶圓為基礎的技術，到 目前為止尚未對光-散射玻璃基板投之應用投以太多關注。 因此’提出一種‘電池後玻璃處理（post-cell glass treatment)”，能夠解耦（decouple)引進1)光學抗反射及 2)於該氣體/玻璃介面之光散射。因此，取決於最大裝置效 能所欲之光學擴散量’可能使得擴散抗反射處理 23 94994 201126742 (Diffusive Anti-Reflective Treatment;DART)適用於各 種薄膜太陽能電池組構。 III. 2.歸納 本發明建議，在完整電池或模組的製備之後構建該氣 體/玻璃介面49或為該氣體/玻璃介面49產生紋理。該破 璃係曝露於不會毀壞經製成於另一（避開的）侧上所製造之 太陽能電池（或者完全經雷射圖案化之模組）的韻刻處理。 此蝕刻DART處理宜藉由RIE(反應離子蝕刻）電漿蝕刻進行 實施’但不限定於此種製程。同樣可使用微波電漿餘刻 (microwave plasma etching)、機械或化學玻璃姓刻，端 視該玻璃成分而定。於下述條件之下進行5至15分鐘的蝕 刻DART已顯示為用於抗反射效應（antirefiective effect)，本發明之處理達到2小時將額外地提供增強的光 散射特性。 III. 3實施方式 已發現到，反應離子蝕刻反應器中以⑴與SFe混合物 進行的電漿處理（氣體通量比例（gas flux ^衍幻為SFe:〜 =5:卜壓力30mTorr，功率600至1000W，較佳的情況是， 持續超過5分鐘）係適合用於蝕刻Sch〇tt硼矽玻璃 (Borofloat)33 〇 為了避免損害電池堆疊，必須採取保護措施。如所屬 領域中所習知者’該;^層堆疊43與該背面接點層47(第9 圖）以及有時反射層（refleetive layer)48係藉由真空或 接近真空的製程步驟（如PECVD、LpcvD、pVD)進行沉積。 24 94994 201126742 =上程應使用於該製程的這個階段，則必須保護 ” 以免受到前側_製程的影響。可藉由 ==機械性手段(如具有夹固插架的載體裝設)來達 其中’該框架提供密封手段，能夠允許僅曝 路出基板41前側那些需經以打製程處理的部分。又或者， 可使用可移除的黏著薄膜或者可移除的塗料。本發明人發 現到令人驚舒的是眾所周知的白色塗料反射體（特徵⑻ 亦足狗提供保護，以免於⑽刻步驟所造成的曝露。由於 該擴散白色塗料反射體無論如何都必須應用於該模組組合 製程稍後之步驟中，故基本上無須額外的手段。對於非常 廣泛的DART處理而言，因為該處理所產生的熱或/及該 DART處理所採用之化學氣體，該白色塗料可改變其特性。 因此，對於長時間的處理或者能夠加熱該樣本（sample)的 處理而言，宜在施加白色塗料之前進行dart，或者提供足 夠的冷卻以避免負面效應。 第11圖顯示一系列玻璃/TC0/a-Si:Hpin/TC0結構之 經測量的總反射係數。於接近-鏡面的光入射時，於該氣體 /玻璃（Schott硼矽玻璃33)介面有7至6%的反射損失。藉 由使用範圍在400至650奈米内之典型的市售（Schott)寬 頻AR-塗佈會使得總反射降低至Rt〇tARcglase3%。這樣符合經 降低的反射RtotflatglaSs-Rt(DtARCglass=4%。本發明的擴散抗反射 處理（DART)持續至少15分鐘即能夠得到與昂貴的AR-塗佈 類似的Rm。進入該裝置的光強度的對應增益係完全轉換 成為該薄膜裝置之光電流（Jsc)3. 5至4%的相對增益。 25 94994 201126742 可留意到第11圖中，該AR-塗佈反射損失於400至 650奈米的範圍之間顯現出一些波長-相依性 (wavelength-dependency)(干擾邊緣），不同於平坦的玻璃 組構。這是由於該ARC效應依靠的是介電薄膜堆疊内之干 擾。然而，可看出該DART玻璃之干擾邊緣（fringe)之振幅 係降低的。 這是某些光學擴散效應必須發生在該氣體/DART介面 的實驗證據。藉由觀察經處理的玻璃表面形態（其粗糙度以 及形態隨著钱刻次數而形成）（於第11圖所示）可以看到上 述現象。因此，該DART處理可適用於僅僅產生抗反射效應 (短暫處理時間）或者抗反射+光-散射效應（較長的玻璃處 理時間）。 第12圖與第13圖顯示Schott硼石夕玻璃33之經處理 表面之掃描式電子顯微分析（scanning eiectrc)n micrograph)’該Schott硼矽玻璃33係以變動時間進行蝕 刻（具有〇2與SFe之反應離子蝕刻反應器（玻璃通量比例 SF6/〇2=1.67)、壓力5mTorr、以及i〇〇〇w之放電功率）。第 12圖· 5分鐘電漿處理，第13圖：120分鐘電漿處理。 第14圖顯示對串疊型微晶電池所測量到的不具有（無 AR，較低的曲線）以及具有DART處理（12〇分鐘，較高的曲 線）之外部量子效率EQE曲線。該頂部a_Si:H電池中與該 微晶體底部電池中之Jsc增益優於期望的4%表示來自該 DART處理對於增進光捕捉的貢獻。 這是一個優點，藉由這樣可進一步最大化該矽層中入 94994 26 201126742 射光的吸收。因此，該DART之擴散成分能夠適用於該前方 TC0光學散射特性，以及適用於該裝置厚度（串疊塑-或者 . 單一接面）。舉例而言，倘若該玻璃之DART增進長波長光 ； (〉700奈米）之光-散射，則該微晶體底部電池得以保持較 ’ 薄的厚度，用於與該頂部電池進行電流匹配。 可利用蝕刻該玻璃達較長時間而得到此效應。此效應 允許增加長波長範圍内的光-散射，這是一種難以從所生長 並研發用於a-Si :H電池之具有紋理的ZnO中得到之性質。 典型上’用於將微晶太陽能電池沉積於相當平坦的 ZnO上之最佳玻璃|虫刻製程需要較長時間，因為其必須具 有用於微aa碎底部電池的光—散射增加。最佳独刻時間也將 取決於該串疊型微晶電池内所存在的中間反射體存在與 否。 最後’已經觀察到DART與微晶太陽能電池的特別組 5並非限疋於增加的jsc，也可導致增加的v。。與ff。 所有這些範例皆指出DART允許針對TCO/a-Si : · H/TC0層厚度組合之幾乎任何組合的最大效率 作最佳化的修改。 上述應用已經使用於非常高效率之測試電池，倘若其 成本相較於所期望的3. 5-4%的模組功率增加並未過高，則 上述應用亦可應用於工業薄膜a-Si : Η矽模組。該反射係 數的角度相依性（angUlar dependenCy)非常小；也就是 說即使對於运離接近-鏡面（near-specular)的光入射角 度而s ’反射損失亦係降低的。因此，不僅較高的效率能 27 94994 201126742 藉由DART達到，實際的戶外應用中之模組的年度能源生產 (yearly energy pr〇duction)(kWh/kWp)也會因為 DART 特 性之微弱之角度相依性而受到正面的影響。習知之寬頻 AR-薄膜塗佈亦可經最佳化用於將角度相依性最小化，但是 這是用於最佳化此類塗佈的額外的、限制性的條件。 這種應用具有增加微晶串疊型太陽能電池效率以及 增強光捕捉能力的潛力，用於藉由前方玻璃/TC〇/Si/TC〇 裝置系統之最佳化結合來進一步縮減該Si吸收體（到現在 為止’於該底部電池之光電流有10%的增益，於一些情況 下有增加的V〇c與FF)。應了解到，上述内容所給定之數值 係取決於許多參數且無法輕易給定大致的成分配方 (recipe)。本發明之DART處理之曝露時間取決於該蝕刻機 器的能力、玻璃的類型（厚度、化學成分）、所使用的前方 與背面接點（尤其是，其霧度因子）、技術（aSi或微晶）、 對於各種技術中用於該電池的吸收體層厚度、中間反射體 的使用與否、以及-最後但並非最不重要的是僅得到抗反射 效應（短時間蝕刻）或者得到擴散加上抗反射（長蝕刻時 間）。於所屬技術領域具有通常知識者將基於上述基本教示 而對於各種製程環境採取必要的改變。 IV·在背面接點TC0沉積之前之經控制且經加速的氧化 用於藉由快速的氧化處理製造薄膜矽光伏打裝置以改善 良率與電性效能之方法 本專利申請案的這個部分係實質上取自2009年9月 18曰向美國專利商標局提出申請序號61/243,628之美國 28 94994 201126742 臨時申請案，而其係關於製造薄膜太陽能電池之方法。此 部分強調能夠降低此類薄膜太陽能電池之漏電流之處理。 . 尤其，本發明是有關於薄膜矽層或者藉由氧化最後沉積的 、 矽表面而形成部分薄膜太陽能電池之多層結構的氧化表面 ^ 處理。 為了評估良率，係於低光強度下（強度低於AM1. 5的 10%)測量（在背面接點沉積與電池圖案化之後）該等電池之 開路電壓L。在這些測量條件下，顯現出低於議m v開路 電壓之電池係被視為（部分）分流（shUnted)且於服5完 全照明之下將顯現出不良的電性效能。第15圖顯示顯現出 低於6财（亦即，所謂的部分分流）的照明開路電壓Voc之 二接點測試電池之標準机5電流（電壓）曲線以及在背面 氧化的相同ρ-的-個測試電 =)的電&(電壓）曲線（亦即，根據上述内容所提出的純化裝 有的原因使得薄膜石夕太陽能電池分流。舉 而厂該m轉點上的好料 響。但是倘若粒子俜兮梦番+ ㈣田負面的衫 從本質上凸起：之分流行為的原因，則可利用 從本質上凸起的背面接點（如公開文 述）來消除其效應。 ^ ZUU9/077605所 密度、低品質外料存在，如第16@=/中觀察到有低 中此财缺陷的區域所造成的負面效 94994 29 201126742 應已經描述於 Sakai et al，. J. of Non-Cryst. Solids 115 (1989) p. 198-200 for a-Si :H cel Is 以及 M. Python et al1----- Jsc QE Voc FF 00~ 70. 67 ΤοΓδό- ------- (mA/cm2) (mV) Efficiency 16. 81 903. 03^ 'θΤΤΤοο' _____«) 16. 98 10 73 10. 95 1. 02 0.88 0. lmo consisting of two steps (Table 2 for the example of the standard p-layer, the upper part): 1 · PM c - S i: Η - for microcrystals Conditional deposition of germanium material p _ layer 2 · Pa SiC : p-type doping of H-deposited amorphous germanium and carbon alloy ^ 94994 19 201126742 The proposed layer stack is surface treated, the surface treatment includes three Procedure (lower part of Table 2): 1. Surface treatment: The TC0 layer 42 was briefly exposed (5 seconds) to a plasma having p/zc conditions without a doping gas. The plasma conditions were selected to be the same as those of step 2, but without any dopant gases. 2. p/z c-Si:H- deposited p-layer for 65 seconds under conditions of microcrystalline material 3. pa-SiC: p-type doping of H-deposited amorphous germanium and carbon alloy Layer Table 3 shows the absolute value "Standard P" of a single junction amorphous solar cell and the "Surface Treatment + Standard P Layer" and relative gain of the present invention. The examples described in Table 2 show the results, but are not limiting. The treatment temperature can be varied between 150 and 280 ° C without departing from the spirit of the invention. A frequency between 13.56 MHz and 82 MHz (13.56 MHz spectral wave) can be successfully used. For this deposition process, the ratio between S i H4, H2, and dopants (if any) CH4, TMB, PH3 is appropriate and can be easily derived from Table 2. The power applied to the process chamber will affect the desired deposition rate, but will also affect the crystallinity of the layer and its stability. Since the size of the battery in this example is 1 cm2, the individual power density per square centimeter (cm2) can be easily derived from Table 2. The process of the present invention is understood to be a process for depositing a doped germanium layer on the surface of a TC0, including performing a first plasma processing process step with a first set of process parameters, followed by essentially the same (first) set The process parameters, but containing a dopant gas or precursor, are used to perform the second plasma deposition process step. For example, the p-#c layer is deposited with a concentration ratio of 20 94994 201126742 - Shi Xi burning (SiH4/H2) between 0.1% and 10%, preferably between 1%. Between 5% and having a dopant concentration ratio (dopant / Shi Xizhuo) of 0.01%; to (5) rut is better, between 〇. 05% to 〇 · 5% with 10 The power density of -mW/cm2 to 1 W/cm2 is preferably between 5 〇mW/cm2 and 300 mW/cm and has a pressure between 〇5 and 12% red. The ratio of the first-process step to the duration of the first-plus-second process step should be between 5 and 20% and/or (in absolute terms) between 3 and 15 seconds. The situation is between 5 and 1 second. The above parameters are typically used in a KAI-MPECVD reactor operating at 40 MHz and having an electrode surface of approximately 3 〇〇〇 cm 2 . This process can be extended to KAI 1200 or similar industrial reactors such as the commercially available reactor from Oerlikon Solar. The TCO (ZnO) layer can be deposited on a system known as TC0 1200 (also from Oerlik〇n s〇lar). The method of the present invention can be applied to all types of thin film tantalum photovoltaic layer stacks in an advantageous manner, wherein the doped window layer must be deposited on the TC0 front contact. The tantalum photovoltaic layer stack can be a single junction amorphous, tandem junction microcrystalline, tandem junction amorphous, or the like. DART-diffusion anti-reflection treatment method for manufacturing a photovoltaic device by improving a carrier substrate. This part of the patent application is substantially filed on September 18, 2009, to the US Patent and Trademark Office for application number 61/ 243, 689 of the United States interim application, and it is related to the improvement of the process of using this battery or module for the use of thin and sturdy-based 94949 21 201126742 solar. More specifically, this patent application relates to a processing process for a substrate or a superstrate for a thin film tantalum solar cell. III. 1 Disadvantages of Prior Art There has been a continuing effort in the art to improve battery efficiency while reducing manufacturing costs. This balance is quite difficult to maintain. In order to improve the electrical conversion efficiency of the photovoltaic (PV) device, the most impinging light should be absorbed as much as possible within the turbulent layer. This portion is achieved by 1) minimizing the reflectance loss (reflectance 1 〇 ss) and 2) introducing the light-scattering optical interface near the photovoltaic layer. A first optical interface gas/glass interface 49. (9th 阖) which produces a uight intensity loss in the cover p-i-n configuration. In order to avoid a 4% loss typically due to light reflection from this interface, two main techniques are known: anti-reflective film coating (ARC) or anti-reflective etching (chemical, plasma or mechanical). In order to obtain light-scattering from the optical interface, a thick-chain interface is usually used, and part A is a TCO/Si interface, which is located at reference point 42 (front contact) and 44 and 46 and 47 (back contact) in the g-th diagram. between. However, intense light-scattering requires very coarse TC 〇, which makes subsequent dense 矽 growth and laser patterning of the device more difficult. Therefore, it is desirable to introduce a rough gas/glass and/or rough glass/TC0 interface by using textured giasses. However, the use of an initially textured glass system is quite expensive, and the basic 22 94994 201126742 laser patterning, the process steps can cause problems. Typically, a thin tantalum solar cell pin deposited in a p_i-n form on a flat AR coated glass will exhibit a 3 to 4% increase in photocurrent to directly increase cell efficiency. However, the cost of dielectric-coating for sale in the visible-near IR range (broadband) is quite high. Therefore, the AR coated side is particularly useful for the manufacture of high efficiency (highest recording) batteries. As far as the author himself is aware, the second known technique for producing anti-reflective glass (i.e., anti-reflective money) has not been used in the manufacture and processing of thin film solar cells. This is quite surprising, as further surnames of the glass moon & additional enough to cause light-scattering of the first gas/glass interface. However, this effect may not be apparent due to the additional difficulty of laser construction for cells deposited on initially textured glass. Indeed, the patterned laser beam entering the device from the glass side will also experience this light-scattering effect, and therefore, the concentration intensity required for the defined materiale ablation will be partially loss. As a result, it is more difficult to laser and scratch the battery and module on the light-scattering glass. When the monolithic series connection is a key component of photovoltaics, compared to the conventional wafer-based technology, so far has not paid much attention to the application of light-scattering glass substrates. . Therefore, a 'post-cell glass treatment' is proposed which can decouple the introduction of 1) optical anti-reflection and 2) light scattering from the gas/glass interface. Therefore, depending on the maximum device performance The desired amount of optical diffusion 'may make the diffusion anti-reflection treatment 23 94994 201126742 (Diffusive Anti-Reflective Treatment; DART) suitable for various thin film solar cell structures. III. 2. Inductively proposed in the present invention, in a complete battery or module The gas/glass interface 49 is constructed or textured for the gas/glass interface 49. The glass system is exposed to solar cells that are fabricated without destroying the side that is made on the other (avoided) side (or completely Rhythm processing by laser patterned module. This etching DART process should be carried out by RIE (Reactive Ion Etching) plasma etching 'but not limited to this process. Microwave plasma residual can also be used ( Microwave plasma etching), mechanical or chemical glass, depending on the composition of the glass. 5 to 15 minutes of etching under the following conditions DART has been shown to be resistant An antirefiective effect, the treatment of the invention for up to 2 hours will additionally provide enhanced light scattering properties. III. 3 Embodiments have been found in a reactive ion etching reactor with a plasma treatment of (1) a mixture with SFe ( The gas flux ratio (SFe: SFe: ~ = 5: Bu pressure 30mTorr, power 600 to 1000W, preferably, lasts for more than 5 minutes) is suitable for etching Sch〇tt boron bismuth glass (Borofloat) 33 〇 In order to avoid damage to the battery stack, protective measures must be taken. As is known in the art, the layer stack 43 and the back contact layer 47 (Fig. 9) and sometimes the reflective layer The 48 series is deposited by vacuum or near vacuum process steps (such as PECVD, LpcvD, pVD). 24 94994 201126742 = The upper stage should be used at this stage of the process, it must be protected from the front side process. By == mechanical means (such as the carrier with the clamping insert) to reach the 'the frame provides a sealing means, can allow only the front side of the substrate 41 to be exposed to the process of processing Alternatively, a removable adhesive film or a removable coating can be used. The inventors have found that the well-known white paint reflector is surprising (feature (8) also provides protection for dogs (10). The exposure caused by the engraving step. Since the diffused white paint reflector must be applied to the later steps of the module assembly process anyway, substantially no additional means are required. For very extensive DART processing, the white coating can change its properties due to the heat generated by the treatment or/and the chemical gases used in the DART treatment. Therefore, for long-term processing or treatment capable of heating the sample, it is desirable to perform dart before applying white paint or to provide sufficient cooling to avoid negative effects. Figure 11 shows the measured total reflection coefficient for a series of glass/TC0/a-Si:Hpin/TC0 structures. When the near-mirror light is incident, there is a reflection loss of 7 to 6% in the gas/glass (Schott boron germanium glass 33) interface. A typical commercially available (Schott) wideband AR-coating using a range of 400 to 650 nm reduces the total reflection to Rt〇tARcglase 3%. This is consistent with the reduced reflection RtotflatglaSs-Rt (DtARCglass = 4%. The diffusion anti-reflective treatment (DART) of the present invention can achieve Rm similar to expensive AR-coating for at least 15 minutes. The light intensity entering the device The corresponding gain is completely converted into a photocurrent (Jsc) of the thin film device of 3.5 to 4% relative gain. 25 94994 201126742 It can be noted that in the 11th figure, the AR-coated reflection loss is 400 to 650 nm. Some wavelength-dependency (interference edges) appear between the ranges, unlike flat glass fabrics, because the ARC effect relies on interference within the dielectric film stack. However, it can be seen The amplitude of the fringe of the DART glass is reduced. This is the experimental evidence that some optical diffusion effects must occur in the gas/DART interface. By observing the morphology of the treated glass surface (its roughness and morphology The above phenomenon can be seen by the number of times the money is engraved (as shown in Fig. 11). Therefore, the DART processing can be applied to generate only anti-reflection effects (short processing time) or anti-reflection. + light-scattering effect (longer glass treatment time). Figures 12 and 13 show scanning electron microscopy (scanning eiectrc) n micrograph of the treated surface of Schott Boron Glass 33 'The Schott Boron The neodymium glass 33 is etched at a varying time (reactive ion etching reactor with 〇2 and SFe (glass flux ratio SF6/〇2=1.67), pressure 5 mTorr, and discharge power of i〇〇〇w). Figure 12 · 5 minutes plasma treatment, Figure 13: 120 minutes plasma treatment. Figure 14 shows an external quantum efficiency EQE curve measured for a tandem microcrystalline cell without (no AR, lower curve) and with DART treatment (12 〇 min, higher curve). The Jsc gain in the top a_Si:H cell and the bottom cell of the microcrystal is better than the desired 4% indicating the contribution from the DART process to enhancing light trapping. This is an advantage by which the absorption of the incoming light of 94994 26 201126742 can be further maximized. Therefore, the diffusion component of the DART can be applied to the front TC0 optical scattering characteristics, as well as to the thickness of the device (serial-stacked - or . single junction). For example, if the glass DART enhances long-wavelength light (>700 nm) light-scattering, the microcrystalline bottom cell is maintained at a relatively thin thickness for current matching with the top cell. This effect can be obtained by etching the glass for a longer period of time. This effect allows for an increase in light-scattering over a long wavelength range, a property that is difficult to obtain from textured ZnO grown and developed for a-Si:H cells. Typically, the best glass used to deposit a microcrystalline solar cell onto a relatively flat ZnO process requires a long time because it must have an increase in light-scattering for the microaaa bottom cell. The optimum etch time will also depend on the presence or absence of an intermediate reflector present in the tandem microcrystalline cell. Finally, it has been observed that the special group 5 of DART and microcrystalline solar cells is not limited to increased jsc, but can also result in increased v. . With ff. All of these examples indicate that DART allows for optimization of the maximum efficiency for almost any combination of TCO/a-Si: · H/TC0 layer thickness combinations. The above applications have been used in very efficient test cells. If the cost is not too high compared to the expected 3. 5-4% of the module power, the above applications can also be applied to industrial film a-Si: Η矽 module. The angular dependence of the reflection coefficient (angUlar dependenCy) is very small; that is, the s ' reflection loss is reduced even for the near-specular light incident angle. Therefore, not only is the higher efficiency 27 94994 201126742 achieved by DART, the annual energy production (kWh/kWp) of the modules in actual outdoor applications is also dependent on the weak angle of DART characteristics. Sexually and positively affected. Conventional broadband AR-film coatings can also be optimized for minimizing angular dependence, but this is an additional, limiting condition for optimizing such coatings. This application has the potential to increase the efficiency of the microcrystalline tandem solar cell and enhance the light trapping capability for further reducing the Si absorber by an optimized combination of the front glass/TC〇/Si/TC〇 device system ( Up to now, the photocurrent at the bottom cell has a gain of 10%, and in some cases increased V〇c and FF). It should be understood that the values given above are dependent on a number of parameters and that it is not easy to give a rough recipe. The exposure time of the DART treatment of the present invention depends on the ability of the etching machine, the type of glass (thickness, chemical composition), the front and back joints used (especially, its haze factor), the technique (aSi or microcrystalline) ), the thickness of the absorber layer for the battery in various technologies, the use of the intermediate reflector, and - last but not least, only the anti-reflection effect (short-time etching) or diffusion plus anti-reflection (long etching time). Those having ordinary skill in the art will take the necessary changes to various process environments based on the above basic teachings. IV. Controlled and accelerated oxidation prior to deposition of the back contact TC0 for the manufacture of thin-film photovoltaic devices by rapid oxidation treatment to improve yield and electrical performance. This part of the patent application is essentially U.S. Patent Application Serial No. 61/243,628, filed on Sep. 18, 2009, to the U.S. Patent Application Serial No. 61/243,628, which is incorporated herein by reference. This section emphasizes the ability to reduce the leakage current of such thin film solar cells. In particular, the present invention relates to an oxide surface treatment of a thin film structure or a multilayer structure in which a partial thin film solar cell is formed by oxidizing the finally deposited tantalum surface. To evaluate the yield, the open circuit voltage L of the cells was measured at low light intensity (intensity below 10% of AM 1.5) after back contact deposition and cell patterning. Under these measurement conditions, a battery system exhibiting an open circuit voltage lower than the mv is considered to be (partially) shunted and will exhibit poor electrical performance under full illumination of the device 5. Figure 15 shows the standard 5 current (voltage) curve of the two-contact test cell showing the open circuit voltage Voc of less than 6 (that is, the so-called partial shunt) and the same ρ- of the oxidation on the back side. Test the electric & (voltage) curve of electricity =) (that is, according to the purification installation proposed above, the thin film solar cell is shunted. The factory is good at the m turn point. But if Particles 俜兮梦番+ (4) The negative shirts of the field are essentially bulging: the reason for the popularity is that the backside joints (such as the open text) that are raised in essence can be used to eliminate the effect. ^ ZUU9/077605 Density, low-quality external materials exist, such as the negative effect of the area with low-medium financial defects observed in 16@=/. 94994 29 201126742 should have been described in Sakai et al,. J. of Non-Cryst. Solids 115 (1989) p. 198-200 for a-Si :H cel Is and M. Python et al

Solar Energy Materials and Solar Cells 93, Issue l〇 (2009) p.1714-1720 for microcrystalline siliconSolar Energy Materials and Solar Cells 93, Issue l〇 (2009) p.1714-1720 for microcrystalline silicon

Solar Cells 中。 第16圖顯示藉由PECVD沉積於粗糙玻璃/TCO蓋板上 之a-Sip-i-n太陽能電池的剖面的傳輸電子顯微分析（該 顯微分析的底部）。該圓圈區域顯不出存在有低密度且有孔 的矽材料。該TEM顯微分析係出現在3D層堆疊中之2D “ $ 漏範圍（leaking boundary)”之投影圖。此種範圍係於該 基板的凹陷處觀察到。此類低密度材料拖累該整體裝置電 性效能，且因此預期有高度的電子效能缺陷。 眾所周知，對於非常薄的p-i-n裝置（i-層厚度小於 200奈米，ρ-層厚度小於10奈米）或者沉積於具高度紋理 的前方接點上之p-i-n裝置（非常粗糙的TCOs或者具有非 常尖銳的凹陷角度之表面的玻璃/TC0蓋板）而言，要得到 高良率相當的困難。於這些情況下，倘若於PECVD η-層沉 積之後直接沉積該背面接點，則電池會部分或總體分流。 然而，我們已經觀察到於氣體環境中保存未完成的裝 置（亦即，在η-層PECVD沉積之後以及在沉積背面接點之 前）持續幾天能夠增加（稍後的）完成的裝置的良率與轉換 效率。 這些有缺陷的範圍已經被識別為電流洩漏範圍。這些 低密度且有缺陷的材料區域可發生於該PECVD反應器内之 94994 30 201126742 b « 層生長（layer以抓让）期間或者於該PECVD反應器外之層 卸除（layer unloading)期間（自沉積溫度（〜2〇(rc)至環境 • 溫度）。根據第17圖所繪示之等效電路，其對於裝置電性 - 特性的負面影響係隨著如剖面圖所測量到的線性密度 (linear density)而專比例地增加暗漏電流（dark ieakage current)(對於微晶石夕而言：參考Martiri Python et al. Solar Energy Materials and Solar Cells Volume 93,In Solar Cells. Figure 16 shows a transmission electron microscopic analysis of the cross section of an a-Sip-i-n solar cell deposited on a rough glass/TCO cover by PECVD (bottom of the microscopic analysis). This circular area shows the presence of a low density and porous material. The TEM microscopy is a 2D "leaking boundary" projection that appears in the 3D layer stack. This range is observed in the depression of the substrate. Such low density materials drag the overall device electrical performance and are therefore expected to have high levels of electronic performance defects. It is well known for very thin pin devices (i-layer thickness less than 200 nm, ρ-layer thickness less than 10 nm) or pin devices deposited on highly textured front contacts (very rough TCOs or very sharp In the case of a glass/TC0 cover on the surface of the recessed angle, it is quite difficult to obtain a high yield. In these cases, if the back contact is deposited directly after the PECVD η-layer is deposited, the cell will be partially or totally shunted. However, we have observed that the preservation of unfinished devices in a gaseous environment (ie, after η-layer PECVD deposition and before deposition of backside contacts) can increase the yield of (later) completed devices for several days. And conversion efficiency. These defective ranges have been identified as current leakage ranges. These low density and defective regions of material may occur during the 949.4 30 201126742 b «layer growth (layer grabbing) or during layer unloading outside the PECVD reactor in the PECVD reactor (from Deposition temperature (~2〇(rc) to environment•temperature). According to the equivalent circuit shown in Figure 17, the negative effect on the electrical-characteristics of the device is the linear density measured as shown in the cross-section ( Linear density) and the proportion of dark ieakage current (for microcrystalline eve: refer to Martiri Python et al. Solar Energy Materials and Solar Cells Volume 93,

Issue 10, October 2009，pages 1714-172〇)。第 π 圖顯 不顯現出洩漏範圍的粗糙基板上之薄膜矽太陽能電池的簡 化等效電路。這些洩漏範圍係在圖中繪示為第二二極體具 有南暗電流Jdiode2” 。 第18圖顯示泡漏範圍密度對於微晶矽太陽能電池之暗 電流密度J。2之效應（於此範例中稱為“崩裂（crack)，，）。第 18 圖係取自 M. Python，PhD dissertation，Instituted Microtechnology， University 〇f Neuchatel， 2009 。原Issue 10, October 2009, pages 1714-172〇). The πth figure shows a simplified equivalent circuit of a thin film 矽 solar cell on a rough substrate which does not show a leak range. These leakage ranges are shown in the figure as the second diode has a south dark current Jdiode2". Figure 18 shows the effect of the bubble leak range density on the dark current density J.2 of the microcrystalline solar cell (in this example) It is called "crack,". Figure 18 is taken from M. Python, PhD dissertation, Instituted Microtechnology, University 〇f Neuchatel, 2009. original

始標題.對於各種基板上共同沉積的mc Si:H電池中經TEM 顯微分析所估計的p—i—n組構而言，Jq2與崩裂密度之間的 關係。於高效太陽能電池中係觀察到低k與低崩裂密度。 對於給疋的PECVD沉積條件，如剖面圖中所觀察到的 有缺陷的範圍之線性密度係取決於蓋板形態；以及對於給 定的蓋板形態’可找到降低這些有缺陷的茂漏範圍密度的 PECVD沉積條件。以下所描述的條件能夠停用（七丄V*) 化些Λ漏範圍，以此方式能夠顯著地改善該裝置電性特性 與良率。 94994 31 201126742 ιν. 1先前技術的缺點 在用於增進良率的η-層沉積之後於氣體環境中保存 之效應發生得非常慢。對於相當平坦、標準的前方接點而 言’為了得到高良率必須保存於氣體環境中大約1〇個鐘 頭’而對於具有高度紋理的TC0或者對於關鍵的、薄的 p-i-n裝置而言’為了得到高良率必須保存一個星期。 IV. 2.歸納 本發明建議在沉積背面接點TC0之前，提供薄膜太陽 能電池之矽層堆疊之經控制且經加速的氧化。 於第一實施例中，個別的矽表面係曝露於富含H2〇及/ 或30%出〇2的氣體環境中長達約1小時，較佳的情況是， 於100°C的溫度下長達1至2小時。提高溫度將能夠降低 曝露時間。於第二實施例中，該矽表面應該於室溫下曝露 於臭氧中長達1小時。於本實施例之變化例中，溫度係設 定於約100°c，以加速與臭氧的氧化製程。已發現到，曝 露於此種環境下長達5至15分鐘係有效的。於進一步的變 化例中，周遭的壓力已經設定為〇.5mbar持續達15分鐘。 更高的臭氧濃度能夠進一步降低該處理的持續期間。於第 三實施例中，係於該n-層沉積之後使用軟性氧化電漿 (soft oxidizing plasma)(例如：C2F6、C〇2、〇2、SF6)。較 佳情況是，應實施該軟性氧化電漿（功率l〇〇w(於3000 cm2 的電極面積上），溫度200。〇達數秒鐘，較佳的情況是， 超過10秒鐘。已經發現到，超過一分鐘的處理並沒有幫 助。改變有效功率與基板溫度將可變更曝露時間而不會偏 32 94994 201126742 離本發明所主張的範,。 IV.3·實施方式 本說明書中所描 設背面接點之前的處理者=關於在η'層沉積之後而在鋪 並且即便批積於料/處理較氣體環境—保存製程更快 米）上的薄ρ+η I =才造的蓋板（例如：Ζη◦廳>100奈 <200奈米）或者標準厚^之—薄的:層厚度，卜層厚度 , 度的層厚度>200奈米）亦 能二侍财夠的良率。在該氧化處理之後，該裝置的電性 效肥係經改善（如第15圖所示，主要在於開路電壓盘填充 因子）。這魏理包括氧化化學劑（QXidizing如㈣ a_)與溫度及壓力之結合，能夠使得氧化製程於曝露於 周遭氣體環境下的期間發生得非常慢。明顯地，於個別實 施例中’所有這些處理皆可經電漿輔助（plasma assisted. ) ° 於本說明書中，氧化反應係被理解為傳統化學，亦即 為典型的氧化還原反應（rebox reaction)，其中，電子係 從一種物質轉移至另一種物質。本說明書中，氧化劑係接 受電子的物質。因此，該氧化劑並非限定於氧。舉例而言， 即便因為氟、硫、氯、氮等其中一些作為石夕中的摻雜元素 具有負面的效應而不被優先使用，氟、硫、氯、氮等仍可 為矽之化學氧化劑。已經研究出數種加速氧化製程的可能 方法。典型上較快的處理需要少於1小時，較佳的情況是， 少於或等於5分鐘。 對於這些實施例而言，已採用習知a~si : H p-i-n層 94994 33 201126742 堆疊（i-層厚度240奈米，初始效率>11%)之標準狀態。已 經評估有數種氧化製程經過評估。 在η-層沉積之後，已經觀察到 1) 將p-i-n裝置於爐中以100°C溫度下曝露於潮濕的 氣體環境（含有濃度30%之去離子之H2〇或H2〇2的 “Becher”玻璃）中達1小時，較佳的情況是2小時，能夠 使得關鍵的TCO之良率自〇增進至大約80%，且該經處理 的電池顯現出良好的I(V)特性。 2) 將p-i-n裝置於爐中於室溫（及1 atm)下曝露於自 市售臭氧產生器所提供之氣體所得到之臭氧（〇3)中達1小 時或更久’能夠於高度具有紋理的TC0上得到高良率與良 好的KV)特性。溫度提升至i〇〇°c加速了與臭氧的氧化製 程。溫度與曝露時間之結合係根據前方TC〇粗糙度/紋理而 提供最佳化的良率：於爐中以1〇〇〇c的溫度對標準Zn〇(第 19圖中稱為“平坦的持續臭氧處理5分鐘可明顯改善 良率’但是對於高度具有紋理的Zn㈣言，達到高良率所 需的較佳處理時間係15分鐘（第16圖中稱為 “粗縫的”）。 ，長的曝露時間可能並非如此有效率。於或更高的 範例溫度以及〇. 5mbar的真空下曝露於&中持續）5分鐘 (如於ZnO LPCVD設備中，在背面接點沉積之前）係用於n一 粒積與背面接點沉積之間另—種可能的臭氧氧化方式。 於氧，室巾彻較〶的臭氧濃度（例如：利賴氧產生臭氧) 可使传氧化時間甚至少於5分鐘。 )臭氧曝路的替代方式係在層沉積之後施加軟性 94994 201126742 ' 氧化電漿（例如：C2F6、C〇2、〇2、SF6)。較佳的情 市售類似Oerlikon Solar ΚΑΙ之PECVD系統中 疋於 的权性氧電漿·（功率300 mW/cm2，溫度2〇〇t)(’只數& ：是，超過10秒）會導致在關鍵的tco上達到古= 圭的情況 •標準Μ上達到改善的電池效能。 喊率並且於 第19圖以兩種不同的前方TC〇類型顯示臭氧曝露時 間對於p-i-n裝置良率之影響。在5分鐘之後就會有些許 改善’較佳的持續時間係15分鐘。 本發明所提出的快速氧化製程使得製造於標準TC〇上 之電池之轉換效率增加。此外，能夠使用各種前方TC〇/玻 璃組合，尤其是具有較高粗糙度以及較高光散射特性之前 方TC0/玻璃。 可成功實現非常薄（i-層的厚度少於1〇〇奈米）且具有 良好I(V)特性的a-Si :Hp-i-n，並且最終可實施於a-Si : H pin-pin串疊型電池，開啟了用於穩定且以a_Si : H為 基礎的高效能電池與粗糙TC0之潜力。 亦可應用此類我化處理用於停用微晶體單一接面電 池中與微晶電池中的洩漏範圍。 【圖式簡單說明】 如上所述，本發明已經藉由範例與所包含的圖式進行 詳細描述。該等圖式顯示； 第1圖顯示LPCVD-ZnO類型Α之表面之掃描式電子顯 微鏡（SEM)顯微分析； 第2圖顯示沉積於玻璃（厚度1mm之Schott硼矽玻璃 35 94994 201126742 33)上之LPCVD-ZnO類型A總體透射比（上側圖，經測量而 無指數匹配液體（index matching 1 iquid))與擴散透射比； 第3圖顯示2008年所測量的結果。厂。。、/sc、//數值、 及效率於初始與吸收光狀態中如同該i-層厚度之函數 [7]〇LPCVD-ZnO係用以作為前方TC0(於600奈米之霧度係 20%)。該i-層厚度係自180變化至400奈米，而沉積速率 係3. 35 A/s。對於經改善的統計數據而言，考量4至7 個電池（對於各種厚度而言）； 第4圖顯示2009所測量的結果。^、心、/7數值、 及效率於初始與吸收光狀態中如同該i-層厚度之函數。 LPCVD-ZnO類型A係用以作為前方TC0(於600奈米之霧度 係12%)。該i-層厚度係自180變化至350奈米，而沉積速 率係1. 75 A/s。對於經改善的統計數據而言，考量4至7 個電池（對於各種厚度而言）； 第 5 圖顯示由 Oerlikon Solar-Lab Neuchatel 所製 備並測量之最高紀錄單一接面a-Si : Η吸收光電池； 第6圖顯示a-Si:H單一接面太陽能電池（NREL確認） 所得到之最高紀錄穩定效率（1〇. 〇9%)之丨（v)。該電池係沉 積於R&D ΚΑΙ™ -M系統（52x41平方公分基板尺寸）中。所 使用的superstrate係厚度lmm的Schott硼石夕玻璃33之 玻璃’於其上沉積有具高霧度因子的LpCVD_zn〇(ZnO類型 B)。於此電池上施加有本發明内部之ar ; 第7圖顯示推導自於NREL對最高紀錄電池3497所測 量之NREL相對QE與AM1. 5下短路電流密度之絕對外部量 36 94994 201126742 子效率（abs EQE)。此i-層厚度為250奈米之電池係於開 路電壓條件下事先吸收光； 第8圖顯示LPCVD-ZnO上最佳的p-i(180奈米）-η - a-Si · Η(吸收光）10x10平方公分迷你模組之Ι(ν)曲線， • 係由JRC於Ispra之ESTI實驗室所側量得到； 第9圖顯示基本、簡單的光伏打電池； 第10圖顯示外部量子效率（EQE)資料； 第11圖顯示一系列玻璃/TCO/a-Si : Η接腳/TC0結構 之經測量總反射係數； 第12圖顯示經钮刻的Schott棚石夕玻璃33之玻璃之 經處理表面之掃描電子顯微分析（5分鐘電漿處理）； 第13圖顯示經蝕刻的Sch〇ti：硼矽玻璃33之玻璃之 經處理表面之掃描電子顯微分析（12〇分鐘電漿處理）； 第14圖顯示對於不具有（無AR，下侧曲線）與具有 DART處理（12〇分鐘，上側曲線）之串疊型微晶電池所測量 的外部電子效率（EQE)曲線； 第15圖顯示三接點測試電池之標準AM1. 5 I(v)曲線； 第16圖顯示藉由PECVD所沉積之a-Si : Η接腳太陽 能電池之剖面之傳輸電子顯微分析； 第17圖繪示粗糙基板上薄膜矽太陽能電池之簡化等 效電路，顯現出洩漏範圍； 第18圖顯示洩漏範圍密度於微晶矽太陽能電池暗電 流J。2上之效應；以及 第19圖以兩種不同的前方TC0類型顯示臭氧曝露時 37 94994 201126742 間對於接腳裝置良率之影響。 上述實施例係作為範例，而非局限本發明。 考文獻] [1] u. Krolletal., Thin Sol id Fi lms 451-452 (2004), pp. 525-530.Heading. Relationship between Jq2 and cracking density for the p-i-n configuration estimated by TEM microanalysis in co-deposited mc Si:H cells on various substrates. Low k and low cracking density were observed in high efficiency solar cells. For the PECVD deposition conditions given to the crucible, the linear density of the defective range as observed in the cross-section depends on the form of the cover; and for a given cover morphology, a reduction in the density of these defective leaks can be found. PECVD deposition conditions. The conditions described below can disable (seven 丄V*) the leakage range, which can significantly improve the electrical characteristics and yield of the device. 94994 31 201126742 ιν. 1 Disadvantages of the prior art The effect of preserving in a gaseous environment after the η-layer deposition for increasing the yield occurs very slowly. For fairly flat, standard front contacts, 'in order to get high yields, it must be kept in a gas environment for about 1 hour' and for highly textured TC0 or for critical, thin pin devices' in order to get high quality The rate must be saved for one week. IV. 2. INTRODUCTION The present invention suggests providing controlled and accelerated oxidation of the ruthenium stack of thin film solar cells prior to deposition of backside contacts TC0. In the first embodiment, the individual ruthenium surface is exposed to a gas atmosphere rich in H2 〇 and/or 30% 〇 2 for up to about 1 hour, preferably at a temperature of 100 ° C. Up to 1 to 2 hours. Increasing the temperature will reduce the exposure time. In the second embodiment, the surface of the crucible should be exposed to ozone at room temperature for up to 1 hour. In a variation of this embodiment, the temperature is set at about 100 ° C to accelerate the oxidation process with ozone. It has been found that exposure to such an environment for up to 5 to 15 minutes is effective. In a further variation, the ambient pressure has been set to 〇5 mbar for up to 15 minutes. Higher ozone concentrations can further reduce the duration of the treatment. In the third embodiment, a soft oxidizing plasma (e.g., C2F6, C〇2, 〇2, SF6) is used after the n-layer deposition. Preferably, the soft oxidizing plasma (power l〇〇w (on an electrode area of 3000 cm2), temperature 200. should be applied. The enthalpy is several seconds, preferably more than 10 seconds. It has been found The process of more than one minute does not help. Changing the effective power and the substrate temperature will change the exposure time without biasing 32 94994 201126742. From the scope of the invention, IV.3·Embodiment The processor before the face contact = the thin ρ+η I = on the η' layer after deposition and even if it is stacked in the material/treatment compared to the gas environment - the saving process is fast (for example) : Ζ ◦ & & 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 After the oxidation treatment, the electrical fertilizer of the device was improved (as shown in Fig. 15, mainly in the open circuit voltage pad filling factor). This combination of oxidizing chemicals (QXidizing (4) a_) in combination with temperature and pressure can cause the oxidation process to occur very slowly during exposure to ambient gases. Obviously, in individual embodiments, 'all of these treatments can be plasma assisted. In the present specification, the oxidation reaction is understood to be a conventional chemistry, that is, a typical redox reaction. Where electrons are transferred from one substance to another. In the present specification, the oxidizing agent is a substance that receives electrons. Therefore, the oxidizing agent is not limited to oxygen. For example, fluorine, sulfur, chlorine, nitrogen, etc., may be chemical oxidants of ruthenium even if some of fluorine, sulfur, chlorine, nitrogen, and the like have a negative effect as a doping element in Shixia. Several possible methods of accelerating the oxidation process have been developed. Typically, faster processing requires less than one hour, and preferably less than or equal to five minutes. For these examples, the standard state of the conventional a~si: H p-i-n layer 94994 33 201126742 stack (i-layer thickness 240 nm, initial efficiency > 11%) has been employed. Several oxidation processes have been evaluated. After the η-layer deposition, it has been observed that 1) the pin device is exposed to a humid gas atmosphere at a temperature of 100 ° C in a furnace ("Becher" glass containing 30% deionized H2 〇 or H 2 〇 2) In the case of 1 hour, preferably 2 hours, the critical TCO yield can be increased from about 80 to about 80%, and the treated battery exhibits good I(V) characteristics. 2) Exposing the pin device to the ozone (〇3) obtained from the gas supplied by the commercial ozone generator at room temperature (and 1 atm) for 1 hour or longer 'can be highly textured High yield and good KV characteristics are obtained on TC0. The temperature rise to i〇〇°c accelerates the oxidation process with ozone. The combination of temperature and exposure time provides optimum yield based on front TC〇 roughness/texture: in the furnace at a temperature of 1〇〇〇c versus standard Zn〇 (referred to as “flat continuous in Figure 19” Ozone treatment for 5 minutes can significantly improve yield 'but for highly textured Zn (4), the preferred processing time required to achieve high yield is 15 minutes (referred to as "coarse" in Figure 16). Long exposure The time may not be so efficient. Exposure to & for 5 minutes at or above a 5 mbar vacuum (as in ZnO LPCVD equipment, before back contact deposition) is used for n Another possible mode of ozone oxidation between the granulation and the back contact deposition. In oxygen, the ozone concentration of the chamber towel (for example, the production of ozone by the lysine) can make the oxidation time even less than 5 minutes. An alternative to ozone exposure is to apply soft 94949 201126742 ' oxidized plasma (eg C2F6, C〇2, 〇2, SF6) after layer deposition. It is better to buy a PECVD system similar to Oerlikon Solar. Weighted oxygen plasma 300 mW/cm2, temperature 2〇〇t) ('only number & : yes, more than 10 seconds) will lead to the situation of the ancient = gui on the key tco • Standard Μ achieve improved battery performance. The effect of ozone exposure time on the pin device yield is shown in Figure 19 with two different front TC〇 types. There is some improvement after 5 minutes. The preferred duration is 15 minutes. The proposed rapid The oxidation process increases the conversion efficiency of the cells fabricated on standard TC〇. In addition, various front TC〇/glass combinations can be used, especially TC0/glass with higher roughness and higher light scattering characteristics. Thin (i-layer thickness less than 1 〇〇 nanometer) and a-Si:Hp-in with good I(V) characteristics, and finally can be implemented in a-Si : H pin-pin tandem battery, Turns on the potential for stable and a_Si: H-based high-performance batteries and rough TC0. This type of processing can also be used to deactivate the leakage range in microcrystalline single-junction cells and microcrystalline cells. [Simple description of the diagram] As described above The invention has been described in detail by way of examples and the accompanying drawings. The drawings show: FIG. 1 shows scanning electron microscopy (SEM) microscopy of the surface of LPCVD-ZnO type tantalum; FIG. 2 shows deposition LPCVD-ZnO type A overall transmittance (top panel, measured without index matching 1 iquid) and diffuse transmittance on glass (Schott boron germanium glass 35 94994 201126742 33) (thickness 1 mm); The figure shows the results measured in 2008. plant. . , /sc, / / value, and efficiency in the initial and absorbed light state as a function of the thickness of the i-layer [7] 〇 LPCVD-ZnO is used as the front TC0 (20% in the 600 nm haze system) . The thickness of the i-layer is varied from 180 to 400 nm, and the deposition rate is 3.35 A/s. For improved statistics, consider 4 to 7 batteries (for various thicknesses); Figure 4 shows the results measured in 2009. ^, heart, /7 value, and efficiency are a function of the thickness of the i-layer in the initial and absorbed light states. LPCVD-ZnO type A was used as the front TC0 (12% haze at 600 nm). The thickness of the i-layer was varied from 180 to 350 nm, and the deposition rate was 1.75 A/s. For improved statistics, consider 4 to 7 batteries (for various thicknesses); Figure 5 shows the highest recorded single junction a-Si prepared by Oerlikon Solar-Lab Neuchatel: Η absorbing photocell Figure 6 shows the highest record stable efficiency (1〇. 〇9%) obtained by a-Si:H single junction solar cells (NREL confirmed) (v). The battery was deposited in an R&D ΚΑΙTM-M system (52 x 41 cm 2 substrate size). The superstrate used was a glass of Schott Boron Glass 33 having a thickness of 1 mm, on which LpCVD_zn(R) (ZnO type B) having a high haze factor was deposited. The internal ar of the present invention is applied to the battery; Figure 7 shows the absolute external amount of the short-circuit current density of NREL relative to QE and AM1.5 measured from NREL for the highest recorded battery 3497 36 94994 201126742 Sub-efficiency (abs EQE). The battery with an i-layer thickness of 250 nm absorbs light in advance under open circuit voltage; Figure 8 shows the best pi (180 nm)-η - a-Si · Η (absorbed light) on LPCVD-ZnO The Ι(ν) curve of the 10x10 cm2 mini-module, • is obtained by JRC at the ESTI laboratory of Ispra; Figure 9 shows the basic, simple photovoltaic cell; Figure 10 shows the external quantum efficiency (EQE) Figure 11 shows a series of glass/TCO/a-Si: measured total reflection coefficients for the Η pin/TC0 structure; Figure 12 shows the treated surface of the glass with the button engraved Schott shed glass 33 Scanning electron microscopy (5 minutes plasma treatment); Figure 13 shows scanning electron microscopy (12 〇 minute plasma treatment) of the treated surface of the etched Sch〇ti: boron bismuth glass 33; Figure 14 shows the external electronic efficiency (EQE) curve measured for a tandem microcrystalline cell without (no AR, lower curve) and with DART treatment (12 〇 minutes, upper curve); Figure 15 shows three connections Point test battery standard AM1. 5 I (v) curve; Figure 16 shows by PECVD A-Si: transmission electron microscopic analysis of the profile of the tantalum solar cell; Figure 17 shows a simplified equivalent circuit of the thin film tantalum solar cell on the rough substrate, showing the leakage range; Figure 18 shows the leakage range density In the microcrystalline solar cell dark current J. Effect on 2; and Figure 19 shows the effect of the yield on the pin device when the ozone exposure is shown in two different front TC0 types. The above embodiments are by way of example and not of limitation. References] [1] u. Krolletal., Thin Sol id Fi lms 451-452 (2004), pp. 525-530.

[2] U. Kroll et al.，Proc 19th EU PVSEC (Paris 2004)， paper 3A0.8.1.[2] U. Kroll et al., Proc 19th EU PVSEC (Paris 2004), paper 3A0.8.1.

[3] J. Meier, J. Spitznagel，U. Kroll，C· Bucher， S. Fay, T. Moriarty, A. Shah, Thin Solid Films 451-452 (2004) p. 518.[3] J. Meier, J. Spitznagel, U. Kroll, C. Bucher, S. Fay, T. Moriarty, A. Shah, Thin Solid Films 451-452 (2004) p. 518.

[4] 0· Kluth et al，Proc 20th EU PVSEC (Barcelona 2005) , paper 3DV. 3. 38. t5] U. Krolletal., Proc. 23rd EU PVSEC (Milan 2007), paper 3C0. 1.2，p. 1795-1800.[4] 0· Kluth et al, Proc 20th EU PVSEC (Barcelona 2005) , paper 3DV. 3. 38. t5] U. Krolletal., Proc. 23rd EU PVSEC (Milan 2007), paper 3C0. 1.2, p. 1795 -1800.

[6] S. Benagli et al.，Proc. 21st EU PVSEC (Dresden 2006) ，paper 3DV. 3. 42，p.1719-1723.[6] S. Benagli et al., Proc. 21st EU PVSEC (Dresden 2006), paper 3DV. 3. 42, p.1719-1723.

[7] S. Benagli et al.，Proc· 24th EU PVSEC (Valencia 2008), paper 3AV. 2.23, p. 2414-2418.[7] S. Benagli et al., Proc· 24th EU PVSEC (Valencia 2008), paper 3AV. 2.23, p. 2414-2418.

[8] J. Meier et al, Proc 19th EU PVSEC (Paris 2004)， paper 3BP. 1.2 .[8] J. Meier et al, Proc 19th EU PVSEC (Paris 2004), paper 3BP. 1.2 .

[9] J. Meier et al.， Proc. 3rd WCPEC (Osaka 2003) session S2. A. Green, Keith Emery, Yoshihiro Hishikawa and Wilhelm Warta, Progress in Photovoltaics: 38 94994 201126742[9] J. Meier et al., Proc. 3rd WCPEC (Osaka 2003) session S2. A. Green, Keith Emery, Yoshihiro Hishikawa and Wilhelm Warta, Progress in Photovoltaics: 38 94994 201126742

II

Research and Applications 2009; 17:320-326. 【主要元件符號說明】 無 39 94994Research and Applications 2009; 17:320-326. [Key Symbol Description] None 39 94994

Claims (1)

201126742 七、申請專利範圍： 1 ’種用於製造非晶石夕p- i -η太陽能電池之方法，該電池 包括抗反射塗佈以及經摻雜的LPCVD ΖηΟ前方與背面接 點’其中’該經摻雜的LPCVDZnO前方與背面接點係由 大型粒狀物所構成之多晶膜，該大型粒狀物的末端如同 角錐出現於生長表面，該方法包括： 藉由LPCVD沉積該前方接點； 藉由電漿輔助化學氣相沉積沉積該p-i-n太陽能 電池之矽層； 藉由LPCVD沉積該背面接點；以及 設置該抗反射塗佈。 2.如申請專利範圍第1項所述之方法，其中，以下至少一 者適用： 該方法包括使用厚度1mm之Schott硼矽玻璃33 之玻璃作為蓋板，該Schott硼矽玻璃33之玻璃上沉積 有於600奈米具有70%之霧度因子之LPCVD-ΖηΟ ; 該電池具有超過10%阻障（barrier)的穩定電池效 率，尤其是10. 〇9%的穩定電池效率； 該方法包括於單一腔室電漿輔助化學氣相沉積反 應器中沉積該石夕膜，尤其是於Oerlikon Solar KAI系 統中； 該方法包括將該背面接點與白反射體結合； 該方法包括於丨.75A/s的沉積速率下沉積該i層； 該i層具有丨.73電子伏特的光學能隙（optical 1 94994 201126742 •· bandgap)； 該i層具有250奈米的厚度；以及 該方法包括藉由雷射圖案化而構建該電池。 ·· 3·如申請專利範圍第1項或第2項所述之方法，其中，該 • 非晶矽p-i-n電池包括具有玻璃/氣體介面之基板 /p- i -η接面組構’該玻璃/氣體介面由於該抗反射塗佈 而具有抗反射能力，該方法包括設置具有玻璃/氣體介 面之玻璃基板/p-i-n接面組構，並且接著DART蝕刻該 玻璃/氣體介面之該玻璃表面，以提供該抗反射（AR)以 及所欲之光散射能力（D)。 4. 如申請專利範圍第3項所述之方法，其中，於第一時段 期間實施蝕刻以提供抗反射能力（A R )，並且於經選定的 第二時段期間額外地實施該蝕刻以額外地（AR+D)提供 增加的光散射量。 5. 如申請專利範圍第3項或第4項所述之方法，包括以下 特徵之至少一者： 該玻璃基板/p-i-n接面組構包含第一電極、一個 半導體薄膜p-i-n或n-i-p接面、以及第二電極，上述 各者係依序地堆疊於該基板上，尤其是該LPCVD ZnO 前方接點、該矽層、以及該LPCVDZnO背面接點係依序 地堆疊於該基板上； 該玻璃基板/p-i-n接面組構包含透明的玻璃基板 (transparent substrate of glass)，該透明的玻璃基 板具有透明導電性氧化物層沉積於其上，尤其是具有該 2 94994 201126742 LPCVD ZnO前方接點層沉積於其上；以及 在設置該玻璃基板/p-i-n接面組構之後，藉由钱 刻建立抗反射與散射能力。 6. 如申請專利範圍第4項及第5項所述之方法，復包括以 下步驟.僅在該第二時段期間實施該蚀刻之前，透過該 玻璃/氣體介面實施雷射圖案化的步驟。 7. 如申請專利範圍第3項至第6項其中一項所述之方法， 其中’係藉由反應離子蝕刻實施該蝕刻。 8. 如申請專利範圍第3項至第8項其中一項所述之方法， 包括藉由： 暫時的機械性手段（mechanical means)，較佳的情 況疋具有夾固框架（clamping frame)的載體裝設，其 中’ s亥框架提供密封手段（seaiing means)，以允許僅 曝露出需要被蝕刻的該玻璃表面；或者藉由 可移除的黏著膜（removabie adhesive film)或可 移除的塗料（removable paint)，較佳的情況是，白反 射體塗料； 保》蒦該p-i-η接面組構，尤其是該石夕層，避免其受 到s玄姓刻該玻璃表面之影響。 9. 如申請專利範圍第1項至第8項其中一項所述之方法， 其中’該非晶矽p-i-n太陽能電池包括： 基板；以及 第一電極，尤其是該LPCVDZn◦前方接點、一個半. 導體薄臈p-i-n或n_i_p接面，尤其是該矽層、以及第 94994 3 201126742 二電極，尤其是該LPCVDZnO背面接點，依序地堆疊於 該基板上， 其中，該方法包括： $ s又置该基板以及堆疊於該基板上之該第一電極與 該至少一個接面； 使该接面之表面經受被控制的氧化，以便透過該至 ’個接面停用冷漏範圍（leaking boundary); 該第二電極係直接地或間接地舖設於已受到該氧 化之該表面上方。 1〇.如申料利範_ 9韻狀方法，其中，該非晶石夕 p-i-n太陽能電池具有以下特徵之至少一者： 係薄膜太陽能電池； 係薄膜矽太陽能電池； 該表面係最後經沉積的薄_層之表面； 棚 該基板係透明的，較佳為玻璃，尤其是Schott 石夕玻璃33之玻璃； 一 ~第電極包括或係沉積於該基板上的透明導 性氧化物，尤其是該經摻雜的LPCVD ZnO前方接點； 者的個接面包括氫化的微晶⑧或非晶石夕或兩 該接面^層之厚度係小於_奈米，而該P層之厚度. 該表二10 Γ，且該接面較佳的情況係p-— 今第雷Γ曰的表面’較佳的情況是經？謂所沉積者 5亥第一電極係於大約⑽。C的溫度下進行沉積；者 94994 4 201126742 該第電極包括或係該基板上所沉積的透明導電 性氧化物’且較佳的情況是，其表面上具有紋理 (textured)，該至少一個接面係鋪設於該第一電極的表 面上’ S亥導電性氧化物較佳的情況係具有粗縫度大於 100奈米RMS之紋理的zn〇。 11·如申請專利範圍第9項或第1G項所述之方法，其中， 該表面 係曝露於富含H20及/或30% H2〇2的氣體環境中， 較佳的情況是，於l〇(rc的溫度下！至2小時；或者 於室溫下曝露於臭氧中大約1小時；或者 β於大約1GG°C的溫度下曝露於臭氧中，較佳的情況 是，5至15分鐘；或者 於〇.5mbar的壓力下曝露於臭氧中15分鐘；或者 曝露於氧化電漿下，較佳的情況是，曝露於含有 匕『6、（：〇2、〇2或SFe的氣體環境中，較佳的情況是，於 3〇〇。mW/cm2電極面積的功率下，且較佳的情況是，於 2〇〇°C的溫度下，較佳的情況是，超過1〇秒但不超過一 分鐘， 該表面較佳的情況係η層的表面。 12. 如申請專利範圍第9項至第U項其中一項所述之方法， 其中，係利用接受電子之氧化劑實施該氧化，該氧化劑 係氧、敦、硫、氯、氮之至少一者。 13. 如申請專利範圍第9項至第12項其中一項所述之方法， 其中’該曝露係經實施最多5分鐘。 94994 5 201126742 、t. 14.如申請專利範圍第1項至第13項其中一項所述之方法， 其中，該非晶矽p-i-n太陽能電池包括 基板； ·· 於該基板上，包括透明導電性氧化物之第一電極 ; 廣，尤其是，該LPCVD ZnO前方接點； 於該第一電極層上，包括經正摻雜的半導體層、純 質的半導體層以及經負摻雜的半導體層與第二電極層 之堆疊層（stacked layer)，尤其是，其中，該等堆疊 半導體層係該p-i-η太陽能電池之該矽層，且該第二電 極層特別是該LPCVD ΖηΟ背面接點， 該方法包括以下步驟： 設置該基板； 於該基板上沉積該第一電極層，該第一電極層包括 該透明導電性氧化物並且具有表面； 於第一時段期間，藉由第一真空處理製程處理該表 面； 於第二時段期間，於包括氣態摻雜物（gaseous dopant)的製程氣體環境（process atmosphere)中，藉 由實施第二真空製程，於經該第一真空處理製程處理之 該表面上，沉積該等經正摻雜與經負摻雜的層之其中一 者； 於包括數量不同於該第二真空製程之氣體環境中 所包括之氣態摻雜物的製程氣體環境中，實施該第一真 空處理製程，否則在其他情況下，實施與該第二真空製 6 94994 201126742 程同等的該第一真空處理製程，並且選擇較該第二時段 為短的該第一時段。 15. 如申請專利範圍第14項所述冬方法，包括於含有SiH4 與H2以及氣態摻雜物濃度存在於該第二真空製程之氣 體環境中介於0%到80%之間之氣態摻雜物之氣體環境 中，較佳的情況是，介於0%到20%之間，實施該第一真 空處理製程作為真空電漿處理製程，從而較佳地藉由該 第二真空製程沉積該經正摻雜的半導體層。 16. 如申請專利範圍第14項所述之方法，其中，該第二真 空製程係真空電漿製程。 17. 如申請專利範圍第14項所述之方法，其中，該第一時 段係經選擇為介於該第一與第二時段之總和的5%至 20%之間，以及其中，較佳的情況是，該第二真空製程 係真空電漿製程，並且以下至少有一者有效： 藉由該第二真空製程所沉積的該一個經摻雜的半 導體層係該經正摻雜的半導體層； 該一個經摻雜的半導體層係於包括3丨114與H2的濃 度比為0. 1%至10%的氣體環境中進行沉積，較佳的情況 是，1%至5% ; 該一個經摻雜的半導體層係於包括SiH4的氣體環 境中進行沉積，且該氣體環境中摻雜物與SiH4的濃度 比係0. 1%至10%，較佳的情況是，0. 05%至0. 5% ; 該一個經摻雜的半導體層係於10 mW/cm2至1 W/cm2的功率密度下進行沉積，較佳的情況是，在 7 94994 201126742 '· _ 50 mW/cm2與 300 mw/Cm2之間； 該一個經摻雜的半導體層係於0. 5 mbar至12 mbar . 的總體壓力下進行沉積； ； 該一個經摻雜的半導體層係於介於150(TC與2800 ·: °Ci間的製程溫度下進行沉積；以及 該一個經摻雜的半導體層係於頻率13. 56 MHz至 82 MHz的射頻功率下進行沉積。 18. —種非晶矽p-i_n太陽能電池，包括抗反射塗佈、矽層 之p-i-n接面、及經摻雜的LPCVD ZnO前方與背面接 點’其中’該經摻雜的LPCVDZnO前方與背面接點係由 大型粒狀物所構成之多晶膜，該大型粒狀物的末端如同 角錐出現於生長表面。 19. 如申請專利範圍第18項所述之非晶矽p-i-n太陽能電 池，其中’以下至少一者適用： 該非晶矽p-i-n太陽能電池包括以厚度1 mm之 Schott硼矽玻璃33之玻璃作為蓋板，該Schott硼矽 玻璃33之玻璃上沉積有於600奈米具有70%之霧度因 子之 LPCVD-ZnO ; 該電池具有超過10%阻障的穩定電池效率，尤其是 10. 09%的穩定電池效率； 該矽膜係沉積於單一腔室電漿辅助化學氣相沉積 反應器中，尤其是於Oerlikon Solar KAI系統中； 該背面接點係與白反射體結合； 該i層係以1. 75 A /s的沉積速率進行沉積； 8 94994 201126742 該i層具有1. 73電子伏特的光學能隙； 該i層具有250奈米的厚度；以及 該電池係藉由雷射圖案化進行構建。 9 94994201126742 VII. Patent application scope: 1 'A method for manufacturing an amorphous stone p-i-η solar cell, the battery including anti-reflective coating and doped LPCVD Ζ Ο front and back contacts 'where' The front and back contacts of the doped LPCVD ZnO are polycrystalline films composed of large granules, and the ends of the large granules appear as a pyramid on the growth surface, the method comprising: depositing the front contact by LPCVD; Depositing a tantalum layer of the pin solar cell by plasma assisted chemical vapor deposition; depositing the back contact by LPCVD; and providing the anti-reflective coating. 2. The method of claim 1, wherein at least one of the following applies: The method comprises using a glass of Schott boron germanium glass 33 having a thickness of 1 mm as a cover plate on which the glass of the Schott boron germanium glass 33 is deposited. LPCVD-ΖηΟ having a haze factor of 70% at 600 nm; the battery has a stable battery efficiency of more than 10% barrier, especially 10. 9% stable cell efficiency; the method is included in a single Depositing the stone film in a chamber plasma-assisted chemical vapor deposition reactor, particularly in an Oerlikon Solar KAI system; the method includes combining the back contact with a white reflector; the method is included in 丨.75A/s The i layer is deposited at a deposition rate; the i layer has an optical energy gap of 73.73 eV (optical 1 94994 201126742 • bandgap); the i layer has a thickness of 250 nm; and the method includes laser irradiation The battery was patterned to build. 3. The method of claim 1 or 2, wherein the amorphous 矽 pin battery comprises a substrate/p-i-n junction structure having a glass/gas interface. / gas interface having anti-reflective capability due to the anti-reflective coating, the method comprising providing a glass substrate/pin junction configuration with a glass/gas interface, and then DART etching the glass surface of the glass/gas interface to provide The anti-reflection (AR) and the desired light scattering ability (D). 4. The method of claim 3, wherein the etching is performed during the first time period to provide an anti-reflection capability (AR), and the etching is additionally performed during the selected second time period to additionally ( AR+D) provides increased amount of light scattering. 5. The method of claim 3, wherein the method comprises: at least one of the following features: the glass substrate/pin junction assembly comprises a first electrode, a semiconductor film pin or nip junction, and a second electrode, each of which is sequentially stacked on the substrate, in particular, the LPCVD ZnO front contact, the germanium layer, and the LPCVDZnO back contact are sequentially stacked on the substrate; the glass substrate/ The pin junction assembly comprises a transparent substrate of glass having a transparent conductive oxide layer deposited thereon, in particular having the 2 94994 201126742 LPCVD ZnO front contact layer deposited thereon And after setting the glass substrate/pin junction structure, the anti-reflection and scattering capabilities are established by money. 6. The method of claim 4, wherein the step of laser patterning is performed through the glass/gas interface only prior to performing the etching during the second period of time. 7. The method of any one of clauses 3 to 6, wherein the etching is performed by reactive ion etching. 8. The method of any one of claims 3 to 8, comprising: by temporary mechanical means, preferably a carrier having a clamping frame Installation, wherein the 'sea frame provides a means of sealing to allow exposure to only the surface of the glass that needs to be etched; or by a removable adhesive film or removable paint ( Removable paint), preferably, a white reflector coating; the pi-n junction structure, especially the layer, avoiding the influence of the glass surface. 9. The method of claim 1, wherein the amorphous 矽pin solar cell comprises: a substrate; and a first electrode, in particular a front junction of the LPCVD Zn 、, one and a half. a conductor thin pin or n_i_p junction, in particular the germanium layer, and a second electrode of the 94949 3 201126742, in particular the LPCVDZnO back contact, are sequentially stacked on the substrate, wherein the method comprises: $ s The substrate and the first electrode stacked on the substrate and the at least one junction; subjecting the surface of the junction to controlled oxidation to disable a leakage boundary through the junction; The second electrode is laid directly or indirectly over the surface that has been subjected to the oxidation. 1〇. The method according to claim 1, wherein the amorphous stone solar cell has at least one of the following characteristics: a thin film solar cell; a thin film solar cell; the surface is finally deposited thin _ The surface of the layer; the substrate is transparent, preferably glass, especially the glass of the Schott stone glass 33; the first electrode comprises or is a transparent conductive oxide deposited on the substrate, especially the blended Miscellaneous LPCVD ZnO front contacts; the junctions of the hydrogenated crystallites 8 or amorphous or the thickness of the junction layer are less than _ nanometer, and the thickness of the layer P. Table 2 Γ, and the better condition of the junction is p--the surface of the current Thunder' is better? It is said that the first electrode of the sediment is about 10 (10). Deposition is carried out at a temperature of C; 94094 4 201126742 The first electrode comprises or is a transparent conductive oxide deposited on the substrate and preferably has a texture on its surface, the at least one junction Preferably, the layered conductive oxide on the surface of the first electrode is zn〇 having a texture having a roughness of more than 100 nanometers RMS. 11. The method of claim 9 or claim 1G, wherein the surface is exposed to a gas atmosphere rich in H20 and/or 30% H2〇2, preferably in a l〇 (at a temperature of rc! to 2 hours; or exposed to ozone at room temperature for about 1 hour; or β is exposed to ozone at a temperature of about 1 GG ° C, preferably 5 to 15 minutes; or Exposure to ozone for 15 minutes under pressure of 5 mbar; or exposure to oxidizing plasma, preferably exposed to a gas atmosphere containing 匕6, (: 〇2, 〇2 or SFe) Preferably, it is at a power of 3 〇〇mW/cm 2 of the electrode area, and preferably, at a temperature of 2 〇〇 ° C, preferably more than 1 〇 second but not more than one. In a minute, the surface is preferably a surface of the η layer. 12. The method according to any one of the items 9 to 5, wherein the oxidizing agent is carried out by using an oxidizing agent that receives electrons. At least one of oxygen, hydrogen, sulfur, chlorine, nitrogen. 13. If you apply for the scope of patent item 9 to The method of any one of the preceding claims, wherein the exposure is performed for a maximum of 5 minutes. 94994 5 201126742, the method of claim 1 , wherein The amorphous 矽pin solar cell includes a substrate; on the substrate, a first electrode including a transparent conductive oxide; and, in particular, the LPCVD ZnO front contact; on the first electrode layer, including a doped semiconductor layer, a pure semiconductor layer, and a stacked layer of the negatively doped semiconductor layer and the second electrode layer, in particular, wherein the stacked semiconductor layers are the pi-n solar cell The enamel layer, and the second electrode layer is particularly the LPCVD Οn Ο back contact, the method comprising the steps of: disposing the substrate; depositing the first electrode layer on the substrate, the first electrode layer comprising the transparent conductive And having a surface; during the first time period, the surface is processed by a first vacuum processing process; during the second time period, including a gaseous dopant In a process atmosphere, by performing a second vacuum process, depositing one of the positively doped and negatively doped layers on the surface processed by the first vacuum processing process; Performing the first vacuum processing process in a process gas environment including a gaseous dopant included in a gas environment different from the second vacuum process, otherwise in other cases, implementing the second vacuum system 6 94994 The first vacuum processing process is equivalent to 201126742, and the first time period shorter than the second time period is selected. 15. The winter method as claimed in claim 14, comprising a gaseous dopant comprising between SiO4 and H2 and a gaseous dopant concentration between 0% and 80% in a gaseous environment of the second vacuum process In the gas environment, preferably between 0% and 20%, the first vacuum processing process is performed as a vacuum plasma processing process, so that the positive vacuum deposition process is preferably performed by the second vacuum process. Doped semiconductor layer. 16. The method of claim 14, wherein the second vacuum process is a vacuum plasma process. 17. The method of claim 14, wherein the first time period is selected to be between 5% and 20% of the sum of the first and second time periods, and wherein In the case where the second vacuum process is a vacuum plasma process, and at least one of the following is effective: the one doped semiconductor layer deposited by the second vacuum process is the positively doped semiconductor layer; a doped semiconductor layer is deposited in a gas atmosphere comprising a concentration ratio of 3丨114 to H2 of 0.1% to 10%, preferably 1% to 5%; the one is doped 0%至0. 5。 The 5% The one doped semiconductor layer is deposited at a power density of 10 mW/cm 2 to 1 W/cm 2 , preferably 7 94994 201126742 '· _ 50 mW/cm 2 and 300 mw/cm 2 The first doped semiconductor layer is deposited at an overall pressure of from 0.5 mbar to 12 mbar . A doped semiconductor layer is deposited at a process temperature of between 150 (TC and 2800 °: °Ci; and the one doped semiconductor layer is tied to a frequency of 13.56 MHz to 82 MHz) Depositing. 18. An amorphous 矽p-i_n solar cell comprising an anti-reflective coating, a pinned junction of the germanium layer, and a doped LPCVD ZnO front and back contact 'where' the doped The front and back contacts of the LPCVD ZnO are polycrystalline films composed of large granules whose ends are like pyramids on the growth surface. 19. Amorphous 矽pin solar energy as described in claim 18 A battery, wherein 'at least one of the following applies: The amorphous 矽pin solar cell comprises a cover glass of Schott borosilicate glass 33 having a thickness of 1 mm, and the glass of the Schott borosilicate glass 33 is deposited at 600 nm with 70 % haze factor LPCVD-ZnO; the battery has a stable cell efficiency of more than 10% barrier, especially 10.09% stable cell efficiency; the ruthenium film is deposited in a single chamber plasma-assisted chemical vapor deposition In the reactor Especially in the Oerlikon Solar KAI system; the back contact is combined with a white reflector; the i layer is deposited at a deposition rate of 1.75 A / s; 8 94994 201126742 The i layer has 1.73 eV Optical energy gap; the i layer has a thickness of 250 nm; and the battery is constructed by laser patterning. 9 94994
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