201123321 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電子元件封裝體（electronics package)，特別是有關於一種利用晶圓級封裝（wafer scale package; WSP)製程製作的電子元件封裝體的隔絕層及其 製作方法。 【先前技術】 在習知的電子元件封裝體中，晶片周圍通常包圍一 層隔絕層，以與後續形成的導線層隔離，上述習知的隔 絕層具有良好的解析度，以便於其中形成開口使後續形 成的導線層電性連接至晶片。然而，習知具有良好的解 析度的隔絕層通常厚度較薄，因而無法兼顧表面平坦性 (coplanar)、機械強度（mechanical strength)以及熱膨脹係 數的匹配性等要求。反之’表面平坦性（coplanar)、機械 強度（mechanical strength)以及熱膨脹係數（coefficient thermal expansion，CTE)匹配性表現較佳的隔絕層則需要 較大的厚度，因而無法達到良好解析度的要求。 因此，亟需一種兼顧上述需求之電子元件封裝體的 隔絕層及其製造方法。 【發明内容】 有鑑於此，本發明之一貫施例係提供一種電子元件 封裝體的製作方法，包括提供一承載晶圓；於上述承載 晶圓上方設置一電子元件晶片’其上設有複數個導電 X8-003/029_9002-A33891 TWF/ianchen 4 201123321 第一隔絕層，覆蓋上述承载晶圓及上述電子 曰曰，其中上述第一隔絕層具有複數個第一開口， =別暴露出上述些導電塾；順應性於上述第一隔絕層 上述些第一開口中形成一第二隔絕層，直中上述第 二隔絕層對應於上述些第一開口的位置具有複數個第二 :口’以分別暴露出上述些導電墊；順應性於上述第二 ，絕層上及上述些第二開σ中形成複數個彼此隔絕的重 佈線路圖案，以電性連接上述些導㈣；於上料重佈 ♦線路圖案上形成電性連接上述些導電塾之複數個導電凸 塊。 本發明之另一實施例係提供一種電子元件封裝體， 包括-承載晶圓；一電子元件晶片，設置於上述‘載晶 圓上方’其中上述電子元件晶片上設有複數個導電塾； =絕豐層，其包括一下層之第一隔絕層和一上層之第 二隔絕層，上述第一隔絕層覆蓋上述承載晶圓及述電 子元件晶片，其中上述隔絕疊層具有複數個開口，以分 •別暴露出上述些導電墊；複數個彼此隔絕的重佈線路二 案，順應性形成於上述隔絕疊層上及上述開口中，且分 別電性連接上述些導電墊；複數個導電凸塊，分別形^ 於上述些重佈線路圖案上，並電性連接上述些導電墊。 【實施方式】 以下以各實施例詳細說明並伴隨著圖式說明之範 例，做為本發明之參考依據。在圖式或說明書描述中， 相似或相同之部分皆使用相同之圖號。且在圖式中，實 Χ8-003/029_9002-Α33891 TWF/ianchen 5 201123321 施例之形狀或是厚度可擴大，並以簡化或是方便標示。 再者，圖式中各元件之部分將以分別描述說明之，值得 注意的是，圖中未緣示或描述之元件，為所屬技術領域 中具有通常知識者所知的形式，另外，特定之實施例僅 為揭示本發明使用之特定方式，其並非用以限定本發明。 本發明實施例的電子元件封裝體係利用晶圓級封裝 (wafer level chip scale package，WLCSP)製程封裝各種包 含主動元件或被動元件（active or passive elements)、數位 電路或類比電路（digital or analog circuits)等積體電路的 電子元件（electronic components)，例如是有關於光電元 件（opto electronic devices)、微機電系統（Micro Electro Mechanical System; MEMS)、微流體系統（micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的 物理感測器（Physical Sensor)。特別是可選擇使用晶圓級 封裝（wafer scale package; WSP)製程對影像感測元件 (image sensors)、發光二極體、太陽能電池（solar cells)、 射頻元件（RF circuits)、加速計（accelerators)、陀螺儀 (gyroscopes)、微制動器（micro actuators)、表面聲波元件 (surface acoustic wave devices)、壓力感測器（process sensors)或喷墨頭（ink printer heads)等半導體晶片進行封 裝。 其中上述晶圓級封裝製程主要係指在晶圓階段完成 封裝步驟後，再予以切割成獨立的封裝體，然而，在一 特定實施例中，例如將已分離之半導體晶片重新分布在 一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封 X8-003/029 9002-A33891 TWF/ianchen 6 201123321 裝製程。另外’上述晶圓級封裝製程亦適用於藉堆疊 (stack)方式安排具有積體電路之多片晶圓，以形成多層積 體電路（multi-layer integrated circuit devices)之電子元件 封裝體。 第lb、2b、3b、4b、5b和6b圖係顯示製作一種根 據本發明一實施例之電子元件封裝體500a的上視示意 圖。第la、2a、3a、4a、5a和6a圖分別為沿第lb、2b、 3b、4b、5b和6b圖之A-A，切線的剖面圖。如第la和lb _ 圖所示’提供一承載晶圓200。在本發明一實施例中，承 載晶圓200可包括不設有任何元件圖案的裸晶圓（bare silicon wafer)，其具有一上表面2〇1和一下表面203。於 承載晶圓200的上表面201設置一電子元件晶片204。在 本發明一實施例中’電子元件晶片204經由例如為導電 銀膠的黏著層202設置於承載晶圓2〇〇上。如第la和1b 圖所示，電子元件晶片204的上表面206設有複數個導 電墊208。上述導電墊208係用來傳遞電子元件晶片 # 的輸入/輸出（1/0)信號、接地(ground)信號或電源（P〇wer) 信號等。 第2a、2b至3a、3b圖係說明本發明一實施例之隔 絕疊層216的形成方式，隔絕疊層216用以將電子元件 晶片204的周圍與後續形成的重佈線路圖案隔離。接著’ 請參考第2a和2b圖，形成一第一隔絕層210，覆蓋承載 晶圓200及電子元件晶片204的上表面206。在本發明一 實施例中’第一隔絕層21 〇係主要用以平坦化承載晶圓 200及電子元件晶片204的表面，其可為利用真空貼附或 X8-003/029_9002-A33 891 TWF/ianchen η 201123321 熱壓合等方式形成的乾膜光阻（dry film photoresist)。第 一隔絕層210可利用微影蝕刻方式在導電墊208的形成 位置上形成複數個第一開口 212，以分別暴露出導電墊 208。 接著，請參考第3a和3b圖，順應性於第一隔絕層 210上及第一開口 212中形成一第二隔絕層214。在本發 明一實施例中’第二隔絕層214係主要形成暴露導電墊 208的開口以便於後續導線繞線的形成，其材質可包括環 氧樹脂、防銲層、氧化矽層、氮化矽層、氮氧化矽層、 金屬氧化物、聚酿亞胺樹脂（polyimide)、苯環丁嫦 (butylcyclobutene:BCB,道氏化學公司）、聚對二曱苯 (parylene)、萘聚合物（polynaphthalenes)、氟碳化物 (fluorocarbons)、丙烯酸酯（accrylates)或其組合。而第二 隔絕層214的形成方式可包括旋轉塗佈（spin coating)、喷 塗（spray coating)、淋幕塗佈（curtain coating)、液相沈積 (liquid phase deposition)、物理氣相沈積（physical vapor deposition; PVD)、化學氣相沈積（chemical vapor deposition; CVD)、低壓化學氣相沈積（low pressure chemical vapor deposition; LPCVD)、電漿增強式化學氣 相沈積（plasma enhanced chemical vapor deposition; PECVD)、快速熱化學氣相沈積（rapid thermal-CVD; RTCVD)或常壓化學氣相沈積（atmospheric pressure chemical vapor deposition; APCVD)。第二隔絕層 214 也 可利用微影蝕刻方式在第一開口 212的形成位置上形成 複數個第二開口 218，以分別暴露出導電墊208。經過上 X8-003/029 9002-A33 891 TWF/ianchen 8 201123321 述製程之後，係形成包括第一隔絕層210和第二隔絕層 214 的一隔絕疊層（isolation combo layer)216。 在本發明一實施例中，隔絕疊層216由下層的第一 隔絕層210和上層的第二隔絕層214層疊而成，其中第 一隔絕層210和第二隔絕層214分別具有不同的功能。 第一隔絕層210係主要用以平坦化承載晶圓200及電子 元件晶片204的表面’因此’相較於第二隔絕層214，例 如為乾膜光阻的第一隔絕層210具有良好的表面平坦性 鲁（coplanar)、較佳的機械強度（mechanical strength)，因而 第一隔絕層210的厚度大於第二隔絕層214的厚度。或 者，也可於第一隔絕層210添加例如二氧化矽（silica)顆 粒’以增加導熱性或調整其熱膨脹係數（coefficient thermal expansion，CTE)以與電子元件晶片204的熱膨脹 係數匹配。而為了要精確地形成暴露導電墊208的開口 以便於後續導線繞線的形成，因此，第二隔絕層214需 要具有較第一隔絕層210佳的解析度（res〇iuti〇n)，且第二 鲁隔絕層214的黏度係數（coefficient of viscosity)低於第一 隔絕層210的黏度係數。藉由具有平坦化功能之第一隔 絕層210和具有良好解析度之第二隔絕層214層疊而成 的隔絕疊層216,可兼具不同材質隔絕層的優點。 之後，請參考第4a和4b圖，其顯示重佈線路圖案 220a 和銲球下金屬層（Under Bump Metallurgy， UBM)220b的形成方式。可利用沉積及微影蝕刻製程’順 應性於第二隔絕層214上及第二開口 218中形成複數個 彼此隔絕的重佈線路圖案220a和銲球下金屬層 X8-003/029_9002-A33 891 TWF/ianchen 201123321 (UBM)220b。每個重佈線路圖案220a的兩末端係分別與 一導電墊208和一銲球下金屬層（UBM)220b電性連接。 銲球下金屬層（UBM)220b為可選擇（optional)的元件，在 其他實施例中，可利用加長重佈線路圖案220a的方式來 取代銲球下金屬層（UBM)220b。 在本發明實施例中，為了使電子元件晶片204的信 號可以傳遞到外界，重佈線路圖案220a可將後續形成的 導電凸塊的位置重新分布，例如從電子元件晶片204的 週邊區域擴展到整個電子元件晶片204 ’而重佈線路圖案 220a也因此可能從電子元件晶片204的週邊區延伸到電 子元件晶片204的中心區。值得注意的是，如第4a圖所 示’為了可以在導電墊數目增加的情形下，仍能維持後 續形成的導電凸塊之間所需的最小間距，形成於任兩個 相鄰的導電塾208上的重佈線路圖案220a係分別朝電子 元件晶片204的内側和外側延伸，舉例來說，電性連接 至任兩個相鄰的導電墊208的重佈線路圖案220a!和 220a2係分別朝電子元件晶片204的内側和外側延伸，因 而分別連接於重佈線路圖案22Oai和22Oa〗的銲球下金屬 層（UBM)220b】* 220t>2係分別位於電子元件晶片204的 内側和外側。舉例而言，由導電材料構成之重佈線路圖 案220a和銲球下金屬層（UBM)220b可以是金屬或金屬合 金，例如錄層、銀層、銘層、銅層或其合金；或者是摻 雜多晶矽、單晶矽、或導電玻璃層等材料。此外，对火 金屬（refractory metal)材料例如鈦、銦、鉻、或是鈦鶴層， 亦可單獨或和其他金屬層結合。而在一特定實施例中， X8-003/029 9002-A33891TWF/ianchen 10 201123321 鎳/金層可以局部或全面性的形成於金屬層表面。 接著，請參考第5a和5b圖，其顯示保護層222的 形成方式。在本發明實施例中，保護層222例如為阻焊 膜（solder mask)，可經由塗佈防銲材料的方式形成保護層 222。然後，對保護層222進行圖案化製程，以於形成暴 露部分銲球下金屬層（UBM)220b的複數個終端接觸墊開 口 224。 然後，請參考第6a和6b圖，由圖案化的光阻層進 φ 行銲料電鍍或是藉由網版印刷等方式，塗佈銲料而填入 保護層222的終端接觸墊開口 224中，最後去除種晶層 或光阻層以及進行迴銲形成銲球（solder ball)或銲墊 (solder paste)’以於電子元件晶片204的上方形成複數個 導電凸塊228。導電凸塊228係鄰接於保護層222，且覆 蓋部分銲球下金屬層（UBM)220b。導電凸塊228係藉由 重佈線路圖案220a和銲球下金屬層（UBM)220b電性連接 電子元件晶片204的導電墊208，其中任兩個相鄰的導電 • 凸塊228分別設置於電子元件晶片214的内側和外側。 在本發明實施例中，導電凸塊228係用以傳遞電子元件 晶片204中的輸入/輸出（I/O)信號、接地（ground)信號或 電源（power)信號。最後，沿切割道SC(scribe line)分割上 述承載晶圓200，以分離出各電子元件晶片204，完成本 發明一實施例的電子元件封裝體500a。 第7圖係顯示本發明另一實施例之電子元件封裝體 500b的剖面示意圖。在本發明另一實施例中，承載晶圓 2〇〇中具有一凹洞（cavity)232，以容納電子元件晶片 X8-003/029_9002-A33891 TWF/ianchen 11 201123321 =4’以降低電子元件封裝體的整體高度。另外，承載晶 圓2〇0可在鄰近凹洞232的頂面201設置有對準圖形 f8在電子兀件晶片204設置於凹洞232中的步驟之 前、’可利用上述對準圖形238將電子元件晶片綱對準 凹，同232的形成位置，以便於將電子元件晶片204放置 於凹洞，32中。如第7圖所示，用以平坦化的第一隔絕 層210係填入凹洞232中’覆蓋凹洞232的底面和側面、 電子元件晶片204的側面和部分頂面2〇6，且覆蓋承載晶 圓200的頂面204。 第8a和9a圖為本發明不同實施例之電子元件封裝 體的上視示意圖，其顯示第一隔絕層21 〇的不同開口樣 式第8b至9b圖分別為沿第8a和9a圖之B-B，切線的 剖面圖。如第8a、8b圖所示’第一隔絕層21〇的開口 212& 可暴露出多個導電墊208。而如第9a、外圖所示，第一 隔絕層210的每一個開口 212b係分別暴露出一個導電墊 208。 本發明實施例的電子元件封裝體5〇〇a或5〇〇b之用 以將電子元件晶片204的周圍與後續形成的重佈線路圖 案隔離的隔絕疊層216是主要由兩層不同功能的隔絕層 層疊而成。其中位於下層的第一隔絕層21〇主要用以平 坦化承載晶圓200及電子元件晶片2〇4的表面。位於上 層的第二隔絕層214主要用以形成暴露導電墊2〇8的開 口以便於後續導線繞線的形成。因此，第一隔絕層21 〇 具有良好的表面平坦性（coplanar)、較佳的機械強度 (mechanical strength)以及熱膨脹係數的匹配性。另外， X8-003/029_9002-A33891 TWF/ianchen 12 201123321 第二隔絕層2i4具有較佳的解析度(res〇lmi〇n)和較低的 黏度係數（coefficient of visc〇sity)。因此，藉由具有平坦 化功能之第-隔絕層21G和具有良好解析度之第二隔絕 層214層疊而成的隔絕疊層216，可兼具不同材質隔絕層201123321 VI. Description of the Invention: [Technical Field] The present invention relates to an electronic package, and more particularly to an electronic component fabricated by a wafer scale package (WSP) process The insulating layer of the package and the manufacturing method thereof. [Prior Art] In a conventional electronic component package, a wafer is usually surrounded by an insulating layer to be isolated from a subsequently formed wiring layer. The above-mentioned conventional insulating layer has a good resolution so as to form an opening therein for subsequent operation. The formed wire layer is electrically connected to the wafer. However, conventionally, an insulating layer having a good degree of resolution is usually thin in thickness, and thus it is impossible to balance the requirements of surface flatness, mechanical strength, and thermal expansion coefficient. On the other hand, the surface layer having good surfaceplanarity, mechanical strength, and coefficient of thermal expansion (CTE) matching requires a large thickness, so that a good resolution cannot be achieved. Accordingly, there is a need for an isolation layer for an electronic component package that meets the above needs and a method of fabricating the same. SUMMARY OF THE INVENTION In view of the above, a consistent embodiment of the present invention provides a method for fabricating an electronic component package, including providing a carrier wafer, and disposing an electronic component wafer above the carrier wafer. Conductive X8-003/029_9002-A33891 TWF/ianchen 4 201123321 The first insulating layer covers the carrying wafer and the electronic cymbal, wherein the first insulating layer has a plurality of first openings, and the other conductive 塾 is not exposed. a second isolation layer is formed in the first openings of the first isolation layer, and the second isolation layer has a plurality of second: ports corresponding to the positions of the first openings to respectively expose The above-mentioned conductive pads; compliance in the second, the upper layer and the second opening σ form a plurality of overlapping wiring patterns that are isolated from each other to electrically connect the above-mentioned guides (4); A plurality of conductive bumps electrically connected to the conductive turns are formed on the pattern. Another embodiment of the present invention provides an electronic component package including: a carrier wafer; an electronic component wafer disposed on the above-mentioned 'carrier wafer', wherein the electronic component wafer is provided with a plurality of conductive defects; a first layer of the lower insulating layer and a second insulating layer of the upper layer, the first insulating layer covering the carrier wafer and the electronic component wafer, wherein the insulating layer has a plurality of openings to divide Do not expose the above-mentioned conductive pads; in the case of a plurality of isolated wiring lines, the compliance is formed on the insulating laminate and the openings, and electrically connected to the conductive pads; respectively; a plurality of conductive bumps, respectively Forming on the above-mentioned redistribution line patterns and electrically connecting the above-mentioned conductive pads. BEST MODE FOR CARRYING OUT THE INVENTION The following is a detailed description of the embodiments and the accompanying drawings are intended to be a reference for the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the figure, the actual shape is 8-003/029_9002-Α33891 TWF/ianchen 5 201123321 The shape or thickness of the example can be expanded and simplified or conveniently marked. In addition, the components of the drawings will be described separately, and it is noted that elements not shown or described in the drawings are known to those of ordinary skill in the art, and The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention. The electronic component packaging system of the embodiment of the present invention utilizes a wafer level chip scale package (WLCSP) process package to package various active or passive elements, digital circuits or analog circuits. The electronic components of an integrated circuit, for example, are related to opto electronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, or utilizing heat and light. A physical sensor that measures physical quantities such as pressure. In particular, wafer scale package (WSP) processes can be used for image sensors, light-emitting diodes, solar cells, RF circuits, accelerators. Semiconductor wafers such as gyroscopes, micro actuators, surface acoustic wave devices, process sensors, or ink printer heads are packaged. The above wafer level packaging process mainly refers to cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed in a supporting crystal. On the circle, the encapsulation process can also be called wafer level seal X8-003/029 9002-A33891 TWF/ianchen 6 201123321 assembly process. Further, the above wafer level packaging process is also applicable to an electronic component package in which a plurality of wafers having integrated circuits are arranged by a stack to form multi-layer integrated circuit devices. The lbs, 2b, 3b, 4b, 5b, and 6b are diagrams showing a top view of an electronic component package 500a according to an embodiment of the present invention. Figures la, 2a, 3a, 4a, 5a, and 6a are cross-sectional views taken along line A-A of the lbs, 2b, 3b, 4b, 5b, and 6b, respectively. A carrier wafer 200 is provided as shown in FIGS. 1a and 1b. In an embodiment of the invention, the carrier wafer 200 may include a bare silicon wafer having no element pattern, having an upper surface 2〇1 and a lower surface 203. An electronic component wafer 204 is disposed on the upper surface 201 of the carrier wafer 200. In an embodiment of the invention, the electronic component wafer 204 is disposed on the carrier wafer 2 via an adhesive layer 202, such as a conductive silver paste. As shown in Figures 1a and 1b, the upper surface 206 of the electronic component wafer 204 is provided with a plurality of conductive pads 208. The conductive pad 208 is used to transmit an input/output (1/0) signal, a ground signal, or a power signal of the electronic component chip #. 2a, 2b to 3a, 3b illustrate the manner in which the barrier stack 216 of one embodiment of the present invention is formed to isolate the periphery of the electronic component wafer 204 from the subsequently formed redistribution trace pattern. Next, please refer to Figures 2a and 2b to form a first isolation layer 210 covering the upper surface 206 of the carrier wafer 200 and the electronic component wafer 204. In an embodiment of the invention, the first insulating layer 21 is used to planarize the surface of the carrier wafer 200 and the electronic component wafer 204, which may be vacuum attached or X8-003/029_9002-A33 891 TWF/ Ianchen η 201123321 Dry film photoresist formed by thermocompression bonding. The first isolation layer 210 may form a plurality of first openings 212 at the formation locations of the conductive pads 208 by photolithography to expose the conductive pads 208, respectively. Next, referring to the figures 3a and 3b, a second insulating layer 214 is formed on the first insulating layer 210 and in the first opening 212 in compliance. In an embodiment of the present invention, the second insulating layer 214 mainly forms an opening for exposing the conductive pad 208 to facilitate the formation of a subsequent wire winding, and the material thereof may include an epoxy resin, a solder resist layer, a tantalum oxide layer, and a tantalum nitride layer. Layer, bismuth oxynitride layer, metal oxide, polyimide, butylcyclobutene (BCB, Dow Chemical Company), parylene, polynaphthalenes , fluorocarbons, accrylates or combinations thereof. The second isolation layer 214 can be formed by spin coating, spray coating, curtain coating, liquid phase deposition, physical vapor deposition (physical). Vapor deposition; PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) , rapid thermal chemical vapor deposition (RTCVD) or atmospheric pressure chemical vapor deposition (APCVD). The second isolation layer 214 can also form a plurality of second openings 218 at the formation locations of the first openings 212 by lithography to expose the conductive pads 208, respectively. After the process of X8-003/029 9002-A33 891 TWF/ianchen 8 201123321, an isolation combo layer 216 comprising a first insulating layer 210 and a second insulating layer 214 is formed. In one embodiment of the invention, the isolation stack 216 is formed by laminating a lower first insulating layer 210 and an upper second insulating layer 214, wherein the first insulating layer 210 and the second insulating layer 214 have different functions, respectively. The first isolation layer 210 is mainly used to planarize the surface of the carrier wafer 200 and the electronic component wafer 204. Therefore, the first isolation layer 210, such as a dry film photoresist, has a good surface compared to the second isolation layer 214. The flatness is coplanar, preferably mechanical strength, and thus the thickness of the first insulating layer 210 is greater than the thickness of the second insulating layer 214. Alternatively, for example, silica particles may be added to the first insulating layer 210 to increase thermal conductivity or adjust its coefficient of thermal expansion (CTE) to match the coefficient of thermal expansion of the electronic component wafer 204. In order to accurately form the opening of the exposed conductive pad 208 to facilitate the formation of the subsequent wire winding, the second insulating layer 214 needs to have a better resolution (res〇iuti〇n) than the first insulating layer 210, and The coefficient of viscosity of the Erlu insulation layer 214 is lower than the viscosity coefficient of the first insulation layer 210. The insulating laminate 216 formed by laminating the first barrier layer 210 having a planarization function and the second barrier layer 214 having a good resolution can have the advantages of different material barrier layers. Thereafter, please refer to Figures 4a and 4b, which show the manner in which the redistribution line pattern 220a and the Under Bump Metallurgy (UBM) 220b are formed. A plurality of isolated wiring patterns 220a and under-welding metal layers X8-003/029_9002-A33 891 TWF may be formed on the second insulating layer 214 and the second opening 218 by using a deposition and lithography process. /ianchen 201123321 (UBM) 220b. The ends of each of the redistribution circuit patterns 220a are electrically connected to a conductive pad 208 and a solder ball under metal layer (UBM) 220b, respectively. The under-ball metal layer (UBM) 220b is an optional component. In other embodiments, the under-ball metal layer (UBM) 220b may be replaced by a lengthened redistribution wiring pattern 220a. In the embodiment of the present invention, in order to transmit the signal of the electronic component wafer 204 to the outside, the redistribution wiring pattern 220a may redistribute the positions of the subsequently formed conductive bumps, for example, from the peripheral area of the electronic component wafer 204 to the whole. The electronic component wafer 204' and the redistributed wiring pattern 220a may thus also extend from the peripheral region of the electronic component wafer 204 to the central region of the electronic component wafer 204. It is worth noting that, as shown in Fig. 4a, in order to maintain the minimum spacing required between subsequently formed conductive bumps in the case where the number of conductive pads is increased, any two adjacent conductive turns are formed. The redistribution line patterns 220a on 208 extend toward the inner side and the outer side of the electronic component wafer 204, respectively. For example, the redistribution line patterns 220a! and 220a2 electrically connected to any two adjacent conductive pads 208 are respectively directed toward The inner side and the outer side of the electronic component wafer 204 are extended, so that the under-bump metal layer (UBM) 220b of the redistribution wiring patterns 22Oai and 22Oa, respectively, is located on the inner side and the outer side of the electronic component wafer 204. For example, the redistribution wiring pattern 220a and the under-ball metal layer (UBM) 220b composed of a conductive material may be a metal or a metal alloy such as a recording layer, a silver layer, an inscription layer, a copper layer or an alloy thereof; or Materials such as heteropolycrystalline germanium, single crystal germanium, or conductive glass layers. Further, a refractory metal material such as titanium, indium, chromium, or a titanium layer may be bonded alone or in combination with other metal layers. In a particular embodiment, the X8-003/029 9002-A33891TWF/ianchen 10 201123321 nickel/gold layer may be partially or fully formed on the surface of the metal layer. Next, please refer to Figures 5a and 5b, which show how the protective layer 222 is formed. In the embodiment of the present invention, the protective layer 222 is, for example, a solder mask, and the protective layer 222 can be formed by applying a solder resist material. The protective layer 222 is then patterned to form a plurality of terminal contact pad openings 224 that expose portions of the under-bump metal layer (UBM) 220b. Then, referring to the figures 6a and 6b, the patterned photoresist layer is soldered or soldered, and the solder is applied to fill the terminal contact pad opening 224 of the protective layer 222. A seed layer or photoresist layer is removed and a solder ball is formed to form a solder ball or a solder paste to form a plurality of conductive bumps 228 over the electronic component wafer 204. The conductive bumps 228 are adjacent to the protective layer 222 and cover a portion of the under bump metallurgy (UBM) 220b. The conductive bumps 228 are electrically connected to the conductive pads 208 of the electronic component wafer 204 by the redistribution wiring pattern 220a and the under bump metallurgy (UBM) 220b, wherein any two adjacent conductive bumps 228 are respectively disposed on the electrons. The inside and the outside of the element wafer 214. In an embodiment of the invention, conductive bumps 228 are used to transfer input/output (I/O) signals, ground signals, or power signals in electronic component wafer 204. Finally, the carrier wafer 200 is divided along the scribe line SC to separate the electronic component wafers 204, and the electronic component package 500a according to an embodiment of the present invention is completed. Fig. 7 is a schematic cross-sectional view showing an electronic component package 500b according to another embodiment of the present invention. In another embodiment of the present invention, the carrier wafer 2 has a cavity 232 therein to accommodate the electronic component wafer X8-003/029_9002-A33891 TWF/ianchen 11 201123321 = 4' to reduce the electronic component package. The overall height of the body. In addition, the carrier wafer 〇0 may be disposed adjacent to the top surface 201 of the recess 232 with an alignment pattern f8 before the electronic component wafer 204 is disposed in the recess 232, and the electrons may be utilized by the alignment pattern 238. The component wafer is aligned to the recess and is formed at the same location as 232 to facilitate placement of the electronic component wafer 204 in the recesses 32. As shown in FIG. 7, the first insulating layer 210 for planarization is filled in the recess 232 to cover the bottom surface and the side surface of the recess 232, the side surface of the electronic component wafer 204, and a portion of the top surface 2〇6, and is covered. The top surface 204 of the wafer 200 is carried. 8a and 9a are top views of the electronic component package of different embodiments of the present invention, showing different opening patterns of the first insulating layer 21 第 8b to 9b are respectively BB along the 8a and 9a, tangent Sectional view. As shown in Figures 8a, 8b, the opening 212& of the first barrier layer 21 can expose a plurality of conductive pads 208. As shown in Fig. 9a and the outer view, each of the openings 212b of the first insulating layer 210 exposes a conductive pad 208, respectively. The insulating package 216 of the electronic component package 5A or 5B of the embodiment of the present invention for isolating the periphery of the electronic component wafer 204 from the subsequently formed redistribution line pattern is mainly composed of two layers of different functions. The insulation layers are laminated. The first insulating layer 21 of the lower layer is mainly used to planarize the surface of the carrier wafer 200 and the electronic component wafer 2〇4. The second insulating layer 214 located in the upper layer is mainly used to form an opening exposing the conductive pads 2〇8 to facilitate the formation of subsequent wire windings. Therefore, the first insulating layer 21 〇 has good surface flatness, good mechanical strength, and thermal expansion coefficient matching. In addition, X8-003/029_9002-A33891 TWF/ianchen 12 201123321 The second insulation layer 2i4 has a better resolution (res〇lmi〇n) and a lower coefficient of viscosity (visc〇sity). Therefore, the insulating laminate 216 which is formed by laminating the first insulating layer 21G having a planarizing function and the second insulating layer 214 having a good resolution can have different insulating layers.
另外，在本發明實施例的電子元件封裝體戋 通中，為了可以在導電墊數目增加㈣料，仍能維 持後續形成的導電凸塊之間所需的最小間距，形成於任 兩個相鄰的導㈣208上的重佈線路圖案⑽係分別朝 電^件晶片綱的内侧和外側延伸，以使任兩個相鄰 =導電凸塊228分別設置於電子元件晶片214的内侧和 外側。以達到高密度電子元件封㈣的要求。 再者，由於上述實施例的電子元件封裝體5_或 〇〇b皆以晶圓級封裝製程製作’因此，電子元件封裝體 小的尺寸。此外，在電子元件封裝體中係使 用重佈線路圖案或導電凸塊電性連接晶片的導電塾，並 導、^^ — ’因此’也可縮小電子元件封裝 卜，用以承載電子元件晶片的承载晶圓可 為不設有任何元件圖案之裸晶圓，可減少製程成本。 =本發明已以實施例揭露如上，然其並非用以限 疋士：明，任何熟習此技藝者，在不脫離本發明之精神 ’當可作些許之更動與潤飾’因此本發明之保 4乾圍當視後附之中請專利範圍所界定為準。 ’、 X8-003/〇29^90〇2-A33891TWF/ianchen 13 201123321 【圖式簡單說明】 第 1 a、2a、3a、4«、< 土 厂 __ . 4a 5a和6a圖係顯示萝作一 本發:-實施例之電子元件封裝體的上視示二 第 lb、2b、3b、4b、® \ 5b和6b圖y刀別為沿第la、2a、 3a、4a、5a和6a圖之A_A，切線的剖面圖。 第7圖係顯示本發明另—眚 貫施例之電子元件封裝體 的剖面不意圖。 第、8a和9a圖為本發明其他實施例之電子元件封裝 體的上視示意圖，其顯示第一隔絕層的不同開口樣式。 第8b至9b圖分別為沿第㈣％圖之b_b，切線的 剖面圖。 【主要元件符號說明】 200〜承載晶圓； 204〜電子元件晶片； 208〜導電墊； 202〜黏著層； 201、206〜上表面； 210〜第一隔絕層； 212、212a、212b、218、224〜開口； 214〜第二隔絕層； 216〜隔絕疊層； 220a、220a〗、220a2〜重佈線路圖案； 220b、220b〗、220b2〜銲球下金屬層； 222〜保護層； 228〜導電凸塊； 232〜凹洞； 238〜對準圖案； 500a、500b〜電子元件封裝體； SC〜切害ij道。 X8-003/029_9002-A33891TWF/ianchen 14In addition, in the electronic component package of the embodiment of the present invention, in order to increase the number of conductive pads (four), the minimum spacing required between the subsequently formed conductive bumps can be maintained, and is formed in any two adjacent The redistribution line patterns (10) on the conductive (four) 208 extend toward the inner side and the outer side of the electronic wafer, respectively, such that any two adjacent = conductive bumps 228 are disposed on the inner side and the outer side of the electronic component wafer 214, respectively. In order to achieve the requirements of high-density electronic component seals (4). Furthermore, since the electronic component package 5_ or 〇〇b of the above embodiment is fabricated by a wafer level packaging process, the electronic component package has a small size. In addition, in the electronic component package, the conductive traces of the wafer are electrically connected by using a redistribution wiring pattern or a conductive bump, and the electronic component package can also be reduced to carry the electronic component wafer. The carrier wafer can be a bare wafer without any component pattern, which can reduce the process cost. The present invention has been disclosed in the above embodiments, but it is not intended to be limited to a gentleman: it is understood that anyone skilled in the art can make some changes and refinements without departing from the spirit of the invention. The scope of the patent application is subject to the definition of the patent. ', X8-003/〇29^90〇2-A33891TWF/ianchen 13 201123321 [Simplified illustration] 1a, 2a, 3a, 4«, < 土厂__ . 4a 5a and 6a Making a hair: - The upper view of the electronic component package of the embodiment shows that the second lb, 2b, 3b, 4b, ® \ 5b, and 6b are along the first, second, third, fourth, fourth, fifth, and fifth Figure A_A, a cross-sectional view of the tangent. Fig. 7 is a cross-sectional view showing the outline of an electronic component package according to another embodiment of the present invention. Figures 8a and 9a are top plan views of electronic component packages in accordance with other embodiments of the present invention showing different opening patterns of the first insulating layer. Figures 8b to 9b are cross-sectional views of the tangent line along b_b of the (iv)% graph, respectively. [Main component symbol description] 200~ carrier wafer; 204~ electronic component wafer; 208~ conductive pad; 202~ adhesive layer; 201, 206~ upper surface; 210~ first isolation layer; 212, 212a, 212b, 218, 224~opening; 214~second insulating layer; 216~isolated stacking; 220a, 220a〗, 220a2~re-routing line pattern; 220b, 220b〗, 220b2~ solder ball under metal layer; 222~protective layer; Bump; 232 ~ recess; 238 ~ alignment pattern; 500a, 500b ~ electronic component package; SC ~ cut ij track. X8-003/029_9002-A33891TWF/ianchen 14