201120850 六、發明說明： 【發明所屬之技術領域】 —本發明係有關於一種電源供應裝置，特別係應用於顯 不面板内的電源供應裝置。 【先前技術】 般而5 ’平面顯示器可分為非自發光顯示器以及自 發光顯示器。液晶顯示器（liquid叩tal display ; lcd)屬於 非自發光顯示器的一種。自發光顯示器包含，電漿顯示器 (plasma display panel ; PDP)、場發射顯示器（field emission display ; FED)、電致發光（electroluminescent ; EL)顯示器 以及有機發光二極體顯示器（organic light emitting diode display ; OLED)。 由於自發光顯示器具有體積薄、重量輕、高發光效率 以及低驅動電壓等優點’故經常被使用。然而，當自發光 顯示器的顯示面板愈大時，其内部的電源線的長度也就愈 長。由於電源線具有一等效阻抗，因而造成電源線兩端的 電壓不同。 【發明内容】 本發明提供一種電源供應裝置，耦接一電源線以及一 參考線。電源線具有一第一及第二節點。參考線具有一第 三及第四節點。第一節點耦接一第一晝素單元之一第一驅 動電晶體。第二節點耦接一第二晝素單元之一第二驅動電 晶體。第一晝素單元之一第一電容耦接於第一驅動電晶體 0773-A34179TWF P2009005 4 201120850 之閘極與第三節點之間。第二畫素 於第二驅動電晶體之問極與第四節點二 包括’ -處理單元以及一第一電壓產生入電：供應裝置 寸制彳= 壓，純_取結果，產生 -:電壓產生單元根據控制信號，提供-第 參考電壓或第二參考電墨予參考線。 弟 及-提:厂:電子系統，包括-電壓轉換裝置以201120850 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a power supply device, particularly to a power supply device in a display panel. [Prior Art] A general 5' flat panel display can be classified into a non-self-luminous display and a self-illuminating display. A liquid crystal display (LCD) is a type of non-self-luminous display. The self-luminous display comprises a plasma display panel (PDP), a field emission display (FED), an electroluminescent (EL) display, and an organic light emitting diode display (organic light emitting diode display; OLED). Self-illuminating displays are often used because of their advantages of thin size, light weight, high luminous efficiency, and low driving voltage. However, as the display panel of the self-luminous display is larger, the length of the internal power supply line is longer. Since the power line has an equivalent impedance, the voltage across the power line is different. SUMMARY OF THE INVENTION The present invention provides a power supply device coupled to a power line and a reference line. The power cord has a first and second node. The reference line has a third and fourth node. The first node is coupled to one of the first pixel units and the first driving transistor. The second node is coupled to a second driving transistor of one of the second pixel units. The first capacitor of the first pixel unit is coupled between the gate of the first driving transistor 0773-A34179TWF P2009005 4 201120850 and the third node. The second pixel is connected to the fourth driving transistor and the fourth node 2 includes a '-processing unit and a first voltage generating power input: the supply device is inch 彳 = pressure, pure _ taking result, generating -: voltage generating unit A reference voltage or a second reference ink is supplied to the reference line based on the control signal. Brother and - mention: factory: electronic system, including - voltage conversion device
出電壓。顯干面:置將一輸入電壓，轉換成-輸 」不面板接收輸出電壓，並包括—電源線、一夫 及二第二元、一第二晝素單元、-處理單元以 二ϊί 。電源線具有—第-節點以及-第 線具有一第三節點以及一第四節點 素早70包括，-第-驅動電晶體以及-第-電容。第一麒 動電晶體_第-節點。第-電容麵接於第一驅動 之閉極與第三節點之間。第二晝素單元包括，一== :晶=及一第二電容。第二驅動電晶體麵接第二節點。 第一電谷耦接於第二驅動電晶體之閘極與 一及第二節點之一者_:二 第:：1號。第一電跑單元根據控侧 扣供一第一或第二參考電壓予參考線。 本發明更提供-種控制方法，適用於一第—及金 素^7〇。第—晝素單元具有—第—驅動電晶體以及—第一 ，今。第—晝素單元具有—第二驅動電晶體以及一第 合。第一驅動電晶體輕接一電源線之 動電晶體刪源線之一第二節點。第一電;輛接:二： 0773-Α34179TWF_P2009005 5 201120850 考線之一第三節點與第一驅動電晶體之閘極之間。第二電 容耦接於參考線之一第四節點與第二驅動電晶體之閘極之 間。本發明之控制方法，包括在一第一期間，提供一操作 電壓予電源線，並擷取該第一及第一節點之—者的電壓， 用以產生一第一參考電壓；在一第二期間，提供一掃描信 號以及一資料信號予第一或第二晝素單元，並提供第一參 考電壓予參考線；在一第二期間，停止提供掃描信號，繼 續提供第一參考電壓；以及在一第三期間，提供一第二參 考電壓予參考線。 為讓本發明之特徵和優點能更明顯易懂，下文特舉出 較佳實施例，並配合所附圖式，作詳細說明如下： 【實施方式】 第1A圖為本發明之電子系統示意圖。如圖所示，電 子系統1〇〇包括，電壓轉換裝置no以及顯示面板do。 電壓轉換裝置110將輸入電壓VlN’轉換成輸出電壓ν〇υτ。 顯示面板120接收輸出電壓V〇UT，並呈現影像。在本實施 例中，輸出電壓Vout係為直流(DC)電壓。 本發明並不限制輸入電壓Vin的種類。在其它可能實 施例中，輸入電壓V1N係為交流(AC)電壓或是直流電壓。 另外，電子系統100可為個人數位助理(PDA)、行動電話 (cellular phone)、數位相機、電視、全球定位系統(Gps)、 車用顯示器、航空用顯示器、數位相框（digital ph〇t〇 frame)、筆記型電腦或是桌上型電腦。 顯示面板120包括，電源線(p〇wer line)121、參考線 0773-A34 丨 79TWF P2009005 6 201120850 122、晝素單元ρ]、P2以及電源供應裝置123。電源線 具有節點K及N2。在本實施例中，電源線121具 端NPS’接收電源供應襄置123所提供的操作電壓、始 如圖所示，節點^至起始端NPs之間的距離大於節。 至起始端NPS之間的距離。 ” Μι 參考線122具有節點叫及凡。在本實施财， 線122具有起始端NRS，接收電源供應農f 12 參考電壓㈣或GND。如圖所示，節 = 之間的距離小於節點乂至起始端叫之間的距離；^卜〜 參考線122具有-結束端，其可接收—接地電壓。在本實 施例中，接地電壓等於參考電壓。 晝素單元卩〗包括軸f晶體MDi以 節點Nl。電容c趣於驅動電晶體_ 之閘極與節點N3之間。查夸罝；B A， 旦素早兀P2包括驅動電晶體md2 以及電谷C2。驅動電晶體A/· 日^ΜΕ>2耦接郎點乂。電容c2耦接 於驅動電晶體MD2之閘極盥節 斤”即點队之間。在本實施例中， 驅動電晶體MD!及w + 1 U2均為卩型電晶體，但並非用以限 制本發明。 電源供應裝置123操取節點…2之一者的電壓， 並根據擷取結果，提供夂者雷 亏電壓Vref或GND參考線 122。在本實施例中，雷泝 丁/ 电原i'應裝置123係榻取笳點％的 電壓，但並非用以限制太钚日曰▲ 亍娜即占 βρ W 12^ ^ X 。在其它實施例中，電源供 應裝置123可操取即點^的電壓。 第1B圖顯示複數金夸留_ ρ ρ 旦素早"〜Pmn的排列方式以及晝 素早70卩”〜卩则與電源飨1 崎121和參考線RLi〜RLn之間的連 0773-A34179TW P2009005 201120850 接關係。在本實施例中，晝素單元Pn〜Pmn係以陣列方式排 列，但並非用以限制本發明。 在第1B圖中，顯示面板120更包括一驅動裝置〗24。 驅動裝置124包括，閘極驅動器（gate driver)125以及源極 驅動器（sourcedriver)126。閘極驅動器125提供掃描信號予 閘極線(gate 。源極驅動器126提供資料信號 予資料線(dataline)DL广DLm。在一可能實施例中，電源供 應裝置123的所有元件或是部分元件，可與驅動裝置124 整合成一積體電路(integrated circuit ; 1C)。 另外’在本實施例中，電源供應裝置123僅根據電源 線121的節點NPU的電壓，產生控制信號Sc以及參考信 號Vref予閘極驅動器125。閘極驅動器125根據控制信號 Sc，選擇性地輸出參考信號Vref或GND予參考線 RL广RLn。在其它實施例中，電源供應裝置123可根據電 源線121上的不同節點的電壓，產生不同的參考信號予閘 極驅動器125。閘極驅動器125再選擇性地將相對應的參 考信號輸出至參考線RL]〜RLn。 舉例而言，假設，第一列(row，水平方向）的晝素單元 Pn〜Pml耦接到參考線RL〗，第二列的晝素單元P12〜pm2轉 接到參考線RL2。在此例中，電源供應裝置123可根據不 同節點（如NPn及NPn)的電壓，產生不同的參考電壓予閣 極驅動器125。閘極驅動器125再選擇性地將相對應的參 考線RM及RL2。 第2A圖為本發明之晝素單元之一可能實施例。由於 畫素單元Pn〜Pmil的結構均相同，故僅以畫素單元Pn為 0773-A34179TWF_P2009005 8 201120850 例，說明晝素單元P11的電路結構。如圖所示，晝素單元 Ρ π包括，切換電晶體M S11、電容C11、驅動電晶體MD11 以及發光元件200。 在本實施例中，切換電晶體MSn係為一 Ν型電晶體， 其閘極耦接閘極線GL!，用以接收掃描信號，其汲極耦接 育料線DL1 ’用以接收貧料信號，其源極搞接驅動電晶體 MD11的閘極。電容C11麵接於節點NRi 1與驅動電晶體MD11 的閘極之間。 驅動電晶體MDn可為一 P型電晶體，其源極耦接節 點NPU，其汲極耦接發光元件200。發光元件200的另一 端接收電壓PVEE。發光元件200可為一發光二極體(LED) 或是一有機發光二極體(OLED)，但並非用以限制本發明。 本發明並不限制發光元件200的種類。 請配合第1B圖，在一第一期間，閘極驅動器125提 供掃描信號予閘極線GL^GLn，並且源極驅動器126亦提 供資料信號予資料線DL^DLm。此時，電源供應裝置123 提供操作電壓PVDD予電源線121。 在一第二期間，電源供應裝置123擷取節點NPU的電 壓，並根據擷取後的結果，產生參考電壓Vref以及控制信 號Sc。閘極驅動器125根據控制信號Sc，透過參考線RL!， 傳送參考電壓Vref予晝素單元Pu〜Pml。因此，節點NRn 的電壓為參考電壓Vref。在此期間，由於閘極線GL!上的 掃描信號導通切換電晶體MSn，故節點Nb的電壓等於資 料線DLi上的資料信號Output voltage. Display dry surface: set an input voltage, convert to - input "Do not accept the output voltage of the panel, and include - power line, one and two second elements, a second pixel unit, - processing unit with two ϊ ί. The power supply line has a -th node and - the first line has a third node and a fourth node element 70 includes, - a - drive transistor and - a - capacitance. The first 麒 电 _ _ node. The first capacitor is connected between the closed end of the first drive and the third node. The second halogen unit includes a ==: crystal = and a second capacitor. The second driving transistor is in contact with the second node. The first electric valley is coupled to the gate of the second driving transistor and one of the first and second nodes _: 2:: 1:. The first electric running unit supplies a first or second reference voltage to the reference line according to the control side buckle. The present invention further provides a control method suitable for a first-and-gold element. The first-cell unit has a -first drive transistor and - first, present. The first halogen unit has a second drive transistor and a first. The first driving transistor is lightly connected to one of the second nodes of the power transistor of the power line. The first electricity; the vehicle connection: two: 0773-Α34179TWF_P2009005 5 201120850 One of the third node of the test line and the gate of the first drive transistor. The second capacitor is coupled between the fourth node of one of the reference lines and the gate of the second driving transistor. The control method of the present invention includes providing an operating voltage to the power line during a first period, and extracting voltages of the first and first nodes for generating a first reference voltage; Providing a scan signal and a data signal to the first or second pixel unit and providing a first reference voltage to the reference line; during a second period, stopping providing the scan signal, continuing to provide the first reference voltage; During a third period, a second reference voltage is supplied to the reference line. In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings: FIG. 1A is a schematic diagram of an electronic system of the present invention. As shown, the electrical subsystem 1 includes a voltage conversion device no and a display panel do. The voltage conversion device 110 converts the input voltage V1N' into an output voltage ν 〇υ τ. The display panel 120 receives the output voltage V〇UT and presents an image. In the present embodiment, the output voltage Vout is a direct current (DC) voltage. The invention does not limit the type of input voltage Vin. In other possible embodiments, the input voltage V1N is an alternating current (AC) voltage or a direct current voltage. In addition, the electronic system 100 can be a personal digital assistant (PDA), a cellular phone, a digital camera, a television, a global positioning system (Gps), a car display, an aerial display, and a digital photo frame (digital ph〇t〇frame). ), a laptop or a desktop computer. The display panel 120 includes a power line 121, a reference line 0773-A34 丨 79TWF P2009005 6 201120850 122, a pixel unit ρ], a P2, and a power supply device 123. The power cord has nodes K and N2. In the present embodiment, the power supply line 121 has the operating voltage provided by the power supply unit 123 at the end NPS'. As shown in the figure, the distance between the node ^ and the starting end NPs is greater than the pitch. The distance to the starting end NPS. Μι reference line 122 has a node called 凡凡. In this implementation, line 122 has a starting end NRS, receiving power supply agricultural f 12 reference voltage (four) or GND. As shown, the distance between the node = is less than the node 乂 to The distance between the start end is called; the reference line 122 has an end end which can receive the ground voltage. In the present embodiment, the ground voltage is equal to the reference voltage. The pixel unit 包括 includes the axis f crystal MDi as a node Nl. Capacitor c is interesting between the gate of the driving transistor _ and the node N3. Check, BA 罝; BA, 素 兀 P2 includes driving transistor md2 and electric valley C2. Driving transistor A / · 日 ^ ΜΕ 2 The coupling of the capacitor c2 is coupled to the gate of the driving transistor MD2, that is, between the teams. In the present embodiment, the driving transistors MD! and w + 1 U2 are both 卩-type transistors, but are not intended to limit the present invention. The power supply device 123 operates the voltage of one of the nodes ... 2, and provides a leader's deficit voltage Vref or GND reference line 122 based on the result of the capture. In the present embodiment, the lightning recovery device/electrical device i's the device 123 is to take the voltage of the 笳 point, but it is not used to limit the 钚 钚 亍 即 即 即 即 ρ ρ ρ ρ ρ ρ ρ β 。 。 。 。 。 。 。 。 In other embodiments, the power supply unit 123 can operate at a voltage of a point. Figure 1B shows the arrangement of multiple gold quarrels _ ρ ρ 旦 早 早 早 早 早 早 早 早 早 早 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 077 In the present embodiment, the pixel units Pn to Pmn are arranged in an array, but are not intended to limit the present invention. In FIG. 1B, the display panel 120 further includes a driving device 24. The driving device 124 includes a gate driver 125 and a source driver 126. The gate driver 125 provides a scan signal to the gate line (gate. The source driver 126 provides a data signal to the data line DL wide DLm. In a possible embodiment, all or part of the components of the power supply device 123 can be integrated with the driving device 124 to form an integrated circuit (1C). In addition, in the present embodiment, the power supply device 123 is only based on the power supply. The voltage of the node NPU of the line 121 generates a control signal Sc and a reference signal Vref to the gate driver 125. The gate driver 125 selectively outputs the reference signal Vr according to the control signal Sc. Ef or GND is referenced to the reference line RL RLn. In other embodiments, the power supply unit 123 can generate different reference signals to the gate driver 125 according to the voltages of different nodes on the power line 121. The gate driver 125 is selectively The corresponding reference signal is output to the reference lines RL]~RLn. For example, it is assumed that the first column (row, horizontal direction) of the pixel units Pn PPm is coupled to the reference line RL, the second column The pixel units P12 to pm2 are switched to the reference line RL2. In this example, the power supply device 123 can generate different reference voltages to the gate driver 125 according to the voltages of different nodes (such as NPn and NPn). The gate driver 125 The corresponding reference lines RM and RL2 are selectively selected. Fig. 2A is a possible embodiment of the pixel unit of the present invention. Since the structures of the pixel units Pn to Pmil are the same, only the pixel unit Pn is used. 0773-A34179TWF_P2009005 8 201120850 For example, the circuit structure of the pixel unit P11 is illustrated. As shown in the figure, the pixel unit Ρ π includes a switching transistor M S11 , a capacitor C11 , a driving transistor MD11 , and a light-emitting element 200. in The switching transistor MSn is a 电-type transistor, the gate is coupled to the gate line GL! for receiving the scan signal, and the drain is coupled to the cultivating line DL1 ' for receiving the lean signal, the source thereof The gate of the driving transistor MD11 is connected. The capacitor C11 is connected between the node NNi 1 and the gate of the driving transistor MD11. The driving transistor MDn may be a P-type transistor having a source coupled to the node NPU and a drain coupled to the light emitting element 200. The other end of the light emitting element 200 receives the voltage PVEE. The light emitting device 200 can be a light emitting diode (LED) or an organic light emitting diode (OLED), but is not intended to limit the present invention. The invention does not limit the kind of the light-emitting element 200. In conjunction with FIG. 1B, in a first period, the gate driver 125 provides a scan signal to the gate line GL^GLn, and the source driver 126 also supplies a data signal to the data line DL^DLm. At this time, the power supply device 123 supplies the operating voltage PVDD to the power supply line 121. During a second period, the power supply unit 123 draws the voltage of the node NPU and generates a reference voltage Vref and a control signal Sc based on the result of the extraction. The gate driver 125 transmits the reference voltage Vref to the pixel units Pu to Pml through the reference line RL! according to the control signal Sc. Therefore, the voltage of the node NRn is the reference voltage Vref. During this period, since the scanning signal on the gate line GL! turns on the switching transistor MSn, the voltage of the node Nb is equal to the data signal on the data line DLi.
Vdata 0 在一第三期間，閘極線GLi上的掃描信號不導通切換 0773-A34179TWF P2009005 9 201120850 電晶體MS]】。因士卜， 郎點Nb的電壓仍等於資料信號 Vdata(假 ό又為 3 V)。丨tl· b主 λ-λ- 夸’郎點NR〗]的電壓仍等於參考雷 壓Vref(假設為lv)。 f-第四期間’閘極驅動器125根據控制信 ==送參考電壓GND予畫素單元p…因此吏 即” 11的電I將由參考電M Vref變化至參考電壓 GND由於電谷C"的輕合效應，故節點Nb的電麗也合下 降VW。因此，節點Nb的電壓Uta·。 θ ;電源線121的等效阻抗所造成的壓降可能會 驅動電晶體MDl】的源極與閘極之間的跨壓，故可藉由控^ 參考線RL】〜RLn的電堡位準，補償因電源線121的等效阻 抗所造成的壓降，因而恢復驅動電晶體MD“ 之間的跨壓。 舉例而言，在第一期間，操作電屡PVDD等於5V， 資料線DL]上的資料信號ν·Α等於3V。因此，驅動電晶 體MD】】的源極與閘極之間的跨壓(v『Vs)等於鄉^v)。 假設，電源線121的等效電阻造成lv的壓降。因此， 在第二期間’故節點NPn的電壓（即驅動電晶體助"的源 極電壓）為4V(5V-1V)。電源供應裝置123根據節點Np" 的電壓得知電源線121的等效電阻造成1V的屬降，故將 參考電壓Vref設定成1V。因此’在第二期間，節點NR】] 的電壓為lv。由於節點·的電壓仍為3V，故驅動電晶體 MDn的源極與閘極之間的跨壓將由原先的2v變化成 1V(4V-3V)。 在第三期間，由於節點NR"的電壓仍為lv,並且節 0773-A34I79TWF P2009005 201120850 點Nb的電壓仍為3V，故驅動電晶體MDn的源極與閘極 之間的跨壓仍維持在IV。 在第四期間，郎點Nb的電壓VNb=VDATA_Vl"ef(即 3V-1V)。由於節點NP]〗的電壓為4V，而節點Nb的電壓 VNb=2 V ’故驅動電晶體MD1 1的源極與閘極之間的跨壓由 IV恢復成2V。 第2B圖為本發明之晝素單元之另一可能實施例。第 2B圖相似第2A圖，不同之處在於，第2B圖多了控制電 φ 晶體MCn。在本實施例中，控制電晶體MCn係為一 N型 電晶體，其閘極接收發光信號SEM，其汲極耦接驅動電晶 體MDn之汲極，其源極耦接發光元件200。 本發明並不限制晝素單元的内部結構。只要晝素單元 具有一驅動電晶體以及一電容，便可作為本發明所述之晝 素單元，其中該晝素單元内的驅動電晶體係耦接到一電源 線，並且該晝素單元内的電容係耦接在一參考線以及該驅 動電晶體的閘極之間。 • 第3圖為本發明之電源供應裝置123之一可能實施 例。如圖所示，電源供應裝置123包括處理單元310以及 電壓產生單元330。處理單元310擷取電源線121上的任 一節點的電壓，並根據擷取結果，產生控制信號Sc。在本 實施例中，處理單元310係擷取節點NPn的電壓VNP1]。 另外，節點NP„至電源線121之起始端NPS之間的距離大 於節點NP12至電源線121之起始端NPS之間的距離。 在本實施例中，處理單元310包括，減法器 (subtraction)311 以及比較器（comparator)312。減法器 311 0773-A34179TWF P2009005 11 201120850 計算操作電壓PVDD與該被擷取的電壓（即節點NPn的電 壓Vnpii)之間的差偉。在本實施例中，減法器311所計算 的差值係作為參考電壓Vref。 比較器312根據減法器311所計算的差值(Vref)以及 參考信號Sref，產生控制信號Sc。在本實施例中，當減法 器311所計算的差值小於參考信號Sref時，控制信號Sc 為一禁能狀態；當減法器311所計算的差值大於參考信號 Sref時，則控制信號Sc為一致能狀態。 電壓產生單元330輸出控制信號Sc以及參考電壓Vref 予閘極驅動器125，其中參考電壓Vref係為減法器311所 計算的差值。在一可能實施例中，參考電壓GND小於參考 電壓Vref。 在本實施例中，當控制信號Sc為致能狀態時，閘極驅 動器125提供參考電壓Vref予參考線RL^RU ;當控制信 號Sc為禁能狀態時，閘極驅動器125提供參考電壓GND 予參考線RLrRLn。在一可能實施例中，電壓產生單元330 可整合於第1B圖所示的閘極驅動器125之中。在此例中， 閘極驅動器125具有複數電壓產生單元330，用以分別控 制參考線RLrRLn的位準。 在本實施例中，電壓產生單元330包括電晶體331及 332。電晶體331可為一 P型電晶體。電晶體332可為一 N 型電晶體。當控制信號Sc為致能狀態時，電晶體331傳送 參考電壓Vref予參考線RL^RLn。當控制信號Sc為禁能 狀態時，電晶體332傳送參考電壓GND予參考線RL^RLn。 另外，在本實施例中，電源供應裝置123更包括電壓 0773-A34179TWF P2009005 12 201120850 產生單元350。電壓產生單元350提供操作電壓pvdd予 電源線121之起始端NPS。在一可能實施例中，處理單元 310根據操作電壓PVDD與該被擷取的電壓（即vNP11)，產 生控制信號Sc。 第4圖為本發明之控制方法之一可能流程圖。本發明 之控制方法適用於第1A圖所示的晝素單元p2。因此， 以下以第1A圖之符號’說明本發明之控制方法之一可能 流程。 • 首先，提供操作電壓PVDD予電源線^ ,並擷取節 點N〗及&之一者的電壓，用以產生參考電壓Vref(步驟 S410) ^在一可能實施例中，參考電壓Vref可為操作電壓 PVDD與該被擷取的電壓之間的差值。 在本實施例中，係擷取節點沁的電壓。節點n2至一 電源供應裝置(如第1A圖所示的符號丨23)之間的距離大於 節點①至電源供應裝置123之間的距離。另外，操作電壓 PVDD可由電源供應裝置123所提供。 籲接著，提供-掃描信號以及一資料信號予該第一或第 一晝素單元，並提供參考電壓Vref予參考線122(步驟 S430)以第1A圖的晝素單元p】為例，此時，驅動電晶體 MD!的閘極電壓約等於資料信號，而節點N 4的電壓約等於 參考電壓Vref。 然後’停止提供該掃描信號，繼續提供參考電壓 yref(步驟S450)。此時，驅動電晶體MD]的閘極電壓仍約 等於資料信號，而節點n4的電壓亦約等於參考電壓Vref。 最後，提供參考電壓GND予參考線122(步驟S470)。 〇773-A34179TWF_P2009005 13 201120850 此時，節點N4的電壓約等於參考電壓GND。在本實施例 中，參考電壓GND小於參考電壓Vref。根據電容C2的特 性，當節點N4的電壓由原先的Vref下降至GND時，驅動 電晶體MD!的閘極電壓將會下降Vref。因此，便可補償因 電源線121的阻抗所造成的壓降。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍内，當可作些許之更動與潤飾， 因此本發明之保護範圍當視後附之申請專利範圍所界定者 為準。 【圖式簡單說明】 第1A圖為本發明之電子系統示意圖。 第1B圖為本發明之電子系統之另一可能實施例。 第2A圖為本發明之晝素單元之一可能實施例。 第2B圖為本發明之晝素單元之另一可能實施例。 第3圖為本發明之電源供應裝置之一可能實施例。 第4圖為本發明之控制方法之一可能流程圖。 【主要元件符號說明】 100 :電子系統； 110 :電壓轉換裝置； 120 :顯示面板； 121 :電源線； 122 :參考線； 0773-A34179TWF P2009005 14 201120850Vdata 0 During a third period, the scan signal on the gate line GLi is not switched. 0773-A34179TWF P2009005 9 201120850 Transistor MS]]. According to Ins, the voltage of the Nb is still equal to the data signal Vdata (fake 3 V again). The voltage of 丨tl·b main λ-λ- boast NR point NR] is still equal to the reference lightning pressure Vref (assumed to be lv). F-fourth period 'gate driver 125 sends reference voltage GND to pixel unit p according to control signal == Therefore, the electric I of 11 will be changed from reference voltage M Vref to reference voltage GND due to electric valley C" The effect is the same, so the voltage of the node Nb is also lowered by VW. Therefore, the voltage of the node Nb Uta·. θ; the voltage drop caused by the equivalent impedance of the power line 121 may drive the source and the gate of the transistor MD1] Between the cross-pressures, the voltage drop caused by the equivalent impedance of the power line 121 can be compensated by controlling the electric gate level of the reference line RL]~RLn, thereby restoring the cross between the driving transistors MD" Pressure. For example, during the first period, the operating power PVDD is equal to 5V, and the data signal ν·Α on the data line DL] is equal to 3V. Therefore, the voltage across the source and the gate of the driving transistor [v] is equal to the township ^v). Assume that the equivalent resistance of the power line 121 causes a voltage drop of lv. Therefore, in the second period 'the voltage of the node NPn (i.e., the source voltage of the driving transistor assist) is 4V (5V - 1V). The power supply device 123 knows that the equivalent resistance of the power supply line 121 causes a 1V drop in accordance with the voltage of the node Np", so the reference voltage Vref is set to 1V. Therefore, during the second period, the voltage of the node NR]] is lv. Since the voltage of the node is still 3V, the voltage across the source and gate of the driving transistor MDn will be changed from the original 2v to 1V (4V - 3V). During the third period, since the voltage of the node NR" is still lv, and the voltage of the node 0773-A34I79TWF P2009005 201120850 point Nb is still 3V, the voltage across the source and the gate of the driving transistor MDn is maintained at IV. . In the fourth period, the voltage of the point Nb is VNb = VDATA_Vl " ef (i.e., 3V - 1V). Since the voltage of the node NP] is 4V and the voltage of the node Nb is VNb = 2 V ', the voltage across the source and the gate of the driving transistor MD1 is restored to 2V by IV. Figure 2B is another possible embodiment of the pixel unit of the present invention. Fig. 2B is similar to Fig. 2A except that the control Fig. 2B has an additional control φ crystal MCn. In the present embodiment, the control transistor MCn is an N-type transistor, the gate of which receives the illuminating signal SEM, the drain of which is coupled to the drain of the driving transistor M11, and the source of which is coupled to the illuminating element 200. The invention does not limit the internal structure of the halogen unit. As long as the pixel unit has a driving transistor and a capacitor, it can be used as the pixel unit of the present invention, wherein the driving transistor system in the pixel unit is coupled to a power line, and the pixel unit The capacitor is coupled between a reference line and a gate of the driving transistor. • Fig. 3 is a possible embodiment of the power supply unit 123 of the present invention. As shown, the power supply unit 123 includes a processing unit 310 and a voltage generating unit 330. The processing unit 310 captures the voltage of any node on the power line 121, and generates a control signal Sc according to the captured result. In the present embodiment, the processing unit 310 draws the voltage VNP1] of the node NPn. In addition, the distance between the node NP „to the start end NPS of the power line 121 is greater than the distance between the node NP12 and the start end NPS of the power line 121. In this embodiment, the processing unit 310 includes a subtractor 311. And a comparator 312. The subtractor 311 0773-A34179TWF P2009005 11 201120850 calculates the difference between the operating voltage PVDD and the drawn voltage (ie, the voltage Vnpii of the node NPn). In this embodiment, the subtractor The difference calculated by 311 is taken as the reference voltage Vref. The comparator 312 generates the control signal Sc based on the difference (Vref) calculated by the subtracter 311 and the reference signal Sref. In the present embodiment, when the subtracter 311 calculates When the difference is smaller than the reference signal Sref, the control signal Sc is in a disabled state; when the difference calculated by the subtracter 311 is greater than the reference signal Sref, the control signal Sc is in a consistent energy state. The voltage generating unit 330 outputs the control signal Sc and The reference voltage Vref is supplied to the gate driver 125, wherein the reference voltage Vref is the difference calculated by the subtractor 311. In a possible embodiment, the reference voltage GND is less than the reference voltage V. In the embodiment, when the control signal Sc is in an enabled state, the gate driver 125 supplies the reference voltage Vref to the reference line RL^RU; when the control signal Sc is in the disabled state, the gate driver 125 provides the reference voltage. GND is referenced to the reference line RLrRLn. In a possible embodiment, the voltage generating unit 330 can be integrated in the gate driver 125 shown in FIG. 1B. In this example, the gate driver 125 has a complex voltage generating unit 330 for In order to separately control the level of the reference line RLrRLn. In the present embodiment, the voltage generating unit 330 includes transistors 331 and 332. The transistor 331 can be a P-type transistor. The transistor 332 can be an N-type transistor. When the control signal Sc is in an enabled state, the transistor 331 transmits the reference voltage Vref to the reference line RL^RLn. When the control signal Sc is in the disabled state, the transistor 332 transmits the reference voltage GND to the reference line RL^RLn. In this embodiment, the power supply device 123 further includes a voltage 0773-A34179TWF P2009005 12 201120850 generating unit 350. The voltage generating unit 350 provides an operating voltage pvdd to the start end NPS of the power line 121. In an example, the processing unit 310 generates a control signal Sc according to the operating voltage PVDD and the captured voltage (ie, vNP11). Figure 4 is a possible flowchart of one of the control methods of the present invention. The control method of the present invention is applicable to The pixel unit p2 shown in Fig. 1A. Therefore, the possible flow of one of the control methods of the present invention will be described below with reference to the symbol 'of Figure 1A'. • First, the operating voltage PVDD is supplied to the power supply line ^, and the voltage of one of the nodes N and & is used to generate the reference voltage Vref (step S410). In a possible embodiment, the reference voltage Vref may be The difference between the operating voltage PVDD and the drawn voltage. In this embodiment, the voltage of the node 撷 is taken. The distance between the node n2 to a power supply device (e.g., symbol 丨 23 shown in Fig. 1A) is greater than the distance between the node 1 and the power supply device 123. In addition, the operating voltage PVDD can be provided by the power supply unit 123. Next, a scan signal and a data signal are supplied to the first or first pixel unit, and a reference voltage Vref is supplied to the reference line 122 (step S430), taking the pixel unit p of FIG. 1A as an example. The gate voltage of the driving transistor MD! is approximately equal to the data signal, and the voltage of the node N4 is approximately equal to the reference voltage Vref. Then, the supply of the scan signal is stopped, and the reference voltage yref is continuously supplied (step S450). At this time, the gate voltage of the driving transistor MD] is still approximately equal to the data signal, and the voltage of the node n4 is also approximately equal to the reference voltage Vref. Finally, the reference voltage GND is supplied to the reference line 122 (step S470). 〇773-A34179TWF_P2009005 13 201120850 At this time, the voltage of the node N4 is approximately equal to the reference voltage GND. In this embodiment, the reference voltage GND is smaller than the reference voltage Vref. According to the characteristics of the capacitor C2, when the voltage of the node N4 drops from the original Vref to GND, the gate voltage of the driving transistor MD! will drop by Vref. Therefore, the voltage drop due to the impedance of the power supply line 121 can be compensated. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a schematic view of an electronic system of the present invention. Figure 1B is another possible embodiment of the electronic system of the present invention. Figure 2A is a possible embodiment of a halogen unit of the present invention. Figure 2B is another possible embodiment of the pixel unit of the present invention. Fig. 3 is a view showing a possible embodiment of the power supply device of the present invention. Figure 4 is a possible flow chart of one of the control methods of the present invention. [Main component symbol description] 100: electronic system; 110: voltage conversion device; 120: display panel; 121: power supply line; 122: reference line; 0773-A34179TWF P2009005 14 201120850
Pi、p2、Pn〜Pmn :晝素單元； 123 :電源供應裝置； 124 :驅動裝置； 125 :閘極驅動器； 126 :源極驅動器； MSU :切換電晶體；Pi, p2, Pn~Pmn: halogen unit; 123: power supply device; 124: driving device; 125: gate driver; 126: source driver; MSU: switching transistor;
Cl 1 ·電容， MD11 .驅動電晶體， 200 :發光元件； MCU :控制電晶體； 310 :處理單元； 311 :減法器； 312 :比較器； 331、332 :電晶體； 330、350 :電壓產生單元。Cl 1 ·capacitor, MD11. drive transistor, 200: light-emitting element; MCU: control transistor; 310: processing unit; 311: subtractor; 312: comparator; 331, 332: transistor; 330, 350: voltage generation unit.
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