201119170 六、發明說明： 【發明所屬之技術領域】 本發明係有關於切換式電源轉換’特別是關於可在债測到異 常負載變動或輕載狀態時關斷一二次侧開關之切換式電源轉換。 【先前技術】 在電子設備之供電中，切換式電源轉換器因其具有高轉換效 率及小型零件尺寸之優勢而廣被採用。 以返馳式交流轉直流電源轉換器為例，圖1展示了包括一二 次侧同步整流控制器之習知返馳式交流直流電源轉換器之方塊 _ 圖。如圖1所示，該架構包含有一 N型金氧半(NM0S)電晶體1(Π、 一主變壓器102、一 Ν型金氧半（NM0S)電晶體103、一電容104及 一二次側同步整流控制器1〇5。 在該架構中’該刚OS電晶體1〇1係用以反應一脈衝寬度調變 (PWM)信號VG1以控制該主變壓器1〇2之電能轉換。 該主變壓器1 〇2係用以將輸入直流電源VlN轉換成一直流輸出 電壓V〇。 ^該NM0S電晶體103係耦接至該主變壓器102之二次側，用以 φ模擬一整流二極體以在該二次侧同步整流控制器105之二次侧閘 控2说Vg2控制下’在該NMOS電晶體1〇1開啟時截斷該二次側之 電流路徑’及在該NMOS電晶體1〇1關閉時釋放磁通能量至該電容 1〇4及一負載(未示於圖1中）。 及電谷104係用以承載該直流輸出電壓v〇。 ，，次側同步整流控制器105係用以依一二次側電壓信號V» Ϊ生该:士側閘控信號Vc2以開、關該NM0S電晶體103，其中該二 二側電壓信|虎％在該_s電晶體1〇1導通時會產生瞬間上升電 壓。 藉由一 PWM控制器（未示於圖1中）之PWM信號VG1使該NMOS 曰曰體101週期性地開啟、關閉，及該NMOS電晶體1〇3之配今叹、201119170 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a switched power supply conversion, particularly to a switching power supply capable of turning off a secondary side switch when an abnormal load change or a light load condition is detected. Conversion. [Prior Art] In the power supply of electronic equipment, the switching power converter is widely used because of its high conversion efficiency and small part size. Taking a flyback AC to DC power converter as an example, Figure 1 shows a block diagram of a conventional flyback AC/DC power converter including a secondary side synchronous rectifier controller. As shown in FIG. 1, the architecture includes an N-type MOS (NM0S) transistor 1 (Π, a main transformer 102, a 金-type MOS (NM0S) transistor 103, a capacitor 104, and a secondary side. Synchronous rectification controller 1〇5. In this architecture, 'the OS OS1〇1 is used to react to a pulse width modulation (PWM) signal VG1 to control the power conversion of the main transformer 1〇2. 1 〇 2 is used to convert the input DC power source V1N into a DC output voltage V〇. The NM0S transistor 103 is coupled to the secondary side of the main transformer 102 for φ simulating a rectifying diode to The secondary side gate control 2 of the secondary side synchronous rectification controller 105 says that the Vg2 control 'cuts the current path of the secondary side when the NMOS transistor 1〇1 is turned on' and when the NMOS transistor 1〇1 is turned off The magnetic flux energy is released to the capacitor 1〇4 and a load (not shown in FIG. 1). The electric valley 104 is used to carry the DC output voltage v〇, and the secondary side synchronous rectification controller 105 is used to The secondary side voltage signal V» generates the: the side gate control signal Vc2 to open and close the NMOS transistor 103, wherein the two sides are electrically The pressure letter|the tiger% generates an instantaneous rising voltage when the _s transistor 1〇1 is turned on. The NMOS body 101 is periodically made by the PWM signal VG1 of a PWM controller (not shown in FIG. 1). Turn on, off, and match the NMOS transistor 1〇3,
L 0 J 3 201119170 關，輸入電，即可經由該主變壓器1〇2轉換至輸出端。 然而，當該直流輸出電壓v。面臨劇烈負载變化，該NM〇s電晶 體101之導通時間—由該PWM信號〜控制—將在一暫態期間内產 生巨大變f，而該NM0S電晶體1Q3在該暫態期間内之開、關可能 因此無法落在正確的時點上—因該二次側閘控信號I可能無法跟 知壞的風險。另外’當該電源轉換器處於輕載時，因驅動該_s 電晶體⑽❿消耗之功率可能比未設二次側同步整流控制器之電 源轉換器其整流二極體本身之功耗還大。 n因提供—解決方案，其可在魏轉換11面臨劇烈負 或輕载狀況時妥適關斷二次側開關以避免災難發生及/或 使功耗極小化。 【發明内容】 麵明之Γ目的在於提供一用於切換式電源轉換器之二次側 關斷- -'Μ貝丨1電源轉換器面臨劇烈負載變化或輕載狀況時妥適 關斷一-人側開關，以避免災難發生及/或使功耗極小化。 ΐΓί之S目的在於提供—用於娜式電源轉換器之二次 電源轉換器面臨劇烈負载變化或輕載狀況時妥 適關，二人侧⑽免災難發生及/錢雜極小化。 為達成本發明前述目的’ 一種用於切換 側保護方法乃被提出，其係依— 關，射該二次側電壓伸關斷一二次側開 之下降㊣㈣庙认々虎，、有對應各二次側放電期間起始點 測二相鄰該上升緣之時間間二： 束，以及在二接續該放電結束職之相· 疋百分比生-第—瞒信號關斷該二次 、σ 換器置本步ΐ出—種用於切換式電源轉 人側保置，其係依—二次側電壓信號關斷一二_ ^ 〇 1 201119170 開關，其中該二二人側電壓信號具有對應於各二 點之下降緣，及對應於各該二次側放電期 電4間起始 ^ ^5 ^ 門門隔以牌致夂放雷έ士击、s « 後里測一相鄰該上升緣之時 間間&讀致各放電結束週期；以及—暫態保護触 接續該放電結束週期之相對差異超過一預定百分比時 t 關斷信號以關斷該二次側開關。 王弟一 ，使貴審查委員能進一步瞭解本發明之結 的，兹附關式及較佳具體實_之詳細 m及其目 【實施方式】 料Ϊίί ® 較佳實_實施之二次侧 保護裝置之一:人側同步整流控制器之方塊圖。如圖 次姻步錢控制器包括一别開〆關控 = 測模組搬、-嶋。3、一 SR閃鎖器謝及 =_ -係用以依一二次侧電壓信號^生 μ -…而電期間不致與主侧充電期間重疊，豆 具有龍於各二次嫩_結束點之^ 升緣及對應於各二次側放電期間起始點之下降緣。 異常莫組202係用以在該二次側電壓信號域於 浐，1 =思私一強制關斷信號V0FF以強制關斷該二次側電晶 體:、中該異常狀態可對應至一劇烈 ::;鄰之相對差異超過-預定百分比 續OlTpf^上升緣與該下降緣之時間間隔超過一預定期間。 诚，装m輸及用產生—騎信號v_之一輸出 高邏輯出端會在該二輸入端其中任一為高邏輯準位時呈現 該涨閃鎖器204及該驅動n 205係用以依該導通信號“及 201119170 該關斷信*； v_T2產生一二次側閑控 號^會在該關斷信號Vre讀於高邏輯 =其呈 =二邏=控信 依圖2之二次側同步整流控!^位時呈現低邏輯準位。 出。請參照圖3，其繪示依本發明二次側保護方法乃被提 之流程圖。如圖3所示，該方法包括^例之二次側保護方法 側電壓信號其二相鄰上升緣之1下二驟·重複量測-二次 (步驟认在二接續該放電結束字1m致各放電結束週期 該二次側電壓信號^升緣步驟b)，·重複量測 電期間（步驟c).以及在仰^緣之時間間隔以獲致各停止放 J二，驟C)，以及在•止放電期間超過 一第一關斷信號以關斷該二次側開關（步驟d)e 、生 在步驟a，該二次側電壓信號之 間之結束時點。 i升緣係代表該二次側放電期 在^驟b ’該預疋百分比可為例如但不限於挪。 ，二驟c ’|負載變輕’則該停止放電期間會變長。 50%。竭&該預定綱可為例如但不限於前—放電結束週期之 昭圓ΓίΓ異常狀態偵測模組挪可以圖4之裝置實施。請參 = 依本發明—較佳實施例實施之二次侧保護裝置之方 ^圖。如圖4所示，該裝置包括—對比較器他〜搬、一問= 、-雙態觸變單元404、-料發脈衝產生單元.、一 ，開;關407〜408、-對電流源409〜41〇、一對電容411〜412、一暫 態保護模組413、一輕載偵測模組414及一 〇R閘415。 β該比較器401係用以依一二次側電壓信號％及一第一參考電 壓Vth，》產生一第一重置信號Vreseti，而該比較器4〇2係用以依該二 次侧電壓信號Vd及一第二參考電壓Vthdisdiend產生一第一設置信號 Vseti ’ 其中 Vth,dischend大於 vthOT。 該閂鎖器403係用以依該第一重置信號Vreseti及該第一設置信 201119170 號Vsm產生一二次侧放電狀態信號Vwdisch，其中該二次侧放電狀態 ^號Vwdiseh為一脈衝信號’其上升緣代表該二次侧放電期間之結 束而其下降緣則代表該二次側放電期間之起始。 ，雙態觸變單元404係用以依V2nddisdl產生一第一選擇信號Vseia 及一第二選擇號乂_ ’其中vsela之脈衝係與Vseib之脈衝交替呈現。 該單發脈波產生單元405係用以依Vsela產生一第一放電脈衝 RESETA，而該單發脈波產生單元4〇6則係用以依產生一第二 放電脈衝RESETB。L 0 J 3 201119170 Off, input power, can be converted to the output via the main transformer 1〇2. However, when the DC output voltage v. Faced with a severe load change, the on-time of the NM〇s transistor 101 - controlled by the PWM signal ~ will produce a large change f during a transient period, and the NM0S transistor 1Q3 is turned on during the transient period, It may therefore not be possible to fall at the correct point in time - because the secondary side gating signal I may not be at risk of knowing. In addition, when the power converter is under light load, the power consumed by driving the _s transistor (10) may be greater than the power consumption of the rectifying diode itself of the power converter without the secondary side synchronous rectification controller. n Provided by a solution that properly shuts down the secondary side switch to avoid a disaster and/or minimize power consumption when the Wei transition 11 is subjected to severe negative or light load conditions. SUMMARY OF THE INVENTION It is an object of the present invention to provide a secondary side turn-off for a switching power converter - a 'Μ贝丨 1 power converter that is properly shut down when subjected to severe load changes or light load conditions. Side switches to avoid disasters and/or minimize power consumption. ΐΓί's purpose is to provide - the secondary power converter for the Na-type power converter is subject to severe load changes or light load conditions, and the two-person side (10) is free of disasters and/or minimization of money. In order to achieve the aforementioned object of the present invention, a method for switching side protection is proposed, which is based on the off-state, and the second-side voltage is turned off and the second side is turned off. During the secondary side discharge period, the starting point is measured two times adjacent to the rising edge: the beam, and the phase at the end of the second discharge of the discharge, the percentage of the lifetime - the first - 瞒 signal turns off the second, σ The device is set to be used for switching power supply to the side protection, which is based on the secondary side voltage signal to turn off the _ ^ 〇 1 201119170 switch, wherein the two-person voltage signal has a corresponding The falling edge of each two points, and corresponding to each of the secondary side discharge period, the first 4 ^^5 ^ gates are separated by a card to release the Lei Shishi, s « after the measurement of an adjacent rising edge During the time & read each discharge end period; and - the transient protection contact continues the discharge end period when the relative difference exceeds a predetermined percentage t turn off the signal to turn off the secondary side switch. Wang Diyi, the reviewer can make a better understanding of the knot of the present invention, the details of the attached and better details and its objectives [implementation] material Ϊ ίί ® better _ implementation of the secondary side protection One of the devices: a block diagram of the human side synchronous rectification controller. As shown in the figure, the controller of the money includes a separate control = test module move, - 嶋. 3. A SR flash locker and =_ - is used to generate a μ-... according to a secondary side voltage signal. During the period of electricity, it does not overlap with the main side charging period, and the bean has a dragon at each second tender_end point. ^ The rising edge corresponds to the falling edge of the starting point during each secondary side discharge. The abnormal group 202 is used to forcibly turn off the secondary side transistor in the secondary side voltage signal domain, 1 = thinking a forced off signal V0FF: wherein the abnormal state can correspond to a sharp: :; The relative difference of the neighbors exceeds the predetermined percentage. The time interval between the rising edge of the OlTpf^ and the falling edge exceeds a predetermined period. The output of the high-logic output is generated when the one of the two inputs is at a high logic level, and the flash lock 204 and the drive n 205 are used to generate the high-logic output. According to the turn-on signal "and 201119170 the turn-off letter *; v_T2 generates a secondary side idle control number ^ will be read in the turn-off signal Vre in high logic = its = two logic = control according to Figure 2 The side synchronous rectification control shows a low logic level. Referring to Fig. 3, a flowchart of the secondary side protection method according to the present invention is shown. As shown in Fig. 3, the method includes The secondary side protection method side voltage signal of the two adjacent rising edges of the next two steps · repeated measurement - secondary (step recognizes that the second end of the discharge end word 1m causes each discharge end period of the secondary side voltage signal ^ The rising edge step b), the repeated measurement period (step c), and the time interval between the elevations to obtain each stop release J2, C), and during the • discharge discharge exceeds a first shutdown signal To turn off the secondary side switch (step d)e, which is generated in step a, the end point between the secondary side voltage signals. The secondary side discharge period may be, for example, but not limited to, shifting, and the second step c '|load becomes lighter, then the discharge will become longer during the stop discharge. 50%. Exhaustion & The configuration may be, for example, but not limited to, a front-end discharge cycle, and the abnormal state detection module may be implemented by the device of Figure 4. Please refer to the side of the secondary protection device implemented in accordance with the present invention. ^ Figure. As shown in Figure 4, the device includes - for the comparator he ~ move, a question =, - two-state thixotropic unit 404, - material pulse generation unit., one, open; off 407 ~ 408, - For the current source 409~41〇, a pair of capacitors 411~412, a transient protection module 413, a light load detection module 414 and a R gate 415. The comparator 401 is used for one time. The side voltage signal % and a first reference voltage Vth, a first reset signal Vreseti is generated, and the comparator 4〇2 is configured to generate a first according to the secondary side voltage signal Vd and a second reference voltage Vthdisdiend A setting signal Vseti 'where Vth, dischend is greater than vthOT. The latch 403 is used to follow the first reset signal Vreset i and the first setting letter 201119170 Vsm generates a secondary side discharge state signal Vwdisch, wherein the secondary side discharge state ^Vwdiseh is a pulse signal 'the rising edge thereof represents the end of the secondary side discharge period and the drop thereof The edge represents the beginning of the secondary side discharge period. The two-state thixotropic unit 404 is configured to generate a first selection signal Vseia and a second selection number 乂 _ according to V2nddisdl, wherein the pulse of the vsela and the pulse of Vseib The single-shot pulse generation unit 405 is configured to generate a first discharge pulse RESETA according to Vsela, and the single-shot pulse generation unit 4〇6 is configured to generate a second discharge pulse RESETB.
^ "亥開關4〇7係用以反應RESETA而對該電容411實施放電，而 η亥開關408則係用以反應RESETB而對該電容412實施放電。 一該，流源409及該電容411係用以在^13之控制下產生一第 一斜波乜號Vrampa，而該電流源410及該電容412則係用以在 之控制下產生-第二斜波信號V_B，其中¥_及ν_均具有由一 部分及-保持部分組成之基本符號，# v_展現該斜線 ^㈣即展現該保持部分，反之亦然，且該ν_& v_ 在各該保持部分之電壓代表各該放電結束週期。 產生Γ T在，之上升緣依v一 產生第關斷jg#uv_，以在二接續該二次侧放電結束_ V隱4及VRAMPB在各該保持部分之電壓代表一之相對差異 — =^比時’ _該二次側電晶體。該預定百分比可為例如但不^^ "Hai switch 4〇7 is used to discharge RESETA to discharge the capacitor 411, and ηhai switch 408 is used to react to RESETB to discharge the capacitor 412. In one case, the current source 409 and the capacitor 411 are used to generate a first ramp frequency Vrampa under the control of ^13, and the current source 410 and the capacitor 412 are used to generate under the control - second The ramp signal V_B, wherein both ¥_ and ν_ have a basic symbol consisting of a part and a holding part, #v_presenting the oblique line ^(4) exhibiting the holding part, and vice versa, and the ν_& v_ is in each The voltage of the holding portion represents each of the discharge end periods. The ΓT is generated, and the rising edge of the rising edge of jg#uv_ is generated by v1, so that the second discharge ends at the end of the second _V hidden 4 and the voltage difference of VRAMPB in each of the holding portions represents a difference - =^ When the time ' _ the secondary side of the transistor. The predetermined percentage can be, for example, but not ^
=載，模組414係用以在Wh之下降緣，經由V 或=_而在¥_或v_之斜線上升部分獲得取樣電壓，以 ^測V:之上升緣與下降緣之時_隔峨致各停 間’以及备在㈣之下降緣所獲得之該取樣電壓（代 ^ ，電期間）超過-預雜界電s (代表—預找間）日^表U一 第-騎㈣㈣晴該二次側_。該預定綱 ’ 於前一放電結東週期之50%。 -、’]如但不限 201119170 該OR開415具有分_接該第一關斷信號v圓及該第二騎 ί说甘°12,二輸入端，及用以產生該強制關斷舰K一輸出 細端會在該二輸人端其中任-為高邏輯準位時呈現 尚邏輯準位。 請巧圖5a，其繪示圖4裝置在面臨職⑼獅也瞧 iUm〇de ;不連續電流模式)轉變至CCM ((bntin_ Cuirent 續電流模式）時之工作波形圖。如圖5a所示，v_在ν_ ,弟個上升緣局於V_之麵，故v_由低邏輯準位變為高邏 輯準位；而VR_在K帛5個上升緣係介於^之娜與順 之間，故Vom由高邏輯準位變為低邏輯準位。 請參照® 5b ’其繪示圖4裝置在面臨CQf轉變至廳時之工 作波形圖。如圖5b所示’ v_在V2nddisch之第3個上升緣低於ν·Α 之々95% ’故V麵由低邏輯準位變為高邏輯準位；* ^刪在ν逢也 之第5個上升緣係介於v瞧之95%與刪之間，故v_由高邏 輯準位變為低邏輯準位。 請參照圖_5〇，其繪示圖4裝置在面臨輕載狀況時之工作波形 圖。如圖5c所示’在Vhddisdi之各下降緣Vrampb係高於一參考電壓R ωΑ()Α 且1係高於-參考電壓Vll_，故v_s該輕麵間保持高邏輯 • 準位。 該暫態保護模組413可依本發明一較佳實施例實施於圖6之 電路中。如圖6所示，該電路包括一放大器6(Π、電阻6〇2〜6〇4、 一對比較器605〜606、一反及閘6〇7及一閂鎖器6〇8。 該放大器601及電阻602〜604係用以產生一第一臨界電壓 V酿’其為ν·Α之95%，及一第二臨界電壓ν_，其為VRm之|〇5%。 該比車父器605具有耦接Vrampb之一正輸入端，耦接Vrefa之一負 輸入端，及用以產生一過早信號Vpreoffb之一輸出端，其中該過早信 號％_8在VRAMPB低於VREFA之狀況下係為低邏輯準位，在其餘狀況下 則為高邏輯準位。 201119170 該比較益6G6具有之—負輸人端，她v_』之一正 輸入&及用以產生過遲號νΝ〇τ咖之一輸出端，其中該過遲信 號vNOT:在高於Vref〇之狀況下係為低邏輯準位，在其餘狀^ 下則為局邏輯準位。 «亥反及閘607具有分別輕接ypRE_及._之二輸入端，及用 二產ίΓΪ出範_#丄"之—輸出端，其中該輸*端會在該二 輸入端其中任—為低邏解辦呈現高邏輯準位，亦即，當“ 低於之95%或高於V峨之顧時’ ν一會呈 時具，接w之―資料輸入端,接“ 日^脈輸入端及用以產生一第一關斷信號v刪之一狀離輸出端。 ^ 一關斷^ V〇FF1會在ν_之上升緣採取 自電週期之相對差異超過 作波時之工 t V_4於傾解位，w處 :上=低 與WH之間，故Vp_及V_B均處於高緣係介於U 輯準位，而ν_由高邏輯準位變為低邏輯準位。，。一处於低邏 作波形圖。如圖7b所示，“在Wh之^ D3m=M時之工 故v_NDB處於低邏輯準位，Va琴處於高邏 升緣间於V_， 準位變為高邏輯準位；而v_在K苐t ’而V_由低邏輯 與V_-H之間，故VpR_& v_均處 ^上升緣係介於V_ 輯準位，而v_由高邏輯準位變為低邏準位，W處於低邏 圖8繪示依本發明一較佳實施例實 圖。如圖8所示，該電路包括-對放大器載偵測模組電路 一對比較器謝〜_、—開關網及器=、電阻齡臟、 201119170 該對放大器801〜802及電阻803〜806係用以產生〜 電壓Vl—lgada，其為V_a2 50% ’及一第四臨界電壓％ 二£^界 之 50%。 '^為 Vrampb 該比較器807具有輕接之一正輸入端，耗接Vl 輸入端，及用以產生一第一輕載信號VLLD1之一輸出端，=之—負 -輕載信號¥_在V_高於之狀況下係為 ς中該第 其餘狀況下則為低邏輯準位。 1仅’在 該比較器808具有耦接Vrampb之一正輸入端，輕接％ 輸入端’及用以產生一第二輕載信號Vlld2之一輸出端=之—負 二輕載信號ν_2在V_B高於vLL0ADA之狀況下倍 、中該第 其餘狀況下則為低邏解位。 〜’在 該開關809具有分別輕接VlLD1及Vl破二輸 之一控制輸入端，及用以產生一輕載信號Vl—LD之一 接Vsela 該輸出端係在K控制下，與該第—輕载信號其中 載信號VL_LD2交替連接。 久錄第二輕 該閃鎖ϋ 810具有輕接K一資料輪入端，轉接 時脈輸入端及用以產生-第二關斷信號騙之 :吣之- 第二關斷信號“會在V2nddlsch之下降緣採取Κ該 呈現兩邏輯準位，代表該停止放電期間超過該預定 Ί2 一個二次側放電結束週期之5〇%。 / 3，其為前 請參照圖9,其繪示圖8電路在價測 圖。如圖9所示，在“灿之各下降緣之工作波形 係尚於VL_，故V⑽及V⑽乃處於高邏 v_ 邏輯準位，而W卩嶋該_間保亦處於高 所以’經甴本發明較佳實施例之實施 轉換器在面臨劇烈負載變化或輕載狀況時妥適關二 避免災難發生及/或使雜極小化。子文通關斷一-人侧開關以 本案所揭示者，乃較佳實施例，舉凡局部之變更或 201119170 ^翻朗㈣之人所胁雜者，俱不脫 於習=特顯示其迥異 貝審查委㈣察，並祈早日辭專利，俾嘉惠 【圖式簡單說明】 圖1 -不意圖’其繪示包括—二次烟步整流控制器之習知 、驰式交流直流電源轉換器之方塊圖。 圖2為-示意圖，其緣示具有依本發明一較佳實施例實施之 二次側保護裝置之二次側同步整流控制器之方塊圖。 圖3為一示意圖，其繪示依本發明一較佳實施例之二次侧保 蠖方法之流程圖。 圖4為-示賴，其繪示依本發明―較佳實補實施之二次 側保護裝置之方塊圖。 圖5a為一示意圖，其繪不圖4装置在面臨DCM轉變至^^時 之工作波形圖。 圖5b為一tf意圖，其繪不圖4裴置在面臨CCM轉變至[^诞時 之工作波形圖。 圖5c為-示意圖’其繪示圖4裝置在偵測到輕載狀態時之工 作波形圖。 圖6為-示意圖’鱗示依本發明_較佳實施例實施之暫態 保護模組電路圖。 圖7a為一示意圖，其繪示圖6電路在面臨CCM轉變至DCM時 之工作波形圖。 圖7b為一示意圖，其繪示圖6電路在面臨DCM轉變至CCM時 之工作波形圖。 圖8為-祕圖’鱗示依本判-紐實施破施之輕載『 [ 201119170 偵測模組電路圖。 圖9為一示意圖，其繪示圖8電路在偵測到輕載狀態時之工 作波形圖。 【主要元件符號說明】 NM0S 電晶體 101、103 變壓器102 電容 104、411 〜412 二次侧同步整流控制器105 SR開/關控制模組201 • 異常狀態偵測模組202 OR 閘 203、415 SR閂鎖器204 驅動器205 比較器 401 〜402、605〜606、807〜808 閂鎖器 403、608、810 雙態觸變單元404 單發脈衝產生單元405〜406 開關 407〜408、809 • 電流源409〜410 暫態保護模組413 輕載偵測模組414 放大器601、801〜802 電阻 602〜604、803〜806 反及閘607 12=, the module 414 is used to obtain the sampling voltage at the rising edge of the _ or v_ via V or =_ at the falling edge of Wh, to measure the rising edge and the falling edge of V: The sampling voltage (in the period of electricity generation) obtained by the stoppages of each stop and the falling edge of (4) exceeds - pre-complex electricity s (representative - pre-finding) day ^ table U-first-riding (four) (four) sunny The secondary side _. The schedule is 50% of the previous discharge junction cycle. -, '], but not limited to 201119170 The OR open 415 has a split_connected to the first turn-off signal v-circle and the second rider, said the second input, and used to generate the forced shut-off ship K An output thin end will present a logical level when the two input terminals are at a high logic level. Please refer to Figure 5a, which shows the working waveform of the device of Figure 4 in the face of (9) lion 瞧iUm〇de; discontinuous current mode) transition to CCM ((bntin_ Cuirent continuous current mode). As shown in Figure 5a, V_ is in ν_, the younger rising edge is on the V_ side, so v_ is changed from low logic level to high logic level; and VR_ is in K帛5 rising edge is between ^之娜和顺之Therefore, Vom changes from high logic level to low logic level. Please refer to ® 5b ' which shows the working waveform of the device in the face of CQf transition to the hall. Figure 5b shows 'v_ in V2nddisch The third rising edge is lower than ν·Α 々 95% ', so the V-plane changes from a low logic level to a high logic level; * ^ deletes the fifth rising edge of ν 逢 也 between v瞧95 Between % and ,, so v_ changes from high logic level to low logic level. Please refer to Figure _5〇, which shows the working waveform of the device of Figure 4 in the face of light load conditions, as shown in Figure 5c. 'Vrampb in Vhddisdi is higher than a reference voltage R ωΑ()Α and 1 is higher than - reference voltage V11_, so v_s maintains a high logic level in the light surface. The transient protection module 413 can According to the invention The preferred embodiment is implemented in the circuit of Figure 6. As shown in Figure 6, the circuit includes an amplifier 6 (Π, resistors 6〇2~6〇4, a pair of comparators 605-606, a reverse gate 6〇). 7 and a latch 6〇8. The amplifier 601 and the resistors 602-604 are used to generate a first threshold voltage V which is 95% of ν·Α, and a second threshold voltage ν_, which is VRm The 车 5% has a positive input coupled to one of the Vrampbs, coupled to one of the negative inputs of the Vrefa, and an output for generating a premature signal Vpreoffb, wherein the premature signal %_8 is a low logic level when VRAMPB is lower than VREFA, and a high logic level in the remaining conditions. 201119170 The comparison 6G6 has a negative input, and her v_』 is positive input & And an output for generating an over-numbered νΝ〇τ coffee, wherein the too late signal vNOT: is a low logic level in a state higher than Vref〇, and a local logic level in the remaining state. «Hai anti-gate 607 has the input terminals of ypRE_ and ._, respectively, and the output of the second-generation _ 丄 _ _ _ quot quot quot quot quot 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出In the two input terminals, there is a high logic level for the low logic office, that is, when "below 95% or higher than V峨", the time will be met, and the data will be received. The input terminal is connected to the "day pulse input terminal and is used to generate a first turn-off signal v to delete one of the output terminals. ^ A turn-off ^ V〇FF1 will take the self-power cycle relative to the rising edge of ν_ The difference is more than the work time of the wave t V_4 in the decompression position, w: upper = low and WH, so Vp_ and V_B are in the high edge is in the U level, and ν_ is in the high logic level Becomes a low logic level. ,. One is in a low logic waveform. As shown in Fig. 7b, "when the Wh ^ D3m = M, the v_NDB is at a low logic level, the Va piano is at a high logic edge at V_, the level becomes a high logic level; and v_ is at K苐t ' and V_ is between low logic and V_-H, so VpR_& v_ is at the rising edge of the V_ level, and v_ is changed from the high logic level to the low logic level, W In the low logic diagram 8, a real image according to a preferred embodiment of the present invention is shown. As shown in FIG. 8, the circuit includes a pair of comparators for the amplifier-mounted detection module circuit, and the switch network and the device= , resistance age, 201119170 The pair of amplifiers 801 ~ 802 and resistors 803 ~ 806 are used to generate ~ voltage Vl - lgada, which is V_a2 50% ' and a fourth threshold voltage % of the 50% of the boundary. '^ For the Vrampb, the comparator 807 has one positive input terminal, consumes the Vl input terminal, and is used to generate one of the first light load signals VLLD1, and the = negative-light load signal ¥_ at V_ If it is higher than the other conditions, it is a low logic level. 1 Only 'the comparator 808 has one positive input coupled to Vrampb, the light is connected to the % input' and is used to generate a The output of one of the two light-loaded signals Vlld2 = the negative two light-loaded signal ν_2 is lower than the condition of V_B higher than vLL0ADA, and the lower of the remaining conditions is the low logic bit. One of the control inputs of VlLD1 and Vl is disconnected, and one of the light-loaded signals Vl-LD is connected to Vsela. The output is connected under K control, and is alternately connected with the first-light load signal VL_LD2. The second record of the second light flash lock ϋ 810 has a light K-data wheel, the switch clock input and the second-off signal to deceive: 吣之 - the second turn-off signal "will At the falling edge of V2nddlsch, the two logic levels are presented, representing that the stop discharge period exceeds the predetermined threshold 〇2 by 5〇% of a secondary side discharge end period. / 3, which is before. Please refer to FIG. 9 , which shows the circuit diagram of FIG. 8 . As shown in Figure 9, the operating waveform of each of the falling edges is still VL_, so V(10) and V(10) are at the high logic v_ logic level, and W卩嶋 is also high. The implementation of the preferred embodiment of the invention is suitable for avoiding disasters and/or minimizing the noise in the face of severe load changes or light load conditions. The sub-switch is a person-side switch disclosed in the present case. In the preferred embodiment, the person who is partially changed or the person who is threatened by the 201119170 ^ 朗 ( (4) is not inferior to the Xi 特 显示 迥 迥 审查 审查 审查 审查 审查 审查 审查 审查 审查 审查 审查 审查 审查 审查 审查 审查 审查 审查 审查 审查 审查 审查 审查 审查 审查BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 - is not intended to illustrate a block diagram of a conventional, chirp AC/DC power converter including a secondary reciprocating rectifier controller. FIG. 2 is a schematic diagram showing the same according to the present invention. FIG. 3 is a block diagram showing a secondary side protection method according to a preferred embodiment of the present invention. FIG. 3 is a schematic diagram of a secondary side synchronous rectification controller according to a preferred embodiment of the present invention. FIG. Figure 4 is a diagram showing the preferred embodiment of the invention. Figure 5a is a schematic diagram showing the operation waveform of the device in the face of DCM transition to ^^. Figure 5b is a tf intent, which is not shown in Figure 4. Facing the CCM transition to [^'s work waveform diagram. Figure 5c is - Schematic', which shows the operation waveform of the device of Figure 4 when the light load state is detected. Figure 6 is a schematic diagram of the scale according to the invention _ FIG. 7a is a schematic diagram showing the operation waveform of the circuit of FIG. 6 in the face of CCM transition to DCM. FIG. 7b is a schematic diagram showing the circuit of FIG. The working waveform of the DCM is changed to the CCM. Figure 8 is a schematic diagram of the "Current diagram" according to the judgment - New implementation of the light-loading [201119170 detection module circuit diagram. Figure 9 is a schematic diagram, its diagram The working waveform of the 8 circuit when the light load condition is detected. [Main component symbol description] NM0S transistor 101, 103 Transformer 102 Capacitor 104, 411 ~ 412 Secondary side synchronous rectification controller 105 SR on/off control module 201 • abnormal state detection module 202 OR gate 203, 415 SR latch 204 Driver 205 Comparators 401 to 402, 605 to 606, 807 to 808 Latchers 403, 608, 810 Two-state thixotropic unit 404 Single-shot pulse generating units 405 to 406 Switches 407 to 408, 809 • Current sources 409 to 410 State protection module 413 light load detection module 414 amplifier 601, 801~802 resistors 602~604, 803~806 reverse gate 607 12