201116987 ζνν^-Αάδ 32300twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電源控制 一種預先對域板待機電壓端放電的電源控有關於 【先前技術】 先進技術擴展（Advanced Techn〇1()gy ATX)主機板規格由英特爾公司在咖年^目= 數的電源供應H都是使用ΑΤχ規格，其巾 接^ 常使用的有20 Pin與24pi ，接杰取 厂的接腳。主機板上的晶片組，包括:;;:==·) _v)的放電時間可能不同===的待機電壓 壓(SB3V)放電時間也不㈤。 一南橋的待機電 當主機板中的晶片（例如南橋晶片）放 * 源供應器所提供電壓將可能造成晶 :才电 =但=揮加強的功能，更會造成整無= 電~SB3Vi^、法開機。此外，在系統開機完成前，待機 電郎㈣與SB5V)會造成功率雜 ^ 的功率消耗。 生王頰汗的不必要 【發明内容】 本發明提供一種電源控制電路，可預 機電壓端放電以預防待機電壓端放電不衫而造成 训116987 2008-235 32300twf.d〇c/n 產生異常現象。 本發明提出—種電源控制電路， 、供電開 接地之間。供電開關單電源端與 並根據系統電壓關單元與供電開關單元， 開關單元。其中的第-放電開關單元與供電 壓’當判斷_小：一第：二^電壓以產生-判斷電 -放電開關單元以對第ί電控，單元導通第 於第二預設電壓時， 二 仃电，虽判斷電壓大 电源触細供電，其中第二預 早^對弟- 在本㈣之—實施财，上述之第_^—預設電= 括弟-假負載與第_PM〇s電 ，開關早兀包 :假_接地’第 電開電電：:=包括第二放 當判斷電壓小於第 [大於弟-預設電壓時，控制單元_第二ϋ所電 在本發明之—實_巾，上述之第二放# t — 二假負載舆第二_電晶體。其中，第二:;載= 電源端，而第—ΡΜ〇ρ〜曰-弟假負載輕接第 201116987 ^008-^35 32300twf.doc/n 二龟脉艰 J&m - ^ -日日 娵極端與汲極端分別耦 假負載與接地’ fs電晶體的閘_接於控 在本發明之一實施例Φ， 晶體，其源極_:端相 在=rtp===7峨制單元: 厭η士 ^ 虽判崤電壓大於第一褚却带 ㈣，控制單元關閉第—放電開關單元。《預汉電 較單ΐ本ίΓϊ一實施例！，上述之控制單元包括第一比 較單元。第_3單=單元1二比較單元以及第三比 推拉電路齡Α 比較系統與—參考電壓。 於與參考:mb較單元與系統電壓，當系統電愿大 推拉電路的輪m出系統電壓。延遲單元耦接於 二比& 以延遲系統電麗以產生判斷電愿。第 斷電延遲單元與第—放電開關單元，根據判 元。另外、，第Γ5又電屢之比較結果控制第—放電開關單 —電ί本一實施，中，亡述之第一比較單元包括第 電阻串接於電池:二::運算放大器:第二電阻與第— 參考電墨。第二ί 間’以分壓電池電屋而產生 負輪入端無拉〜异放大器之正輸入端輕接***電虔，其 接弟一電阻與第二電阻的共同接點。 201116987 2008-235 32300twf.doc/n201116987 ζνν^-Αάδ 32300twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a power supply control for a power supply for pre-discharging a standby voltage terminal of a domain board. [Prior Art] Advanced Technology The extension (Advanced Techn〇1() gy ATX) motherboard specifications are used by Intel Corporation in the year of the year. The power supply H is used in the specification. The towel is often used with 20 pins and 24pi. The pin of the factory. The chip set on the motherboard, including:;;:==·) _v) The discharge time may be different === standby voltage (SB3V) discharge time is not (five). The standby power of a south bridge is the voltage supplied by the source device when the chip in the motherboard (such as the south bridge chip) is placed. The power will be crystallized: but the function of the power supply will be reduced, and the power will be reduced to SB3Vi^. The law is turned on. In addition, standby power (4) and SB5V) will cause power consumption of the power supply before the system is turned on. Unnecessary of the king's cheek sweat [Invention] The present invention provides a power supply control circuit that can be pre-charged at the voltage end to prevent the discharge of the standby voltage terminal and cause the phenomenon of 116987 2008-235 32300twf.d〇c/n . The invention proposes a power control circuit, and the power supply is grounded. The power supply switch has a single power supply terminal and is connected to the power supply switch unit and the switch unit according to the system voltage. The first-discharge switch unit and the supply voltage 'when judging _ small: one: two voltages to generate--determining the electric-discharge switch unit to the third electronic control, the unit conducting the second preset voltage,仃 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Electric, switch early bag: false _ grounding 'the first electric open electric::= including the second release when the judgment voltage is less than the [greater than the younger - the preset voltage, the control unit _ the second ϋ electric in the invention - the real _ towel, the above second release #t - two false load 舆 second _ transistor. Among them, the second:; load = power terminal, and the first - ΡΜ〇ρ ~ 曰 - brother dummy load lightly connected to the 201116987 ^008-^35 32300twf.doc / n two turtles difficult J & m - ^ - day 娵The extreme and the 汲 extreme are respectively coupled with the dummy load and the grounding 'the gate of the fs transistor _ is controlled in an embodiment of the invention Φ, the crystal, the source _: the end phase is at =rtp===7 峨 unit: 厌η士^ Although the voltage is greater than the first 褚 but with (4), the control unit turns off the first discharge switch unit. "Pre-Han Electric is more than an example!" The control unit described above includes a first comparison unit. The third _3 single = unit 1 two comparison unit and the third ratio of the push-pull circuit Α comparison system and - reference voltage. In comparison with the reference: mb compared to the unit and system voltage, when the system is willing to push the circuit of the circuit m out of the circuit voltage. The delay unit is coupled to the second ratio & to delay the system to generate a judgment. The first power-off delay unit and the first-discharge switch unit are based on the judgment. In addition, the third comparison and the result of the comparison of the first control of the discharge-single-single-electrical implementation, in the first comparison unit, includes the first resistor connected in series with the battery: two:: operational amplifier: second resistor And the first - reference ink. The second ί is produced by dividing the battery house. The negative input terminal is not pulled. The positive input terminal of the different amplifier is connected to the system power supply, and the second contact of the resistor and the second resistor is connected. 201116987 2008-235 32300twf.doc/n
電晶觸四=:中體’拉電路包括咖S 其閉極端輕接至第一運算 ^ ί四=?Γ推拉電路之輸出端而轉接電阻。科 %晶體之源極端耦接NMOS電晶體之^^ 端’苐四PMOS帝曰挪—、 兒日日版原極 曰俨的pw 毛曰曰體之及極端輕接接地，第四mos電 曰曰體的閘_接至第一運算放大器的輸出端。 電 電容在之种，上述之延遲單元包括電阻與 電阻的另-端與接地之間。 以而電痛接於 極體在實施例中，上述之延遲單元更包括—二 &的陽極端耦接電阻與電容的共同接點，二描 體的陰極端軸接推拉電路的輸出。 —極 三電：本ΓΓ實施例中’上述之第二比較單元包括第 :r:;:蝴壓與接地之間，“= 元以接收;;：二第二運算放大器之正輸入端搞接延遲單 電阻41= ’第二運算放大器的負輸入端耗接第- 過第五電“接點H算放大器的輸出端透 电1耦接至弟一 PMOS電晶體的閘極。 六電ί本實刺中：上述之苐三比較單元包括第 阻串接於李與弟二運具放大為。第六電阻與第七電 二預設電if與接地之間，以分壓系統電壓而產生第 屯反。弟三運算放大器之正輸入端耦接第六電阻與 201116987 JUUH-235 32300twf.doc/n 第七電阻的共同接點，第三運算放大器 斷電壓’第三運算放大器的輪出端 又^入端耦接判 三PMOS電晶體的閘極。 /电阻耦接至第 在本發明之一實施例中，上述 設電壓。 ，考电壓等於第—預 基於上述，本發明利用控制單元 第一預設電壓、第二預設電壓的比較4 ^判斷電壓與 電壓的電源端進行放電，並對電源端進行供^預先對待機 電腦主機板上晶片的待機電壓達到完使供應 避免待機電壓㈣存電壓使 ， 件產生異常現象。 Τ，、待機電壓相關的元 為讓本發明之上述特徵和優點 舉實施例’並配合所附圖式作詳細說明如 ，下之4寺 【實施方式】 下面將參考附圖詳細闡 說明了本發明的示範實施例，其:附圖， 似的元件。 $门私旒私不同樣或相 在筆兄型電腦中，其電源模 電源或電池電源轉換A )電尉、應讀將交後 供主機板上之電片如:勝、_4 作，造成南橋晶片會影響後端的系統正常％ 片+作動等問題產生。因此，本實施^ 201116987 2008-235 32300twf.doc/n 路針對各種系統電壓可能在關機後產生放電不 «紅常運作的問題提出解決方式。^ 源模組系統圖。電源槎Γίΐ 實施例之電腦之電 -電壓轉換電路：:且匕括電源轉接器(adapter) 108、第 112。雪、语絲杻 电源控制電路100、第二電壓轉換哭 η2。電源轉接器108用才 ，第-電細二;源至第一電壓轉換電路 SB5V-IN，麸後再轉拖 曰將電源轉換系統電屋 SB3V，輸出待機雷厂為系統所需的待機電壓與 彌出捋機電壓SB5V的跬戥淼盔铱 ^ ουτι ’而輸出待機電虔SB —電源端 Φ，佐她帝/sp cm ，為苐一 ％源端OUT2。# …i B3V可經由第二電 /、 電壓SB5V分壓而得。, + ‘換電路112對待機 系統中，用來對第-電源端0UT1 口?電源松絚 行供電與放電等操作，以防止待機電OUT2進 機後產生放電不完全的問題。 、SB5V在關 電源控制電路1〇〇包括和制；_ 單元104、第二放電開關單元m與：；^、第;放電開關 -放電開關單元104叙接於第1源嫂，早几106。第 GND之間，第二放電開關單元…、UT1與—接％ OUT2與一接地GND之間。供電 ⑽妾於第二電源端 電壓SB5VJN與第一電源端〇UTl 106耦接於*** 接第—放電開關單元1G4、第二放電θ °。控制單元102_ 開關單元106，並根據系統電壓_單元與供電 一放電開闕單元104、第二放電開 \的變化來控制第 ^兀116與供電開闕 201116987 2UU«-235 32300twf.d〇c/n 單元106的導通狀態。 斷先延遲系統電壓職损以產生一判 〇。元丨〇首^彳斷電壓VE小於一第一預設電壓時，控制 =102導通第—放電開關單元刚與第二放電開關單元 ^ =對第—電源端OUT1與第二電源端OUT2進行放 二_田判斷電愿VE大於第一預設電壓(例如3V)時，控制 早7^〇 2會關閉第—放電開關單元1 〇 4與第二放電開關單 ^」當判斷賴VE大於一第二預設電麗(例如4V)時， 、工一早元$ ;通供電開關單元106以對第一電源端OUT1 進仃供電。電源模組即根據電壓SB5V_IN 電壓給主_統使用。 毅對應的 猎由上述的放電流程’可使主機系統114中之晶片（例 =^所接枚的待機電壓SB5V或SB3V達到完全放電， 雙上的殘存電壓使主機线114中的相關元件 袖、主^吊ί象。例如主機系統114的CM 〇 S時間不預期地 π除。其中，第二預設電壓大於第一預設電壓。也就口 統^ SB5V损上升的過程中，電源控制電ί 曰先對第一電源端0UT1與第二電源端〇UT2進 书’然後在线電壓SB5V_IN大於第二預設電壓時才 =源端OUT1與第二電源端qUT2進行充電以拉高待機 %壓SB5V或SB3V的電壓值。 值付注意的是’上述以待機電壓SB5V、SB3v =為例來卿本實闕之技術手段，然本實施例並不^ 於待機電壓SB5V、犯3V的輸出端，也可以應用於其他電 201116987 2008-235 32300twf.doc/n ::機個數亦不受限，也可以單純使用 只要增力:;應的s㈣的輸出端， 出端，㈣—入^ 即可適用於多組電壓源的輸 出、，使其元纽電後再拉高其麵值。 接下來’進-步說明電源控制 2是依照本發明另-實施例之電源控制電路的;、二2 ; 源控制電路100包括㈣罝分⑽〜电㈣万塊圖。電 一放帝&控制 弟一放電開關104、第 比較早心°2、—第二比較單元204、一第= 比較單元2_4早拉=二 推拉雷政？⑽彻结 兒峪川8’延遲早兀210耦接於 ^拉電路鹰與弟二比較單元2〇4、第三比較單元裏之 獅輕接於系統電麼_损與接地 路二出f/、統電麼SB5V_IN的變化控制推拉電 ==統電壓SB5V_iN大於-參考電壓時， --〇 ° 統電心 例如0.5杪延間可她_求而定， 電路I士椹。& _ 1 ησ _的电路結構則例如是RC延遲 變化ϊ控制;艮據判斷電壓VE的電壓 盥否，第L ΐ 與第二放電開關116的導通Electro-Crystal Touch 4 =: The middle body 'pull circuit includes the coffee S. Its closed extreme light is connected to the first operation ^ 四 four =? Γ push-pull circuit output and the transfer resistance. The source of the % crystal is extremely coupled to the NMOS transistor ^^ terminal '苐四 PMOS 曰 曰 — 、 、 、 、 、 、 、 、 、 、 PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS The gate of the body is connected to the output of the first operational amplifier. The capacitor is of the type described above, and the delay unit includes a resistor and a resistor connected between the other end and the ground. In the embodiment, the delay unit further includes an anode terminal coupled to the common junction of the resistor and the capacitor, and a cathode terminal of the second trace connected to the output of the push-pull circuit. - Pole three electric power: In the embodiment of the present invention, the second comparison unit mentioned above includes: r:;: between the butterfly and the ground, "= the element is received;;: the second input of the second operational amplifier is connected Delay single resistor 41 = 'The negative input of the second operational amplifier consumes the first - fifth power" The output of the contact H amplifier is connected to the gate of the PMOS transistor. The six electric 本 实 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : The sixth resistor and the seventh resistor are between the preset power if and the ground, and the voltage is divided by the voltage of the system. The positive input terminal of the third operational amplifier is coupled to the common junction of the sixth resistor and the seventh resistor of 201116987 JUUH-235 32300twf.doc/n, and the third operational amplifier is disconnected from the voltage of the third operational amplifier. The gate of the three PMOS transistors is coupled. / Resistor Coupling to the first embodiment of the present invention, the above voltage is set. The test voltage is equal to the first-pre-based on the above, the present invention utilizes the comparison of the first preset voltage and the second preset voltage of the control unit to determine the voltage and voltage of the power supply terminal for discharging, and the power supply terminal is provided for pre-stationary standby. The standby voltage of the chip on the computer main board is completed, so that the supply avoids the standby voltage (4), and the voltage is abnormal.待机,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Exemplary embodiments of the invention, which are: like elements. $ 私私私私 is not the same or in the pen brother type computer, its power mode power supply or battery power conversion A) 尉, should be read and will be delivered to the motherboard on the chip such as: win, _4, resulting in the South Bridge The chip will affect the normal system of the back end, such as slice + actuation. Therefore, this implementation ^ 201116987 2008-235 32300twf.doc / n way for various system voltages may generate a discharge after shutdown does not solve the problem of red operation. ^ Source module system diagram. Power supply 槎Γίΐ The power of the computer of the embodiment - voltage conversion circuit: and includes the power adapter (adapter) 108, the 112th. Snow, wire, power control circuit 100, second voltage conversion cry η2. The power adapter 108 is used, the first-electrical second; the source to the first voltage conversion circuit SB5V-IN, the bran is then turned and dragged to convert the power supply system to the electric house SB3V, and the standby standby lightning factory is the standby voltage required by the system. And the output of the standby voltage SB5V 铱 ι ι ι 而 而 输出 输出 输出 输出 — — — — — — — — 电源 电源 电源 电源 电源 电源 电源 电源 电源 电源 电源 电源 电源 电源 电源 电源 电源 佐 佐 帝 帝 帝# ...i B3V can be obtained by dividing the voltage by the second electric /, voltage SB5V. , + ‘Change circuit 112 for standby system, used to power supply and discharge of the first power supply terminal OUT1 power supply to prevent incomplete discharge after standby power OUT2 enters the machine. The SB5V is in the power supply control circuit 1 〇〇 includes; _ unit 104, second discharge switch unit m and:; ^, the first; discharge switch - discharge switch unit 104 is connected to the first source 嫂, a few 106. Between the GND, the second discharge switch unit ..., UT1 and - are connected between % OUT2 and a ground GND. The power supply (10) is connected to the second power terminal voltage SB5VJN and the first power terminal 〇UT1 106 is coupled to the system to the first discharge switch unit 1G4 and the second discharge θ °. The control unit 102_ is connected to the switch unit 106, and controls the first 116 and the power supply opening 201116987 according to the change of the system voltage_unit and the power supply-discharge opening unit 104 and the second discharge opening. 2UU«-235 32300twf.d〇c/ n The conduction state of unit 106. The system voltage loss is delayed first to generate a penalty. When the first 彳 彳 彳 voltage VE is less than a first predetermined voltage, the control = 102 is turned on, the first discharge switch unit and the second discharge switch unit ^ = the first power supply terminal OUT1 and the second power terminal OUT2 are placed. When the second _ field judges that the VE is greater than the first preset voltage (for example, 3V), the control early 7^〇2 will turn off the first discharge switch unit 1 〇4 and the second discharge switch unit ^" when determining that the VE is greater than one When the second preset battery (for example, 4V) is used, the power supply switch unit 106 supplies power to the first power terminal OUT1. The power module is used by the main system according to the voltage SB5V_IN. According to the above discharge process, the wafer in the host system 114 can be fully discharged, and the residual voltage on the double causes the relevant component sleeves in the host line 114, For example, the CM 〇S time of the host system 114 is unexpectedly divided by π. The second preset voltage is greater than the first preset voltage. In the process of increasing the SB5V loss, the power supply controls the power. ί 进 First enter the first power terminal 0UT1 and the second power terminal 〇UT2 'When the line voltage SB5V_IN is greater than the second preset voltage, then the source terminal OUT1 and the second power terminal qUT2 are charged to increase the standby % pressure SB5V Or the voltage value of SB3V. The value pays attention to the above-mentioned technical means of using the standby voltages SB5V and SB3v = as an example. However, this embodiment does not use the standby voltage SB5V and the output of 3V. Can be applied to other electric 201116987 2008-235 32300twf.doc / n :: the number of machines is not limited, you can also simply use as long as the force:: s (four) of the output, the end, (four) - into ^ can be applied After the output of multiple sets of voltage sources, The following is a description of the power supply control 2 in accordance with another embodiment of the present invention; 2 2; the source control circuit 100 includes (4) a division (10) to an electrical (four) million diagram. A dynasty & control brother a discharge switch 104, the first early heart °2, - the second comparison unit 204, a = comparison unit 2_4 early pull = two push pull Lei Zheng? (10) Chu Jie children 峪chuan 8' delay early兀210 is coupled to the pull circuit eagle and brother 2 comparison unit 2〇4, the third comparison unit in the lion light connection to the system power _ loss and grounding circuit two out f /, the power SB5V_IN change control push and pull == The system voltage SB5V_iN is greater than - the reference voltage, the 〇 ° system core such as 0.5 杪 delay can be determined by her, the circuit I g 椹. & _ 1 ησ _ circuit structure is, for example, RC delay variation ϊ control; according to the voltage VE of the judgment voltage VE, the conduction between the Lth ΐ and the second discharge switch 116
”否弟二比較早元206則判斷電壓V 201116987 2Wti-23S 3230〇uvf.d〇c/n 制供電開關l〇6的導通與否。 繼=斷電壓VE小於第—預設電壓時，第1較單元 204會導通第—妓脅q_ 乐一比率乂早兀 …，以分別對，=早兀1〇4與第二放電開關單元 行放恭J對弟一電源端〇吨和第二電源端〇UT2進 1U斷電壓VE大於第-預設電壓時，第二比較 早兀204會關閉第一放電開關 車 亓116』枣兀川4與弟二放電開關單 第三比/二輕m料A於第二預設電壓時， sb7v m3ΐ會導通供電開關單元106，讓系統電壓 電以摇徂2 Τ 娜V與第二電源端SB3ν進行供 預設電壓。也就是說，電源控:電⑶ :;;=T1與第二電源端_進行放電 接下來，進一步說明上述電源控制電路ι〇 =構’請參照圖3是依照本實施例之電源控=路 圖。圖4是依照圖3實施例之電源控制電路的 ^路 序圖。請同時參照圖3與圖4，第一比較單元^交化時 阻幻、R2與運算放大器302。其中電.阻r 包括電 電池電壓VBAT與接地GND之間， 串接於一 觀丁以於電阻iu、R2的共同接點上產生 1 電池電壓 電池電壓VBAT例如是主機板上的電池带界处♦考電墼。 例如是3V。運算放大器3〇2之正、負輪八而翏考電壓 電屋SBW-IN與參寺電屡（3V)，';以H別執接*** SB5V-IN與參考電壓的大小。 ^ Λ系統電壓 201116987 2008-235 32300twf.doc/n 推拉電路 208 由 NMOS (N channel metal oxide semiconductor transistor ’ 簡稱 NMOS)電晶體 Ml 與 PMOS (P channel metal oxide semiconductor transistor，簡稱 PMOS)"No brother two compares early 206 to determine the voltage V 201116987 2Wti-23S 3230 〇 uvf.d 〇 c / n power supply switch l 〇 6 conduction or not. After = break voltage VE is less than the first - preset voltage, the first 1Compared to unit 204, it will turn on the first--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- When the terminal UT2 enters 1U, the voltage VE is greater than the first-preset voltage, and the second is earlier than 204, the first discharge switch 亓 116 is turned off. Zaochuanchuan 4 and the second discharge switch are single third ratio/two light materials. When A is at the second preset voltage, sb7v m3ΐ turns on the power supply switch unit 106, and the system voltage is supplied with a preset voltage by shaking 2 ΤV and the second power terminal SB3ν. That is, power control: electricity (3) :;; = T1 and the second power supply terminal _ discharge next, further explain the above-mentioned power supply control circuit ι〇 = configuration 'Please refer to FIG. 3 is a power supply control = road map according to the embodiment. FIG. 4 is implemented according to FIG. For example, the schematic diagram of the power control circuit of the power supply circuit. Please refer to FIG. 3 and FIG. 4 at the same time, the first comparison unit is blocked, R2 and transported. The amplifier 302. The electric resistance r includes a battery voltage VBAT and a ground GND, and is connected in series to generate a battery voltage at a common contact of the resistors iu and R2. The battery voltage VBAT is, for example, a battery on the motherboard. For example, it is 3V. The operational amplifier 3〇2 is positive and negative, and the voltage is SBW-IN and the temple is repeated (3V), '; -IN and the size of the reference voltage. ^ ΛSystem voltage 201116987 2008-235 32300twf.doc/n Push-pull circuit 208 is composed of NMOS (N channel metal oxide semiconductor transistor NMOS) transistor M1 and PMOS (P channel metal oxide semiconductor transistor, Referred to as PMOS)
电曰日體Q1串接組成，其閘極皆連接於運算比較器的 輸出。延遲單元210由電阻R9、電容c與二極體D1組成， 電阻R9與電容C串聯耦接於推拉電路2〇8的輸出與接地 GND之間，二極體D1與電阻R9並聯。其中，電阻R9 與電容c的共用接點輸出判斷電壓VE。延遲單元21〇主 要是藉由RC電路來延遲推拉電路駕所輸出的系統電塵 SB5C-IN，藉此讓後端的第一電源端〇UT1與第二電源端 OUT2在電源連接駿_拔的情況下有更長的時間可以 進行放電。The eMule body Q1 is composed in series, and its gates are all connected to the output of the operational comparator. The delay unit 210 is composed of a resistor R9, a capacitor c and a diode D1. The resistor R9 and the capacitor C are coupled in series between the output of the push-pull circuit 2〇8 and the ground GND, and the diode D1 is connected in parallel with the resistor R9. The common contact of the resistor R9 and the capacitor c outputs the determination voltage VE. The delay unit 21〇 mainly delays the system electric dust SB5C-IN output by the push-pull circuit by the RC circuit, thereby allowing the first power terminal 〇UT1 and the second power terminal OUT2 of the back end to be connected to the power supply. There is a longer time to discharge.
第一比較單兀204甴電阻R3、R4與運算放大器抓 所組成，電阻R3、R4串聯耦接於電池電壓VBAT與接地 GND之間^其共用接點產生第—預設電壓，本實施例設定 為3V。運算放大器304的正輸入端叙接於判斷電壓ve， 負輸入端耗接於電阻R3、R4的共關點以接收第讲 電壓。運算放大器304的輪出經由電阻R5雛於 電晶體Q2與Q3的閘極。第三比較單元2〇6由電阻％、 R7與運算放大器306所組成，電阻R6、R7 池電壓VBAT與躺GND之間，其共用接點產生第； 设電壓’本貫施例設定為4V。運算放大器3〇6的負輪入立山 輕接於判斷電壓VE，正輸入端耗接於電阻R6、R7的丘: 接點以接收第二預㈣壓。運算放A||鳥的輸出經^電 12 201116987 /uus-/i5 3230〇twf.doc/n 阻R8耦接於PMOS電晶體Q4的閘極。The first comparison unit 204 甴 resistors R3 and R4 are composed of an operational amplifier, and the resistors R3 and R4 are coupled in series between the battery voltage VBAT and the ground GND. The common contact generates a first preset voltage, which is set in this embodiment. It is 3V. The positive input terminal of the operational amplifier 304 is connected to the determination voltage ve, and the negative input terminal is connected to the common point of the resistors R3 and R4 to receive the first voltage. The turn-off of operational amplifier 304 is entangled in the gates of transistors Q2 and Q3 via resistor R5. The third comparison unit 2〇6 is composed of the resistors % and R7 and the operational amplifier 306. The resistors R6 and R7 are connected between the cell voltage VBAT and the GND, and the common contact is generated. The set voltage is set to 4V. The negative wheel of the operational amplifier 3〇6 is connected to the determination voltage VE, and the positive input terminal is connected to the mound of the resistors R6 and R7: the contact to receive the second pre-four voltage. Operation A||Bird's output is passed. 12 201116987 /uus-/i5 3230〇twf.doc/n Resistor R8 is coupled to the gate of PMOS transistor Q4.
第一放電開關單元1〇4包括假負載SRl與pM〇s恭曰 體Q2 ’假負載SR1與PM0S電晶體Q2串聯耦接於= 電源端ουτι與接地GND之間，PM0S電的一 則透過電阻R5耦接於運算放大器3〇4的輸出。二j極 開關單元U6包括假負載SR2與pM〇s 了 J 載SR2與PM0S電晶體Q3串聯叙接於第二電源^負 與接地GND之間，pm〇S電晶體〇3'、 2 R5耦接於運算放大器3〇4的輸出。、甲玉，透，電阻 PM0S電晶體q4構成，1 p z、幵 1關早兀106由 Q4 壓隱的輸_，PM0S 源端咖(待機電 R8減於運算放大器306的輸；；體Q4的閘極則透過電阻 接下來，進一步說明電源控制 式，請同時參照目4，#系 路100的電路作動方 SB·會開始上升，當***電源時，系統電壓 考電壓時，運算放大H 3G2的輸4^^=的參 Ml，讓推拉電路2〇8的輸 _ V通NM0S電晶體 可視為將系統電壓SB5V4N|電壓SB5V-IN 土升， 元21〇會延遲系統電壓SB5V1IN楚遲單元210。延遲單 出判斷電壓VE。因此，判斯電壓段時間後(0.5秒)輸 統電壓SB5V-IN延遲約〇 5 的電壓上升曲線較系 第二比較單元204根據判斷^ 4所不 PMOS電晶體q2、q3的導 Μ VE的變化來決定 /、令’當判斷電壓VE小於 201116987 2008-235 3230〇twf.doc/n 第一預設電壓(本實施例設定為3V)時，運算放大器304輸 出低電位以導通PMOS電晶體Q2、Q3 ’此時第一電源端 ουτι與第二電源端〇UT2可對地進行放電。當判斷電麼 VE大於第一預設電壓(本實施例設定為3V)時，運算放大 器3〇4輪出高電位以關閉PM〇S電晶體Q2、Q3，此時已 經完成放電動作。 第三比較單元204根據判斷電壓VE的變化來決定 PMOS電晶體q4的導通與否，當判斷電壓VE大於第二預 〇又包壓(本實施例設定為4V)時，運算放大器3〇4輸出低電 =以V通PMOS電晶體Q4，此時系統電壓SB5V-IN會被 導通至第一電源端〇UT1以產生待機電壓sb5V。由於待 機電壓SB3V是由待機電壓SB5V轉換而得，因此待機電 ^ SB3V也會隨彳摘電壓SB5V上升而上升至對應的電壓 值0 由上述可知’第二比較單元204會在系統電壓 B^v-m上升至第―職電壓前對第—電源端〇υτι與第 放電，避免錯誤的電壓準位造成後端 1德1 統電壓犯5物上升至第二預設 單元204會導通充電開關單元106，讓 作動以產生待機電壓SB5V、SB3V。經由上 本實施例之電壓㈣電路則加速電源端 ΐ錯*的電壓位準影響系統晶片的正常作動。 匕外，由於在判斷電壓VE上 耵，PMOS電晶體〇4 0 _认Μ 升]弟一預0電£之 Q疋處於關閉狀態，待機電壓SB5V、 14 201116987 2υυδ-ζ^5 32300twf.doc/n SB3不會隨系統電虔SB5V咖升高 SBW、SB3的負載在系統電壓sb5vJ^少待機電塵 成的功率·。也就是說，可減 升^間中所造 功率消耗。 崎機過私中所造成的 綜上所述，本發明利用控制單 第一預設電厂㈣比較結果，來預先對二S =電壓與 行放電，並·_電壓和第二預 ^的電源端進 對電源端進行供電，以使供應電 上 壓達到完全放電後再被供電，避免待機 主機板t與待機電壓相關的元件產生異常現象。子电堅使 雖然本發明已以實施例揭露如上，麸 本發明，任何所屬技術領域中具有通常知識ί， 本發明之精神和範圍内，當可作些許之更動與 發明之保護範圍當視後附之申請專利範圍所界定者為^本 【圖式簡單說明】 圖。圖1是依照本發明<實施例之電腦之電源模級系統 圖。圖2是依照本發明另-實施例之電源控制電路的方塊 圖3是依照本發明另一實施例之電源控制電路的方塊 圖。 圖4是依照圖3實施例之電源控制電路的電壓變化時 序圖。 15 201116987 2008-235 32300twf.doc/n 【主要元件符號說明】 100 :電源控制電路 102 :控制單元 104:第一放電開關單元 106 :供電開關單元 108 :電源轉接器 110、112 :電壓轉換電路 114 :主機系統 116 :第二放.電開關單元 202、204、206 :比較單元· 210 :延遲單元 208 :推拉電路 302〜306 :運算放大器 R1〜R9 :電阻 SIU、SR2 :假負載 VBAT :電池電壓 D1 :二極體 C :電容 R9 :電阻 ·The first discharge switch unit 1〇4 includes a dummy load SR1 and pM〇s, and the Q2' dummy load SR1 and the PM0S transistor Q2 are coupled in series between the power supply terminal ουτι and the ground GND, and the PM0S power is transmitted through the resistor R5. The output is coupled to the output of the operational amplifier 3〇4. The two-j pole switching unit U6 includes a dummy load SR2 and pM〇s. The J-loaded SR2 and the PM0S transistor Q3 are connected in series between the second power supply and the ground GND, and the pm〇S transistor 〇3', 2 R5 is coupled. Connected to the output of the operational amplifier 3〇4. , Jiayu, through, resistance PM0S transistor q4, 1 pz, 幵1 off early 106 by Q4 pressure hidden _, PM0S source end coffee (standby power R8 minus the input of operational amplifier 306;; body Q4 The gate is further transmitted through the resistor, and further explains the power control type. Please refer to the head 4, the circuit SB of the #路路100 will start to rise. When the system power is applied, the system voltage is measured, and the operation is amplified by H 3G2. The input M1 of the ^^^=, the input _V-pass NM0S transistor of the push-pull circuit 2〇8 can be regarded as the system voltage SB5V4N| voltage SB5V-IN soil rise, the element 21 〇 will delay the system voltage SB5V1IN Chu delay unit 210. Delaying the single-out determination voltage VE. Therefore, after the voltage period of the voltage period (0.5 seconds), the voltage rise curve of the transmission voltage SB5V-IN is delayed by about 〇5, which is determined by the second comparison unit 204 according to the determination of the non-PMOS transistor q2. The change of the VE of the q3 determines whether /, when the judgment voltage VE is less than the first preset voltage of 201116987 2008-235 3230 〇 twf.doc / n (the embodiment is set to 3 V), the operational amplifier 304 outputs low. Potential to turn on the PMOS transistor Q2, Q3 'At this time, the first power terminal ουτι The second power terminal 〇UT2 can discharge to the ground. When it is judged that the VE is greater than the first preset voltage (the embodiment is set to 3V), the operational amplifier 3〇4 turns out a high potential to turn off the PM〇S transistor Q2. Q3, the discharge operation has been completed at this time. The third comparison unit 204 determines whether the PMOS transistor q4 is turned on or not according to the change of the determination voltage VE, and determines that the voltage VE is greater than the second pre-compression and is over-compressed (this embodiment is set to 4V), the operational amplifier 3〇4 outputs low power = V-pass PMOS transistor Q4, at this time the system voltage SB5V-IN will be turned on to the first power terminal 〇UT1 to generate the standby voltage sb5V. Since the standby voltage SB3V is Since the standby voltage SB5V is converted, the standby power SB3V also rises to the corresponding voltage value 0 as the voltage SB5V rises. From the above, the second comparison unit 204 rises to the first voltage at the system voltage B^vm. The first pair of power-supply terminals 〇υτι and the first discharge, avoiding the wrong voltage level, causing the back-end voltage to rise to the second preset unit 204, the charging switch unit 106 is turned on, and the operation is performed to generate the standby voltage. SB5V, SB3V. via The voltage (four) circuit of this embodiment accelerates the voltage level of the power supply terminal to affect the normal operation of the system chip. In addition, since the voltage VE is judged, the PMOS transistor 〇4 0 _ Μ 升 ] 弟 弟 预 预0 £ Q之 is off, standby voltage SB5V, 14 201116987 2υυδ-ζ^5 32300twf.doc/n SB3 will not increase with system 虔 SB5V coffee SBW, SB3 load in system voltage sb5vJ^ less standby power The power of dust. In other words, the power consumption created in the room can be reduced. In summary, the present invention utilizes the comparison result of the first preset power plant (4) of the control list to pre-discharge two S = voltage and row, and the voltage of the second pre-power The terminal supplies power to the power supply terminal, so that the supply voltage is fully discharged and then supplied with power, thereby avoiding abnormalities in components related to the standby voltage of the standby motherboard t. Although the present invention has been disclosed in the above embodiments, the present invention has the ordinary knowledge in the art, and within the spirit and scope of the present invention, when some modifications and scope of protection can be made, The definition of the scope of the patent application is ^ [simplified description of the diagram]. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a diagram showing a power supply level system of a computer in accordance with an embodiment of the present invention. 2 is a block diagram of a power supply control circuit in accordance with another embodiment of the present invention. FIG. 3 is a block diagram of a power supply control circuit in accordance with another embodiment of the present invention. Fig. 4 is a timing chart showing the voltage change of the power supply control circuit in accordance with the embodiment of Fig. 3. 15 201116987 2008-235 32300twf.doc/n [Main component symbol description] 100: power supply control circuit 102: control unit 104: first discharge switch unit 106: power supply switch unit 108: power adapter 110, 112: voltage conversion circuit 114: host system 116: second discharge. electric switch unit 202, 204, 206: comparison unit 210: delay unit 208: push-pull circuit 302 to 306: operational amplifiers R1 to R9: resistors SIU, SR2: dummy load VBAT: battery Voltage D1: Diode C: Capacitor R9: Resistance·
Ml : NMOS電晶體 Q1~Q4 : PMOS 電晶體 VE :判斷電壓 SB5V-IN:系統電壓 SB5V、SB3V :待機電壓 OUT1:第一電源端 OUT2 :第二電源端 GND :接地 16Ml : NMOS transistor Q1~Q4 : PMOS transistor VE : Judgment voltage SB5V-IN: System voltage SB5V, SB3V : Standby voltage OUT1: First power terminal OUT2 : Second power terminal GND : Ground 16