TW201114065A - Group III nitride semiconductor light emitting element, production method thereof, and lamp - Google Patents

Group III nitride semiconductor light emitting element, production method thereof, and lamp Download PDF

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TW201114065A
TW201114065A TW99105986A TW99105986A TW201114065A TW 201114065 A TW201114065 A TW 201114065A TW 99105986 A TW99105986 A TW 99105986A TW 99105986 A TW99105986 A TW 99105986A TW 201114065 A TW201114065 A TW 201114065A
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layer
light
semiconductor layer
type semiconductor
electrode
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TW99105986A
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Chinese (zh)
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Daisuke Hiraiwa
Hironao Shinohara
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Showa Denko Kk
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Led Devices (AREA)

Abstract

Such a Group III nitride semiconductor light emitting is so configured that a semiconductor layer (20) consisting of a n-type semiconductor layer (4), a light emitting layer (5) and a p-type semiconductor layer (6) laminated sequentially is formed on a ground layer (3) formed on a substrate (11), a translucent electrode (7) is formed on the p-type semiconductor layer (6), at least a part of the p-type semiconductor layer (6) is provided with an insulator layer (15), the translucent electrode (7) covers the insulator layer (15), in the surface (7a) of the translucent electrode (7), the positive bonding pad (8) is disposed on a portion A above the insulator layer (15) provided on the p-type semiconductor layer (6), and the sheet resistance of the translucent electrode (7) is lower than the sheet resistance of the n-type semiconductor layer (4).

Description

201114065 六、發明說明： 【發明所屬之技術領域】 本發明係關於具有發光二極體（LED )構造的三族氮 化物半導體發光元件及其製造方法、以及燈。 本申請案係基於在2009年3月2日於日本申請之特願 2009-04 8239號及在2010年2月26日於日本申請之特願 20 10-42 485號而主張優先權，在此引用其內容。 【先前技術】 近年來，作爲發出短波長光的發光元件用的半導體材 料’三族氮化物半導體正受到注目。三族氮化物半導體， 係以通式 AlxGaylruN (O^xSl、OSySl、OSzSl、x + y + z = l)來表示，在由以藍寶石單結晶爲代表之各種氧化物或 三五族化合物所構成之基板上，利用有機金屬化學氣相成 長法（MOCVD法）及分子束磊晶法（MBE法）等來形成。 在使用了三族氮化物半導體的一般發光元件中，將由 三族氮化物半導體所構成之η型半導體層、發光層及p型 半導體層，依此順序積層在藍寶石單結晶基板上。因爲藍 寶石基板爲絕緣體，所以一般而言，該元件構造係使將已 形成在Ρ型半導體層上的正極、及已形成在η型半導體層 上的負極存在於同一面上的構造。對此種三族氮化物半導 體發光元件而言，有以下2種類：在正極使用透光性電極 而從Ρ型半導體側取出光之面上（face-up)方式、及在正 極使用Ag等之高反射膜而從藍寶石基板側取出光之覆晶 (flip-chip)方式。 201114065 使用外部量子效率作爲此種發光元件的輸出指 外部量子效率高的話，便能稱爲高輸出的發光元件 量子效率是以內部量子效率和光取出效率的乘積來 又’內部量子效率係指注入至元件的電流能量 層轉換爲光的比例。另一方面，光取出效率係指在 所發生的光當中能取出至發光元件外部之光的比例 因此，對於使外部量子效率提高，除了改善在 的發光效率以外，也必須改善光取出效率。 爲了改善光取出效率，主要有2個方法。一方 因形成在光取出面的電極等所造成的光吸收降低。 法爲使因發光元件與外部媒體的折射率差異所產生 發光元件內部的光降低。 在此，作爲具有上述組成的氮化鎵系化合物半 件的特性，可舉出朝橫方向擴散的電流是小的。因 流只會注入至電極正下方的半導體，在發光層發出 被電極遮蔽而不會被取出至外部。因此，在這種發 中，通常使用透光性電極，通過該透光性電極而取 過去，對於透光性電極，係使用作成爲將Nii 氧化物、及作爲接觸金屬的Au等組合之層構造者等 導電材料。又，近年來，係作成如下的構成：採用 用ITO等導電性更高的透光性氧化物來將接觸金屬 極力減薄而提高透光性的層構造者，作爲透光性電 效率良好地將來自發光層的光取出至外部》 標。該 。外部 表示。 在發光 發光層 〇 發光層 法爲使 另一方 之封入 導體元 此，電 的光會 光元件 出光。 t Co等 周知的 藉由使 的膜厚 極，能 201114065 又，在過去的發光元件中，爲了獲得高發光輝度’而 要求不僅電極正下方均勻地發光且整體發光層（半導體層） 亦均勻地發光。然而，在半導體層上具備透光性電極’在 其上具備接合墊電極所構成之發光元件中，因爲透光性電 極之朝橫方向擴散的電流小，所以與上述同樣地，造成電 流集中於接合墊電極的正下方。因此，由發光層所產生的 發光作用，與上述同樣地，會集中於接合墊電極的正下方， 恐有發光效率低落而成爲低輝度者之虞。 在此，在具備有如上述的透光性電極所構成之發光元 件中，爲了抑制電流朝接合墊電極正下方集中，而提案將 絕緣層設置在接合墊電極正下方（例如，參照專利文獻1、 2)。在專利文獻1、2所記載之發光元件中，藉由設置上 述構成的絕緣層，可有效地促進電流朝透光性電極的橫方 向擴散，提髙發光效率。然而，在專利文獻1、2中，有在 P側的接合墊電極附近發光會變強，發光效率卻未必會升 高的問題。 [先前技術文獻] [專利文獻] [專利文獻1]日本專利第384 1460號公報 [專利文獻2]特開2008-192710號公報 【發明內容】 [發明所要解決的問題] 本發明係有鑑於上述課題而開發者，目的爲提供一種 201114065 其可 導體 生的 出效 發光 效率 述三 完成 成於 積層 在目U :在 前述 電極 層的 述η 具有高外部量子效率的三族氮化物半導體發光元件， 抑制電流在p側接合墊電極正下方之透光性電極及半 層集中而具有優良的發光效率，同時抑制由電極所產 光吸收及多重反射所造成的損失而具有優良的光取 率。 又，本發明之目的爲提供一種三族氮化物半導體 元件之製造方法，其可製造如上述之具有優良的發光 及光取出效率的發光元件。 再者，本發明之目的爲提供一種燈，其係使用上 族氮化物半導體發光元件所構成，且發光特性優良。 [用以解決課題的手段] 本案發明人爲了解決上述問題而致力檢討，結果 了本發明。即，本發明係有關於以下者。 [1] —種三族氮化物半導體發光元件，其係在已形 基板上之單結晶三族氮化物半導體層上，形成有依序 η型半導體層、發光層及p型半導體層的半導體層， 述Ρ型半導體層上形成透光性電極所構成；其特徵爲 前述Ρ型半導體層上的至少一部分具備絕緣層，同時 透光性電極係形成爲覆蓋前述絕緣層；在前述透光性 的表面中，在前述ρ型半導體層上所具備之前述絕緣 上方設置正極接合墊；前述透光性電極之片電阻比前 型半導體層之片電阻還低。 [2]如上述[1]所記載之三族氮化物半導體發光元件，其 201114065 特徵爲：前述透光性電極之片電阻爲15 型半導體層之片電阻爲20 Ω/□以下。 [3]如上述[1]或[2]所記載之三族氮 件，其特徵爲：使前述透光性電極表面 凹凸形狀。 [4 ]如上述[1 ]至[3 ]中任一項所記載 體發光元件，其特徵爲：前述透光性電 氧化姻錫（ITO: Indium Tin Oxide)、氧化 Zinc Oxide)、氧化銦鎵（IGO: Indium 氧化姻姉（ICO : Indium Cerium Oxide) (TiCh)所構成之群組的至少1種。 [5 ]如上述[1 ]至[4 ]中任一項所記載 體發光元件，其特徵爲：前述絕緣層爲 所構成。 [6]—種三族氮化物半導體發光元件 備：晶晶製程，係在基板上形成單結晶 體層；半導體層形成製程，係在前述三 上依序積層η型半導體層、發光層及p 半導體層；及透光性電極形成製程，係 層上形成透光性電極；其特徵爲：前述 程係在將絕緣層形成於前述Ρ型半導體 後，以覆蓋前述絕緣層的方式將前述透 述Ρ型半導體層上；具備有正極形成製 Ω /□以下，前述η 化物半導體發光元 的至少一部分成爲 之三族氮化物半導 極係使用選自於;由 銦鋅（IZO : Indium Gallium Oxide )、 、及導電性氧化鈦 之三族氮化物半導 由氧化矽（SiCh ) 之製造方法，其具 的三族氮化物半導 族氮化物半導體層 型半導體層而形成 在前述P型半導體 透光性電極形成製 層上的至少一部分 光性電極形成在前 程，係在前述透光 201114065 性電極形成製程之後，在前述透光性電極的表面中，在已 形成於前述p型半導體層上之前述絕緣層上方形成正極接 合墊；進一步地，前述透光性電極形成製程係以使前述透 光性電極之片電阻比前述η型半導體層之片電阻還低的方 式形成前述透光性電極。 [7] 如上述[6]所記載之三族氮化物半導體發光元件之 製造方法，其特徵爲：前述透光性電極形成製程係以使片 電阻成爲15Ω/□以下之方式形成前述透光性電極，前述半 導體層形成製程係以使片電阻成爲20 Ω /□以下之方式形 成前述η型半導體層。 [8] 如上述[6]或[7]中任一項所記載之三族氮化物半導 體發光元件之製造方法，其特徵爲：前述透光性電極形成 製程係在前述透光性電極表面的至少一部分形成凹凸形 狀。 [9] 如上述[6]至[8]中任一項所記載之三族氮化物半導 體發光元件之製造方法，其特徵爲：前述透光性電極形成 製程’係使用選自於由氧化姻錫（ITO: Indium Tin Oxide)、 氧化銦鋅（IZO: Indium Zinc Oxide)、氧化銦鎵（IGO: Indium Gallium Oxide)、氧化銦铈（ICO: Indium Cerium Oxide)、及導電性氧化鈦（Ti〇2)所構成之群組的至少i 種來作爲形成前述透光性電極的材料。 [10] 如上述[6]至[9]中任一項所記載之三族氮化物半導 體發光元件之製造方法，其特徵爲：前述透光性電極形成 201114065 製程係使用氧化矽（SiCh )作爲形成前述絕緣層的材料。 [11]一種燈，係使用上述[1]至[5]中任一項所記載之三 族氮化物半導體發光元件所構成。 [發明的效果] 根據本發明的三族氮化物半導體發光元件，因爲在已 形成於基板上的單結晶三族氮化物半導體層上，形成依序 積層：η型半導體層、發光層及p型半導體層的半導體層， 在ρ型半導體層上形成透光性電極而構成，進一步地，在 Ρ型半導體層上之至少一部分具備絕緣層同時覆蓋絕緣層 地形成透光性電極，在透光性電極的表面中，在ρ型半導 體層上所具備i絕緣層上方設置正極接合墊，所以能抑制 電流集中在透光性電極及半導體層之對應於正極接合墊的 位置，整體元件更均句地發光，藉以提高發光效率。又， 進一步地，因爲將透光性電極的片電阻構成爲比η型半導 體層的片電阻還低，所以能抑制由設置於透光性電極上之 正極接合墊所產生的光吸收及多重反射所造成的損失，而 提高光取出效率。因此，可提供具有優良的發光效率及光 取出效率、具備高外部量子效率的三族氮化物半導體發光 元件。 又，根據本發明的三族氮化物半導體發光元件之製造 方法’因爲是具備：磊晶製程，係在基板上形成單結晶的 三族氮化物半導體層；半導體層形成製程，係在三族氮化 物半導體層上依序積層：η型半導體層、發光層及ρ型半 -10- 201114065 導體層而形成半導體層；及透光性電極形成製程，係在P 型半導體層上形成透光性電極；透光性電極形成製程係在 將絕緣層形成於p型半導體層上的至少一部分後，以覆蓋 絕緣層的方式將透光性電極形成在p型半導體層上；具備 有正極形成製程，係在透光性電極形成製程之後，在透光 性電極的表面中，在已形成於p型半導體層上之絕緣層上 方形成正極接合墊；進一步地，透光性電極形成製程係以 使透光性電極之片電阻比η型半導體層之片電阻還低的方 式形成透光性電極的方法，所以能製造如上述的具有優良 的發光效率及光取出效率、具備高外部量子效率的三族氮 化物半導體發光元件。 再者，本發明的燈，因爲是使用本發明的三族氮化物 半導體發光元件所構成者，所以會成爲具有優良的發光特 性者。 【實施方式】 以下，就本發明之三族氮化物半導體發光元件（以下， 有簡稱爲發光元件的情況）及其製造方法，以及燈的一實 施形態，一邊適宜地參照第1圖至第7圖一邊說明。 [三族氮化物半導體發光元件（發光元件）] 本發明之發光元件1，係如第1圖及第2圖所示之一 例，槪略構成爲：在已形成於基板11的主面11a上之單結 晶的基底層（三族氮化物半導體層）3上，形成依序積層 有η型半導體層4、發光層5及p型半導體層6的半導體層 -11- 201114065 20，在p型半導體層6上形成透光性電極7所構成，在p 型半導體層6上的至少一部分具備絕緣層15，同時透光性 電極7係形成爲覆蓋絕緣層15。又，第1圖及第2圖所示 之例的發光元件1係作成透光性電極7之片電阻比η型半 導體層4之片電阻還低的構成者。又，在圖示例中，在基 板11與基底層3之間設置緩衝層2，同時在透光性電極7 上具備正極接合墊8，在經除去一部分半導體層20而露出 的η型半導體層4具備有負極接合墊9。又，圖示例的發光 元件1，係將其平面形狀作成正極接合墊8與負極接合墊9 分開的方向，即，第2圖中晶片長度尺寸（L)比晶片寬度 尺寸（W)還長，而構成爲略長方形狀。又，在本發明中， 在第2圖所示的平面形狀中，能將晶片寬度尺寸W :晶片 長度尺寸 L 定爲 1 : 1 ( L/W = 1 ) ~1 : 2.7 ( L/W = 2.7 )的範 圍，構成爲正方形狀晶片或長方形狀晶片。 本實施形態所說明的例之發光元件1，係利用上述構 成來構成爲如圖示例的發光二極體（LED )。 以下，就發光元件1的積層構造詳細說明。 『基板』（基板的材料） 在本實施形態的發光元件中，作爲能用於如上述的基 板11的材料，只要是可在表面上磊晶成長三族氮化物半導 體結晶之基板材料即可，並無特別限定，能選擇各種材料 來使用。可舉出例如，藍寶石、SiC、矽、氧化鋅、氧化鎂、 氧化錳、氧化锆、氧化锰鋅鐵、氧化鎂鋁、硼化鉻、氧化 -12- 201114065 鎵、氧化銦、氧化鋰鎵、氧化鋰鋁、氧化銨鎵、氧化鑭緦 鋁鉬、氧化總鉬、氧化欽、鈴、鶴、鉬等。又’在上述各 基板材料之中’特佳爲使用藍寶石。又’較佳爲在由基板 11(由藍寶石所構成）的C面所構成的主面lla上’形成 稍後詳述的緩衝層2。 又，上述各基板材料之中，在使用已知會因在高溫下 接觸到氨而引起化學變性的氧化物基板及金層基板等’在 不使用氨的情況下將緩衝層2成膜，同時以使用氨的方法 來將基底層3成膜時，因爲緩衝層2也發揮了塗層（coat layer)的作用，所以在防止基板11的化學性變質方面是有 效的。 又，在利用濺鍍法形成緩衝層2的情況，因爲可將基 板11的溫度抑制爲較低，所以即使是在使用由具有會在高 溫下分解的性質之材料所構成的基板11時，亦可在不會對 基板11造成損傷的情況下將各層成膜至基板上。 『緩衝層』 在本發明，較佳爲在基板11的主面lla上形成緩衝層 2，在其上形成基底層3。緩衝層2，係例如以AlxGa,.xN ( 0 S X S 1 )的組成積層在基板1 1上，例如，能藉由以電漿來 使含五族元素的氣體及金屬材料活性化而反應的反應性濺 鍍法來形成。如本實施形態，藉由使用已電漿化的金屬原 料的方法來成膜的膜有容易獲得配向的作用。 緩衝層2,有緩和基板11與基底層3晶格常數的差異， -13- 201114065 容易發揮在基板11的c面上形成已進行c軸配向的單結晶 層的功能。因此’若將單結晶的三族氮化物半導體層（基 底層3)積層在緩衝層2上，便能形成結晶性更優良的基 底層3。又’在本實施形態中，亦可作成省略緩衝層2的 構成。 在本實施形態中，緩衝層2較佳爲由上述AlxGa,.xN(0 SxSl)的組成所構成，更佳爲A1N » —般而言，作爲積 層在基板上的緩衝層’較佳爲作成含有A1的組成，只要是 可以一般式AlxGa，_xN (OSxSl)表示的三族氮化物化合 物’便能使用任何材料，再者，亦能作成含有作爲五族的 As及P的組成。其中’在將緩衝層2作成含A1的組成之 情況’較佳爲作成GaAIN，在此情況，更佳爲使A1的組成 爲50%以上。又，緩衝層2最佳爲作成由A1N所構成的構 成。又，作爲構成緩衝層2的材料，能使用具有與三族氮 化物半導體相同的結晶構造者，較佳爲晶格長度接近構成 後述基底層的三族氮化物半導體者，週期表的三a族元素 的氮化物是特別合適的。 形成緩衝層2的三族氮化物的結晶，具有六方晶系的 結晶構造’能藉由控制成膜條件來作成單結晶膜。又，三 族氮化物的結晶，可藉由控制上述成膜條件來作成由以六 角柱爲基本的集合組織（texture )所構成的柱狀結晶（多 結晶）。又，在此說明的柱狀結晶，係指在與鄰接的結晶 粒之間形成結晶粒界而分隔，其本身的縱剖面形狀成爲柱 -14- 201114065 狀的結晶。 從緩衝功能的觀點來看，緩衝層2較佳爲單結晶構 造。如上述，三族氮化物的結晶具有六方晶系的結晶，形 成以六角柱爲基本的組織。三族氮化物的結晶，藉由控制 成膜條件等，不只可使在上方向上成長的結晶成膜成爲可 能，亦可使在面內方向上成長的結晶成膜成爲可能。將具 有此種單結晶構造的緩衝層2成膜在基板11上時，由於緩 衝層2的緩衝功能有效地發揮作用，所以其上所成膜的三 族氮化物半導體之層會成爲具有良好配向性及結晶性的結 晶膜。 緩衝層2的膜厚較佳係定爲0.01~0.的範圍。藉由 將緩衝層2的膜厚定爲此範圍，可製得具有良好配向性， 在將由三族氮化物半導體所構成的各層成膜在緩衝層2上 時，可有效地發揮作爲塗層的功能之緩衝層2。若緩衝層2 的膜厚低於0.01私m，會有不能獲得作爲上述塗層的充分功 能，又，不能充分獲得緩和基板11與基底層3之間晶格常 數差異之緩衝作用的情況。又，以超過0.5/zm的膜厚形成 緩衝層2時，與緩衝作用及作爲塗層功能沒有變化無關， 成膜處理時間會變長，有生產性降低之虞。又，緩衝層2 的膜厚更佳係定爲0.02-0.1/zm的範圍。 『三族氮化物半導體層（基底層）』 本發明之發光元件1所具備之基底層（三族氮化物半 導體層）3係如上述由三族氮化物半導體所構成，能藉由 -15- 201114065 過去周知的MOCVD法在緩衝層2上進行積層而成膜。 作爲基底層3的材料，雖然能使用例如AlxGayIiwN (OSxSl’0盔 ySl，OSzSl，x+y+z=l)，但是就能 形成結晶性良好的基底層3的觀點來看，更佳爲使用 AUGahN 層（OSySl，較佳爲 OSySO.5，更佳爲 OSyS 0.1)。又，基底層3的材料，如上述，雖然可使用與緩衝 層2不同的材料，但是也可使用與緩衝層2相同的材料。 又，依需要，可將基底層3作成在1χ1017~1χ1019個/ cm 3的範圍內掺雜η型雜質的構成，亦能作成未掺雜（<1 xlO17個/cm 3)的構成，就維持良好結晶性的觀點而言以未 掺雜者爲佳。 在基板11爲導電性的情況，藉由將掺雜劑（dopant) 掺雜至基底層3而作成導電性，能在發光元件的上下形成 電極。另一方面，在將絕緣性材料用於基板11的情況，因 爲須作成將正極及負極的各電極設置在發光元件之相同面 的晶片構造，所以將基底層3作成未掺雜的結晶者，因結 晶性良好，故較佳。作爲掺雜至基底層3的η型雜質’未 特別限定，可舉出例如：Si、Ge及Sn等，較佳可舉出Si 及Ge。 基底層3的厚度，定爲1〜8/zm範圍，就可製得結晶性 良好的基底層的觀點來看是較佳的；定爲2〜5#m範圍’能 縮短成膜所須的製程時間，就生產性提高的觀點來看是更 佳的。 •16- 201114065 『半導體層』 形成在基底層3上的半導體層2〇,係由η型 4、發光層5、及ρ型半導體層所構成，其中各層 氮化物半導體構成。此種半導體層2〇的各層 MOCVD法形成，藉此可製得結晶性更高者。 「η型半導體層」 η型半導體層4通常是由η型接觸層4a及η 4b所構成。又，η型接觸層4a亦可兼作η型包覆 η型接觸層4a爲用以設置負極的層。作爲η 4a，較佳爲由AUGai,層（〇$χ<ι,較佳爲〇gx 佳爲OSxSO.l)所構成。又，較佳爲將η型雜S 型接觸層4a’當含有1x10"〜ixl02〇/cm 3 ，較佳駕 xl019/cm 3濃度的η型雜質時，就維持與負極的良 觸的觀點來看是較佳的。作爲η型雜質，並無特另 可舉出例如Si、Ge及Sn等，較佳爲可舉出Si及 η型接觸層4a的膜厚較佳係定爲〇.5~5//m， 定在l~3/zm的範圍。若η型接觸層4a的膜厚位 圍，可將半導體的結晶性維持爲良好。 較佳爲在η型接觸層4a與發光層5之間設置 層4b。η型包覆層4b爲進行朝發光層5注入載子 子的層。η型包覆層4b可以AlGaN、GaN、GaInNl 又，亦可作成此等構造的異質接合或已積層複數 格構造。在以GalnN形成η型包覆層4b的情況， 半導體層 係由三族 ，可利用 型包覆層 層4 b 〇 型接觸層 S 0.5 ，更 1掺雜至η 1χ1018~1 好歐姆接 丨的限定， Ge。 更佳爲設 在上述範 η型包覆 及封閉載 弄來形成。 次的超晶 作成比發 -17- 201114065 光層5的GalnN的帶隙（band gap)還大當然是較佳的。 雖然η型包覆層4b的膜厚並無特別的限定，但是較佳 爲0.005〜0.5// m，更佳爲0.005〜0.1/zm。η型包覆層4b的 的η型掺雜濃度較佳爲ixi〇i7~ixi〇2°/cm 3，更佳爲 xl019/cm 3。若掺雜濃度在此範圍，則就維持良好結晶性及 降低元件的動作電壓的觀點來看是較佳的。 在本發明之發光元件1中，如後述細節般，係作成使 透光性電極7的片電阻Rsl比η型半導體層4的片電阻RS2 還低的構成。又，在本發明中，較佳係透光性電極7的片 電阻Rsl爲15Ω/□以下，n型半導體層4的片電阻Rs2爲 20 Ω /□以下。如此一來，作爲控制透光性電極7及η型半 導體層4的片電阻的手段，例如有適宜調整膜厚的方法。 在將η型半導體層4的片電阻作成上述的情況，較佳係將 η型半導體層4整體的膜厚定爲4/zm以下，更佳係定爲3 μ m以下》 又，作爲控制η型半導體層4的片電阻Rs2的方法， 亦能以控制Si等η型雜質的掺雜量的方法來進行，藉由將 該掺雜量定爲上述範圍，可將片電阻Rs2控制在所期望的 範圍。 又，在將η型包覆層4b作成含有超晶格構造之層的情 況，省略詳細的圖示，可爲含有將η側第1層及η側第2 層予以積層的構造者，η側第1層爲由具有100埃以下之膜 厚的三族氮化物半導體所構成，η側第2層係由與該η側第 -18- 201114065 1層的組成相異，同時具有100埃以下之膜厚的三族氮化物 半導體所構成。又，η型包覆層4b亦可爲含有將η側第1 層及η側第2層交替地重複積層的構造者。又，較佳地， 可作成將前述η側第1層或η側第2層之任一者連接至發 光層5的構成。 如上述的η側第1層及η側第2層能作成例如含有Α1 的AlGaN系（可簡寫爲AlGaN)、含有In的GalnN系（可 簡寫爲GalnN ) 、GaN的組成。又，η側第1層及η側第2 層，亦可爲GalnN/GaN的交替構造、AlGaN/GaN的交替構 造、GalnN/AlGaN的交替構造、組成相異的GalnN/GalnN 的交替構造（本發明之「組成相異」的說明係指各元素組 成比不同’以下相同）、組成相異的AlGaN/AlGaN的交替 構造。在本發明中，η側第1層及η側第2層較佳爲 GalnN/GaN的交替構造或組成相異的GaInN/GaInN。 上述η側第1層及n側第2層的超晶格層，較佳係分 別爲60埃以下’更佳係分別爲4〇埃以下，最佳係分別爲 10埃〜40埃的範圍。—旦形成超晶格層的η側第1層及η 側第2層的膜厚超過丨〇〇埃，則結晶缺陷便容易侵入而不 佳。 上述η側第1層及η側第2層亦可爲分別經掺雜的構 造’又’亦可爲捧雜構造/未掺雜構造的組合。作爲被掺雜 的雜質’對於上述材料組成能無任何限制地適合使用過去 周知者。例如’作爲η型包覆層，在使用GaInN/GaN的交 -19- 201114065 替構造、或組成相異的GalnN/GalnN的交替構造者的情況 下，適合以Si作爲雜質。又，上述之η側超晶格多層膜’ 即使以GalnN及AlGaN、GaN爲代表的組成相同’也可― 面將掺雜適宜地ON、OFF —面製作。 如上述，利用將η型包覆層4b作成含有超晶格構造的 層構成，可作成發光輸出顯著提升、電氣特性優良的發光 元件1。 「發光層」 作爲積層在η型半導體層上的發光層，可舉出具有單 一量子井構造或多重量子井構造等構造的發光層5。作爲 如第1圖所示的量子井的井層，在作成呈現出藍色發光之 構成的情況，通常使用Ga^IiuN (0<y<0.4)組成之三族 氮化物半導體；在如本發明之呈現綠色發光的井層5b的情 況，可使用0&1.γΙη,Ν(0·07<γ<0.20)等，提高銦的組成 者。 在如本發明之多重量子井構造的發光層5的情況，較 佳爲以上述Gar,InyN作成井層5b，以帶隙能量比井層5b 還大的AhGai.；cN(0Sx<0.3)作爲障壁層5a。又，可將雜 質掺雜至井層5b及障壁層5a，或者，亦可不掺雜。 又’作爲井層5b的膜厚’較佳爲能作成可獲得量子效 果程度的膜厚例如l~l〇nm’就發光輸出的觀點來看更佳爲 作成2~6nm。 「P型半導體層」 -20- 201114065 P型半導體層6，通常是由P型包覆層6a及p型接觸 層6b所構成。又，p型接觸層6b亦可兼作p型包覆層6a。 P型包覆層6a爲將載子封入及注入發光層5的層。作 爲p型包覆層6a的組成，只要是可以帶隙能量比發光層5 大的組成來將載子封入發光層5者，即無特別的限定，較 佳可舉出AhGa^NCiXxSO.O者》若p型包覆層6a由 此種AlGaN所構成，則從將載子封入發光層的觀點來看是 較佳的。p型包覆層6a的膜厚並無特別的限定，較佳爲 l~400nm，更佳爲5~100nm°p型包覆層6a的p型掺雜濃度 較佳爲 Ixl018~lxl021/cm 3，更佳爲 lxl019~lxl〇2°/cm 3。若 p 型掺雜濃度爲上述範圍，便可在不會使結晶性降低的情況 下製得良好的P型結晶。 又，P型包覆層6a亦可作成進行複數次積層的超晶格 構造。 又，在將P型包覆層6a作成含有超晶格構造的情況， 省略詳細的圖示，可爲含有積層有p側第1層及p側第2 層者，該P側第1層係由具有100埃以下之膜厚的三族氮 化物半導體所構成，該p側第2層係由與該p側第1層的 組成相異，同時具有100埃以下之膜厚的三族氮化物半導 體所構成。又，亦可爲含有將p側第1層及p側第2層交 替地重複積層的構造者。 上述的p側第1層及p側第2層亦可爲各自不同的組 成，例如AlGaN、GalnN或GaN中的任一組成，又，亦可 -21- 201114065 爲GalnN/GaN的交替構造、AlGaN/GaN的交替構造、或 GalnN/AlGaN的交替構造。在本發明中，p側第1層及p側 第2層較佳爲AlGaN/AlGaN或AlGaN/GaN的交替構造。 上述P側第1層及P側第2層的超晶格層，較佳係各 自爲60埃以下，更佳係各自爲40埃以下，最佳係各自爲 1 0埃〜40埃的範圍。若形成超晶格層的p側第1層及p側 第2層的膜厚超過1〇〇埃，則會成爲含有較多結晶缺陷的 層，故不佳。 上述P側第1層及P側第2層可爲分別掺雜的構造， 或，亦可爲掺雜/未掺雜構造的組合。作爲被掺雜的雜質， 對於上述材料組成能毫無任何限制地適合使用過去周知 者。例如，作爲p型包覆層，在使用AlGaN/GaN的交替構 造或組成相異的 AlGaN/AlGaN的交替構造者的情況，Mg 適合作爲雜質。又，上述之p側超晶格多層膜，即使以GalnN 及AlGaN、GaN爲代表的組成相同，也可一面將掺雜適宜 地ON、OFF —面製作。 如上述，藉由將p型包覆層6a作成含有超晶格構造的 層構成，可作成使發光輸出顯著提升、電氣特性優良的發 光元件1。 P型接觸層6b爲用以設置正極的層。p型接觸層6b， 較佳爲AlxGa^NCOSxSO.O 。若A1組成爲上述範圍， 則從維持良好的結晶性及與P歐姆電極的良好歐姆接觸的 觀點來看是較佳的。若含有Ixl018~lxl021/cm 3濃度（較佳 -22- 201114065 爲5χ1019〜5xl02°/cm3濃度）的p型雜質（掺雜劑），則從 維持良好的歐姆接觸、防止龜裂（crack)發生、維持良好 的結晶性的觀點來看是較佳的。作爲p型雜質，並無特別 的限定，例如較佳可舉出Mg。p型接觸層6b的膜厚，並無 特別的限定，較佳爲0.01〜0.5//m，更佳爲0.05〜0.2#m。 若P型接觸層6b的膜厚在該範圍，則從發光輸出的觀點來 看是較佳的。 『絕緣層』 在本發明的發光元件中，在P型半導體層6上的至少 —部分，第1圖及第2圖所示之例的發光元件1係在約略 中央附近，具備有由絕緣材料所構成的絕緣層15。又，在 圖示例，絕緣層15係以被透光性電極7覆蓋的方式形成。 作爲絕緣層1 5的材料並無特別的限定，能毫無任何限 制地使用過去周知的絕緣性氧化膜等，其中較佳爲使用氧 化矽（Si〇2)。 過去，形成透光性電極7的導電性薄膜係作成正下方 不具備由絕緣材料所構成的絕緣層15之構成，因爲該導電 性薄膜朝橫方向（膜內方向）的電流擴散比朝縱方向（半 導體層方向）的電流擴散還小，所以容易在形成於其上的 接合墊電極（正極接合墊8)的正下方發生電流集中。因 此，會有使得在發光層5中可獲得發光作用的區域只有接 合墊電極的正下方，從發光元件所取出的光的發光效率降 低而無法獲得所期望的輝度的問題。 -23- 201114065 在本發明，如第1圖及第2圖所示，可藉由 導體層6上具備被透光性電極7覆蓋之上述構成 15’來促進電流在透光性電極7的膜內擴散。即 性電極8及半導體層20中，電流主要擴散至絕緣 對應於正極接合墊8的位置之周邊部。藉此，因 層5的絕緣層15的正下方位置，可抑制發光作用 邊部、及負極接合墊9的周邊部可獲得良好的發 所以從發光元件所取出之光的發光效率得以提升 能實現內部量子效率優良，發光輝度提高的發光 使用第5圖的圖表，說明藉由將絕緣層15設 墊電極（正極接合墊8)的正下方，來獲得抑制 在絕緣層15及對應於正極接合墊8的位置，而將 至其周邊部的效果。第5圖爲顯示發光元件之順[ΐ 及發光輸出（Ρ〇)的關係的圖表，圖表中，曲線（a (c)顯示已設置絕緣層之本發明的發光元件的特 第5圖的圖表中，曲線（d) 、 （e)顯示未具備 發光元件的特性。 如第5圖的圖表所示，可瞭解到設置絕緣層 散至該絕緣層及正極接合墊的周邊部之本發明 件，相較於未設置絕緣層的發光元件，即使是在 (I )相同的情況下也可獲得高發光輸出。認爲這 由在p型半導體層6上設置絕緣層15’而在透光 及半導體層20中，電流可擴散至絕緣層15及對 在P型半 的絕緣層 ，在透光 層1 5、及 爲在發光 ，在其周 光作用， 。因此， 件 1。 置在接合 電流集中 電流擴散 ]電流（I ) )、（b )、 :性。又， 絕緣層的 使電流擴 的發光元 順向電流 是因爲藉 性電極7 應於正極 -24- 201114065 接合墊8的位置A的周邊部，涵蓋該周邊部、設置在η型 半導體層4之負極接合墊9的周邊部都會有效地發光。 又，作爲絕緣層15的厚度，較佳爲50~5 00nm的範圍， 更佳爲100〜300nm的範圍。若絕緣層15的厚度在上述範圍 的話，便能更有效地獲得如上述之抑制電流集中的作用。 又，絕緣層1 5的俯視形狀並無特別的限定，能適宜地 選擇例如約略圓形狀及約略四角形狀等而採用，作爲能將 電流有效地擴散的形狀，可舉出約略圓形等。如此，在將 絕緣層1 5形成爲俯視約略圓形的情況下，較佳爲將其直徑 形成爲比正極接合墊8的直徑大不超過30/zm的範圍，又， 更佳爲大不超過10/zm的範圍。 『透光性電極』 透光性電極7爲由具備導電性的氧化膜等所構成的透 光性電極，能毫無任何限制地使用在該技術領域所通常使 用的透光性材料。作爲此種材料，可舉出含有例如，ITO (In2〇3-Sn〇2 ) 、AZO ( ZnO-AI2O3 ) 、IZO ( Ιη2〇3-ΖηΟ ：氧BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Group III nitride semiconductor light-emitting device having a light-emitting diode (LED) structure, a method of manufacturing the same, and a lamp. The present application claims priority based on Japanese Patent Application No. 2009-04 8239, filed on March 2, 2009, and Japanese Patent Application No. 20 10-42 485, filed on Feb. 26, 2010. Quote its content. [Prior Art] In recent years, a semiconductor material for a light-emitting element that emits short-wavelength light, a Group III nitride semiconductor, has been attracting attention. A Group III nitride semiconductor, represented by the general formula AlxGaylruN (O^xSl, OSySl, OSzSl, x + y + z = l), is composed of various oxides or tri-five compounds represented by single crystals of sapphire The substrate is formed by an organometallic chemical vapor phase growth method (MOCVD method) and a molecular beam epitaxy method (MBE method). In a general light-emitting device using a group III nitride semiconductor, an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer composed of a group III nitride semiconductor are sequentially laminated on a sapphire single crystal substrate. Since the sapphire substrate is an insulator, in general, the element structure is such that a positive electrode formed on the Ρ-type semiconductor layer and a negative electrode formed on the n-type semiconductor layer are present on the same surface. There are two types of such a group III nitride semiconductor light-emitting device: a face-up method in which a light-transmitting electrode is used for a positive electrode and a light is taken out from a 半导体-type semiconductor side, and Ag or the like is used for a positive electrode. A high-reflection film and a flip-chip method in which light is taken out from the sapphire substrate side. 201114065 Using external quantum efficiency as the output of such a light-emitting element means that the external quantum efficiency is high, the quantum efficiency of the light-emitting element, which can be called high output, is the product of internal quantum efficiency and light extraction efficiency, and the internal quantum efficiency is injected into The current energy layer of the component is converted to the proportion of light. On the other hand, the light extraction efficiency means the ratio of light which can be taken out to the outside of the light-emitting element among the generated light. Therefore, in order to improve the external quantum efficiency, it is necessary to improve the light extraction efficiency in addition to the improvement in the luminous efficiency. In order to improve the light extraction efficiency, there are mainly two methods. One of the light absorption due to the electrode or the like formed on the light extraction surface is lowered. The method is to reduce the light inside the light-emitting element due to the difference in refractive index between the light-emitting element and the external medium. Here, as a characteristic of the gallium nitride-based compound half having the above composition, a current which is diffused in the lateral direction is small. Since the current is only injected into the semiconductor directly under the electrode, it is shielded by the electrode in the light-emitting layer and is not taken out to the outside. Therefore, in such a hair, a translucent electrode is usually used, and the translucent electrode is used. For the translucent electrode, a layer in which a Nii oxide and Au as a contact metal are combined is used. A conductive material such as a constructor. In addition, in recent years, a layer structure having a light-transmissive property in which a contact metal is extremely thinned by a light-transmitting oxide having higher conductivity such as ITO is used, and the light-transmitting electrical efficiency is excellent. The light from the luminescent layer is taken out to the external mark. The. External representation. In the illuminating layer 〇 the illuminating layer method is such that the other side encloses the conductor element, and the electric light illuminates the optical element. It is known that t Co and the like have a thick film thickness, and in the conventional light-emitting element, in order to obtain high light-emitting luminance, it is required to uniformly emit light not only directly under the electrode but also in the entire light-emitting layer (semiconductor layer). Glowing. However, in the light-emitting element including the light-transmitting electrode ′ having the bonding pad electrode on the semiconductor layer, since the current which is diffused in the lateral direction of the light-transmitting electrode is small, current is concentrated in the same manner as described above. Just below the bond pad electrode. Therefore, in the same manner as described above, the light-emitting effect by the light-emitting layer is concentrated immediately below the bonding pad electrode, and the light-emitting efficiency is lowered to become a low-intensity one. Here, in the light-emitting element including the light-transmitting electrode as described above, in order to suppress current concentration directly below the bonding pad electrode, it is proposed to provide the insulating layer directly under the bonding pad electrode (for example, refer to Patent Document 1 2). In the light-emitting element described in Patent Documents 1 and 2, by providing the insulating layer having the above-described configuration, it is possible to effectively promote the diffusion of current into the lateral direction of the translucent electrode, thereby improving the luminous efficiency. However, in Patent Documents 1 and 2, there is a problem that the light emission is strong in the vicinity of the bonding pad electrode on the P side, and the luminous efficiency does not necessarily increase. [Prior Art Document] [Patent Document 1] Japanese Patent No. 384 1460 [Patent Document 2] JP-A-2008-192710 SUMMARY OF INVENTION [Problems to be Solved by the Invention] The present invention has been made in view of the above. The developer of the subject aims to provide a kind of emission-generating luminous efficiency of a conductive material in 201114065. The three-layer nitride semiconductor light-emitting device having a high external quantum efficiency in the above-mentioned electrode layer is formed in the layer U. The suppression current concentrates on the translucent electrode and the half layer directly under the p-side bonding pad electrode, and has excellent luminous efficiency, and suppresses loss due to light absorption and multiple reflection by the electrode, and has excellent light extraction rate. Further, an object of the present invention is to provide a method for producing a group III nitride semiconductor device which can produce a light-emitting device having excellent light-emitting and light-removing efficiency as described above. Further, an object of the present invention is to provide a lamp which is formed using an upper nitride semiconductor light-emitting device and which has excellent light-emitting characteristics. [Means for Solving the Problem] The inventors of the present invention have made efforts to review in order to solve the above problems, and as a result, have invented the present invention. That is, the present invention relates to the following. [1] A Group III nitride semiconductor light-emitting device formed on a single-crystal Group III nitride semiconductor layer on a patterned substrate, wherein a semiconductor layer of a sequential n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer is formed And forming a translucent electrode on the semiconductor layer; wherein at least a part of the Ρ-type semiconductor layer is provided with an insulating layer, and the translucent electrode is formed to cover the insulating layer; In the surface, a positive electrode bonding pad is provided above the insulating layer provided on the p-type semiconductor layer; and a sheet resistance of the light transmitting electrode is lower than a sheet resistance of the front type semiconductor layer. [2] The group III nitride semiconductor light-emitting device according to the above [1], wherein the sheet resistance of the light-transmitting electrode is such that the sheet resistance of the 15-type semiconductor layer is 20 Ω/□ or less. [3] The three-group nitrogen member according to the above [1] or [2], wherein the surface of the light-transmitting electrode has an uneven shape. [4] The bulk light-emitting device according to any one of the above [1] to [3] wherein the light-transmitting ITO (Indium Tin Oxide), oxidized Zinc Oxide, or indium gallium oxide (Io): At least one of the groups of the above-mentioned [1] to [4], wherein the bulk light-emitting device according to any one of the above [1] to [4], The invention is characterized in that: the insulating layer is formed. [6] - a group of nitride semiconductor light-emitting devices: a crystal crystal process, forming a single crystal layer on a substrate; a semiconductor layer forming process, sequentially layering on the foregoing three a n-type semiconductor layer, a light-emitting layer, and a p-semiconductor layer; and a translucent electrode forming process, wherein the transmissive electrode is formed on the layer; wherein the process is performed after the insulating layer is formed on the germanium-type semiconductor The insulating layer is formed on the ruthenium-type semiconductor layer; the positive electrode is formed to have a Ω / □ or less, and at least a part of the η semiconductor illuminator is selected from the group III nitride semiconductor; Indium Zinc (IZO : Indium Gallium Oxide ) And a group III nitride semiconductor of conductive titanium oxide is produced by a method of producing yttrium oxide (SiCh) having a group III nitride semiconducting nitride semiconductor layer type semiconductor layer formed on the P-type semiconductor. At least a part of the photoelectrode formed on the electrode formation layer is formed in the front stage, and after the light transmissive 201114065 electrode formation process, the surface of the translucent electrode is formed on the p-type semiconductor layer Further, a positive electrode bonding pad is formed on the insulating layer; and the translucent electrode forming process is such that the translucent electrode is formed such that the sheet resistance of the translucent electrode is lower than the sheet resistance of the n-type semiconductor layer. (7) The method for producing a group III nitride semiconductor light-emitting device according to the above [6], wherein the translucent electrode forming process is such that the sheet resistance is 15 Ω/□ or less to form the translucent electrode. The semiconductor layer forming process is such that the n-type semiconductor layer is formed so that the sheet resistance is 20 Ω /□ or less. [8] As in any of the above [6] or [7] In the method for producing a group III nitride semiconductor light-emitting device, the translucent electrode formation process is characterized in that at least a part of the surface of the translucent electrode is formed into a concavo-convex shape. [9] As described above [6] to [ The method for producing a group III nitride semiconductor light-emitting device according to any one of the preceding claims, wherein the light-transmitting electrode formation process is selected from the group consisting of oxidized by ITO (Indium Tin Oxide). At least i of a group consisting of Indium Zinc Oxide, Indium Gallium Oxide, Indium Cerium Oxide, and Conductive Titanium Dioxide It is used as a material for forming the above-mentioned translucent electrode. [10] The method for producing a group III nitride semiconductor light-emitting device according to any one of the above [6] to [9], wherein the translucent electrode formation 201114065 process uses yttrium oxide (SiCh) as a method The material of the foregoing insulating layer is formed. [11] A lamp comprising the group III nitride semiconductor light-emitting device according to any one of the above [1] to [5]. [Effects of the Invention] According to the group III nitride semiconductor light-emitting device of the present invention, since a sequential layer is formed on the single-crystal Group III nitride semiconductor layer which has been formed on the substrate: an n-type semiconductor layer, a light-emitting layer, and a p-type The semiconductor layer of the semiconductor layer is formed by forming a translucent electrode on the p-type semiconductor layer. Further, at least a part of the germanium-type semiconductor layer is provided with an insulating layer and covers the insulating layer to form a translucent electrode. In the surface of the electrode, since the positive electrode bonding pad is provided above the i insulating layer provided on the p-type semiconductor layer, it is possible to suppress current from being concentrated on the position of the translucent electrode and the semiconductor layer corresponding to the positive electrode bonding pad, and the overall element is more uniform. Luminescence, in order to improve luminous efficiency. Further, since the sheet resistance of the translucent electrode is made lower than the sheet resistance of the n-type semiconductor layer, light absorption and multiple reflection by the positive electrode bonding pad provided on the translucent electrode can be suppressed. The resulting loss increases the efficiency of light extraction. Therefore, a Group III nitride semiconductor light-emitting device having excellent luminous efficiency and light extraction efficiency and having high external quantum efficiency can be provided. Further, the method for producing a group III nitride semiconductor light-emitting device according to the present invention includes: an epitaxial process for forming a single-crystal Group III nitride semiconductor layer on a substrate; and a semiconductor layer formation process for a group III nitrogen The semiconductor layer is sequentially laminated: an n-type semiconductor layer, a light-emitting layer, and a p-type semi--10-201114065 conductor layer to form a semiconductor layer; and a transparent electrode forming process for forming a transparent electrode on the P-type semiconductor layer The translucent electrode formation process is characterized in that after the insulating layer is formed on at least a portion of the p-type semiconductor layer, the translucent electrode is formed on the p-type semiconductor layer so as to cover the insulating layer; After the translucent electrode forming process, a positive electrode bonding pad is formed over the insulating layer formed on the p-type semiconductor layer in the surface of the translucent electrode; further, the translucent electrode is formed into a process to make the light transmissive A method of forming a translucent electrode in such a manner that the sheet resistance of the electrode is lower than that of the n-type semiconductor layer, so that it is possible to produce an excellent luminescence effect as described above. And Group III nitride semiconductor light-emitting element light extraction efficiency, with high external quantum efficiency. Further, since the lamp of the present invention is composed of the group III nitride semiconductor light-emitting device of the present invention, it has excellent light-emitting characteristics. [Embodiment] Hereinafter, the group III nitride semiconductor light-emitting device of the present invention (hereinafter, simply referred to as a light-emitting device), a method for manufacturing the same, and an embodiment of a lamp are appropriately referred to FIGS. 1 to 7 The figure shows. [Group III nitride semiconductor light-emitting device (light-emitting device)] The light-emitting device 1 of the present invention is an example of the first embodiment and the second embodiment, and is configured to be formed on the main surface 11a of the substrate 11. On the single crystal base layer (Group III nitride semiconductor layer) 3, a semiconductor layer 11-201114065 20 in which an n-type semiconductor layer 4, a light-emitting layer 5, and a p-type semiconductor layer 6 are sequentially laminated is formed in a p-type semiconductor The translucent electrode 7 is formed on the layer 6, and at least a part of the p-type semiconductor layer 6 is provided with the insulating layer 15, and the translucent electrode 7 is formed to cover the insulating layer 15. Further, in the light-emitting element 1 of the example shown in Fig. 1 and Fig. 2, the sheet resistance of the translucent electrode 7 is lower than the sheet resistance of the n-type semiconductor layer 4. Further, in the illustrated example, the buffer layer 2 is provided between the substrate 11 and the underlying layer 3, and the positive electrode bonding pad 8 is provided on the translucent electrode 7, and the n-type semiconductor layer exposed by removing a part of the semiconductor layer 20 is provided. 4 is provided with a negative electrode bonding pad 9. Further, the light-emitting element 1 of the illustrated example has its planar shape formed in a direction in which the positive electrode bonding pad 8 and the negative electrode bonding pad 9 are separated, that is, the wafer length dimension (L) in FIG. 2 is longer than the wafer width dimension (W). And formed into a slightly rectangular shape. Further, in the present invention, in the planar shape shown in Fig. 2, the wafer width dimension W: wafer length dimension L can be set to 1:1 (L/W = 1) ~ 1 : 2.7 (L/W = The range of 2.7) is a square wafer or a rectangular wafer. The light-emitting element 1 of the example described in the embodiment is configured as a light-emitting diode (LED) as shown in the drawing by the above configuration. Hereinafter, the laminated structure of the light-emitting element 1 will be described in detail. "Substrate" (material of the substrate) In the light-emitting device of the present embodiment, as the material which can be used for the substrate 11 as described above, a substrate material which can crystallize and grow a group III nitride semiconductor crystal on the surface may be used. It is not particularly limited, and various materials can be selected for use. For example, sapphire, SiC, bismuth, zinc oxide, magnesium oxide, manganese oxide, zirconium oxide, manganese zinc iron oxide, magnesium aluminum oxide, chromium boride, oxidation-12-201114065 gallium, indium oxide, lithium gallium oxide, Lithium aluminum oxide, gallium ammonium oxide, lanthanum aluminum molybdenum oxide, total molybdenum oxide, oxidized chin, bell, crane, molybdenum, and the like. Further, it is preferable to use sapphire among the above-mentioned respective substrate materials. Further, it is preferable that the buffer layer 2, which will be described in detail later, is formed on the principal surface 11a formed by the C-plane of the substrate 11 (made of sapphire). Further, among the above-mentioned substrate materials, an oxide substrate and a gold layer substrate which are known to be chemically denatured by contact with ammonia at a high temperature are used, and the buffer layer 2 is formed without using ammonia, and When the base layer 3 is formed by a method using ammonia, since the buffer layer 2 also functions as a coat layer, it is effective in preventing chemical deterioration of the substrate 11. Moreover, in the case where the buffer layer 2 is formed by the sputtering method, since the temperature of the substrate 11 can be suppressed to be low, even when the substrate 11 composed of a material having a property of being decomposed at a high temperature is used, Each layer can be formed onto the substrate without causing damage to the substrate 11. "Buffer layer" In the present invention, it is preferable that the buffer layer 2 is formed on the main surface 11a of the substrate 11, and the under layer 3 is formed thereon. The buffer layer 2 is laminated on the substrate 11 by, for example, a composition of AlxGa, .xN (0 SXS 1 ), for example, a reaction which can be activated by activating a gas containing a Group 5 element and a metal material by plasma. Sex sputtering method to form. According to the present embodiment, the film formed by the method using the plasma-formed metal material has an effect of easily obtaining an alignment. The buffer layer 2 has a difference in lattice constant between the substrate 11 and the underlying layer 3, and -13-201114065 easily functions to form a single crystal layer having c-axis alignment on the c-plane of the substrate 11. Therefore, when a single-crystal Group III nitride semiconductor layer (base layer 3) is laminated on the buffer layer 2, a base layer 3 having more excellent crystallinity can be formed. Further, in the present embodiment, the configuration in which the buffer layer 2 is omitted may be employed. In the present embodiment, the buffer layer 2 is preferably composed of the above-described composition of AlxGa, .xN (0 SxSl), and more preferably A1N is generally used as a buffer layer laminated on the substrate. The composition containing A1 can be any material as long as it is a group III nitride compound which can be represented by the general formula AlxGa, _xN (OSxSl), and can also be composed of As and P which are group five. In the case where the buffer layer 2 is formed into a composition containing A1, GaAIN is preferably formed. In this case, the composition of A1 is more preferably 50% or more. Further, the buffer layer 2 is preferably formed of A1N. Further, as the material constituting the buffer layer 2, a crystal structure having the same crystal structure as the group III nitride semiconductor can be used, and it is preferable that the lattice length is close to that of the group III nitride semiconductor constituting the underlayer described later, and the three-group a of the periodic table. Nitrides of the elements are particularly suitable. The crystal of the group III nitride which forms the buffer layer 2 has a hexagonal crystal structure. The single crystal film can be formed by controlling the film formation conditions. Further, the crystal of the group III nitride can be formed into a columnar crystal (polycrystal) composed of a hexagonal column-based aggregate texture by controlling the film formation conditions. In addition, the columnar crystal described herein means that a crystal grain boundary is formed between adjacent crystal grains, and the vertical cross-sectional shape thereof is a column-shaped structure of the column -14-201114065. From the viewpoint of the buffer function, the buffer layer 2 is preferably of a single crystal structure. As described above, the crystal of the group III nitride has hexagonal crystals, and forms a structure based on a hexagonal column. By controlling the film formation conditions and the like, it is possible to form not only a crystal film which grows in the upper direction but also a crystal film which grows in the in-plane direction. When the buffer layer 2 having such a single crystal structure is formed on the substrate 11, since the buffer function of the buffer layer 2 functions effectively, the layer of the group III nitride semiconductor formed thereon becomes a good alignment. Sexual and crystalline crystalline film. The film thickness of the buffer layer 2 is preferably in the range of 0.01 to 0. By setting the film thickness of the buffer layer 2 to this range, it is possible to obtain a good alignment property, and when each layer composed of a group III nitride semiconductor is formed on the buffer layer 2, it can be effectively exhibited as a coating layer. Functional buffer layer 2. If the film thickness of the buffer layer 2 is less than 0.01 m, a sufficient function as the above coating layer may not be obtained, and a buffering action for alleviating the difference in lattice constant between the substrate 11 and the underlayer 3 may not be sufficiently obtained. Further, when the buffer layer 2 is formed with a film thickness of more than 0.5/zm, the film formation treatment time is prolonged regardless of the buffering action and the function as the coating layer, and the productivity is lowered. Further, the film thickness of the buffer layer 2 is preferably in the range of 0.02 to 0.1/zm. "Group III nitride semiconductor layer (base layer)" The underlying layer (Group III nitride semiconductor layer) 3 included in the light-emitting element 1 of the present invention is composed of the above-described group III nitride semiconductor, and can be constituted by -15- 201114065 A conventionally known MOCVD method is performed by laminating a film on the buffer layer 2. As the material of the underlayer 3, for example, AlxGayIiwN (OSxSl'0 helmet ySl, OSzSl, x+y+z=1) can be used, but it is more preferable to use a base layer 3 having good crystallinity. AUGahN layer (OSySl, preferably OSySO.5, better OSyS 0.1). Further, as the material of the underlayer 3, as described above, a material different from that of the buffer layer 2 may be used, but the same material as that of the buffer layer 2 may be used. Further, if necessary, the underlayer 3 may be formed by doping n-type impurities in the range of 1 χ 1017 to 1 1019 / cm 3 , and may be made undoped ( The structure of <1 x lO17 / cm 3) is preferably undoped from the viewpoint of maintaining good crystallinity. In the case where the substrate 11 is electrically conductive, conductivity is formed by doping a dopant onto the underlayer 3, whereby an electrode can be formed on the upper and lower sides of the light-emitting element. On the other hand, in the case where an insulating material is used for the substrate 11, since the wafer structure in which the respective electrodes of the positive electrode and the negative electrode are provided on the same surface of the light-emitting element is required, the underlayer 3 is made into an undoped crystal. It is preferred because of its good crystallinity. The n-type impurity 'doped to the underlayer 3 is not particularly limited, and examples thereof include Si, Ge, and Sn, and preferably Si and Ge. The thickness of the underlayer 3 is set to be in the range of 1 to 8/zm, which is preferable from the viewpoint of obtaining a base layer having good crystallinity; and the range of 2 to 5 #m can shorten the film formation. The process time is better from the standpoint of productivity improvement. 16-201114065 "Semiconductor Layer" The semiconductor layer 2 formed on the underlayer 3 is composed of an n-type 4, a light-emitting layer 5, and a p-type semiconductor layer, each of which is composed of a nitride semiconductor. Each of the layers of the semiconductor layer 2 is formed by MOCVD, whereby crystallinity is higher. "n-type semiconductor layer" The n-type semiconductor layer 4 is usually composed of n-type contact layers 4a and η 4b. Further, the n-type contact layer 4a may also serve as an n-type cladding. The n-type contact layer 4a is a layer for providing a negative electrode. As η 4a, preferably by AUGai, layer (〇$χ <ι, preferably 〇gx is preferably OSxSO.l). Further, it is preferable that the n-type hetero-S-type contact layer 4a' maintains a good contact with the negative electrode when it contains 1x10"~ixl02?/cm3, preferably an n-type impurity having a concentration of xl019/cm3. It is better to see. The n-type impurity is not particularly limited to, for example, Si, Ge, and Sn. Preferably, the thickness of the Si and n-type contact layer 4a is preferably 〇.5 to 5//m. Set in the range of l~3/zm. When the thickness of the n-type contact layer 4a is small, the crystallinity of the semiconductor can be maintained to be good. Preferably, a layer 4b is provided between the n-type contact layer 4a and the light-emitting layer 5. The n-type cladding layer 4b is a layer for injecting carriers into the light-emitting layer 5. The n-type cladding layer 4b may be AlGaN, GaN or GaInNl, or may be a heterojunction or a laminated multi-layer structure of such a structure. In the case where the n-type cladding layer 4b is formed by GalnN, the semiconductor layer is composed of three groups, and the type of cladding layer 4b is used as the contact layer S0.5, and more is doped to η1χ1018~1. Limited, Ge. More preferably, it is formed by the above-described θ-type cladding and closed-loading. It is of course preferable that the secondary supercrystal is larger than the band gap of the GalnN of the light layer 5 of -17-201114065. The film thickness of the n-type cladding layer 4b is not particularly limited, but is preferably 0.005 to 0.5/m, more preferably 0.005 to 0.1/zm. The n-type doping concentration of the n-type cladding layer 4b is preferably ixi〇i7~ixi〇2°/cm 3 , more preferably xl019/cm 3 . When the doping concentration is in this range, it is preferable from the viewpoint of maintaining good crystallinity and lowering the operating voltage of the device. In the light-emitting element 1 of the present invention, the sheet resistance Rs1 of the translucent electrode 7 is made lower than the sheet resistance RS2 of the n-type semiconductor layer 4, as will be described later. Further, in the present invention, it is preferable that the sheet resistance Rs1 of the translucent electrode 7 is 15 Ω/□ or less, and the sheet resistance Rs2 of the n-type semiconductor layer 4 is 20 Ω / □ or less. As a means for controlling the sheet resistance of the translucent electrode 7 and the n-type semiconductor layer 4, for example, there is a method of appropriately adjusting the film thickness. In the case where the sheet resistance of the n-type semiconductor layer 4 is as described above, it is preferable to set the thickness of the entire n-type semiconductor layer 4 to 4/zm or less, more preferably 3 μm or less. The method of controlling the sheet resistance Rs2 of the semiconductor layer 4 can also be carried out by a method of controlling the doping amount of an n-type impurity such as Si. By setting the doping amount to the above range, the sheet resistance Rs2 can be controlled to be desired. The scope. In the case where the n-type cladding layer 4b is formed as a layer including a superlattice structure, detailed description thereof may be omitted, and a structure including a layer on which the n-side first layer and the n-side second layer are laminated may be included. The first layer is composed of a group III nitride semiconductor having a film thickness of 100 angstroms or less, and the second layer of the η side is different from the composition of the first layer of the η side -18 to 201114065, and has a thickness of 100 Å or less. It is composed of a group III nitride semiconductor having a film thickness. Further, the n-type cladding layer 4b may have a structure in which the n-side first layer and the n-side second layer are alternately laminated. Further, preferably, any one of the n-side first layer or the n-side second layer may be connected to the light-emitting layer 5. The η-side first layer and the η-side second layer can have, for example, a composition of AlGaN-based (AlGaN, abbreviated as AlGaN), GalnN-based (which can be abbreviated as GalnN), or GaN. Further, the first layer on the η side and the second layer on the η side may be an alternate structure of GalnN/GaN, an alternate structure of AlGaN/GaN, an alternate structure of GalnN/AlGaN, and an alternate structure of GalnN/GalnN having different compositions (this) The description of the "different composition" of the invention means an alternate structure of AlGaN/AlGaN having different compositional compositions and different compositional compositions. In the present invention, the n-side first layer and the n-side second layer are preferably GalnN/GaN alternating structures or compositions having different compositions of GaInN/GaInN. The above-mentioned n-side first layer and n-side second layer superlattice layer are preferably 60 angstroms or less, respectively, more preferably 4 angstroms or less, and most preferably 10 angstroms to 40 angstroms. When the thickness of the first layer on the η side and the second layer on the η side of the superlattice layer exceeds 丨〇〇, crystal defects are less likely to intrude. The η-side first layer and the η-side second layer may also be a doped structure ‘or’ or a combination of a mixed structure/undoped structure. As the impurity to be doped, it is suitable for use in the above-mentioned material composition without any limitation. For example, in the case of using an n-type cladding layer, an alternating structure of GalnN/GalnN having a different structure or a composition of GaInN/GaN, Si is used as an impurity. Further, the above-described n-side superlattice multilayer film ’ can be formed by appropriately turning ON and OFF the surface even if the composition represented by GalnN, AlGaN, or GaN is the same. As described above, by forming the n-type cladding layer 4b as a layer structure including a superlattice structure, it is possible to produce the light-emitting element 1 in which the light-emitting output is remarkably improved and the electrical characteristics are excellent. "Light-emitting layer" As the light-emitting layer laminated on the n-type semiconductor layer, a light-emitting layer 5 having a structure such as a single quantum well structure or a multiple quantum well structure can be cited. As a well layer of a quantum well as shown in Fig. 1, in the case of a configuration in which blue light is emitted, Ga^IiuN (0 is usually used). <y <0.4) a group of nitride semiconductors; in the case of the well layer 5b exhibiting green luminescence as in the present invention, 0 > 1. γ Ι η, Ν (0·07) <γ <0.20), etc., to improve the composition of indium. In the case of the light-emitting layer 5 of the multiple quantum well structure of the present invention, it is preferable to form the well layer 5b with the above Gar, InyN, and AhGai. with a band gap energy larger than the well layer 5b; cN (0Sx) <0.3) as the barrier layer 5a. Further, impurities may be doped to the well layer 5b and the barrier layer 5a, or may be undoped. Further, the film thickness of the well layer 5b is preferably a film thickness of, for example, 1 to 10 nm, which is a degree of quantum effect, and is preferably 2 to 6 nm from the viewpoint of light emission. "P-type semiconductor layer" -20- 201114065 The P-type semiconductor layer 6 is usually composed of a P-type cladding layer 6a and a p-type contact layer 6b. Further, the p-type contact layer 6b may also serve as the p-type cladding layer 6a. The P-type cladding layer 6a is a layer in which a carrier is enclosed and injected into the light-emitting layer 5. The composition of the p-type cladding layer 6a is not particularly limited as long as it has a composition having a band gap energy larger than that of the light-emitting layer 5, and is preferably a group of AhGa^NCiXxSO.O. When the p-type cladding layer 6a is made of such AlGaN, it is preferable from the viewpoint of encapsulating the carrier into the light-emitting layer. The film thickness of the p-type cladding layer 6a is not particularly limited, but is preferably from 1 to 400 nm, more preferably from 5 to 100 nm. The p-type doping concentration of the p-type cladding layer 6a is preferably Ixl018 to lxl021/cm 3 . More preferably, it is lxl019~lxl〇2°/cm 3. When the p-type doping concentration is in the above range, a good P-type crystal can be obtained without lowering the crystallinity. Further, the P-type cladding layer 6a may be formed as a superlattice structure in which a plurality of layers are laminated. In the case where the P-type cladding layer 6a is formed to include a superlattice structure, a detailed illustration thereof may be omitted, and the P-side first layer and the p-side first layer may be laminated. It is composed of a group III nitride semiconductor having a film thickness of 100 angstroms or less, and the p-side second layer is composed of a group III nitride having a film thickness different from that of the p-side first layer and having a film thickness of 100 angstroms or less. Made up of semiconductors. Further, it is also possible to include a structure in which the p-side first layer and the p-side second layer are alternately laminated. The p-side first layer and the p-side second layer may have different compositions, for example, any of AlGaN, GalnN, or GaN, or -21-201114065 may be an alternate structure of GalnN/GaN, AlGaN. An alternate structure of /GaN or an alternate structure of GalnN/AlGaN. In the present invention, the p-side first layer and the p-side second layer are preferably an alternate structure of AlGaN/AlGaN or AlGaN/GaN. The superlattice layers of the P-side first layer and the P-side second layer are preferably each 60 angstroms or less, more preferably 40 angstroms or less, and most preferably each having a range of 10 angstroms to 40 angstroms. When the thickness of the p-side first layer and the p-side second layer which form the superlattice layer exceeds 1 μA, it is a layer containing a large number of crystal defects, which is not preferable. The P-side first layer and the P-side second layer may be respectively doped structures, or may be a combination of doped/undoped structures. As the impurity to be doped, it is suitable for the above-mentioned material composition to be used without any limitation. For example, as the p-type cladding layer, Mg is suitable as an impurity in the case of using an alternate structure of AlGaN/GaN or an alternate structure of AlGaN/AlGaN having a different composition. Further, the above-described p-side superlattice multilayer film can be produced by appropriately turning ON and OFF the doping even if the composition represented by GalnN, AlGaN, or GaN is the same. As described above, by forming the p-type cladding layer 6a as a layer structure including a superlattice structure, it is possible to produce the light-emitting element 1 which is excellent in light-emitting output and excellent in electrical characteristics. The P-type contact layer 6b is a layer for providing a positive electrode. The p-type contact layer 6b is preferably AlxGa^NCOSxSO.O. When the composition of A1 is in the above range, it is preferable from the viewpoint of maintaining good crystallinity and good ohmic contact with the P ohmic electrode. If a p-type impurity (dopant) having a concentration of Ixl018~lxl021/cm3 (preferably -22-201114065 is 5χ1019~5xl02°/cm3) is used, the ohmic contact is maintained and the crack is prevented from occurring. It is preferable from the viewpoint of maintaining good crystallinity. The p-type impurity is not particularly limited, and for example, Mg is preferable. The film thickness of the p-type contact layer 6b is not particularly limited, but is preferably 0.01 to 0.5/m, more preferably 0.05 to 0.2 m. When the film thickness of the P-type contact layer 6b is in this range, it is preferable from the viewpoint of light-emitting output. In the light-emitting element of the present invention, the light-emitting element 1 of the example shown in Fig. 1 and Fig. 2 is at least partially in the P-type semiconductor layer 6, and is provided with an insulating material. The insulating layer 15 is formed. Further, in the example of the drawing, the insulating layer 15 is formed to be covered by the translucent electrode 7. The material of the insulating layer 15 is not particularly limited, and a conventionally known insulating oxide film or the like can be used without any limitation. Among them, cerium oxide (Si 〇 2) is preferably used. In the past, the conductive thin film forming the translucent electrode 7 is configured such that the insulating layer 15 made of an insulating material is not provided directly below, because the current spreading ratio of the conductive film in the lateral direction (in the film inner direction) is in the longitudinal direction. Since the current diffusion in the (semiconductor layer direction) is small, current concentration is likely to occur right under the bonding pad electrode (positive electrode bonding pad 8) formed thereon. Therefore, there is a problem that the region where the light-emitting effect can be obtained in the light-emitting layer 5 is directly under the pad electrode, and the light-emitting efficiency of the light extracted from the light-emitting element is lowered to obtain the desired luminance. -23- 201114065 In the present invention, as shown in FIG. 1 and FIG. 2, the film of the translucent electrode 7 can be promoted by the above-described configuration 15' including the translucent electrode 7 on the conductor layer 6. Internal diffusion. In the electrode 8 and the semiconductor layer 20, the current mainly diffuses to the peripheral portion of the insulating portion corresponding to the position of the positive electrode bonding pad 8. Thereby, it is possible to suppress the light-emitting side portion and the peripheral portion of the negative electrode bonding pad 9 from being able to obtain a good emission due to the position directly under the insulating layer 15 of the layer 5, so that the light-emitting efficiency of the light extracted from the light-emitting element can be improved. The internal quantum efficiency is excellent, and the light emission is improved. The light emission is improved by using the graph of FIG. 5, and the insulating layer 15 is provided directly under the pad electrode (positive electrode bonding pad 8) to obtain the suppression of the insulating layer 15 and the positive electrode bonding pad. The position of 8 will be the effect to its peripheral part. Fig. 5 is a graph showing the relationship between the illuminating element and the light-emitting output (Ρ〇) of the light-emitting element. In the graph, the curve (a (c) shows the chart of the fifth drawing of the light-emitting element of the present invention in which the insulating layer is provided. In the graphs (d) and (e), the characteristics of the light-emitting element are not provided. As shown in the graph of Fig. 5, it can be understood that the present invention in which the insulating layer is dispersed to the peripheral portion of the insulating layer and the positive electrode bonding pad is known. Compared with a light-emitting element in which an insulating layer is not provided, a high light-emitting output can be obtained even in the case where (I) is the same. It is considered that this is provided by providing an insulating layer 15' on the p-type semiconductor layer 6 in light transmission and semiconductor. In the layer 20, the current can be diffused to the insulating layer 15 and the insulating layer on the P-type half, in the light-transmitting layer 15 and in the light-emitting layer, acting in the peripheral light thereof. Therefore, the device is placed in the junction current concentration. Current diffusion] current (I)), (b), : sex. Further, the forward current of the illuminating element of the insulating layer for expanding the current is because the squeezing electrode 7 is disposed at the peripheral portion of the position A of the bonding pad 8 of the positive electrode-24-201114065, covering the peripheral portion and disposed at the n-type semiconductor layer 4 The peripheral portion of the negative electrode bonding pad 9 is effective to emit light. Further, the thickness of the insulating layer 15 is preferably in the range of 50 to 500 nm, and more preferably in the range of 100 to 300 nm. If the thickness of the insulating layer 15 is within the above range, the effect of suppressing current concentration as described above can be more effectively obtained. In addition, the shape of the insulating layer 15 is not particularly limited, and it can be suitably selected, for example, from a substantially circular shape to a substantially square shape. The shape in which the current can be effectively diffused is, for example, a substantially circular shape. As described above, in the case where the insulating layer 15 is formed in a substantially circular shape in plan view, it is preferable to form the diameter to be larger than the diameter of the positive electrode bonding pad 8 by not more than 30/zm, and more preferably not more than The range of 10/zm. "Translucent electrode" The translucent electrode 7 is a translucent electrode made of a conductive oxide film or the like, and a translucent material which is generally used in the technical field can be used without any limitation. Examples of such a material include ITO (In2〇3-Sn〇2), AZO (ZnO-AI2O3), and IZO (Ιη2〇3-ΖηΟ: oxygen).

化銦鋅；Indium Zinc Oxide ) 、GZO ( ZnO-Ga2〇3 ) 、IGO (In2〇3-Ga2〇3) 、ICO(In2〇3-Ce2〇3)、已掺雜任意雜質元 素的氧化鈦（TiO〇等的材料。又，在該等材料中，針對 氧化鈦，亦可使用將一部分TiCh還原的還原型Ti〇2.x，只 要是導電性者即可。又，作爲掺雜至氧化鈦的材料，可舉 出例如Nb等。 又，在本發明中，更佳爲使用ITO、IZO、IGO、ICO、 -25- 201114065 及導電性氧化鈦中的至少任何1種。 又，作爲形成透光性電極7的方法亦無特別 能使用以在該技術領域所熟知的慣用手段來設置 光性電極7的構造亦能含有過去周知的構造、毫 制地使用任何構造者。又，透光性電極7，也可 緣層15的全面，同時覆蓋p型半導體層6上的大 方式來形成，亦可隔著間隙形成爲格子狀及樹形 在形成透光性電極9後，可施加以合金化及透明 之熱退火，或者亦可不施加熱退火。 在本發明的發光元件中，將透光性電極7 (Rsl )作成比在半導體層20所具備的η型半導 片電阻（Rs2)還低的構成。本案發明人等發現， 透光性電極7與η型半導體層4之各片電阻Rs：l、 係控制成由下式（Rsl < Rs2 )表示的關係，抑制 層20中之對應於正極接合墊8之位置的發光，藉 正極接合墊8所產生的光吸收及多重反射所造成 藉此，可製得光取出效率提升，光取出效率優良 高發光輸出的發光元件1。 針對藉由將透光性電極7的片電阻Rsl及η 層4的片電阻Rs2的關係設成下式（Rsl < RS2) 係而獲得的效果，一邊參照第6圖所示圖表一 下。第6圖爲顯示透光性電極及η型半導體層之 高低關係、與順向電流（I )及發光輸出（ρ〇 )的 的限定， 。又，透 無任何限 以覆蓋絕 致全面之 狀。又， 化爲目的 的片電阻 體層4的 能藉由將 Rs2的關 在半導體 此抑制由 的損失。 ，且具備 型半導體 所示之關 邊說明如 片電阻的 關係之間 -26- 201114065 的相關性的圖表。第6圖的圖表中顯示，曲線（a)是片電 阻關係爲Rsl<Rs2的情況，曲線（b)爲Rsl与Rs2幾乎相 等的情況，曲線（c )爲Rsl > Rs2的情況。 如第6圖的圖表所示，可知片電阻的關係爲Rsl < Rs2 的情況，相較於Rsl与Rs2幾乎相等的情況或Rsl > Rs2的 情況，即使是相同的順向電流（I)也可獲得高發光輸出 (Po)。認爲這是因爲在各片電阻的關係爲Rsl < Rs2.的情 況，主要是，除了正極接合墊8的周邊部以外，在靠近η 側的負極接合墊9的位置之半導體層20會發光，所以能抑 制由正極接合墊8所造成的損失。 在過去的發光元件中，一般認爲將η型半導體層4及 Ρ側的透光性電極7的片電阻作成相同的程度，來使電流 均勻地擴散至透光性電極7及半導體層20是較佳的。然 而，在這樣的構成中，會有導致如上述的發光效率及光取 出效率低落的問題。 在本發明之發光元件1中，如上述，藉由使Ρ側的透 光性電極7的片電阻Rsl低於η型半導體層4的片電阻 Rs2，來控制在對應於正極接合墊8之位置的發光》藉此， 能抑制由正極接合墊8所產生的光吸收及多重反射所造成 的損失，能實現光取出效率高、具備優良的發光強度之發 光元件1 » 又，透光性電極7的片電阻Rsl較佳爲15Ω/□以下。 如上述，使透光性電極7的片電阻Rsl低於η型半導體層4 -27- 201114065 的片電阻Rs2,更佳爲，藉由先將n型半導體層4的片電阻 Rs2定爲20Ω/□以下，再將透光性電極7的片電阻Rsl定 爲15Ω/□以下，可穩定地獲得光取出效率提高的效果。 又，作爲控制透光性電極7的片電阻Rs 1的方法，並 無特別的限定，例如，可藉由將膜厚增厚，或者是，施加 退火處理來降低片電阻Rsl。 作爲透光性電極7的厚度，較佳爲100nm以上。可利 用將透光性電極7定爲上述的厚度，來將片電阻Rsl控制 在15Ω/□以下。又，作爲透光性電極7的最大厚度，考慮 生產性，較佳係定爲600nm以下。 又，在本發明之發光元件1中，以作成在透光性電極 7的表面形成凹凸的構成爲更佳。藉此，源自透光性電極7 的光取出效率提高，同時藉由將凹凸的形狀或尺寸適當 化，可控制透光性電極7的片電阻Rs 1。 『接合墊（電極）』 在本發明的發光元件1中，是將正極接合墊8設置在 透光性電極7上，以接觸於已具備η型半導體層4的η型 接觸層的方式來設置負極接合墊9。 「正極接合墊」 如第1圖及第2圖所示，正極接合墊8是設置在與ρ 型半導體層6及絕緣層15接觸之由透光性導電氧化膜層所 構成的透光性電極7上的一部分。又，圖示例的正極接合 墊8係在透光性電極7的表面7a中’設置在對應於絕緣層 -28- 201114065 15的位置A。 正極接合墊8係爲了與電路基板及導線框等進行電性 連接而設置。作爲正極接合墊，周知者有使用Au、Al、Ni 及Cu等的各種構造，能毫無任何限制地使用該等周知的材 料、構造》 正極接合墊8的厚度，較佳爲在100~ 1 500nm的範圍 內。又，接合墊的特性上，由於厚度越大接合能力越高， 所以正極接合墊8的厚度更佳爲300nm以上。 在本實施形態所說明的發光元件1中，如上述，較佳 爲將正極接合墊8設置在透光性電極7的表面7a中對應於 絕緣層15的位置A。藉此構成，可穩定地獲得如上述之抑 制電流集中的效果、能抑制因在正極接合墊8的光吸收或 多重反射所造成的損失之效果。又，藉由抑制電流集中在 正極接合墊8的正下方，尤其可在以高電流驅動發光元件 的情況下獲得發光輸出（Po)提升的效果。 又，在本實施形態中，亦可構成例如將省略圖示的貫 穿孔設置在透光性電極7的表面7a中對應於絕緣層15的 位置A，透過貫穿孔而與絕緣層15接觸地設置正極接合墊 8。藉由作成此種構成，可獲得正極接合墊8的接合強度提 高的效果》 「負極接合墊」 負極接合墊9係以接觸於半導體層20的η型半導體層 4的方式形成。因此，在形成負極接合墊9之際，將發光 -29- 201114065 層5及p型半導體層6的一部分除去而使η型半導體層4 的η型接觸層露出，在其上形成負極接合墊9。 作爲負極接合墊9，各種組成及構造是周知的，能毫 無任何限制地使用該等周知組成及構造，能以在此技術領 域所熟知的價用手段來設置》 又，上述正極接合墊8及負極接合墊9'在發光元件1 上之形成位置及電極中心間距離，並無特別的限定。儘管 如此，爲了獲得更優良的發光效率及光取出效率，較佳爲 適宜調整各接合墊的形成位置及電極中心間距離。例如， 在構成如第1圖及第2圖所示例的俯視約略長方形的發光 元件1的情況，首先，作成：將負極接合墊9配置在發光 元件1之長邊方向的一端側附近，將正極接合墊8配置在 發光元件1的約略中央附近或長邊方向的另一端側附近的 構成，從使易於獲得如上述的高發光效率及光取出效率的 觀點來看是較佳的。 在本發明，如上述，將透光性電極7的片電阻（Rsl) 作成比設置於半導體層20的η型半導體層4的片電阻（Rs2) 還低的構成。藉此，可抑制在電流從負極接合墊9,透過η 型半導體層4而在發光層5及ρ型半導體層6流通，流入 透光性電極7之際的電流集中，所以可製得發光效率優良 的發光元件1。 『發光元件俯視的晶片尺寸』 在本發明中，就發光元件1俯視的晶片尺寸，即，正 -30- 201114065 極接合墊8與負極接合墊9分開方向的電極分開方向尺寸 (晶片長度尺寸）L、及在與該電極分開方向正交的方向上 的晶片寬度尺寸W，並無特別的限定。例如，可將電極分 開方向尺寸L及晶片寬度尺寸W，作成使俯視的晶片形狀 成爲正方形狀的尺寸比，或是，亦可作成成爲長方形狀的 尺寸比，不論是何種情況，皆可獲得由本發明所產生的發 光效率提高的效果。 儘管如此，爲了使藉由上述構成所獲得的發光效率提 高的效果更加顯著，如第2圖所示的例子，更佳爲將其俯 視形狀作成使電極分開方向尺寸L比晶片寬度尺寸w還長 的約略長方形狀。 如本發明之發光元件1所示，在具備上述構成的絕緣 層15、作成使透光性電極7的片電阻Rsl比η型半導體層 4的片電阻Rs2還低之構成的發光元件的情況下，較佳爲 將其驅動電流（順向電流）IF定爲5 ~30mA程度的範圍來 使用。以此種條件所驅動的發光元件，可用於例如行動電 話或筆記型個人電腦的背光用途等。如此一來，可以較小 的電流來驅動發光元件1，而適合用於上述的背光用途等》 以下就在以上述條件驅動發光元件1的情況下更佳的 晶片尺寸詳細敘述。 本實施形態的發光元件1，藉由將其俯視之電極分開 方向尺寸L定爲400#m以上，更加爲定在400〜550/zm的 範圍，將晶片寬度尺寸W定爲180;/m以上，更加爲定在 -31- 201114065 180〜260 μιη的範圍，可構成爲俯視約略長方形狀。在該情 況，例如，能將俯視之晶片尺寸（WxL )定爲260x550 // m 或 240x400// m、180x400// m 等組合。 藉由將發光元件定爲上述範圍的晶片尺寸及形狀，在 透光性電極7及半導體層20中，電流可有效地擴散至絕緣 層15及對應於正極接合墊8的位置A的周邊部。藉此，使 位置A的周邊部、或設置在η型半導體層4的負極接合墊 9的周邊部有效地進行發光的作用更顯著，可獲得優良的 發光效率。 又’在本實施形態中，將發光元件1的縱橫尺寸，即， 電極分開方向尺寸Lx晶片寬度尺寸W定爲上述範圍後，將 其俯視之面積定爲180,000 jam2程度以下，從使上述發光效 率提高的效果變顯著的觀點來看是較佳的。例如，在晶片 尺寸（WxL)爲280x550ym的情況下，使俯視面積成爲 154,000// m2，在晶片尺寸（WxL)爲260x550// m的情況下 使俯視面積成爲143,OOOym2’在240x400" m的情況下成 爲 96,000vm2’ 在 180x400ym 的情況下成爲 72,000/zm2。 又’在本實施形態中，將發光元件1的電極分開方向 尺寸Lx晶片寬度尺寸W，及俯視面積定爲上述範圍後，將 其俯視之縱橫尺寸比，即（電極分開方向尺寸L)/ (晶片 寬度尺寸W)定爲1.5〜2.7的範圍，從使上述發光效率提高 的效果變顯著的觀點來看是較佳的。例如，在晶片尺寸（W xL)爲260x5 50 a m的情況下，使縱橫尺寸比（l/W)成爲 -32- 201114065 2.12，在 240x400//m 的情況下使（L/W ) = 1.67，又，在 1 80x400 // m 的情況下使（L/W) =2_2。 又，上述正極接合墊8與負極接合墊9的電極中心間 距離係由發光元件1的電極分開方向尺寸L所限制。在本 實施形態中，將發光元件1的俯視尺寸及形狀定爲上述條 件後，將電極中心間距離定爲次式{發光元件的電極分開 方向尺寸Lx0.5~0.75 }的範圍，從使本發明所產生的效果 變顯著，同時不會產生發光不均，可獲得更高的發光效率 的觀點來看是較佳的。 如以上說明，依照本發明的發光元件1，藉由在已形 成於基板11上的單結晶基底層3上，形成已依序積層有η 型半導體層4、發光層5及ρ型半導體層6的半導體層20, 在Ρ型半導體層6上形成透光性電極7，進一步地，在ρ 型半導體層6上的至少一部分設置絕緣層15同時把透光性 電極7形成爲覆蓋絕緣層15，在透光性電極7的表面7a 中，在P型半導體層6上所具備的絕緣層15、在前述絕緣 層上方的位置A設置有正極接合墊8，所以能抑制電流集 中在透光性電極7及半導體層20中對應於正極接合墊8的 位置，整體元件可更均勻地發光，藉此發光效率得以提高。 又，因爲作成使透光性電極7的片電阻Rsl比η型半導體 層4的片電阻RS2還低的構成，所以能抑制由設置在透光 性電極7上的正極接合墊8所產生的光吸收或多重反射所 造成的損失，光取出效率得以提高。因此，可提供發光效 -33- 201114065 率及光取出效率優良，且具備高外部量子效率的發光元件 1 ° 又，可將本發明的發光元件作成如下構成：例如，作 爲基板，如第3圖及第4圖所示，採用具有由平面111(由 (0001) C面所構成）、及複數個凸部H2所構成的主面 110之基板100，進一步地，基底層103係藉由以覆蓋平面 111及凸部112的方式磊晶成長三族氮化物半導體來形成 在主面1 10上。 第3圖及第4圖所示之例的基板11A形成有複數個凸 部112。然後，將在基板100的主面110中未形成凸部112 的部分作成由（ 00 01) C面所構成的平面111»因此，如第 3圖及第4圖所示之例，基板100的主面110係由平面111 (由C面所構成）、及複數個凸部112所構成。 如圖示例所顯示般，凸部11 2係由非平行於C面的表 面112c所構成，C面不會出現在該表面112c。該112，係 基部11 2a的平面形狀呈約略圓形，作成外形爲朝上部漸漸 變小的形狀，將側面1 1 2b作成朝外側彎曲的碗狀（半球狀） 的形狀。又，如後述細節，凸部在由藍寶石以外的氧化物 或氮化物所構成的情況下也可作成圓柱形。又，作爲凸部 112的平面配置，係等間隔地配置成棋盤格狀。 凸部112’係將基部寬度di定在0.05~1.5ym的範圍， 將高度h定在0.05〜l/zm的範圍且爲基部寬度di的1/4以 上，將鄰接之凸部112間的間隔d2定爲基部寬度d,的0.3〜5 -34- 201114065 倍。在此，凸部112的基部寬度ch，係指在凸部112的底 邊（基部12a)之最大寬度的長度。又，鄰接的凸部112 間的間隔d2，係指最接近的凸部1 1 2的基部1 1 2a的邊緣之 間的距離。 鄰接之凸部1 1 2間的間隔d2較佳係定爲基部寬度d,的 0.5 ~5倍。若凸部112間的間隔d2低於基部寬度d,的0.3 倍，則在使構成η型半導體層4(半導體層20)的基底層 103磊晶成長之際，會變得難以促進從由C面所構成之平 面111上開始的磊晶成長，變得難以利用基底層103來把 凸部112完全埋入，而有無法充分獲得基底層103之表面 103a的平坦性的情況。因此，在將形成LED構造的半導體 層的結晶形成於埋覆凸部112的基底層103上的情況，該 結晶必然會形成許多凹陷（Pit )，而造成所形成之三族氮 化物半導體發光元件的輸出及電性特性等惡化。又，若凸 部1 1 2間的間隔ch超過基部寬度ch的5倍，則在使用基板 100來形成三族氮化物半導體發光元件的情況下，在基板 100、與已形成在基板100上的三族氮化物半導體層的界面 之光漫射（diffused reflection)的機會減少，而有變得不 能充分提高光取出效率之虞。 較佳爲將基部寬度ch定爲0.05~1.5μιη。若基部寬度 i低於0.05 vm，則在使用基板100來形成三族氮化物半導 體發光元件的情況下，有無法充分獲得使光漫射的效果之 虞。又，若基部寬度di超過1.5#m，則難以埋覆凸部112 -35- 201114065 地使基底層1 03磊晶成長。又，即使能形成平坦性及結晶 性良好的基底層，基底層與發光層之間的應變（strain)也 會變大，而導致內部量子效率低落。又，若在上述範圍內 將基部寬度cl·作成更小的構成，則可獲得發光元件的發光 輸出進一步提高的效果。又，更佳爲將基部寬度定爲 0.05 〜1 y m。 較佳爲將凸部112的高度h定爲0.05~l//m。若凸部 112的高度h低於0.05//m，則在使用基板100來形成三族 氮化物半導體發光元件的情況下，會有無法充分獲得使光 漫射的效果之虞。又，若凸部112的高度h超過l#m，則 難以埋覆凸部112地使基底層103磊晶成長，有無法充分 獲得基底層103表面的平坦性的情況。 又，較佳爲將凸部112的高度h定爲基部寬度1的1/4 以上。若凸部1 12的高度h低於基部寬度ch的1/4，則在使 用基板100來形成三族氮化物半導體發光元件的情況下有 無法充分獲得使光漫射的效果、及使光取出效率提高的效 果之虞。 又，凸部112的形狀，並未限定於第3圖及第4圖所 示的例，只要是由非平行於C面的表面所構成者，便可爲 任何的形狀。例如，亦可是基部的平面形狀爲約略多角形， 作成外形會朝向上部漸漸變小的形狀，側面1 1 1會朝向外 側彎曲的形狀。又，亦可作成側面爲由外形會朝向上部漸 漸變小的斜面所構成之約略圓錐狀及約略多角錐狀。又， -36- 201114065 側面的傾斜角度亦可爲2段式變化的形狀。又 節’在凸部係由藍寶石以外的氧化物或氮化物 況，亦可作成圓柱形。又，凸部112的平面配 示例限定’可爲等間隔，亦可不爲等間隔。又 的平面配置可爲四角形狀，亦可爲三角形狀， 則（random)。 又，被設置在基板100上的凸部112,可藉 的製造方法，利用蝕刻基板100來形成，但不 例如，亦可在基板上，藉由使形成凸部的其他 基板100的C面上來形成凸部。在基板上，作 部的其他材料沉積的方法，能使用例如，濺鍍沒 CVD法等各種方法。又，作爲形成凸部的材料 用氧化物或氮化物等、具有幾乎與基板的材料 率的材料，在基板爲藍寶石的情況下，能使用 Al2〇3、SiN、ZnO 等。 如上述的一例，因爲藉由將基板100作成 面111及凸部112所構成的主面110之上述構 板100、與後述細節的基底層1〇3的界面隔著 作成凹凸，所以可利用光的漫射來減低光封閉 的內部，能實現光取出效率優良的發光元件。 [三族氮化物半導體發光元件之製造方法] 本發明之三族氮化物半導體發光元件的製 下之方法，其具備：磊晶製程，係在基板u的 ，如後述細 所構成的情 置亦不受圖 ，凸部112 亦可爲無規 由後述細節 限定於此。 材料沉積在 爲使形成凸 5、蒸鍍法、 ，較佳爲使 相等的折射 例如Si〇2、 已具備由平 成，來將基 緩衝層102 至發光元件 造方法係如 主面1 1 a上 -37- 201114065 形成單結晶的基底層（三族氮化物半導體層）3:半導體層 形成製程，係在基底層3上依序積層η型半導體層4、發光 層5及ρ型半導體層6而形成半導體層20;及透光性電極 形成製程，係在Ρ型半導體層6上形成透光性電極7;透光 性電極形成製程係在將絕緣層15形成於ρ型半導體層6上 的至少一部分後，以覆蓋絕緣層15的方式將透光性電極7 形成在Ρ型半導體層6上；具備有正極形成製程，係在透 光性電極形成製程之後，在透光性電極7的表面7a中，在 已形成於P型半導體層6上之絕緣層15上方的位置A形成 正極接合墊8，進一步地，透光性電極形成製程係以使透 光性電極7之片電阻比η型半導體層4之片電阻還低的方 式形成透光性電極7。 以下，針對本發明之製造方法所具備的各製程詳細說 明。 『緩衝層形成製程』 在本發明的製造方法中，較佳爲在磊晶製程之前，具 備有：在基板11的主面11a上形成緩衝層2的緩衝層形成 製程。又，在本發明中，因爲亦可作成省略緩衝層的構造， 所以在該情況下亦可不進行緩衝層形成製程。 「基板之前處理」 在本實施形態中，較佳爲在將基板11導入濺鍍裝置的 腔室內後，形成緩衝層2之前，使用電漿處理所產生的逆 濺鍍等方法來進行前處理。 -38- 201114065 「緩衝層之成膜」 在基板11進行前處理之後，在基板11的主面lla上， 利用反應性濺鍍法，將AUGa^xN (0SXS1)組成的緩衝 層2加以成膜。在利用反應性濺鍍法形成具有單結晶構造 的緩衝層2時，較佳爲將濺鍍裝置之腔室內的氮流量對氮 原料及惰性氣體的流量之比，控制成使氮原料成爲50~ 100 %的範圍，更佳係定爲75%左右。又，在形成具有柱狀結 晶（多結晶）構造的緩衝層2的情況，較佳爲將濺鍍裝置 之腔室內的氮流量對氮原料及惰性氣體的流量之比，控制 成使氮原料成爲1~50%的範圍，更佳係定爲25%左右。 又’緩衝層並不限定於上述的反應性濺鍍法，例如， 亦可使用MOCVD法來形成，但是從製程簡化的觀點來看， 較佳爲使用反應性濺鍍法來形成。 『磊晶製程及半導體層形成製程』 接著，在磊晶製程，在上述緩衝層形成製程之後，如 第1圖所示’在已形成於基板11的主面lla上之緩衝層2 上’使單結晶的三族氮化物半導體磊晶成長，以覆蓋主面 lla的方式來形成基底層（三族氮化物半導體層）ι〇3。 又’在本發明中’在晶晶製程中形成由三族氮化物半 導體所構成的基底層3後’在半導體層形成製程中，在基 底層3上形成由η型半導體層4、發光層5及p型半導體層 6的各層所構成的半導體層20» 又’在本實施形態中，在分別使用三族氮化物半導體 -39- 201114065 來成膜各層的磊晶製程及半導體形成製程中，就兩製程共 通的構成，會省略一部分說明。 在本發明中，在形成基底層3、η型半導體層4、發光 層5及ρ型半導體層6之際氮化鎵系化合物半導體（三族 氮化物半導體）的成長方法並無特別的限定，能適合使用 反應性濺鍍法、MOCVD(有機金屬化學氣相成長法）、HVPE (氫化物氣相成長法）、ΜΒΕ (分子束磊晶法）等來使氮 化物半導體成長之已知的全部方法。該等方法中，利用 MOCVD法時’能使用作爲載氣的氫（η2 )或氮（Ν2 )，作 爲三族原料的Ga源的三甲基鎵（TMG)或三乙基鎵（TEG)， 作爲A1源的三甲基鋁（TMA )或三乙基鋁（TEA )，作爲 In源的三甲基銦（TMI )或三乙基銦（TEI )，作爲五族原 料的N源的氨（NH3)、肼（H)等。又，作爲掺雜劑， 對於η型’能利用作爲Si原料的矽烷（SiH4 )或二矽烷 (ShHe )，作爲Ge原料的鍺烷氣體（GeH4 )及四甲基鍺 ((CiL·) 4Ge)及四乙基鍺（（c2H〇 4Ge)等之有機鍺化 合物。利用MBE法時’也能利用元素狀的鍺來作爲掺雜源。 對於P型，使用例如雙環戊二烯鎂（Cp2Mg )或用雙乙烯環 戊二烯鎂（EtCp2Mg)來作爲Mg原料。 又’上述的氮化鎵系化合物半導體，除了 Al、Ga及In 以外，還可含有其他的三族元素，可依需要，含有Ge、Si、 Mg、Ca、Zn，及Be等掺雜劑元素。再者，不限於意圖添 加的元素，也有根據成膜條件等而有包含：必須含有的雜 -40- 201114065 質、及包含在原料、反應管材質的微量雜質的情況。 本發明中，在上述各方法中，從可獲得結晶性良好的 膜的觀點來看較佳爲使用MOCVD法，在本實施形態中，針 對在磊晶製程及半導體層形成製程中使用MOCVD法的例 子加以說明。 「磊晶製程（基底層的形成）」 在磊晶製程中，如第1圖所示，在已形成於基板1丨上 的緩衝層2上，使用過去周知MOCVD法來形成基底層3。 在本實施形態中，說明使用MOCVD法來形成基底層3 的方法，但是作爲積層基底層3的方法並無特別的限定， 只要是能使差排環化（dislocation loop)產生的結晶成長 方法，便能毫無任何限制地使用。尤其是，由於MOCVD 法及MBE法、VPE法等能使遷移（migration)產生，所以 從可形成結晶性良好的膜的觀點來看是適合的。其中，從 能製得結晶性特別良好的膜的觀點來看，以使用MOCVD 法更爲適合。 較佳爲將成膜基底層3時之基板11的溫度，即基底層 3的成長溫度定爲800°C以上。這是因爲藉由將成膜基底層 3時之基板11的溫度增高來使原子的遷移變得容易，差排 環化容易進行的緣故’更佳爲900°C以上，最佳爲1 000°C 以上。又，由於成膜基底層3時之基板1 1的溫度，必須比 結晶分解的溫度還低溫’所以較佳爲低於1200°C »只要成 膜基底層3時的基板11的溫度在上述範圍內，便可製得結 -41·- 201114065 晶性良好的基底層3。 又，對於基底層3，可依需要，掺雜雜質來成膜，但 從結晶性提高的觀點來看，以作成未掺雜（undope)爲佳。 又，亦可使用反應性濺鍍法來成膜由三族氮化物半導 體所構成的基底層。在使用濺鍍法的情況，相較於M0CVD 法及MBE法等，可將裝置作成簡便的構成。 「半導體層形成製程」 接著，在半導體層形成製程中，在上述磊晶製程後， 如第1圖所示，在基底層3上，使用過去周知的M0CVD法 來積層由η型半導體層4、發光層5及p型半導體層6之各 層所構成的半導體層20。 (η型半導體層之形成） 在利用上述磊晶製程形成之基底層3上，藉由使用過 去周知的M0CVD法，依序積層η型接觸層4a及η型包覆 層4b，來形成η型半導體層4。作爲形成η型接觸層4a及 η型包覆層4b的成膜裝置，可適宜變更各種條件而使用與 用於成膜上述基底層3及後述發光層5的M0CVD裝置相同 的裝置。又，亦可利用反應性濺鍍法來形成η型接觸層4a 及η型包覆層4b ^ 在本發明之製造方法，是以使透光性電極7的片電阻 Rsl變得比η型半導體層4的片電阻Rs2還低的方式來作爲 形成透光性電極7的方法。又，針對n型半導體層4,必須 將其片電阻以成爲例如20 Ω /□以下的方式一邊控制一邊 -42- 201114065 形成。 如此，作爲控制η型半導體層4的片電阻的方法，可 適宜採用如上述的由膜厚適當化所產生的方法及控制Si等 η型雜質的掺雜量的方法。 (發光層之形成） 接著，利用過去周知的MOCVD法，在η型包覆層4b (η型半導體層4)上形成發光層5。在本實施形態所形成 的發光層5，如第4圖所例示，係具有開始於GaN障壁層 且結束於GaN障壁層的積層構造，交替地積層由GaN所構 成的7層障壁層5a、及由未捧雜（non-dope)的Ga〇.sIiid.zN 所構成的6層井層5b而形成。又，在本實施形態的製造方 法中，能使用與用於成膜上述η型半導體層4的成膜裝置 (MOCVD裝置）相同者來成膜發光層5。 (Ρ型半導體層之形成） 接著，在發光層5上，即在成爲發光層5的最上層之 障壁層5a上，使用過去周知的M0CVD法來形成由ρ型包 覆層6a及ρ型接觸層6b所構成之ρ型半導體層6。針對ρ 型半導體層6之形成，可適宜變更各種條件而使用與用於 形成η型半導體層4及發光層5的MOCVD裝置相同的裝 置。又’亦可使用反應性濺鍍法來形成構成ρ型半導體層 6之Ρ型包覆層6a及ρ型接觸層6b。 在本實施形態中’首先，將由已掺雜Mg的AluGauN 所構成的P型包覆層6a形成在發光層5 (最上層的障壁層 -43- 201114065 5a)上，接著，在其上形成由已掺雜Mg的AlmGac.MN所 構成的P型接觸層6b。此時，能將相同的MOCVD裝置用 於積層P型包覆層6a及p型接觸層6b。又，如上述，作爲 P型雜質，不僅限於Mg ’亦能同樣地使用例如鋅（Zn )等。 『透光性電極形成製程』 接著，在透光性電極形成製程中，如第1圖所示，在 將絕緣層15形成於p型半導體層6上的至少一部分後，以 覆蓋絕緣層15的方式將透光性電極7形成在p型半導體層 6上。又，在透光性電極形成製程中，以使透光性電極7 的片電阻成爲比η型半導體層4的片電阻還低的方式來形 成透光性電極7。 「絕緣層之形成」 首先，在Ρ型半導體層6上的至少一部分，在第1圖 及第2圖所示之例中，於約略中央附近，形成由絕緣材料 所構成的絕緣層15。 作爲用於形成絕緣層1 5的材料並無特別的限定，能毫 無任何限制地使用過去周知的絕緣性氧化膜等，能使用例 如氧化矽（SiCh )。 又，作爲形成絕緣層1 5的方法，能毫無任何限制地使 用例如職鍍法等過去周知的方法。 「透光性電極之形成」 接著，在藉由上述方法所形成的ρ型半導體層6上， 以覆蓋絕緣層1 5的方式積層ιζο，藉以形成透光性電極7。 -44 - 201114065 作爲形成透光性電極7的方法，並無特別的限定，能 以在該技術領域所熟知的慣用手段來設置。又，其構造亦 能毫無任何限制地使用包含過去周知構造的任何構造者。 透光性電極7除了 IZO以外，還可使用ITO、ITO、IGO、 ICO、AZO、GZO或導電性氧化鈦（TiOO等的材料來形成。 又，亦可在形成透光性電極7後，實施以合金化或透明化 爲目的的熱退火。 又’在本實施形態的透光性電極形成製程中，較佳爲 在透光性電極7的表面7a形成凹凸。藉此，源自透光性電 極7的光取出效率提高，同時可利用適宜調整凹凸的形狀 及尺寸，來控制透光性電極7的片電阻Rsl。 又，作爲控制透光性電極7的片電阻Rsl的方法，除 了將上述之膜厚適當化的方法以外，可舉出實施退火處理 的方法。在對透光性電極7施加退火處理的情況，較佳爲 在氮氣環境中，在定爲500°C以上、900°C以下的溫度範圍 的條件下進行。藉此，使透光性電極7的結晶組織成爲六 方晶，可使片電阻Rsl有效地減低。在此，若退火溫度超 過9 00°C ’則由IZO所構成的透光性電極的結晶組織會成 爲立方晶，而變得難以適合地控制片電阻RS1。 藉由採用上述各方法，可易於一邊將透光性電極7的 片電阻Rs 1作成例如1 5 Ω /□以下，一邊將透光性電極7及 η型半導體層4之各片電阻Rsl、RS2的關係控制爲以下式 (Rsl < Rs2)表示的關係。 -45- 201114065 『正極接合墊電極之形成』 接著，在本實施形態的製造方法中，具備有正極形成 製程，係在透光性電極形成製程後，在透光性電極7的表 面7a中，對應於形成在p型半導體層6上的絕緣層15的 位置A形成正極接合墊8。又，在本實施形態中，藉由蝕 刻除去半導體層20的既定位置，來使η型半導體層4露出 而形成露出區域，且在該露出區域形成負極接合墊9。 「正極形成製程」 首先，在透光性電極7的表面7a，在對應於已形成於 p型半導體層6上的絕緣層15的位置A，形成正極接合墊 8。該正極接合墊8能藉由例如，以過去周知的方法從透光 性電極7的表面側開始依序積層Ti、Al、Au的各材料來形 成。 「負極接合墊之形成」 在形成負極接合墊9之際，首先，藉由利用乾蝕刻等 方法將已形成於基板11上之P型半導體層6、發光層5及 η型半導體層4的一部分除去，來使η型接觸層4a的一部 分露出。然後，在該露出區域上，能藉由例如以過去周知 的方法從露出區域的表面側開始依序積層Ni、Al、Ti、及 Au的各材料來形成省略詳細圖示之4層構造的負極接合墊 9 〇 又，在本發明中，當以上述操作順序及條件來製造發 光元件1時，如上述，較佳爲將俯視形狀作成如第2圖所 -46- 201114065 示的例子般，使電極分開方向尺寸L比晶片寬度尺寸W還 長的約略長方形狀來形成。藉此，可製造發光效率更優良 的發光元件1。 根據以上說明之本發明的三族氮化物半導體發光元件 之製造方法，可製造發光效率及光取出效率優良且具備高 外部量子效率的發光元件1，因該方法，係具備：磊晶製 程，係在基板11的主面11a上形成單結晶的基底層（三族 氮化物半導體層）3;半導體層形成製程，係在基底層3上 依序積層η型半導體層4、發光層5及p型半導體層6而形 成半導體層20;及透光性電極形成製程，係在ρ型半導體 層6上形成透光性電極7 ;透光性電極形成製程係在將絕 緣層15形成於Ρ型半導體層6上的至少一部分後，以覆蓋 絕緣層15的方式將透光性電極7形成在ρ型半導體層6 上；具備有正極形成製程，係在透光性電極形成製程之後， 在透光性電極7的表面7a中，在已形成於ρ型半導體層6 上之絕緣層15上方的位置A形成正極接合墊8;進一步地， 透光性電極形成製程係以使透光性電極7之片電阻比η型 半導體層4之片電阻還低的方式形成透光性電極7» [燈] 本發明的燈係使用本發明之三族氮化物半導體發光元 件所構成者。 作爲本發明的燈，能舉出例如，將本發明之三族氮化 物半導體發光元件與螢光體組合所構成者。已組合三族氮 -47- 201114065 化物半導體發光元件與螢光體的燈，能藉由同行業業者周 知的手段作成同行業業者周知的構成。又，過去以來，已 知有藉由組合三族氮化物半導體發光元件與螢光體來改變 發光色的技術，在本發·明的燈中亦可毫無任何限制地採用 此種技術。 第7圖係示意地顯示使用本發明之三族氮化物半導體 發光元件所構成的燈之一例的槪略圖。第5圖所示的燈80 爲砲彈型者，可使用第1圖及第2圖所示之發光元件如 第7圖所示，發光元件1之正極接合墊8係以引線（wire) 83接著於2條框（frame) 81、82中之一方（在第7圖爲框 81)，發光元件1之負極接合墊9係以引線84接合於另一 方的框82，藉以安裝發光元件1。又，發光元件！的周邊 係以由透明樹脂所構成的模（m ο 1 d ) 8 5來封裝。 因爲本發明的燈是使用本發明的發光元件1所構成 者，所以成爲具備優良發光特性者》 又’本發明的燈，亦能用於一般用途的砲彈型、攜帶 的背光用途的側視（side view )型、用於顯示器的上視（top view )型等任何用途。 [實施例] 接著’列示實施例及比較例來更詳細地說明關於本發 明之三族氮化物半導體發光元件及其製造方法、及燈，但 本發明並不限定於該等實施例。 [實施例1] • 48 - 201114065 在本實施例中，藉由如以下所說明的操作順序，來製 作發光元件的樣品（參照第1圖〜第4圖、第7圖等）。 首先，準備具有由藍寶石基板的（0001 ) C面所構成 之主面11a基板11°在此’在本實施例中’使用在主面11a 上形成有省略圖示的複數個凸部者作爲基板Π (參照在第 3、4圖中已形成在主面110上的凸部112)。又，在本實 施例，使用將已形成在主面11a的凸部的基部寬度i定爲 1.3ym，高度h定爲0.7#m，間隔ch定爲0.7//m的基板。 然後，在基板11的主面11a上，使用RF濺鍍法來形 成由具有單結晶構造之A1N所構成之厚度爲5 Onm的緩衝層 2。此時，使用具備高頻率式的電源，且具有可在靶材內移 動磁鐵的位置的機構，作爲濺鍍成膜裝置。 在以此方式製得的緩衝層2上，使用以下所示之減壓 MOCVD法來形成由三族氮化物半導體所構成的基底層3 (磊晶製程）。 首先，將從濺鍍成膜裝置取出之已形成緩衝層2的基 板11導入用於以MOCVD法來成長三族氮化物半導體的反 應爐內。然後’一邊持續流通氨氣體一邊在氫氣體環境中， 使基板11的溫度升溫至1120°C，開始將三甲基鎵（TMG ) 供給至氣相成長反應爐內，在緩衝層2上使未掺雜的GaN 磊晶成長至3#m的膜厚爲止。 形成基底層3後，接著利用相同的MOCVD裝置來形成 由GaN所構成之11型接觸層43的初期層（半導體層形成製 -49- 201114065 程）。此時，對η型接觸層4a掺雜Si。結晶成長係依據除 了使作爲Si的掺雜劑原料之SiH4流通以外，與基底層相同 的條件來進行。 接著，在利用上述操作順序所製作的η型半導體層4a 上，使用相同的MOCVD裝置來積層η型包覆層4b。 又，在形成η型半導體層4時，藉由適宜調整Si掺雜 量，以下述表1所示的範圍來適宜調整其片電阻。 接著，在利用上述操作順序所製作的η型包覆層4b 上，使用相同的MOCVD裝置來積層發光層5。 在本實施例所形成之發光層5具有由障壁層5 a(由GaN 所構成）、及井層5b (由Ga〇.85In〇.l5N所構成）所構成之多 重量子井構造。當形成該發光層5時，在由掺雜Si的GalnN 及GaN的超晶格構造所構成的η型包覆層4b上，首先，形 成障壁層5a，在該障壁層5a上，形成由Gamlno.^N所構 成之井層5b。在重複6次這樣的積層操作順序後，在第6 次所積層之井層5b上，形成第7個障壁層5a，作成將障壁 層5a配置在具有多量子井構造的發光層5的兩側。 藉由以上的操作順序來形成多量子井構造的發光層5。 上述的各製程後，接著使用相同的MOCVD裝置，成膜 具有由4層未掺雜的Ala.oeGao.iuN、及3層已掺雜Mg的GaN 所構成之P型包覆層6a °然後，進一步在其上，成膜膜厚 爲200nm之由已掺雜Mg的GaN所構成之p型接觸層6b， 作成P型半導體層6。 -50- 201114065 如此一來，將η型半導體層4、發光層5及p型半導體 層6之各層依此順序積層在基底層3上而形成半導體層20。 接著，使用以上述操作順序所製得的晶圓’依以下所 示之操作順序，製作一種半導體發光元件的發光二極體 (LED )(參照第1圖及第2圖）。 首先，在P型半導體層6上的l·個部位，使用周知的 濺鍍法，形成由Si〇2K構成的絕緣層15。此時，以200nm 的膜厚形成絕緣層15，同時作成直徑lOOym的圓形狀。 接著，使用周知的光微影技術，以覆蓋絕緣層15的方 式，在P型半導體層6上成膜由IZO材料所構成的層，藉 以形成透光性電極7 (透光性電極形成製程）。此時，藉 由將膜厚定爲400nm，同時在氮氣體環境下施加退火，來 以下述表1所示之數値適宜調整透光性電極7的片電阻。 接著，利用周知的光微影技術，在透光性電極7的表 面7a中，在其下層之對應於絕緣層15的位置，依序積層 Ti、A1及Au，藉以形成3層構造的正極接合墊8 (正極形 成製程）。此時，將正極接合墊8形成爲直徑90/zm的圓 形狀。 然後，藉由在半導體層20及透光性電極7的一部分施 加乾蝕刻來除去，設置η型接觸層6a露出的露出區域後， 在其上依序積層Ni、Al、Ti及Au的各層，藉以形成如第1 圖及第2圖所示的負極接合墊9。又，此時，將晶圓俯視 中之正極接合墊8與負極接合墊9的中心間距離定爲440 -51- 201114065 β m。 接著，將已形成各電極之晶圓基板11的背面側硏削及 硏磨而作成鏡子狀的面後，將該晶圓切斷成240 /zm (晶片 寬度尺寸W) x600//m (電極分開方向尺寸L)見方的長方 形晶片而作成LED (發光二極體）的晶片（發光元件1)。 然後，藉由將該晶片，以使正極接合墊8及負極接合 墊9在上的方式載置於導線框81上，以金線連接至導線 框，來製作燈80 (參照第7圖）。 然後，測定在以上述方法所製作之燈的p側（正極接 合墊8 )與η側（負極接合墊9 )的電極間流通20mA，依 需要流通100mA的順向電流時的發光輸出Po ( mW )，將 結果顯不於下述表1。 [實施例2~5，比較例1、2] 在實施例2〜5，比較例1、2中，將透光性電極的厚度、 及在晶圓俯視的正極接合墊及負極接合墊的中心間距離定 爲下表1所示之條件，又，除了爲了使各片電阻的關係成 爲下表1所示的關係而適宜調整的事項以外，以與上述實 施例1同樣的方法，製作已作成240 // mx600 μ m見方的長 方形三族氮化物半導體發光元件的晶片。然後，與上述同 樣地，使用該晶片來製作燈。 然後，以與上述同樣的方法，測定在燈的P側（正極 接合墊）及η側（負極接合墊）的電極間流通20mA，依需 要流通100mA的順向電流時的發光輸出P〇(mW) » 52- 201114065 將在上述實施例1~5及比較例1、2中片電阻及透光性 電極的厚度以及發光輸出（P〇)的測定結果顯示於下表1。 [表」J_ 片電阻（Ω/Cl) 透光性電極 正極-負極接 發光輸出（Po: mW) No. η型半導 透光性電 的膜厚 合墊的距離 IF = IF = 體層：Rs2 極：Rsl (nm ) (βτη) 20mA 100mA 實施例1 14 7 400 440 19.1 73 實施例2 14 4 600 440 18.9 _ 實施例3 9 7 400 440 18.8 實施例4 9 4 600 440 18.6 . 實施例5 6 4 600 440 18.6 . 比較例1 9 13 250 440 17.2 . 比較例2 6 13 250 440 16.5 • [實施例6〜9] 在實施例6~9中，將透光性電極的厚度、及各片電阻 的關係定爲下表2所示之條件，又，除了爲了使晶圓俯視 中之電極分開方向尺寸（L:晶片長度尺寸）及與其正交之 方向上的晶片寬度尺寸（W)、以及正極接合墊與負極接 合墊的中心間距離成爲下表2所示的關係而適宜調整的事 項以外，以與上述實施例1同樣的方法，製作三族氮化物 半導體發光元件的晶片。然後，與上述同樣地，使用該晶 片來製作燈。 然後’以與上述同樣的方法，測定在燈的p側（正極 接合墊）及η側（負極接合墊）的電極間流通20mA，依需 -53- 201114065 要流通100mA的順向電流（IF :驅動電流）時的發光輸出 Po ( mW )。 將在上述實施例6〜9中發光元件的規格、及發光輸出 (Po )的測定結果顯示於下述表2。 -54- 201114065 發光輸出（Po : mW) IF= 100mA CN S oo w-» g IF= 20mA 19.0 严< 16.0 18.5 俯視之各部分的尺寸 電極中心 間距離 (μ m) o ON m CN 220 〇 cn 面積 (WxL : μνα2) 143000 96000 72000 15460 縱橫尺寸 比（L/W ) oi 卜 cs cs o CN 晶片寬度尺寸 W ( jU m ) s CN 240 o oo § CS ΐ 3 5 S ε ί > ^ 4 ψ； rK U ^ ^5： 1¾ 550 400 1 400 〇 VT) 透光性電 極的膜厚 (nm) 400 o s 400 400 片電阻（Ω/ϋΙ) 透光性電極 (Rsl) 卜 寸 卜 卜 η型半導體 層（Rs2) 寸 σ\ Os 〇· 實施例6 實施例7 實施例8 實施例9 -ςιο_ s 201114065 [評估結果] 如表1所示，具備本發明之發光元件之構成的實施例 1的樣品，在順向電流（IF ) 20mA的發光輸出（Po)成爲 19.lmW，又，在將順向電流定爲100 mA的情況下發光輸出 爲7 ，獲得非常優良的發光輸出。又，在將透光性電極 7的片電阻Rsl調整爲比η型半導體層4的片電阻Rs2還低 之實施例2〜5之各個樣品中，各自的發光輸出成爲18.6mW 以上，能確認具備有高發光輸出。 對此，將透光性電極的片電阻定爲比η型半導體層的 片電阻還高的電阻値、不滿足在本發明所規定的關係之比 較例1、2的各樣品，發光輸出成爲16.5〜17.2mW，相較於 上述各實施例的樣品，變成低輸出。 認爲比較例1、2的樣品是因爲透光性電極的片電阻比 η型半導體層的片電阻還高，所以主要是對應於p側的正 極接合墊位置之半導體層發光，因此會產生由正極接合墊 所造成的光吸收及多重反射，而光取出率低落。 又，表2所示之實施例6 ~ 9的結果，係使在晶圓俯視 的電極分開方向尺寸（L)及晶片長度尺寸（w)、及正極 接合墊與負極接合墊的電極中心間距離適宜變化的例。 例如’實施例6是將晶片尺寸定爲L=550/zm、W=260 从m ’縱橫比=2.12的例，發光輸出成爲w.omw，而成爲 高輸出。 又’實施例7是將晶片尺寸定爲L=400jtzm、W=240 -56- 201114065 ym的例，發光輸出成爲17.5mW，而成爲高輸出 又，在實施例6及7中，皆將電極中心間距離 y m。 又，實施例8是將晶片尺寸定爲L=400//m ym的例，發光輸出成爲16.0mW，而成爲高輸出 又，.實施例9是將晶片尺寸定爲L=550#m 的例，發光輸出成爲18.5 mW，而成爲高輸出 實施例9中，將電極中心間距離定爲340 /z m。 在此，在將順向電流IF定爲20mA的情況中 實施例6的晶片形狀的樣品，其發光輸出會比其 的晶片形狀的情況還高。又，在將順向電流IF定 的情況中，作成如實施例9的晶片形狀的樣品， 出會比其他實施例的晶片形狀的情況還高。 如此，由表2所示之實施例6〜9的結果可得 將發光元件的俯視尺寸適當化，可更顯著地獲得 光效率之本發明的效果。 即，可知本發明係利用使透光性電極的片電 型半導體層的片電阻來獲得上述效果，更佳爲藉 寬度尺寸W:晶片長度尺寸L定爲1: 1( L/W = 1 (L/W= 2.7 )範圍的比例，構成爲正方形及長條 而在順向電流IF爲5~30mA的條件中，發光效率 提高。 在上述各實施例的發光元件中，由於透光性 定爲2 2 0 、W = 1 80 〇 、W = 280 。又，在 ，作成如 他實施例 爲 1 00m A 其發光輸 知，藉由 能提高發 阻低於η 由將晶片 )〜1 : 2.7 形晶片， 更有效地 電極的片 -57- 201114065 電阻比η型半導體層的片電阻還低，所以相較於比較例的 發光元件，可抑制電流集中在正極接合墊（ρ側）的周邊， 而使整體元件更均句地發光，發光效率提高。 如此，可瞭解本發明的三族氮化物半導體發光元件， 可抑制電流集中在電極正下方，使整體元件更均句地發 光，而具有優良的發光效率，同時抑制由電極所產生的光 吸收或多重反射所造成的損失而具有優良的光取出效率， 具備高發光強度。 【圖式簡單說明】 第1圖係示意地說明本發明之三族氮化物半導體發光 元件之一例的圖，爲顯示在基板的主面上形成緩衝層、及 由三族氮化物半導體所構成之基底層，在其上形成半導體 層，同時在該半導體層上形成絕緣層及透光性電極的積層 構造的剖面圖。 第2圖係示意地說明本發明之三族氮化物半導體發光 元件之一例的圖，爲第1圖所示之三族氮j匕物半導體發光 元件的平面圖。 第3圖係示意地說明本發明之三族氮化物半導體發光 元件之其他例的圖，爲顯示在基板的主面上形成緩衝層、 及由單結晶的三族氮化物半導體所構成之基底層的積層構 造的剖面圖。 第4圖係示意地說明本發明之三族氮化物半導體發光 元件之其他例的圖，爲第3圖之主要部分的立體圖。 -58- 201114065 第5圖係示意地說明本發明之三族氮化物半導體發光 元件之一例的圖’爲顯示順向電流（I )及發光輸出（P〇 ) 的關係的圖表。 第6圖係示意地說明本發明之三族氮化物半導體發光 元件之一例的圖，爲顯示透光性電極及η型半導體層之片 電阻的高低關係、與順向電流（I )及發光輸出（Ρ〇 )的關 係之間的相關性的圖表。 第7圖係示意地說明使用本發明之三族氮化物半導體 發光元件所構成的燈之一例的槪略圖。 【主要元件符號說明】 1 4 5 6 7 7a 8 11 > 100 11a' 110 15 20 80 三族氮化物半導體發光元件（發光元件） η型半導體層 發光層 Ρ型半導體層 透光性電極 表面（透光性電極） 正極接合墊 基板 主面 絕緣層 半導體層 .燈 位置（在透光性電極的表面中對應於絕 -59- 201114065 緣層的位置）Indium Zinc Oxide, GZO (ZnO-Ga2〇3), IGO (In2〇3-Ga2〇3), ICO(In2〇3-Ce2〇3), titanium oxide doped with any impurity element A material such as TiO ruthenium or the like. Further, in the above materials, a reduction type Ti 〇 2.x which reduces a part of TiCh may be used as the titanium oxide, as long as it is electrically conductive. Further, in the present invention, at least one of ITO, IZO, IGO, ICO, -25-201114065, and conductive titanium oxide is more preferably used. The method of the photoelectrode 7 is also not particularly applicable to the configuration in which the photoelectrode 7 is provided by conventional means well known in the art, and it can also contain a conventionally known structure, and any constructor can be used. The electrode 7 may be formed by covering the entire surface of the p-type semiconductor layer 6 at the same time, or may be formed in a lattice shape and a tree shape via a gap. After the transparent electrode 9 is formed, an alloy may be applied. And transparent thermal annealing, or may not apply thermal annealing. In the case where the translucent electrode 7 (Rs1) is formed to be lower than the n-type semi-conductive sheet resistor (Rs2) included in the semiconductor layer 20, the inventors of the present invention have found that the translucent electrode 7 and the n-type semiconductor layer are found. 4 pieces of resistor Rs: l, is controlled to be of the following formula (Rsl < Rs2), the light emission corresponding to the position of the positive electrode bonding pad 8 in the suppression layer 20 is caused by the light absorption and the multiple reflection by the positive electrode bonding pad 8, thereby improving the light extraction efficiency. The light-emitting element 1 having an excellent light-emitting output with high light extraction efficiency. The relationship between the sheet resistance Rs1 of the translucent electrode 7 and the sheet resistance Rs2 of the η layer 4 is set as follows (Rsl < RS2) The effect obtained by the system is referred to the chart shown in Fig. 6. Fig. 6 is a view showing the relationship between the high-low relationship between the translucent electrode and the n-type semiconductor layer, and the forward current (I) and the light-emission output (ρ〇). In addition, there is no limit to cover the overall situation. Further, the purpose of the sheet resistor layer 4 which is intended to be suppressed is to suppress the loss of Rs2 in the semiconductor. The graph showing the correlation between the relationship between the sheet resistance and the relationship between the sheet resistance and the -26- 201114065 is shown in the figure. The graph in Figure 6 shows that the curve (a) is the sheet resistance relationship Rsl <In the case of Rs2, the curve (b) is a case where Rsl and Rs2 are almost equal, and the curve (c) is a case of Rsl > Rs2. As shown in the graph of Fig. 6, it can be seen that the relationship of the sheet resistance is Rsl. < In the case of Rs2, a high light-emitting output (Po) can be obtained even with the same forward current (I) as compared with the case where Rsl and Rs2 are almost equal or Rsl > Rs2. I think this is because the relationship between the resistances of the pieces is Rsl. In the case of Rs2., in addition to the peripheral portion of the positive electrode bonding pad 8, the semiconductor layer 20 at the position close to the negative electrode bonding pad 9 on the n side emits light, so that the loss caused by the positive electrode bonding pad 8 can be suppressed. . In the conventional light-emitting element, it is considered that the sheet resistance of the n-type semiconductor layer 4 and the translucent electrode 7 on the side of the crucible is made the same level, and the current is uniformly diffused to the translucent electrode 7 and the semiconductor layer 20 Preferably. However, in such a configuration, there is a problem that the luminous efficiency and the light extraction efficiency are lowered as described above. In the light-emitting element 1 of the present invention, as described above, the position corresponding to the positive electrode bonding pad 8 is controlled by making the sheet resistance Rs1 of the translucent electrode 7 on the side of the crucible lower than the sheet resistance Rs2 of the n-type semiconductor layer 4. Therefore, it is possible to suppress the loss due to light absorption and multiple reflection by the positive electrode bonding pad 8, and to realize a light-emitting element having high light extraction efficiency and excellent light-emitting intensity. The sheet resistance Rsl is preferably 15 Ω/□ or less. As described above, the sheet resistance Rs1 of the translucent electrode 7 is made lower than the sheet resistance Rs2 of the n-type semiconductor layer 4-27-201114065, and more preferably, the sheet resistance Rs2 of the n-type semiconductor layer 4 is first set to 20 Ω/ In the following, the sheet resistance Rsl of the translucent electrode 7 is set to 15 Ω/□ or less, and the effect of improving the light extraction efficiency can be stably obtained. Further, the method of controlling the sheet resistance Rs 1 of the translucent electrode 7 is not particularly limited. For example, the sheet resistance Rsl can be lowered by thickening the film thickness or by applying an annealing treatment. The thickness of the translucent electrode 7 is preferably 100 nm or more. The sheet resistance Rs1 can be controlled to 15 Ω/□ or less by setting the translucent electrode 7 to the above thickness. Further, the maximum thickness of the translucent electrode 7 is preferably 600 nm or less in consideration of productivity. Further, in the light-emitting element 1 of the present invention, it is more preferable to form a structure in which irregularities are formed on the surface of the light-transmitting electrode 7. Thereby, the light extraction efficiency from the translucent electrode 7 is improved, and the sheet resistance Rs 1 of the translucent electrode 7 can be controlled by optimizing the shape or size of the concavities and convexities. In the light-emitting element 1 of the present invention, the positive electrode bonding pad 8 is provided on the translucent electrode 7 so as to be in contact with the n-type contact layer including the n-type semiconductor layer 4. The negative electrode bonding pad 9. "Positive electrode bonding pad" As shown in Figs. 1 and 2, the positive electrode bonding pad 8 is a translucent electrode formed of a translucent conductive oxide film layer which is provided in contact with the p-type semiconductor layer 6 and the insulating layer 15. Part of 7 on. Further, the positive electrode tab 8 of the illustrated example is disposed in the surface 7a of the translucent electrode 7 at a position A corresponding to the insulating layer -28-201114065. The positive electrode bonding pad 8 is provided to be electrically connected to a circuit board, a lead frame, or the like. As the positive electrode bonding pad, various structures such as Au, Al, Ni, and Cu can be used, and the thickness of the known positive electrode and the positive electrode bonding pad 8 can be used without any limitation, and it is preferably 100 to 1 Within the range of 500 nm. Further, in the characteristics of the bonding pad, the bonding ability is higher as the thickness is increased, so that the thickness of the positive electrode bonding pad 8 is more preferably 300 nm or more. In the light-emitting element 1 described in the present embodiment, as described above, it is preferable to provide the positive electrode bonding pad 8 at the position A corresponding to the insulating layer 15 on the surface 7a of the light-transmitting electrode 7. With this configuration, the effect of suppressing current concentration as described above and the effect of suppressing loss due to light absorption or multiple reflection of the positive electrode bonding pad 8 can be stably obtained. Further, by suppressing the concentration of the current directly under the positive electrode bonding pad 8, the effect of improving the light emission output (Po) can be obtained particularly when the light emitting element is driven at a high current. Further, in the present embodiment, for example, a through hole (not shown) may be provided on the surface 7a of the translucent electrode 7 at a position A corresponding to the insulating layer 15, and may be provided in contact with the insulating layer 15 through the through hole. Positive electrode bonding pad 8. With such a configuration, the effect of improving the bonding strength of the positive electrode bonding pad 8 can be obtained. "Negative electrode bonding pad" The negative electrode bonding pad 9 is formed to be in contact with the n-type semiconductor layer 4 of the semiconductor layer 20. Therefore, when the negative electrode bonding pad 9 is formed, a part of the light-emitting layer -29-201114065 and a part of the p-type semiconductor layer 6 are removed to expose the n-type contact layer of the n-type semiconductor layer 4, and the negative electrode bonding pad 9 is formed thereon. . As the negative electrode bonding pad 9, various compositions and configurations are well known, and such known compositions and structures can be used without any limitation, and can be provided by a price means well known in the art. Further, the above positive electrode bonding pad 8 The position at which the negative electrode bonding pad 9' is formed on the light-emitting element 1 and the distance between the centers of the electrodes are not particularly limited. In spite of this, in order to obtain more excellent luminous efficiency and light extraction efficiency, it is preferable to adjust the formation position of each bonding pad and the distance between the centers of the electrodes. For example, in the case of constituting the light-emitting element 1 having a substantially rectangular shape in plan view as shown in the first embodiment and the second embodiment, first, the negative electrode bonding pad 9 is disposed in the vicinity of one end side in the longitudinal direction of the light-emitting element 1, and the positive electrode is provided. The bonding pad 8 is disposed in the vicinity of the approximate center of the light-emitting element 1 or in the vicinity of the other end side in the longitudinal direction, and is preferable from the viewpoint of easily obtaining the high luminous efficiency and the light extraction efficiency as described above. In the present invention, as described above, the sheet resistance (Rs1) of the translucent electrode 7 is made lower than the sheet resistance (Rs2) of the n-type semiconductor layer 4 provided in the semiconductor layer 20. By this, it is possible to suppress the current concentration when the current flows from the negative electrode bonding pad 9 through the n-type semiconductor layer 4 and flows through the light-emitting layer 5 and the p-type semiconductor layer 6 and flows into the transparent electrode 7, so that luminous efficiency can be obtained. Excellent light-emitting element 1. "The wafer size in the plan view of the light-emitting element" In the present invention, the wafer size in the plan view of the light-emitting element 1, that is, the electrode separation direction dimension (wafer length size) in the direction in which the positive bonding pad 8 and the negative electrode bonding pad 9 are separated from each other. L and the wafer width dimension W in the direction orthogonal to the direction in which the electrodes are separated are not particularly limited. For example, the electrode separation direction dimension L and the wafer width dimension W can be made to have a square shape in a plan view, or a rectangular shape ratio can be obtained, which can be obtained in any case. The effect of improving the luminous efficiency produced by the present invention. However, in order to make the effect of improving the luminous efficiency obtained by the above configuration more remarkable, as in the example shown in Fig. 2, it is more preferable to make the shape of the plan view such that the electrode separation direction dimension L is longer than the wafer width dimension w. The shape is roughly rectangular. As shown in the light-emitting element 1 of the present invention, in the case of the light-emitting element having the above-described insulating layer 15 and having a sheet resistance Rs1 of the light-transmitting electrode 7 lower than the sheet resistance Rs2 of the n-type semiconductor layer 4 Preferably, the driving current (forward current) IF is set to a range of 5 to 30 mA. A light-emitting element driven by such a condition can be used for, for example, a backlight for a mobile phone or a notebook type personal computer. In this way, the light-emitting element 1 can be driven with a small current, and is suitable for use in the above-described backlight use or the like. Hereinafter, a more detailed wafer size will be described in the case where the light-emitting element 1 is driven under the above-described conditions. In the light-emitting element 1 of the present embodiment, the electrode width dimension L in the plan view is set to 400 #m or more, and more preferably in the range of 400 to 550/zm, and the wafer width dimension W is set to 180 Å or more. Further, it is set to a range of -31 to 201114065 180 to 260 μm, and can be configured to have a substantially rectangular shape in plan view. In this case, for example, the wafer size (WxL) in plan view can be set to a combination of 260x550 // m or 240x400//m, 180x400//m or the like. By setting the size and shape of the light-emitting element in the above range, in the translucent electrode 7 and the semiconductor layer 20, current can be efficiently diffused to the insulating layer 15 and the peripheral portion of the position A corresponding to the positive electrode bonding pad 8. Thereby, the peripheral portion of the position A or the peripheral portion of the negative electrode bonding pad 9 provided in the n-type semiconductor layer 4 is more effectively illuminated, and excellent luminous efficiency can be obtained. In the present embodiment, the vertical and horizontal dimensions of the light-emitting element 1, that is, the electrode separation direction dimension Lx, the wafer width dimension W are set to the above range, and the area of the light-emitting element 1 is set to be about 180,000 jam2 or less. It is preferable from the viewpoint that the effect of the improvement becomes remarkable. For example, when the wafer size (WxL) is 280 x 550 ym, the plan view area is 154,000 / / m 2 , and when the wafer size (WxL) is 260 x 550 / / m, the plan view area is 143, OOOym 2 ' at 240 x 400 &m; In the case of 96,000vm2', it becomes 72,000/zm2 in the case of 180x400ym. In the present embodiment, the electrode separation direction dimension Lx, the wafer width dimension W, and the plan view area of the light-emitting element 1 are set to the above-described ranges, and the aspect ratio in the plan view, that is, (the electrode separation direction dimension L) / ( The wafer width dimension W) is in the range of 1.5 to 2.7, and is preferable from the viewpoint of making the effect of improving the above-described luminous efficiency remarkable. For example, in the case where the wafer size (W xL) is 260 x 5 50 am, the aspect ratio (l/W) is -32-201114065 2.12, and in the case of 240x400//m (L/W) = 1.67, Also, (L/W) = 2_2 in the case of 1 80x400 // m. Further, the distance between the center of the electrode of the positive electrode bonding pad 8 and the negative electrode bonding pad 9 is limited by the dimension L of the electrode separating direction of the light-emitting element 1. In the present embodiment, after setting the size and shape of the light-emitting element 1 in the above-described condition, the distance between the centers of the electrodes is defined as the range of the sub-type {electrode separation direction dimension Lx0.5 to 0.75} of the light-emitting element. The effect produced by the invention becomes remarkable, and at the same time, it is preferable from the viewpoint of not producing uneven light emission and obtaining higher luminous efficiency. As described above, according to the light-emitting element 1 of the present invention, the n-type semiconductor layer 4, the light-emitting layer 5, and the p-type semiconductor layer 6 are sequentially laminated on the single crystal base layer 3 which has been formed on the substrate 11. The semiconductor layer 20 is formed with a translucent electrode 7 on the Ρ-type semiconductor layer 6. Further, at least a portion of the p-type semiconductor layer 6 is provided with an insulating layer 15 while the translucent electrode 7 is formed to cover the insulating layer 15. In the surface 7a of the translucent electrode 7, the insulating layer 15 provided on the P-type semiconductor layer 6 and the positive electrode bonding pad 8 are provided at the position A above the insulating layer, so that current concentration can be suppressed from being concentrated on the translucent electrode. 7 and the position of the semiconductor layer 20 corresponding to the positive electrode bonding pad 8, the entire element can emit light more uniformly, whereby the luminous efficiency is improved. In addition, since the sheet resistance Rs1 of the translucent electrode 7 is made lower than the sheet resistance RS2 of the n-type semiconductor layer 4, the light generated by the positive electrode bonding pad 8 provided on the translucent electrode 7 can be suppressed. The light extraction efficiency is improved by the loss caused by absorption or multiple reflection. Therefore, it is possible to provide a light-emitting element having a high luminous efficiency and a light extraction efficiency and having a high external quantum efficiency of 1 °. The light-emitting element of the present invention can be configured as follows: for example, as a substrate, as shown in FIG. As shown in Fig. 4, a substrate 100 having a principal surface 110 composed of a plane 111 (consisting of a (0001) C plane) and a plurality of convex portions H2 is used, and further, the base layer 103 is covered by The plane 111 and the convex portion 112 are epitaxially grown to form a group III nitride semiconductor to be formed on the principal surface 110. The substrate 11A of the example shown in Figs. 3 and 4 is formed with a plurality of convex portions 112. Then, a portion where the convex portion 112 is not formed in the main surface 110 of the substrate 100 is formed as a plane 111 composed of a (00 01) C plane. Therefore, as shown in FIGS. 3 and 4, the substrate 100 is The main surface 110 is composed of a flat surface 111 (consisting of a C surface) and a plurality of convex portions 112. As shown in the example, the convex portion 11 2 is composed of a surface 112c which is not parallel to the C surface, and the C surface does not appear on the surface 112c. In the 112, the base portion 11 2a has a substantially circular shape in plan view, and has a shape in which the outer shape gradually decreases toward the upper portion, and the side surface 11 2b is formed into a bowl-shaped (hemispherical) shape that is curved outward. Further, as will be described later, the convex portion may be formed into a cylindrical shape in the case of an oxide or a nitride other than sapphire. Further, the planar arrangement of the convex portions 112 is arranged in a checkerboard shape at equal intervals. The convex portion 112' sets the base width di in the range of 0.05 to 1.5 ym, sets the height h in the range of 0.05 to 1/zm, and is 1/4 or more of the base width di, and the interval between the adjacent convex portions 112. D2 is set to the base width d, which is 0.3 to 5 -34 to 201114065 times. Here, the base width ch of the convex portion 112 means the length of the maximum width of the bottom edge (base portion 12a) of the convex portion 112. Further, the interval d2 between the adjacent convex portions 112 means the distance between the edges of the base portion 1 1 2a of the closest convex portion 1 1 2 . The interval d2 between the adjacent convex portions 1 1 2 is preferably 0.5 to 5 times the base width d. When the interval d2 between the convex portions 112 is less than 0.3 times the width d of the base portion, it becomes difficult to promote the growth of the underlying layer 103 constituting the n-type semiconductor layer 4 (semiconductor layer 20). The epitaxial growth starting on the plane 111 formed by the surface makes it difficult to completely embed the convex portion 112 by the underlying layer 103, and the flatness of the surface 103a of the underlying layer 103 cannot be sufficiently obtained. Therefore, in the case where the crystal of the semiconductor layer forming the LED structure is formed on the underlying layer 103 of the buried bump 112, the crystallization inevitably forms a plurality of pits (Pit), resulting in the formed group III nitride semiconductor light-emitting device. The output and electrical characteristics deteriorate. Further, when the interval ch between the convex portions 1 1 2 exceeds 5 times the width h of the base portion, when the substrate 100 is used to form the group III nitride semiconductor light-emitting device, the substrate 100 and the substrate 100 are formed on the substrate 100. The chance of light diffusion of the interface of the group III nitride semiconductor layer is reduced, and there is a possibility that the light extraction efficiency cannot be sufficiently improved. Preferably, the base width ch is set to 0.05 to 1.5 μm. When the base width i is less than 0.05 vm, when the substrate 100 is used to form a group III nitride semiconductor light-emitting device, the effect of diffusing light cannot be sufficiently obtained. Further, when the base width di exceeds 1.5 #m, it is difficult to embed the base layer 103 to epitaxial growth by embedding the convex portions 112-35 to 201114065. Further, even if a base layer having good flatness and crystallinity can be formed, the strain between the underlying layer and the light-emitting layer becomes large, resulting in a decrease in internal quantum efficiency. Further, when the base width cl· is made smaller in the above range, the effect of further improving the light-emitting output of the light-emitting element can be obtained. Further, it is more preferable to set the base width to 0.05 to 1 y m. Preferably, the height h of the convex portion 112 is set to 0.05 to 1/m. When the height h of the convex portion 112 is less than 0.05/m, when the substrate 100 is used to form the group III nitride semiconductor light-emitting device, the effect of diffusing light may not be sufficiently obtained. In addition, when the height h of the convex portion 112 exceeds l#m, it is difficult to embed the convex portion 112 to cause epitaxial growth of the underlying layer 103, and the flatness of the surface of the underlying layer 103 may not be sufficiently obtained. Moreover, it is preferable to set the height h of the convex part 112 to 1/4 or more of the base width 1. When the height h of the convex portion 1 12 is less than 1/4 of the width h of the base portion, when the substrate 100 is used to form the group III nitride semiconductor light-emitting device, the effect of diffusing light and the removal of light cannot be sufficiently obtained. The effect of efficiency improvement. Further, the shape of the convex portion 112 is not limited to the examples shown in Figs. 3 and 4, and may be any shape as long as it is composed of a surface that is not parallel to the C surface. For example, the planar shape of the base portion may be approximately polygonal, and the outer shape may be gradually reduced toward the upper portion, and the side surface 1 1 1 may be curved toward the outer side. Further, it may be formed in a substantially conical shape and a substantially polygonal pyramid shape in which the side surface is formed by a slope which is gradually smaller toward the upper portion. Also, -36- 201114065 The angle of inclination of the side can also be a two-stage change shape. The joint portion is also formed into a cylindrical shape in the case where the convex portion is made of an oxide or a nitride other than sapphire. Further, the plane of the convex portion 112 is exemplified as 'may be equally spaced or not equally spaced. The flat configuration may be a quadrangular shape or a triangular shape, or a random. Further, the convex portion 112 provided on the substrate 100 may be formed by etching the substrate 100. However, for example, the substrate may be formed on the C surface of the other substrate 100 on which the convex portion is formed. Forming a convex portion. On the substrate, a method of depositing other materials in the portion can be performed by various methods such as sputtering without a CVD method. Further, as a material for forming the convex portion, a material having a material ratio almost equal to the substrate, such as an oxide or a nitride, may be used. When the substrate is sapphire, Al2?3, SiN, ZnO or the like can be used. In the above-described example, the interface 100 of the main surface 110 formed by the substrate 100 as the surface 111 and the convex portion 112 and the interface of the underlying layer 1〇3, which will be described later, are separated into irregularities, so that light can be utilized. The diffusion is used to reduce the inside of the light-blocking, and the light-emitting element having excellent light extraction efficiency can be realized. [Manufacturing Method of Group III Nitride Semiconductor Light-Emitting Element] The method for manufacturing a group III nitride semiconductor light-emitting device of the present invention includes an epitaxial process, which is formed on the substrate u and is formed as described later. Regardless of the figure, the convex portion 112 may be irregularly limited to the details described later. The material is deposited so as to form the convex 5, the vapor deposition method, preferably the equal refraction, for example, Si 〇 2, which has been provided with the flat layer, to the base buffer layer 102 to the light-emitting element manufacturing method such as the main surface 1 1 a -37- 201114065 Forming a single crystal base layer (Group III nitride semiconductor layer) 3: A semiconductor layer forming process by sequentially depositing an n-type semiconductor layer 4, a light-emitting layer 5, and a p-type semiconductor layer 6 on the underlying layer 3 Forming the semiconductor layer 20; and forming a translucent electrode, forming a translucent electrode 7 on the Ρ-type semiconductor layer 6; and forming the translucent electrode on at least the insulating layer 15 formed on the p-type semiconductor layer 6. After a part, the translucent electrode 7 is formed on the bismuth-type semiconductor layer 6 so as to cover the insulating layer 15, and the positive electrode forming process is provided, after the translucent electrode forming process, on the surface 7a of the translucent electrode 7. The positive electrode bonding pad 8 is formed at a position A above the insulating layer 15 formed on the P-type semiconductor layer 6. Further, the light-transmitting electrode is formed to have a sheet resistance ratio of the light-transmitting electrode 7 to an n-type semiconductor The layer resistance of layer 4 is still low Translucent electrode 7 is formed. Hereinafter, each process of the manufacturing method of the present invention will be described in detail. "Buffer layer forming process" In the manufacturing method of the present invention, it is preferable that a buffer layer forming process for forming the buffer layer 2 on the main surface 11a of the substrate 11 is performed before the epitaxial process. Further, in the present invention, since the structure in which the buffer layer is omitted may be employed, the buffer layer forming process may not be performed in this case. "Pre-Processing of Substrate" In the present embodiment, it is preferable to perform pre-treatment by a method such as reverse sputtering which is generated by plasma treatment before the substrate 11 is introduced into the chamber of the sputtering apparatus and before the buffer layer 2 is formed. -38- 201114065 "Film formation of buffer layer" After the substrate 11 is pretreated, a buffer layer 2 composed of AUGa^xN (0SXS1) is formed on the main surface 11a of the substrate 11 by reactive sputtering. . When the buffer layer 2 having a single crystal structure is formed by a reactive sputtering method, it is preferable to control the ratio of the nitrogen flow rate in the chamber of the sputtering apparatus to the flow rate of the nitrogen raw material and the inert gas so that the nitrogen raw material becomes 50~. The range of 100% is better than about 75%. Further, in the case of forming the buffer layer 2 having a columnar crystal (polycrystalline) structure, it is preferable to control the ratio of the nitrogen flow rate in the chamber of the sputtering apparatus to the flow rate of the nitrogen raw material and the inert gas so that the nitrogen raw material becomes The range of 1~50% is better than about 25%. Further, the buffer layer is not limited to the above-described reactive sputtering method. For example, it may be formed by an MOCVD method. However, from the viewpoint of process simplification, it is preferably formed by a reactive sputtering method. "Epitor process and semiconductor layer forming process" Next, in the epitaxial process, after the buffer layer forming process, as shown in Fig. 1, 'on the buffer layer 2 formed on the main surface 11a of the substrate 11' The single crystal Group III nitride semiconductor is epitaxially grown to form a base layer (Group III nitride semiconductor layer) ι 3 in such a manner as to cover the main surface 11a. Further, in the present invention, 'the base layer 3 composed of a group III nitride semiconductor is formed in the crystal crystal process'. In the semiconductor layer forming process, the n-type semiconductor layer 4 and the light-emitting layer 5 are formed on the base layer 3. And the semiconductor layer 20» which is formed of each layer of the p-type semiconductor layer 6 in the present embodiment, in the epitaxial process and the semiconductor formation process in which each layer is formed by using a group III nitride semiconductor-39-201114065, The composition of the two processes is common, and some explanations will be omitted. In the present invention, the method of growing the gallium nitride-based compound semiconductor (Group III nitride semiconductor) when forming the underlayer 3, the n-type semiconductor layer 4, the light-emitting layer 5, and the p-type semiconductor layer 6 is not particularly limited. It is suitable to use a reactive sputtering method, MOCVD (organic metal chemical vapor phase growth method), HVPE (hydride vapor phase growth method), ΜΒΕ (molecular beam epitaxy method), etc. to make all known nitride semiconductors grow. method. In these methods, when using the MOCVD method, it is possible to use hydrogen (η2) or nitrogen (Ν2) as a carrier gas, and trimethylgallium (TMG) or triethylgallium (TEG) as a Ga source of a three-group raw material. Trimethylaluminum (TMA) or triethylaluminum (TEA) as the A1 source, trimethylindium (TMI) or triethylindium (TEI) as the source of In, as the N source of ammonia of the five-component raw material ( NH3), 肼 (H), etc. Further, as the dopant, decane (SiH4) or dioxane (ShHe) which is a Si raw material, decane gas (GeH4) which is a Ge raw material, and tetramethylphosphonium ((CiL·) 4Ge) can be used for the η type. And an organic ruthenium compound such as tetraethyl ruthenium ((c2H〇4Ge). When using the MBE method, elemental ruthenium can also be used as a dopant source. For the P type, for example, dicyclopentadienyl magnesium (Cp2Mg) or Bisethylenecyclopentadienyl magnesium (EtCp2Mg) is used as the Mg raw material. Further, the above gallium nitride-based compound semiconductor may contain other tri-group elements in addition to Al, Ga, and In, and may contain Ge as needed. And a dopant element such as Si, Mg, Ca, Zn, or Be. Further, it is not limited to the element to be added, and may be included in the film-forming conditions and the like: the hetero--40-201114065 which is required to be contained, and In the present invention, in the above method, it is preferable to use an MOCVD method from the viewpoint of obtaining a film having good crystallinity, and in the present embodiment, in the case of epitaxy Example of MOCVD method used in process and semiconductor layer formation processes In the epitaxial process, as shown in Fig. 1, a base layer is formed on the buffer layer 2 formed on the substrate 1 by using a conventionally known MOCVD method. 3. In the present embodiment, a method of forming the underlayer 3 by the MOCVD method will be described. However, the method of laminating the underlayer 3 is not particularly limited as long as the crystal growth can be caused by a dislocation loop. The method can be used without any limitation. In particular, since the MOCVD method, the MBE method, the VPE method, and the like can cause migration, it is suitable from the viewpoint of forming a film having good crystallinity. From the viewpoint of producing a film having particularly excellent crystallinity, it is more suitable to use the MOCVD method. It is preferable to set the temperature of the substrate 11 when the underlayer 3 is formed, that is, the growth temperature of the underlayer 3 to 800. This is because the temperature of the substrate 11 when the underlayer 3 is formed is increased, the migration of atoms is facilitated, and the cyclization is facilitated, which is more preferably 900 ° C or higher. It is above 1 000 °C. Since the temperature of the substrate 11 when the base layer 3 is formed must be lower than the temperature of the crystallization decomposition, it is preferably lower than 1200 ° C. » As long as the temperature of the substrate 11 when the base layer 3 is formed is within the above range Then, the base layer 3 having good crystallinity can be obtained. Further, the base layer 3 can be doped with impurities to form a film as needed, but from the viewpoint of improving crystallinity, it is not Preferably, doping is preferred. Further, a base layer composed of a group III nitride semiconductor may be formed by a reactive sputtering method. In the case of using the sputtering method, the device can be made simpler than the M0CVD method, the MBE method, or the like. "Semiconductor layer forming process" Next, in the semiconductor layer forming process, after the epitaxial process, as shown in FIG. 1, the n-type semiconductor layer 4 is laminated on the underlying layer 3 by a conventionally known MOCVD method. The semiconductor layer 20 composed of each of the light-emitting layer 5 and the p-type semiconductor layer 6. (Formation of n-type semiconductor layer) On the underlying layer 3 formed by the above-described epitaxial process, an n-type is formed by sequentially laminating the n-type contact layer 4a and the n-type cladding layer 4b by using a conventionally known MOCVD method. Semiconductor layer 4. As a film forming apparatus for forming the n-type contact layer 4a and the n-type cladding layer 4b, the same apparatus as that used for forming the underlying layer 3 and the luminescent layer 5 to be described later can be used as appropriate. Further, the n-type contact layer 4a and the n-type cladding layer 4b may be formed by a reactive sputtering method. In the manufacturing method of the present invention, the sheet resistance Rs1 of the translucent electrode 7 is made larger than that of the n-type semiconductor. The sheet resistance Rs2 of the layer 4 is also low as a method of forming the translucent electrode 7. In addition, the n-type semiconductor layer 4 must be formed while controlling the sheet resistance to be, for example, 20 Ω / □ or less -42-201114065. As a method of controlling the sheet resistance of the n-type semiconductor layer 4, a method of optimizing the film thickness as described above and a method of controlling the doping amount of the n-type impurity such as Si can be suitably employed. (Formation of Light Emitting Layer) Next, the light emitting layer 5 is formed on the n-type cladding layer 4b (n-type semiconductor layer 4) by a conventionally known MOCVD method. As shown in FIG. 4, the light-emitting layer 5 formed in the present embodiment has a laminated structure starting from a GaN barrier layer and ending in a GaN barrier layer, and a seven-layer barrier layer 5a made of GaN is alternately laminated, and It is formed by a 6-layer well layer 5b composed of non-dope Ga〇.sIiid.zN. Further, in the production method of the present embodiment, the light-emitting layer 5 can be formed using the same film forming apparatus (MOCVD apparatus) for forming the above-mentioned n-type semiconductor layer 4. (Formation of the Ρ-type semiconductor layer) Next, on the light-emitting layer 5, that is, on the barrier layer 5a which is the uppermost layer of the light-emitting layer 5, the conventionally known MOCVD method is used to form the p-type cladding layer 6a and the p-type contact. The p-type semiconductor layer 6 composed of the layer 6b. For the formation of the p-type semiconductor layer 6, the same conditions as those of the MOCVD apparatus for forming the n-type semiconductor layer 4 and the light-emitting layer 5 can be used as appropriate. Further, the ruthenium-type cladding layer 6a and the p-type contact layer 6b constituting the p-type semiconductor layer 6 may be formed by a reactive sputtering method. In the present embodiment, 'first, a P-type cladding layer 6a made of Mg-doped AluGauN is formed on the light-emitting layer 5 (the uppermost barrier layer-43-201114065 5a), and then formed thereon. The P-type contact layer 6b composed of Mg-doped AlmGac.MN. At this time, the same MOCVD apparatus can be used for the laminated P-type cladding layer 6a and the p-type contact layer 6b. Further, as described above, as the P-type impurity, for example, not only Mg' but also zinc (Zn) or the like can be used. "Translucent electrode forming process" Next, in the transparent electrode forming process, as shown in FIG. 1, after the insulating layer 15 is formed on at least a part of the p-type semiconductor layer 6, the insulating layer 15 is covered. The light transmissive electrode 7 is formed on the p-type semiconductor layer 6. In the translucent electrode forming process, the translucent electrode 7 is formed such that the sheet resistance of the translucent electrode 7 is lower than the sheet resistance of the n-type semiconductor layer 4. "Formation of Insulating Layer" First, in at least a part of the Ρ-type semiconductor layer 6, in the examples shown in Figs. 1 and 2, an insulating layer 15 made of an insulating material is formed in the vicinity of the approximate center. The material for forming the insulating layer 15 is not particularly limited, and a conventionally known insulating oxide film or the like can be used without any limitation, and for example, yttrium oxide (SiCh) can be used. Further, as a method of forming the insulating layer 15, a conventionally known method such as a job plating method can be used without any limitation. "Formation of Translucent Electrode" Next, the p-type semiconductor layer 6 formed by the above method is laminated so as to cover the insulating layer 15 to form the translucent electrode 7. -44 - 201114065 The method of forming the translucent electrode 7 is not particularly limited and can be provided by a conventional means well known in the art. Further, the configuration can also use any constructor including a conventionally known structure without any restriction. The translucent electrode 7 may be formed of a material such as ITO, ITO, IGO, ICO, AZO, GZO, or conductive titanium oxide (TiOO) in addition to IZO. Alternatively, after the transparent electrode 7 is formed, the translucent electrode 7 may be used. In the process of forming a translucent electrode according to the present embodiment, it is preferable to form irregularities on the surface 7a of the translucent electrode 7. The light extraction efficiency of the electrode 7 is improved, and the sheet resistance Rs1 of the translucent electrode 7 can be controlled by appropriately adjusting the shape and size of the concavities and convexities. Further, as a method of controlling the sheet resistance Rs1 of the translucent electrode 7, In addition to the method of optimizing the film thickness, a method of performing an annealing treatment may be mentioned. When the annealing treatment is applied to the translucent electrode 7, it is preferably 500 ° C or higher and 900 ° C in a nitrogen atmosphere. In the following temperature range, the crystal structure of the translucent electrode 7 is hexagonal, and the sheet resistance Rs1 can be effectively reduced. Here, if the annealing temperature exceeds 900 ° C, IZO Crystallization of the formed translucent electrode It is difficult to appropriately control the sheet resistance RS1 by the above-described respective methods, and it is easy to make the sheet resistance Rs 1 of the translucent electrode 7 into, for example, 15 Ω / □ or less, by using the above-described methods. The relationship between the sheet resistances Rs1 and RS2 of the photoelectrode 7 and the n-type semiconductor layer 4 is controlled as follows (Rsl) < Rs2) relationship. -45-201114065 "Formation of Positive Electrode Mat Electrode" In the manufacturing method of the present embodiment, a positive electrode forming process is provided, and after the translucent electrode forming process, the surface 7a of the translucent electrode 7 is formed. The positive electrode bonding pad 8 is formed corresponding to the position A of the insulating layer 15 formed on the p-type semiconductor layer 6. Further, in the present embodiment, the predetermined position of the semiconductor layer 20 is removed by etching, and the n-type semiconductor layer 4 is exposed to form an exposed region, and the negative electrode bonding pad 9 is formed in the exposed region. "Positive Electrode Forming Process" First, the positive electrode bonding pad 8 is formed on the surface 7a of the translucent electrode 7 at a position A corresponding to the insulating layer 15 formed on the p-type semiconductor layer 6. The positive electrode bonding pad 8 can be formed by sequentially laminating materials of Ti, Al, and Au from the surface side of the light-transmitting electrode 7 by a conventionally known method. "Formation of Negative Electrode Bonding Pad" When the negative electrode bonding pad 9 is formed, first, a part of the P-type semiconductor layer 6, the light-emitting layer 5, and the n-type semiconductor layer 4 which have been formed on the substrate 11 by dry etching or the like is used. It is removed to expose a part of the n-type contact layer 4a. Then, in the exposed region, a negative electrode having a four-layer structure, which is not shown in detail, can be formed by sequentially laminating materials of Ni, Al, Ti, and Au from the surface side of the exposed region by a conventionally known method. In the present invention, when the light-emitting element 1 is manufactured in the above-described operation sequence and conditions, as described above, it is preferable to form the plan view as shown in Fig. 46-201114065. The electrode separation direction dimension L is formed in a substantially rectangular shape longer than the wafer width dimension W. Thereby, the light-emitting element 1 having more excellent luminous efficiency can be manufactured. According to the method for producing a group III nitride semiconductor light-emitting device of the present invention described above, the light-emitting element 1 having excellent luminous efficiency and light extraction efficiency and having high external quantum efficiency can be manufactured, and the method includes an epitaxial process. A single crystal base layer (Group III nitride semiconductor layer) 3 is formed on the main surface 11a of the substrate 11; a semiconductor layer forming process is performed to sequentially laminate the n-type semiconductor layer 4, the light-emitting layer 5, and the p-type on the base layer 3. The semiconductor layer 20 is formed by the semiconductor layer 6; and the translucent electrode forming process is performed to form the translucent electrode 7 on the p-type semiconductor layer 6; the translucent electrode forming process is performed by forming the insulating layer 15 on the Ρ-type semiconductor layer After at least a part of 6 is formed, the translucent electrode 7 is formed on the p-type semiconductor layer 6 so as to cover the insulating layer 15; and the positive electrode forming process is provided, after the translucent electrode forming process, at the translucent electrode In the surface 7a of the seventh surface, the positive electrode bonding pad 8 is formed at a position A above the insulating layer 15 which has been formed on the p-type semiconductor layer 6; further, the light transmitting electrode is formed into a process to electrically charge the light transmitting electrode 7 Lower than the sheet resistance of η-type semiconductor layer 4 are formed of translucent electrode 7 »light system [Lamp] of the present invention, the present invention is the use of a group III nitride semiconductor light emitting element is constituted by. The lamp of the present invention may be, for example, a combination of the group III nitride semiconductor light-emitting device of the present invention and a phosphor. The combination of the Group III nitrogen-47-201114065 compound semiconductor light-emitting element and the phosphor lamp can be made into a well-known composition of the industry by a means known to those skilled in the art. Further, in the past, a technique for changing the luminescent color by combining a group III nitride semiconductor light-emitting device and a phosphor has been known, and such a technique can be employed without any limitation in the lamp of the present invention. Fig. 7 is a schematic view showing an example of a lamp comprising the group III nitride semiconductor light-emitting device of the present invention. The lamp 80 shown in Fig. 5 is a cannonball type, and the light-emitting elements shown in Figs. 1 and 2 can be used. As shown in Fig. 7, the positive electrode bonding pad 8 of the light-emitting element 1 is followed by a wire 83. In one of the two frames 81 and 82 (block 81 in Fig. 7), the negative electrode bonding pad 9 of the light-emitting element 1 is bonded to the other frame 82 by the lead wires 84, whereby the light-emitting element 1 is mounted. Also, the light-emitting element! The periphery is encapsulated by a mold (m ο 1 d ) 8 5 made of a transparent resin. Since the lamp of the present invention is composed of the light-emitting element 1 of the present invention, it is a lamp having the excellent light-emitting characteristics, and the lamp of the present invention can also be used for a general-purpose projectile type or a side view of a portable backlight ( Side view type, any use for the top view type of the display. [Examples] Next, the group III nitride semiconductor light-emitting device of the present invention, a method for producing the same, and a lamp will be described in more detail by showing the examples and comparative examples, but the present invention is not limited to the examples. [Embodiment 1] • 48 - 201114065 In the present embodiment, a sample of a light-emitting element is produced by an operation sequence as described below (see Figs. 1 to 4, Fig. 7, etc.). First, a main surface 11a having a (0001) C surface of a sapphire substrate is prepared as a substrate. Here, in the present embodiment, a plurality of convex portions (not shown) are formed on the main surface 11a as a substrate. Π (Refer to the convex portion 112 which has been formed on the principal surface 110 in Figs. 3 and 4). Further, in the present embodiment, a substrate having a base width i formed on the convex portion of the principal surface 11a is set to 1.3 μm, a height h is set to 0.7 #m, and a space ch is set to 0.7/m. Then, on the principal surface 11a of the substrate 11, a buffer layer 2 having a thickness of 5 Onm composed of A1N having a single crystal structure was formed by RF sputtering. In this case, a mechanism having a high frequency type power supply and having a position at which the magnet can be moved in the target is used as a sputtering film forming apparatus. On the buffer layer 2 thus obtained, a base layer 3 composed of a group III nitride semiconductor was formed by a reduced pressure MOCVD method shown below (epitaxial process). First, the substrate 11 on which the buffer layer 2 has been taken out from the sputtering film forming apparatus is introduced into a reaction furnace for growing a group III nitride semiconductor by MOCVD. Then, while continuing to flow the ammonia gas, the temperature of the substrate 11 is raised to 1,120 ° C in a hydrogen gas atmosphere, and trimethylgallium (TMG) is started to be supplied to the vapor phase growth reactor, and the buffer layer 2 is not The doped GaN epitaxial growth is continued until a film thickness of 3 #m. After the underlayer 3 was formed, an initial layer of the type 11 contact layer 43 made of GaN was formed by the same MOCVD apparatus (manufactured by the semiconductor layer - 49-201114065). At this time, the n-type contact layer 4a is doped with Si. The crystal growth is carried out under the same conditions as the underlayer except that SiH4 which is a dopant raw material of Si is supplied. Next, the n-type cladding layer 4b is laminated on the n-type semiconductor layer 4a produced by the above-described operation sequence using the same MOCVD apparatus. Further, when the n-type semiconductor layer 4 is formed, the sheet resistance is appropriately adjusted in the range shown in Table 1 below by appropriately adjusting the Si doping amount. Next, the light-emitting layer 5 was laminated on the n-type cladding layer 4b produced by the above-described operation procedure using the same MOCVD apparatus. The light-emitting layer 5 formed in this embodiment has a multi-weight sub-well structure composed of a barrier layer 5a (consisting of GaN) and a well layer 5b (consisting of Ga〇.85 In.15N). When the light-emitting layer 5 is formed, on the n-type cladding layer 4b composed of the Si-doped GalnN and GaN superlattice structure, first, the barrier layer 5a is formed, and on the barrier layer 5a, Gamlno is formed. The well layer 5b formed by .N. After repeating the sequence of such stacking operations six times, the seventh barrier layer 5a is formed on the well layer 5b of the sixth layer, and the barrier layer 5a is disposed on both sides of the light-emitting layer 5 having the multi-quantum well structure. . The light-emitting layer 5 of the multi-quantum well structure is formed by the above operation sequence. After each of the above processes, a P-type cladding layer 6a composed of four layers of undoped Ala.oeGao.iuN and three layers of Mg-doped GaN is formed by using the same MOCVD apparatus. Further, a p-type contact layer 6b made of Mg-doped GaN having a film thickness of 200 nm was formed thereon to form a P-type semiconductor layer 6. In the case of the above, the layers of the n-type semiconductor layer 4, the light-emitting layer 5, and the p-type semiconductor layer 6 are laminated on the underlying layer 3 in this order to form the semiconductor layer 20. Next, a light-emitting diode (LED) of a semiconductor light-emitting device was produced by using the wafers obtained in the above-described operation procedure in accordance with the operation sequence shown below (see Figs. 1 and 2). First, an insulating layer 15 made of Si 2K is formed on a portion of the P-type semiconductor layer 6 by a known sputtering method. At this time, the insulating layer 15 was formed with a film thickness of 200 nm, and a circular shape having a diameter of 100 μm was formed at the same time. Next, a layer made of an IZO material is formed on the P-type semiconductor layer 6 so as to cover the insulating layer 15 by a well-known photolithography technique, thereby forming a translucent electrode 7 (transparent electrode formation process) . At this time, the sheet resistance of the translucent electrode 7 was appropriately adjusted by the number shown in Table 1 below by setting the film thickness to 400 nm while applying annealing in a nitrogen gas atmosphere. Next, Ti, A1, and Au are sequentially laminated on the surface 7a of the translucent electrode 7 at a position corresponding to the insulating layer 15 at the lower surface of the translucent electrode 7 by a well-known photolithography technique, thereby forming a positive electrode junction of a three-layer structure. Pad 8 (positive electrode forming process). At this time, the positive electrode bonding pad 8 was formed into a circular shape having a diameter of 90/zm. Then, by removing dry etching by a part of the semiconductor layer 20 and the translucent electrode 7, the exposed regions of the n-type contact layer 6a are exposed, and then layers of Ni, Al, Ti, and Au are sequentially laminated thereon. Thereby, the negative electrode bonding pad 9 as shown in FIGS. 1 and 2 is formed. Further, at this time, the distance between the centers of the positive electrode bonding pads 8 and the negative electrode bonding pads 9 in the wafer plan view is set to 440 - 51 - 201114065 β m. Next, the back side of the wafer substrate 11 on which the electrodes have been formed is diced and honed to form a mirror-like surface, and then the wafer is cut into 240 /zm (wafer width W) x600 / / m (electrode A wafer (light-emitting element 1) of an LED (light-emitting diode) is formed by dividing a square-shaped wafer of a direction L) square. Then, the wafer is placed on the lead frame 81 so that the positive electrode bonding pad 8 and the negative electrode bonding pad 9 are placed thereon, and the gold wire is connected to the lead frame to fabricate the lamp 80 (see Fig. 7). Then, 20 mA was passed between the electrodes of the p-side (positive electrode bonding pad 8) and the n-side (negative electrode bonding pad 9) of the lamp produced by the above method, and a light output Po (mW) when a forward current of 100 mA was flowed as needed was measured. ), the results are not shown in Table 1 below. [Examples 2 to 5, Comparative Examples 1 and 2] In Examples 2 to 5, Comparative Examples 1 and 2, the thickness of the translucent electrode and the center of the positive electrode bonding pad and the negative electrode bonding pad in plan view of the wafer were used. In the same manner as in the above-described first embodiment, the production was performed in the same manner as in the above-described first embodiment, except that the conditions shown in Table 1 below were appropriately adjusted in order to change the relationship between the resistances of the respective sheets. A wafer of 240 // m x 600 μm square rectangular group III nitride semiconductor light-emitting device. Then, in the same manner as described above, the wafer was used to fabricate a lamp. Then, in the same manner as described above, the light emission output P〇 (mW) was measured when 20 mA was passed between the electrodes of the P side (positive electrode bonding pad) and the η side (negative electrode bonding pad) of the lamp, and a forward current of 100 mA was flowed as needed. » 52-201114065 The measurement results of the sheet resistance and the thickness of the translucent electrode and the luminescence output (P〇) in the above Examples 1 to 5 and Comparative Examples 1 and 2 are shown in Table 1 below. [Table] J_ Chip resistance (Ω/Cl) Transistor electrode positive-negative light output (Po: mW) No. η-type semi-transmissive light film thickness pad distance IF = IF = Body layer: Rs2 Pole: Rsl (nm) (βτη) 20 mA 100 mA Example 1 14 7 400 440 19.1 73 Example 2 14 4 600 440 18.9 _ Example 3 9 7 400 440 18.8 Example 4 9 4 600 440 18.6 . Example 5 6 4 600 440 18.6 . Comparative Example 1 9 13 250 440 17.2 . Comparative Example 2 6 13 250 440 16.5 • [Examples 6 to 9] In Examples 6 to 9, the thickness of the translucent electrode and the resistance of each sheet were The relationship is set to the conditions shown in Table 2 below, in addition to the wafer width dimension (W) in the direction in which the electrode is separated in the plan view and the wafer width dimension (W) in the direction orthogonal thereto, and the positive electrode. A wafer of a group III nitride semiconductor light-emitting device was produced in the same manner as in the above-described first embodiment except that the distance between the center of the bonding pad and the negative electrode bonding pad was changed as shown in Table 2 below. Then, in the same manner as described above, the wafer was used to produce a lamp. Then, in the same manner as described above, 20 mA was passed between the electrodes on the p-side (positive electrode bonding pad) and the η-side (negative electrode bonding pad) of the lamp, and a forward current of 100 mA was flowed as needed -53-201114065 (IF: Light output Po (mW) when driving current). The specifications of the light-emitting elements and the measurement results of the light-emitting output (Po) in the above-described Examples 6 to 9 are shown in Table 2 below. -54- 201114065 Illuminated output (Po : mW) IF= 100mA CN S oo w-» g IF= 20mA 19.0 strict < 16.0 18.5 Dimensions of each part of the plan view The distance between the centers of the electrodes (μ m) o ON m CN 220 〇cn Area (WxL : μνα2) 143000 96000 72000 15460 Aspect ratio (L/W) oi cs cs o CN Width dimension W ( jU m ) s CN 240 o oo § CS ΐ 3 5 S ε ί > ^ 4 ψ; rK U ^ ^5: 13⁄4 550 400 1 400 〇VT) Film thickness of the translucent electrode (nm) 400 os 400 400 piece resistance (Ω/ϋΙ) Translucent electrode (Rsl) 卜 卜 η 半导体 半导体 半导体 半导体 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施201114065 [Evaluation Result] As shown in Table 1, in the sample of Example 1 having the configuration of the light-emitting element of the present invention, the light-emitting output (Po) of the forward current (IF) of 20 mA was 19.lmW, and When the current is set to 100 mA, the light output is 7 and a very good light output is obtained. Further, in each of the samples of Examples 2 to 5 in which the sheet resistance Rs1 of the translucent electrode 7 was adjusted to be lower than the sheet resistance Rs2 of the n-type semiconductor layer 4, the respective light-emitting outputs were 18.6 mW or more, and it was confirmed that Has a high luminous output. On the other hand, the sheet resistance of the translucent electrode was set to be higher than the sheet resistance of the n-type semiconductor layer, and the respective samples of Comparative Examples 1 and 2 which did not satisfy the relationship defined by the present invention showed a luminous output of 16.5. ~17.2 mW, compared to the samples of the above examples, became a low output. It is considered that the samples of Comparative Examples 1 and 2 are because the sheet resistance of the translucent electrode is higher than the sheet resistance of the n-type semiconductor layer, so that the semiconductor layer corresponding to the position of the positive electrode bonding pad on the p-side is mainly emitted, so that Light absorption and multiple reflection caused by the positive electrode bonding pad, and the light extraction rate is low. Further, the results of Examples 6 to 9 shown in Table 2 are such that the electrode separation direction dimension (L) and the wafer length dimension (w) in the plan view of the wafer and the electrode center distance between the positive electrode bonding pad and the negative electrode bonding pad are obtained. Examples of suitable changes. For example, the sixth embodiment is an example in which the wafer size is L = 550 / zm and W = 260 from m ' aspect ratio = 2.12, and the light-emission output becomes w.omw, and becomes a high output. Further, in the seventh embodiment, the wafer size is set to L = 400 jtzm, W = 240 - 56 - 201114065 ym, and the light-emitting output is 17.5 mW, which is a high output. In the examples 6 and 7, the electrode center is used. The distance between ym. Further, in the eighth embodiment, the wafer size is set to L = 400 / /m ym, and the light-emitting output is 16.0 mW, which is a high output. Example 9 is an example in which the wafer size is L = 550 #m. The light-emitting output was 18.5 mW, and in the high-output embodiment 9, the distance between the centers of the electrodes was set to 340 /zm. Here, in the case where the forward current IF was set to 20 mA, the wafer-shaped sample of Example 6 had a higher light-emission output than the case of the wafer shape. Further, in the case where the forward current IF was determined, the sample of the wafer shape as in the ninth embodiment was produced, and the occurrence of the wafer shape was higher than that of the wafer shape of the other examples. As a result of the results of Examples 6 to 9 shown in Table 2, it is possible to obtain a plan view of the light-emitting element in a plan view, and it is possible to more effectively obtain the effect of the present invention of light efficiency. That is, it is understood that the present invention achieves the above effects by using the sheet resistance of the sheet-type semiconductor layer of the light-transmitting electrode, and more preferably, the width dimension W: the wafer length dimension L is set to 1:1 (L/W = 1 ( The ratio of the range of L/W = 2.7) is square and long, and the luminous efficiency is improved in the condition that the forward current IF is 5 to 30 mA. In the light-emitting elements of the above embodiments, the light transmittance is determined as 2 2 0 , W = 1 80 〇, W = 280. Also, in the case of his embodiment is 100 00 A A luminescence, knowing that by increasing the resistance is lower than η by the wafer) ~1 : 2.7 The wafer, the more effective electrode sheet-57-201114065, has a lower sheet resistance than the n-type semiconductor layer, so that the current is concentrated on the periphery of the positive electrode bonding pad (ρ side) compared to the light-emitting element of the comparative example. The overall component is more uniformly illuminated, and the luminous efficiency is improved. Thus, it can be understood that the group III nitride semiconductor light-emitting device of the present invention can suppress current concentration directly under the electrode, cause the entire element to emit light more uniformly, and has excellent luminous efficiency while suppressing light absorption by the electrode or It has excellent light extraction efficiency and high luminous intensity due to the loss caused by multiple reflections. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view schematically showing an example of a group III nitride semiconductor light-emitting device of the present invention, in which a buffer layer is formed on a main surface of a substrate and a group III nitride semiconductor is formed. A base layer on which a semiconductor layer is formed, and a cross-sectional view of a laminated structure of an insulating layer and a translucent electrode is formed on the semiconductor layer. Fig. 2 is a view schematically showing an example of a group III nitride semiconductor light-emitting device of the present invention, and is a plan view of the group III nitrogen semiconductor semiconductor light-emitting device shown in Fig. 1. Fig. 3 is a view schematically showing another example of the group III nitride semiconductor light-emitting device of the present invention, showing a buffer layer formed on the main surface of the substrate and a base layer composed of a single crystal group III nitride semiconductor; A sectional view of the laminated structure. Fig. 4 is a view schematically showing another example of the group III nitride semiconductor light-emitting device of the present invention, and is a perspective view of a main portion of Fig. 3. -58- 201114065 Fig. 5 is a diagram schematically showing an example of a group III nitride semiconductor light-emitting device of the present invention, which is a graph showing a relationship between a forward current (I) and a light-emitting output (P〇). Fig. 6 is a view schematically showing an example of a group III nitride semiconductor light-emitting device of the present invention, showing the relationship between the sheet resistance of the translucent electrode and the n-type semiconductor layer, and the forward current (I) and the light output. (Ρ〇) A chart of the correlation between the relationships. Fig. 7 is a schematic view showing an example of a lamp comprising the group III nitride semiconductor light-emitting device of the present invention. [Description of main component symbols] 1 4 5 6 7 7a 8 11 > 100 11a' 110 15 20 80 Group III nitride semiconductor light-emitting element (light-emitting element) n-type semiconductor layer light-emitting layer Ρ-type semiconductor layer light-transmitting electrode surface ( Translucent electrode) Positive electrode bonding pad substrate main surface insulating layer Semiconductor layer. Lamp position (corresponding to the position of the edge layer of the -59-201114065 in the surface of the translucent electrode)

Rsl 片電阻（透光性電極）Rsl sheet resistance (transparent electrode)

Rs2 片電阻（η型半導體層） -60-Rs2 sheet resistance (n-type semiconductor layer) -60-

Claims (1)

201114065 七、申請專利範圍： 1. 一種三族氮化物半導體發光元件，其係在已形成於基板 上之單結晶三族氮化物半導體層上，形成有依序積層η 型半導體層、發光層及Ρ型半導體層的半導體層，在該ρ 型半導體層上形成透光性電極所構成，其特徵爲， 在該Ρ型半導體層上的至少一部分具備絕緣層，同時 該透光性電極係形成爲覆蓋該絕緣層， 在該透光性電極的表面中，在該Ρ型半導體層上所具 備之該絕緣層的上方設置正極接合墊， 該透光性電極之片電阻比該η型半導體層之片電阻還 低。 2. 如申請專利範圍第1項之三族氮化物半導體發光元件， 其中該透光性電極之片電阻爲15Ω/□以下，該η型半導 體層之片電阻爲20 Ω /□以下。 3. 如申請專利範圍第1或2項之三族氮化物半導體發光元 件，其中使該透光性電極表面的至少一部分成爲凹凸形 狀。 4. 如申請專利範圍第1或2項之三族氮化物半導體發光元 件，其中該透光性電極爲使用選自於由氧化銦錫（ΙΤΟ: Indium Tin Oxide)、氧化銦鋅（IZO: Indium Zinc Oxide)、 氧化銦鎵（IGO: Indium Gallium Oxide)、氧化銦铈（ICO : Indium Cerium Oxide)、及導電性氧化鈦（TiCh)所構成 之群組的至少1種。 -61- 201114065 5. 如申請專利範圍第1或2項之三族氮化物半導體發光元 件，其中該絕緣層爲由氧化矽（SiOO所構成。 6. —種三族氮化物半導體發光元件之製造方法，其具備： 磊晶製程，係在基板上形成單結晶的三族氮化物半導體 層；半導體層形成製程，係在該三族氮化物半導體層上 依序積層η型半導體層、發光層及p型半導體層而形成 半導體層；及透光性電極形成製程，係在該ρ型半導體 層上形成透光性電極；其特徵爲， 該透光性電極形成製程係在將絕緣層形成於該ρ型半 導體層上的至少一部分後，以覆蓋該絕緣層的方式將該 透光性電極形成在該Ρ型半導體層上， 具備有正極形成製程，係在該透光性電極形成製程之 後，在該透光性電極的表面中，在已形成於該ρ型半導 體層上之該絕緣層上方形成正極接合墊， 進一步地，該透光性電極形成製程係以使該透光性電 極之片電阻比該η型半導體層之片電阻還低的方式形成 該透光性電極。 7. 如申請專利範圍第6項之三族氮化物半導體發光元件之 製造方法，其中該透光性電極形成製程係以使片電阻成 爲15Ω/□以下之方式形成該透光性電極，該半導體層形 成製程係以使片電阻成爲20 Ω /□以下之方式形成該η型 半導體層》 8. 如申請專利範圍第6或7項之三族氮化物半導體發光元 -62- 201114065 件之製造方法，其中該透光性電極形成製程係在該透光 性電極表面的至少一部分形成凹凸形狀。 9. 如申請專利範圍第6或7項之三族氮化物半導體發光元 件之製造方法，其中該透光性電極形成製程，係使用選 自於由氧化銦錫（ITO: Indium Tin Oxide)、氧化銦鋅 (IZO : Indium Zinc Oxide )、氧化銦鎵（IGO : Indium Gallium Oxide)、氧化銦鈽（ICO: Indium Cerium Oxide) ' 及導電性氧化鈦（TiCh )所構成之群組的至少1種來作爲 形成該透光性電極的材料。 10. 如申請專利範圍第6或7項之三族氮化物半導體發光元 件之製造方法，其中該透光性電極形成製程係使用氧化 矽（Si〇2)來作爲形成該絕緣層的材料。 1 1 _ 一種燈’係使用如申請專利範圍第丨或2項之三族氮化 物半導體發光元件所構成。201114065 VII. Patent application scope: 1. A group III nitride semiconductor light-emitting device, which is formed on a single-crystal group III nitride semiconductor layer formed on a substrate, and sequentially forms an n-type semiconductor layer, a light-emitting layer and The semiconductor layer of the Ρ-type semiconductor layer is formed by forming a translucent electrode on the p-type semiconductor layer, and at least a part of the Ρ-type semiconductor layer is provided with an insulating layer, and the translucent electrode is formed as Covering the insulating layer, a positive electrode bonding pad is disposed on the surface of the translucent electrode above the insulating layer provided on the germanium-type semiconductor layer, and a sheet resistance of the translucent electrode is higher than that of the n-type semiconductor layer The sheet resistance is also low. 2. The group III nitride semiconductor light-emitting device according to claim 1, wherein the sheet resistance of the light-transmitting electrode is 15 Ω/□ or less, and the sheet resistance of the η-type semiconductor layer is 20 Ω /□ or less. 3. The group III nitride semiconductor light-emitting device according to claim 1 or 2, wherein at least a part of the surface of the light-transmitting electrode has a concavo-convex shape. 4. The group III nitride semiconductor light-emitting device according to claim 1 or 2, wherein the light-transmitting electrode is selected from the group consisting of indium tin oxide (Indium Tin Oxide) and indium zinc oxide (IZO: Indium). At least one of a group consisting of Zinc Oxide, Indium Gallium Oxide, Indium Cerium Oxide, and Conductive Titanium Oxide (TiCh). -61- 201114065 5. The group III nitride semiconductor light-emitting device according to claim 1 or 2, wherein the insulating layer is made of yttrium oxide (SiOO). 6. Manufacture of a group III nitride semiconductor light-emitting device. The method comprises: an epitaxial process for forming a single-crystal Group III nitride semiconductor layer on a substrate; and a semiconductor layer forming process for sequentially depositing an n-type semiconductor layer, a light-emitting layer, and the light-emitting layer on the group III nitride semiconductor layer a p-type semiconductor layer to form a semiconductor layer; and a translucent electrode forming process for forming a translucent electrode on the p-type semiconductor layer; wherein the transmissive electrode forming process is formed by forming an insulating layer thereon After at least a part of the p-type semiconductor layer, the transparent electrode is formed on the germanium-type semiconductor layer so as to cover the insulating layer, and a positive electrode forming process is provided, after the transparent electrode forming process is performed. In the surface of the translucent electrode, a positive electrode bonding pad is formed over the insulating layer formed on the p-type semiconductor layer, and further, the translucent electrode is formed into a process system The translucent electrode is formed such that the sheet resistance of the translucent electrode is lower than the sheet resistance of the n-type semiconductor layer. 7. The method for manufacturing a group III nitride semiconductor light-emitting device according to claim 6 The translucent electrode forming process is such that the translucent electrode is formed so that the sheet resistance is 15 Ω/□ or less, and the semiconductor layer is formed into a process such that the sheet resistance is 20 Ω /□ or less to form the n-type. The method of manufacturing a semiconductor wafer layer according to claim 6 or claim 7, wherein the translucent electrode forming process is at least a part of the surface of the translucent electrode 9. The method for producing a trigonal nitride semiconductor light-emitting device according to claim 6 or 7, wherein the translucent electrode forming process is selected from the group consisting of indium tin oxide (ITO: Indium Tin) Oxide), Indium Zinc Oxide, Indium Gallium Oxide, Indium Cerium Oxide, and Conductive Titanium Dioxide At least one of the group is formed as a material for forming the light-transmitting electrode. 10. The method for producing a group III nitride semiconductor light-emitting device according to claim 6 or 7, wherein the light-transmitting electrode is formed The process uses yttrium oxide (Si〇2) as a material for forming the insulating layer. 1 1 _ A lamp' is constructed using a group III nitride semiconductor light-emitting element as described in claim 2 or 2.
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