201110121 六、發明說明： 【相關申請案之交又參考】 本美國非臨時專利申請案是2〇1〇年2月2曰申嘖之 第.58,072號美國專利申請案之部分接續案，其在％ U.S.C. § 119下主張2009年9月3日申請之第 10_2009-0083148號韓國專利申請案以及2〇1〇年、月25 曰申請之第10-2010-0006475號韓國專利申請案之優先 權，所述韓國專利申請案之整個内容以引用方式併入本文。 【發明所屬之技術領域】 本發明概念是關於半導體元件，且更特定而言是關於 具有垂直結構之非揮發性記憶體元件及其操作方法。 【先前技術】 雖然電子元件之尺寸已變得持續減小，但其仍需處理 大量資料。因此，為減小尺寸且同時維持或改良處理能力， 用於在此等電子元件中使用之非揮發性記憶體元件需減小 尺寸’同時增加其整合程度（integration degree)。為此， 已考慮具有垂直結構之非揮發性記憶體元件代替具有習知 平坦結構之非揮發性記憶體元件。然而，具有垂直結構之 非揮發性記憶體元件製造起來較為複雜，因此其可靠性往 往低於具有平坦結構之較習知記憶體元件。 【發明内容】 根據本發明，提供一種具有垂直結構之非揮發性記憶 體元件及可增強記憶體元件之可靠性的其操作方法。 根據本發明概念之一態樣，提供一種操作非揮發性記 4 201110121 憶體70件之方法。所述方法包含：將接通電壓施加於第一 NAND串之第一串選擇電晶體及第二串選擇電晶體中之每 一者’將第—電壓及第二電壓分別施加於第二NAND串之 第三串選擇電晶體及第四串選擇電晶體；以及將高電壓施 加於與所述第一 NAND串及第二NAND串之記憶體單元 連接之字線。 所述第二電壓可具有高於所述第一電壓之位準。 所述第一電攀可具有低於接地電壓之位準。 所述第二電壓可具有低於所述第四串選擇電晶體之 臨限電壓的位準。 所述第三串選擇電晶體可連接於所述第四串選擇電 晶體與對應於所述第二NAND串之位元線之間。 操作非揮發性記憶體元件之方法可更包括：將第二高 電壓施加於第一至第四串選擇電晶體與所述記憶體單元之 間的虛设早元，其中所述第二高電壓具有低於所述高電壓 之位準。 根據本發明概念之另一態樣，提供一種非揮發性記憶 體元件。所述非揮發性記憶體元件包含：記憶體單元陣列； 以及周邊電路，其經組態以存取所述記憶體單元陣列。所 述記憶體單元陣列包含：基板；多個記憶體單元群，其在 所述基板上以列及行配置。每一記憶體單元群包含沿與所 述基板交叉之方向堆疊之多個記憶體單元；多個第一選擇 電晶體群，其分別提供於所述基板與所述多個記憶體單元 群之間·，以及多個第二選擇電晶體群，其分別提供於所述 201110121 2記憶體單元群上。所述周邊電路可經組態以在程式化 ^作期間獨立地驅動對應於所述多個記憶體單it群之未選 定記憶體單辑的第二選擇電晶體群之第二選擇電晶體。 、所^邊電路可進—步經組態以在程式化操作期間 •選擇電 以不同電麵動所述第二選擇電晶體群之所述第 晶體。 在程式化操作期間，所述第二選擇電晶體群之特 二選擇電晶體可以第-電壓驅動，且所述第二選擇 定第1擇電晶體與所述未選定‘體 夺兀之的另一第二選擇電晶體可以高於所述第一電屋 之第二電壓驅動。 ^ 艮據本發明概念之再—態樣’提供—種記憶體系統。 所述記憶體系統包含：非揮發性記憶體元件；以及控制器， 其經組態讀制所料揮發性記紐元件。所述非揮發性 記憶巧件包含記‘_單元陣列錢經_轉取所述記 憶體單7L_之周邊電路。所述記紐單猶列包含具有 3維結構之㈣記賴單元m_單元串包含提 供於-側之至少兩個第—選擇電晶體及提供於另一側之至 ^個第—選擇電晶體。所述周邊電路可經組態以在程式 化操作期間以不同電壓驅動所述多個記憶體單元串之未選 定記憶體單元串之所述至少兩個第二選擇電晶體。 【實施方式】 下文中’將參見附圖較完整地描述本發明概念之例示 性實施例。然而’本發明概念可以許多不同形式體現，且 201110121 不應闡釋為限於本文陳述之實施例。實情為，提供此等實 施例以使得本發明將本發明概念傳達於熟習此項技術者。 在圖中，可為清楚而誇大每一組件之尺寸。 以下實_巾使狀術語可_為在本發明概念所 從屬之技術領域中大體是已知的。舉例而言，術語「至少 -」包含相關聯所列出項目中之—或多者 含單數形式且亦包含複數形式。# 將瞭解’雖然本文使用術語第一、第二等來描述各種 組件，但此等組件不應由此等術語限制。此等術語用以使 -個組件區別於另-組件’但不意謂要求的組件序列。舉 例而言，在不背離本發明之範#的情況下，第一組件可稱 為第二組件，且類似地，第二組件可稱為第一組件。如本 文使用’術語「及/或」包含相關聯列出項 t的任一及所有組合。 a夕者 將瞭解，當將一組件稱為「在另一組件上」或者「連 接」或「輕接」至另-組件時，其可直接在所述另一 上或者連接或祕至所似—組件，財存在介入组件。 相比而言，當將一組件稱為「直接在另一組件上」或者「首 接連接至」或「直接耗接至」另—組件時，不存在介入組 件。用以描述組件之間的關係的其它詞語應以類似方式解 譯（例如，「在…之間I射「首桩4日日「出 「直接鄰近於」等）。接在··之間」、鄰近於」對 本文使用之術語是僅用於描述特定實施例之目的且 不欲限制本發明。如本文使用，單數形式「一」及「所述 7 201110121 複數形式，除非上下文另外明確指示。將進一 2特括」及/或「包含」在本文中使用時指定 ☆-或t甘 操作、組件及/或零叙存在，但不排 :存在ΐ添加它特徵、步驟、操作、組件、零件及/或其群 ，如「在.·,τ方」、「在··.之下」、「下部」、「在·..···上 部」及類似術語之空間相對術語可用以描述一组 件及或特徵與另-組件及/或特徵之關係，例如圖中所說 明°將瞭解’空間相對術語意欲涵蓋除®中描％之定向;卜 兀件在使用及/或操作中之不同定向。舉例而言，若圖中之 70,翻轉，則描述為「在其它組件或特徵之下」及/或「在 ，，組件或特徵下方」之組件將定向於所述其它組件或特 徵上^」。元件可以其它方式定向（例如，旋轉90度或 處於其匕定向），且相應地解譯本文使用之空間相對描述詞 圖1是根據本發明概念之實施例之非揮發性記憶體元 件的電路圖。參見圖1，一 NAND串NS可在垂直方向上 延伸，亦即，其可具有相對於基板（未圖示）之垂直結構。 NAND串NS可具有至少-對串選擇電晶體TS1及TS2、 多個記憶體單元MC以及至少_對接地選擇電晶體T G!及 TG2。位元線BL可連接至NAND串NS之一端，且共源 極線CSL可連接至ΝΑΝΕ)串NS之另一端。 記憶體單元MC可在垂直方向上串列配置。記憶體單 元MC可儲存資料。多個字線WL0、WL1至WLn-Ι以及 8 201110121 WLn (其中「η」+1為字線之數目）可分別耦接至記憶體 單元MC，以便控制記憶體單元MC。記憶體單元Mc之 總數可根據非揮發性記憶體元件之容量來判定。 串選擇電晶體TS1及TS2可配置於記憶體單元MC之 一端附近。舉例而言，串選擇電晶體TS1及TS2可位於位 元線BL與§己憶體單元MC之間，且可串列連接至記憶體 單元MC。串選擇電晶體TS1及TS2可控制位元線Bl與 記憶體單元MC之間的信號交換。第一串選擇線SSLi可 耦接至第一串選擇電晶體TS1 ,且第二串選擇線SSL2可 麵接至第二串選擇電晶體TS2。因此，第一串選擇電晶體 TS1及第二串選擇電晶體TS2可分離且獨立地操作。 至少一對第一接地選擇電晶體TG1及第二接地選擇 電晶體TG2可彼此鄰近配置於NAND串NS的一端處，所 述一端與記憶體單元MC之另一側處之串選擇電晶體 TS1、TS2相對。舉例而言，接地選擇電晶體TG1、TG2 可位於共源極線CSL與記憶體單元MC之間，且可與記憶 體單το MC串列連接。第一接地選擇線GSU可耦接至第 一接地選擇電晶體TG1，且第二接地選擇線GSL2可耦接 至第二接地選擇電晶體TG2。因此，第一接地選擇電晶體 TG1及第二接地選擇電晶體TG2可分離且獨立地操作。在 此實施例之經修改實例中，第_接地選擇電晶體TG1及第 一接地選擇電晶體TG2可耦接至單一接地選擇線gSl。 下文中’將描述可與非揮發性記憶體元件之此實施例 一起使用之操作方法的實施例。 201110121 在此實例中，對於程式化操作，可將〇v或操作電壓 施加於位元線BL，且可將〇 ν施加於共源極線GSL。當 將〇 V施加於位元線BL時，選擇此NAND串Ns用於程 式化。然而，當將操作電壓施加於位元線B]L時，藉由通 道升壓（channel boosting)防止對此NAND串NS之程式 化。 可將程式化電壓施加於記憶體單sMC中之選擇記憶 體，且可將傳送電壓（passv〇ltage)施加於其餘記憶 體早元傳送電廢可低於程式化電壓，且可高於記憶體單 元MC之臨限電壓。可選擇程式化電壓以便藉由f_n“穿隧 (F-N tunneling)將電荷注入記憶體單元MC。 可將關斷電壓（斷開電壓）施加於第一接地選擇線 GSL1及第二接地選擇線GSL2。可將第一電壓施加於直接 鄰^於記憶體單元MC之第二串選擇線SSL2,且可將第二 電壓施加於直接鄰近於位元線BL之第一串選擇線ssu。 第一電壓可選擇為儘可能低，以便在接通第一串選擇電晶 體的同時降低斷開電流。舉例而言，第二電壓可高於戋等 於第一串選擇電晶體TS1之臨限電壓，且可等於前述操 電壓。 可選擇第一電壓以減小第二串選擇電晶體TS2與鄰 近於其之記憶體單元MC之間的電壓差。舉例而言，/第一 電，可實質上等於傳送電壓。因此’藉由將第—電壓設定 為高於第二電壓、藉由減小傳送電壓與第一電壓之間的 差，可防止產生至鄰近於記憶體單元MC2第二串選擇電 201110121 且因此降低通道升壓 晶體 TS2 之漏電流（leakage current) 效率的情形。 在非揮發性記憶體元件之操作方法之此實施例 雷曰獨立地操作第—_選擇電晶體TS1及第二串選擇 電B日TS2 ’可同時減小斷開電流及漏電流。將參見圖2 至圖4更詳細描述用以防止賴的功能。 為，行讀取操作，可將讀取電壓施加於㈣線BL， 且可將接通」電壓施加於串選擇線SSL1&SSL2以及接 ，選擇線GSL1及GSL2。可將參考電壓施加於選自記憶體 t Γ之記憶體單元Mc，且可將傳送電龍加於其 匕5己憶體早。 為執行抹除操作，可將抹除電壓施加於記憶體單元 MC之主體’且可將G v施加於字線WLG、WL1至WLn-l 以及u此，可同時自記憶體單元Mc抹除資料。 圖2是根據本發_念之另-實闕之麵發性記憶 體疋件之電路®。® 2之轉雜記憶體元件可對應於諸 如圖1所示之多個非揮發性記憶體元件的陣列。因此，此 處將不提㈣期1巾柄之組件之操作或雜的描述。 參見圖2，具有垂直結構之多個NAND串NS11、 NS12、NS2卜NS22可以矩陣組態配置。第一位元線BU 可共同連接至配置於第一行中之NAND串NSU、NS21中 之每一者的一端，且第二位元線BL2可共同連接至配置於 第二行中之NAND串NS12、NS22中之每一者的一端。共 源極線CSL可共同連接至NAND串NS11、NS12、NS21、 201110121 NS22之與第一位元線BL1及第二位元線BL2相對之另一 端。NAND串NS11、NS12、NS21、NS22之數目及位元 線BL1、BL2之數目是例示性繪示，且不限制此實施例或 本發明之範疇。 字線WL0、WL1、…WLn-1、WLn可與配置於其各 別層中之記憶體單元MC共同連接。第一串選擇線ssl 1 可共同輕接至配置於第一列上之NAND串NS11、NS12之 第一串選擇電晶體TS1。第二串選擇線SSL2可共同耦接 至配置於第一列中之NAND串NS1卜NS12之第二串選擇 電晶體TS2。第三串選擇線SSL3可共同麵接至配置於第 二列中之NAND串NS11、NS12之第一串選擇電晶體 TSl〇第四串選擇線SSL4可共同耦接至配置於第二列中之 NAND串NS11、NS12之第二串選擇電晶體TS2。 第一接地選擇線GSL1可共同耦接至配置於第一列上 之NAND串NS11、NS12之第一接地選擇電晶體tgi。第 二接地選擇線GSL2可共同耦接至配置於第一列中之 NAND串NSU、NS12之第二接地選擇電晶體TG2。第三 接地選擇線GSL3可共同耦接至配置於第二列上之NAND 串Nsn、Nsi2之第一接地選擇電晶體1^1。第四接地選 擇線GSL4可共同耦接至配置於第二列中之NAND串 NSU、NS12之第二接地選擇電晶體TG2。 為執行程式化操作，可將0V施加於選自位元線BL1 及BL2之位元線，且可將「接通」電壓（接通電壓）施加 於另一位元線BL1或BL2以用於通道升壓。而且，可將 12 201110121 「接通」電壓施加於選自串選擇線SSL1至SSL4之串選擇 線，且可將「斷開」電壓施加於另一串選擇線SSL1及SSL2 或SSL3及SSL4〇因此’可選擇性地操作共同連接至選定 位兀線及來自NAND串NSU、NS12、NS21以及NS22中 之串選擇線的NAND串。 為執行讀取操作，可將讀取電壓施加於選自位元線 BL1及BL2之位元線’且另一位元線BU或BL2可浮動。 而且’可將「接通」電壓施加於選自串選擇線SSL1至SSL4 之串選擇線’且可將「斷開」電慶施加於另一串選擇線Mu 及SSL2或SSL3及SSL4。因此，可選擇性地操作共同連 接至選^位元線及來自NAND串Nsu、順2、NS2l以 &NS22中之串選擇線的ΝΑΝΕ)串。 為執行抹除操作，可將抹除電壓施加於記憶體單元 MC之主體’且可將0 V施加於字線WL0、WL1至WLn-1 以及WLn。因此’可同時自NAND串NS1卜NS12、NS21 以及NS22之記憶體單元MC抹除資料。 圖增示當在圖2之記憶體元件中執行程式化操作時 的電壓偏置條件。在此程式化操作實例中，蚊配置於第 -列中之第-NAND串NS11中之記憶體單元中的一者經 程式化。亦即，假定配置於第一列及NAND中之第二 NAND $ NS及配置於第二列中之NAND串順卜N 被避免程式化。 見圖2及圖3，由於配置於第一列中之第一 NAND 串NS11中之記憶體單元經程式化，因此將接地電壓να 13 201110121 供應至與第一 NAND串NS11連接之第一位元線BL1。第 二列之第一 NAND串NS21亦與接地電壓Vss提供至之第 一位元線BL1連接。 由於配置於第一列中之第二NAND串NS12被避免程 式化’因此將電源電壓Vcc供應至與第二NAND串NS12 連接之第二位元線BL2。第二列之第二NAND串NS22亦 與電源電壓Vcc供應至之第二位元線BL2連接。 由於第一列之第一 NAND串NS11經程式化，因此將 接通電壓供應至與第一 NAND串NS11連接之第一串選擇 線SSL1及第二串選擇線SSL2。接通電壓可為用以接通第 一 NAND串NS11之第一串選擇電晶體TS1及第二串選擇 電晶體TS2的電壓。舉例而言，接通電壓可為電源電壓 Vcc。 第一列之第二NAND串之第一串選擇電晶體TS1及 第二串選擇電晶體TS2亦分別與第一選擇線SSL1及第二 選擇線SSL2連接。因此，第一列之第二NAND串之第一 串選擇電晶體TS1及第二串選擇電晶體TS2接通。 第二列之第一 NAND串NS21及第二NAND串NS22 被避免程式化。舉例而言，將斷開電壓供應至第三串選擇 線SSL3及第四串選擇線SSL4。斷開電壓是用以斷開第一 NAND串NS21及第二NAND串NS22之第一串選擇電晶 體TS1及第二串選擇電晶體TS2的電壓。舉例而言，斷開 電壓是接地電壓Vss。 將程式化電壓Vpgm及傳送電壓Vpass供應至字線 201110121 WLO-WLn。舉例而言，將程式化電壓Vpgm供應至與選定 5己憶體單元連接之字線。將傳送電壓Vpass供應至與未選 定記憶體單元連接之字線。程式化電壓Vpgm及傳送電壓 Vpass在此實施例中為高電壓’例如8伏或8伏以上。 藉由施加於字線WLO-WLn之高電壓（vpgm及Vpass ) 在配置於第二列中之第一 NAND串NS21及第二NAND串 NS22之記憶體單元中形成通道。所形成通道之電壓由高 電壓（Vpgm及Vpass)升壓。此時，將接地電壓Vss施加 於配置於第二列中之第一 NAND串N s 2丨及第二NAND串 NS22之第二串選擇電晶體TS2之閘極。因此，由於第一 NAND串NS1及第二NAND串NS22之第二串選擇電晶體 TS2之閘極電壓（例如，接地電壓Vss)與汲極電壓（例 如，經升壓之通道電壓）之間的電壓差，可產生閘極引發 没極洩漏（gate induced drain leakage，GIDL )。 而且’將接地電壓Vss施加於與配置於第二列中之第 二NAND串NS22連接之第二位元線BL2。由於與第二 NAND串NS22連接之位元線電壓（例如，接地電壓vss) 與經升壓之通道電壓之間的電壓差，可能會產生第二 NAND串NS22中之額外洩漏。 為解決上述限制’提供根據本發明概念之實施例的控 制記憶體元件之_選擇線之電壓的方法。@此，可控制茂 漏電流。 圖4疋繪不根據本發明概念之實施例之控制電壓之方 法之結果的表。參見圖2及圖4,將第三電壓V3供應至第 15 201110121 三串選擇線SSL3。亦即，將第三電壓V3施加於配置於第 二列中之第一 NAND串NS21及第二NAND串NS22之第 一串選擇電晶體TS1之閘極。舉例而言，第三電壓V3是 用以斷開第一 NAND串NS21及第二NAND串NS22之第 一串選擇電晶體TS1的電壓。 將第四電壓V4供應至第四串選擇線SSL4。亦即，將 第四電壓V4施加於配置於第二列中之第一 NAND串NS21 及第二NAND串NS22之第二串選擇電晶體TS2之閘極。 舉例而言，第四電壓V4是用以斷開第一 NAND串NS21 及第二NAND串NS22之第二串選擇電晶體TS2的電壓。 在第一 NAND串NS21及第二NAND串NS22之第四 電壓V4與經升壓之通道電壓之間的差減小時，在第一 NAND串NS21及第二NAND串NS22之第二串選擇電晶 體TS2中可產生之閘極引發汲極茂漏（gate in(juced drain leakage，GIDL)減小。第四電壓V4之位準經設定以防止 或減小第一 NAND串NS21及第二NAND串NS22之第二 串選擇電晶體TS2中產生之GIDL。舉例而言，第四電壓 V4可具有高於接地電壓Vss之位準。舉例而言，第四電壓 V4可具有接地電壓Vss與第二串選擇電晶體TS2之臨限 電壓之間的位準。 第三電壓V3之位準越低，經由第一 NAnd串ν§21 及第二NAND串NS22之第一串選擇電晶體tsi洩漏至位 元線BL1、BL2之電荷越少。第三電壓v〗之位準可經設 定以防止或減小經由第一 NAND串NS21及第二NAND串 201110121 NS22之第一串選擇電晶體TS1的茂漏。舉例而言，第三 電壓V3可具有低於接地電壓vss之位準。 如上所述，若供應至配置於與經程式化之NAND串 (例如，NS11)不同之列中之NAND串（例如，NS21、 NS22)之串選擇線（例如，ssu、SSL4)的電壓之位準 經控制，則防止或減小可在配置於與經程式化之NAND串 (例如，NS11)不同之列中之NAND串（例如，m21、 NS22)..中產生之戌.漏。因此，增強記憶體元件之可靠性。 而且，在維持洩漏量，即維持記憶體元件之可靠性的 同時，可升高供應至鄰近於串選擇電晶體TS1、TS2之字 線之電壓的位準。亦即，在維持記憶體元件之可靠性的同 時，可增強鄰近於串選擇電晶體TS1、TS2之字線的電壓 窗。 在圖4中，已描述第四電壓V4為斷開電壓。然而， 第四電壓V4可為用以接通配置於第二列中之第一 nand 串NS21及第二NAND串NS22之第二串選擇電晶體TS2 的電壓。舉例而言，第四電壓V4可具有高於第一 ναν〇 串NS21及第二NAND串NS22之第二串選擇電晶體TS2 之臨限電壓的位準。舉例而言，第四電壓V4可具有低於 傳送電壓Vpass之位準。第四電壓V4可具有等於傳送電 壓Vpass之位準。第四電壓V4可具有高於傳送電壓外咖 之位準。 圖5是根據本發明概念之實施例之沿圖2之非揮發性 記憶體元件之位元線方向截取的示意截面圖。參見圖5, 17 201110121 串選擇閉電極〗66可經由接觸插塞（⑺衡plug) i74分 別與第-串選擇線SSL1及第二串選擇線现2連接。接地 選擇間電極162可經由接觸插塞17〇分別與第一接地選擇 線GSL1及第二接地選擇線GSL2連接。 圖6是根據本發明概念之另一實施例之沿圖2之非揮 發性記憶體元件的位元線方域取之示意截面圖。為簡單 描述，省略NAND串陣列部分。參見圖6，接地選擇閘電 極162經由NAND串陣列之一側處的接觸插塞17〇、171 分別與第-接地選擇線GSL1及第二接地選擇線GSL2連 接。而且，控制閘電極164經由NAND串陣列之一侧處的 接觸插塞172分別與字線WLO-WLn連接。串選擇間雷極 動由接觸插塞Π5、176分別與第，串擇 第二串選擇線SSL2連接。 作為實例，串選擇線SSL1、SSL2、字線WLO-WLn 以及接地選擇線GSL1、GSL2可形成於同一層上。舉例而 言，串選擇線SSU、SSL2、字線WLO-WLn以及接地選 擇線GSL1、GSL2可形成於金屬層中。舉例而言，串選擇 線SSL1、SSL2、字線WLO-WLn以及接地選擇線gsLI、 GSL2可形成於金屬〇層或金屬1層中。 圖7是根據本發明概念之再一實施例之沿圖2之非揮 發性記憶體元件之位元線方向截取的示意截面圖。比較圖 7之示意截面圖與圖6之示意截面圖，在圖7中，第一 _ 選擇線SSL1及第二串選擇線SSL2形成於不同層中。作為 實例，第一串選擇線SSL1形成於其中形成第二串選擇線 201110121 SSL2之層上方的層中。舉例而言，第一串選擇線SSL1形 成於金屬1層上。第二串選擇線SSL2形成於金屬〇層上。 圖8是根據本發明概念之另一實施例之沿圖2之非揮 發性s己憶體元件之位元線方向截取的示意截面圖。比較圖 8之不意截面圖與圖7之示意截面圖，在圖8中，字線 WL(MVLn、接地選擇線GSL1、GSL2以及第一串選擇線 SSL1形成於同一層中。舉例而言，字線nwLn、接地 選擇線GSU、GSL2以及第一串選擇線形成於金屬1層 令。第二串選擇線SSL2形成於第一串選擇線SSL1下方的 層中。舉例而言，第二選擇線SSL2形成於金屬〇層中。 圖9是根據本發明概念之另一實施例之沿圖2之非揮 發性記憶體元件之位元線方向戴取的示意截面圖。比較圖 9之示意截面圖與圖8之示意截面圖，在圖9中，接地選 擇閘電極162與單一接地選擇線GSl連接。亦即，接地選 擇電晶體TGI、TG2與接地選擇線GSL·共同連接。 第一串選擇線SSL1、字線WL0_WLn以及接地選擇線 GSL形成於同一層中。舉例而言，第一串選擇線SSL1、 子線WLO-WLn以及接地選擇線gsl形成於金屬1層中。 第二串選擇線SSL2形成於第一串選擇線SSL1下方的層 中。舉例而言，第二選擇線SSL2形成於金屬〇層中。 圖10是根據本發明概念之另一實施例之非揮發性記 憶體元件的電路圖。與圖2所示之記憶體元件相比，為圖 10所示之記憶體元件的選擇電晶體TS1、TS2、TG卜TG2 (類似於記憶體單元）提供電荷儲存層。亦即，選擇電晶體 19 201110121 TSl ' TS2、TGI、TG2及記憶體單元具有相同結構。作為 實例’提供至選擇電晶體TSh TS2、TGI、TG2及記憶體 單元之電射儲存層可為電荷捕集層（charge打叩iayer)。 圖11是說明根據本發明概念之再一實施例之非揮發 性δ己憶體το件的電路圖。與圖1〇之非揮發性記憶體元件相 比，圖11之非揮發性記憶體元件更包括位於串選擇線 SSL1至SSL4與正常字線乳〇至WLn之間的虛設 (dummy)子線dwl。在一實施例中，可在程式化操作期 間將虛設傳送電壓施加於虛設字線DWL中。舉例而言， 虛設傳送電壓之位準可低於正常傳送電壓之位準。 在一實施例中，可於串選擇線SSL1至SSL4與正常 字線至0WLn之間提供_或兩個以上虛設字線。 圖12是說明根據本發明概念之再一實施例之非揮發 性記憶體it件的電路圖，圖1Q之非揮發性記憶體元件相 比，圖12之非揮發性記憶體元件更包括位於接地選擇線 GSL1至GSL4與正常字線肌〇至in之間的虛設字線 =WL。在-實袖巾，可在喊化操作朗將虛設傳送電 壓施加於纽钱DWL卜舉_言，虛財線dwl 之位準可低於正常傳送電壓之位準。 在一實施财，可於接地選擇線GSL1至GSL4與正 常字線漏3至WLn之間提供兩個或兩個以上虛設字線。 圖13是說明根據本發明概念之另一實施例之非揮發 ^己憶體70件的電路圖。與圖1G之非揮發性記憶體元件相 t，圖I3之非揮發性記憶體元件更包括位於串選擇線 20 201110121 SSL1至SSL4與正常字線WL0至WLn之間的第一虛設字 線DWL1以及位於接地選擇線GSU至GSM與正常字線 WL0至WLn之間的第二虛設字線dWL2。在一實施例中， 可在程式化操作期間將虛設傳送電壓施加於第一虛設字線 DWL1及第二虛設字線DWL2巾。舉例而言，虛設傳送電 壓之位準可低於正常傳送電壓之位準。 —在一實施例中，可於串選擇線SSL1至SSL4與正常 子線WL0至WLn之間提供兩個或兩個以上虛設字線。在 一實施例中，可於接地選擇線GSL1至GSL4與正常字線 WL0至WLn之間提供兩個或兩個以上虛設字線。 圖Η是說明根據本發明概念之另一實施例之包含非 揮發性記憶體it件之記憶體树綱的示意方塊圖。參見 f Η ’ NAND單元陣列250可與核心電路單元27〇耦接。 舉例而言，NAND單元陣列25〇可包含參見圖j至圖13 描述之非揮發性s己憶體元件。核心電路單元謂可包含控 :ϋ271、列解碼器272、行解碼器奶、感測放大器274 及/或頁緩衝器275。 制邏輯271可與列解碼器272、行解碼器273及/ 275通化。列解碼器272可經由串選擇線飢、201110121 VI. Description of the invention: [Reference to the relevant application] This non-provisional patent application in the United States is part of the continuation of US Patent Application No. 58,072 of February 2, 2011. % USC § 119 cites the Korean Patent Application No. 10_2009-0083148, filed on September 3, 2009, and the Korean Patent Application No. 10-2010-0006475, filed on September 3, 2012, The entire content of the Korean Patent Application is hereby incorporated by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor elements, and more particularly to non-volatile memory elements having a vertical structure and methods of operating the same. [Prior Art] Although the size of electronic components has been continuously reduced, it still needs to process a large amount of data. Therefore, in order to reduce the size while maintaining or improving the processing capability, the non-volatile memory elements used in such electronic components are required to be reduced in size while increasing their degree of integration. For this reason, non-volatile memory elements having a vertical structure have been considered in place of non-volatile memory elements having a conventional flat structure. However, non-volatile memory elements having a vertical structure are relatively complicated to manufacture, and thus their reliability is often lower than that of conventional memory elements having a flat structure. SUMMARY OF THE INVENTION In accordance with the present invention, a non-volatile memory component having a vertical structure and a method of operating the same that enhances the reliability of the memory component are provided. According to one aspect of the inventive concept, a method of operating a non-volatile memory 70 piece is provided. The method includes applying a turn-on voltage to each of a first string selection transistor and a second string selection transistor of a first NAND string to apply a first voltage and a second voltage to a second NAND string, respectively a third string selection transistor and a fourth string selection transistor; and a high voltage applied to the word lines connected to the memory cells of the first NAND string and the second NAND string. The second voltage may have a higher level than the first voltage. The first electric climb may have a level lower than a ground voltage. The second voltage may have a lower level than a threshold voltage of the fourth string of select transistors. The third string selection transistor can be coupled between the fourth string selection transistor and a bit line corresponding to the second NAND string. The method of operating a non-volatile memory component can further include: applying a second high voltage to a dummy early element between the first to fourth string selection transistors and the memory cell, wherein the second high voltage Has a level lower than the high voltage. According to another aspect of the inventive concept, a non-volatile memory component is provided. The non-volatile memory component includes: an array of memory cells; and peripheral circuitry configured to access the array of memory cells. The memory cell array includes a substrate and a plurality of memory cell groups arranged in columns and rows on the substrate. Each memory cell group includes a plurality of memory cells stacked in a direction crossing the substrate; a plurality of first selected transistor groups respectively provided between the substrate and the plurality of memory cell groups And a plurality of second selection transistor groups respectively provided on the 201110121 2 memory cell group. The peripheral circuitry can be configured to independently drive a second selection transistor of the second selected transistor group corresponding to the unselected memory banks of the plurality of memory single-groups during the programming. The circuit can be stepped in to be configured to operate the first crystal of the second selected transistor group with different electrical faces during the stylizing operation. During the stylization operation, the second selection transistor of the second selected transistor group may be driven by a first voltage, and the second selection determines the first electrification crystal and the unselected 'body' A second selection transistor can be driven above the second voltage of the first electrical house. ^ A memory system is provided in accordance with the concept of the present invention. The memory system includes: a non-volatile memory component; and a controller configured to read the desired volatile token component. The non-volatile memory component includes a peripheral circuit that records the __cell array _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The memorandum includes a three-dimensional structure (4). The m_cell string includes at least two first-selective transistors provided on the - side and the first-selective transistors provided on the other side. . The peripheral circuitry can be configured to drive the at least two second select transistors of the unselected memory cell strings of the plurality of memory cell strings at different voltages during a program operation. [Embodiment] Hereinafter, exemplary embodiments of the inventive concept will be described more fully with reference to the accompanying drawings. However, the inventive concept may be embodied in many different forms, and 201110121 should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention conveys the inventive concept to those skilled in the art. In the figures, the dimensions of each component can be exaggerated for clarity. The following terms can be generally known in the art to which the concepts of the present invention pertain. For example, the term "at least -" includes one or more of the items listed in the associated list, and also includes the plural. # will understand 'Although the terms first, second, etc. are used herein to describe various components, such components are not limited by such terms. These terms are used to distinguish one component from another component, but do not imply a required component sequence. For example, a first component may be referred to as a second component without departing from the scope of the invention, and similarly, a second component may be referred to as a first component. The use of the terms 'and/or' as used herein includes any and all combinations of the associated listed items. A eve will understand that when a component is referred to as "on another component" or "connected" or "lightly connected" to another component, it may be directly on the other or connected or secretly - Components, financial presence intervention components. In contrast, when a component is referred to as "directly on another component" or "first connected to" or "directly connected to" another component, there is no intervening component. Other words used to describe the relationship between the components should be interpreted in a similar manner (for example, "between I" in the first 4 days, "directly adjacent to", etc.). The terminology used herein is used to describe a particular embodiment and is not intended to limit the invention. As used herein, the singular forms "a" and "said 7 201110121 plural forms, unless the context clearly dictates otherwise. "2" and / or "include" are used in this document to specify ☆- or t-operations, components And / or zero, but not: there are ΐ add its features, steps, operations, components, parts and / or its group, such as "under .., τ side", "under ··.", " The spatially relative terms of the lower part, "in the upper part" and the like may be used to describe the relationship between a component and/or feature and another component and/or feature. For example, as illustrated in the figure, The term is intended to encompass the orientation of the % in addition to the orientation of the components; the different orientations of the components in use and/or operation. For example, if 70 is turned over, the components described as "under other components or features" and/or "under, under the components or features" will be directed to the other components or features. . The elements may be otherwise oriented (e.g., rotated 90 degrees or at their 匕 orientation) and the spatially relative descriptors used herein interpreted accordingly. Figure 1 is a circuit diagram of a non-volatile memory element in accordance with an embodiment of the inventive concept. Referring to Fig. 1, a NAND string NS may extend in a vertical direction, that is, it may have a vertical structure with respect to a substrate (not shown). The NAND string NS may have at least a pair of string selection transistors TS1 and TS2, a plurality of memory cells MC, and at least a pair of ground selection transistors T G! and TG2. The bit line BL can be connected to one end of the NAND string NS, and the common source line CSL can be connected to the other end of the string NS. The memory cells MC can be arranged in series in the vertical direction. The memory unit MC can store data. A plurality of word lines WL0, WL1 to WLn-Ι and 8 201110121 WLn (where "η"+1 is the number of word lines) may be coupled to the memory cells MC, respectively, to control the memory cells MC. The total number of memory cells Mc can be determined based on the capacity of the non-volatile memory components. The string selection transistors TS1 and TS2 can be disposed near one end of the memory cell MC. For example, the string selection transistors TS1 and TS2 may be located between the bit line BL and the § memory unit MC, and may be connected in series to the memory cell MC. The string selection transistors TS1 and TS2 control the signal exchange between the bit line B1 and the memory cell MC. The first string selection line SSLi may be coupled to the first string selection transistor TS1, and the second string selection line SSL2 may be coupled to the second string selection transistor TS2. Therefore, the first string selection transistor TS1 and the second string selection transistor TS2 can be operated separately and independently. At least one pair of first ground selection transistor TG1 and second ground selection transistor TG2 may be disposed adjacent to each other at one end of the NAND string NS, the one end and the string selection transistor TS1 at the other side of the memory cell MC TS2 is relative. For example, the ground selection transistors TG1, TG2 may be located between the common source line CSL and the memory cell MC, and may be connected in series with the memory single το MC. The first ground select line GSU can be coupled to the first ground select transistor TG1, and the second ground select line GSL2 can be coupled to the second ground select transistor TG2. Therefore, the first ground selection transistor TG1 and the second ground selection transistor TG2 are detachably and independently operable. In a modified example of this embodiment, the first ground selection transistor TG1 and the first ground selection transistor TG2 may be coupled to a single ground selection line gS1. Hereinafter, an embodiment of an operation method that can be used with this embodiment of a non-volatile memory element will be described. 201110121 In this example, for a stylized operation, 〇v or an operating voltage can be applied to the bit line BL, and 〇ν can be applied to the common source line GSL. When 〇 V is applied to the bit line BL, this NAND string Ns is selected for conversion. However, when an operating voltage is applied to the bit line B] L, stylization of this NAND string NS is prevented by channel boosting. The stylized voltage can be applied to the selected memory in the memory single sMC, and the transfer voltage (passv〇ltage) can be applied to the remaining memory. The early transfer of the electrical waste can be lower than the stylized voltage and can be higher than the memory. The threshold voltage of the unit MC. The stylized voltage can be selected to inject charge into the memory cell MC by f_n "FN tunneling." The turn-off voltage (off voltage) can be applied to the first ground select line GSL1 and the second ground select line GSL2. The first voltage may be applied to the second string selection line SSL2 directly adjacent to the memory cell MC, and the second voltage may be applied to the first string selection line ssu directly adjacent to the bit line BL. The selection is as low as possible to reduce the off current while turning on the first string of selected transistors. For example, the second voltage may be higher than 临 equal to the threshold voltage of the first string selection transistor TS1 and may be equal to The first voltage can be selected to reduce the voltage difference between the second string selection transistor TS2 and the memory cell MC adjacent thereto. For example, /first power can be substantially equal to the transmission voltage. Therefore, by setting the first voltage to be higher than the second voltage, by reducing the difference between the transmission voltage and the first voltage, generation of the second string selection power 201110121 adjacent to the memory cell MC2 can be prevented and thus reduced Channel boost crystal The leakage current efficiency of the body TS2. In this embodiment of the operation method of the non-volatile memory element, the Thunder independently operates the first-select transistor TS1 and the second string selects the power B-day TS2' At the same time, the breaking current and the leakage current are reduced. The function for preventing the sag will be described in more detail with reference to Fig. 2 to Fig. 4. For the line reading operation, the reading voltage can be applied to the (four) line BL, and can be turned on. The voltage is applied to the string selection lines SSL1 & SSL2 and the select lines GSL1 and GSL2. The reference voltage may be applied to the memory unit Mc selected from the memory t ,, and the transmitting electric dragon may be applied to the 匕5 memory. To perform the erase operation, an erase voltage can be applied to the body of the memory cell MC' and G v can be applied to the word lines WLG, WL1 to WLn-1, and u, and the data can be erased from the memory cell Mc at the same time. . Fig. 2 is a circuit diagram of a face-to-face memory device according to the present invention. The switched memory component of ® 2 may correspond to an array of a plurality of non-volatile memory components as shown in FIG. Therefore, the operation or miscellaneous description of the components of the (four) period 1 handle will not be mentioned here. Referring to FIG. 2, a plurality of NAND strings NS11, NS12, NS2 NS22 having a vertical structure may be configured in a matrix configuration. The first bit line BU may be commonly connected to one end of each of the NAND strings NSU, NS21 disposed in the first row, and the second bit line BL2 may be commonly connected to the NAND string disposed in the second row One end of each of NS12 and NS22. The common source line CSL may be commonly connected to the other end of the NAND strings NS11, NS12, NS21, 201110121 NS22 opposite to the first bit line BL1 and the second bit line BL2. The number of NAND strings NS11, NS12, NS21, NS22 and the number of bit lines BL1, BL2 are illustrative and are not intended to limit the scope of this embodiment or the invention. The word lines WL0, WL1, ... WLn-1, WLn can be commonly connected to the memory cells MC disposed in the respective layers thereof. The first string selection line ssl 1 can be collectively connected to the first string selection transistor TS1 of the NAND strings NS11, NS12 arranged in the first column. The second string selection line SSL2 may be coupled to the second string selection transistor TS2 of the NAND string NS1 NS12 disposed in the first column. The third string selection line SSL3 can be commonly connected to the first string selection transistor TS1 and the fourth string selection line SSL4 of the NAND strings NS11 and NS12 arranged in the second column, and can be coupled to the second column. The second string of NAND strings NS11, NS12 selects transistor TS2. The first ground select line GSL1 can be commonly coupled to the first ground select transistor tgi of the NAND strings NS11, NS12 disposed on the first column. The second ground selection line GSL2 can be coupled to the second ground selection transistor TG2 of the NAND strings NSU, NS12 disposed in the first column. The third ground selection line GSL3 can be commonly coupled to the first ground selection transistor 1^1 of the NAND strings Nsn, Nsi2 disposed in the second column. The fourth ground selection line GSL4 can be commonly coupled to the second ground selection transistor TG2 of the NAND strings NSU, NS12 disposed in the second column. To perform the stylization operation, 0V can be applied to the bit line selected from the bit lines BL1 and BL2, and an "on" voltage (on voltage) can be applied to the other bit line BL1 or BL2 for Channel boost. Moreover, the 12 201110121 "on" voltage can be applied to the string selection line selected from the string selection lines SSL1 to SSL4, and the "off" voltage can be applied to the other string selection lines SSL1 and SSL2 or SSL3 and SSL4. The NAND strings that are commonly connected to the selected positioning line and the string selection lines from the NAND strings NSU, NS12, NS21, and NS22 are selectively operable. To perform the read operation, a read voltage may be applied to the bit line 'selected from the bit lines BL1 and BL2' and the other bit line BU or BL2 may float. Further, the "on" voltage can be applied to the string selection line 'selected from the string selection lines SSL1 to SSL4' and the "off" line can be applied to the other string selection lines Mu and SSL2 or SSL3 and SSL4. Therefore, the common connection to the selected bit line and the string from the NAND strings Nsu, 2, NS21 and the string selection lines in the & NS22 can be selectively operated. To perform the erase operation, an erase voltage can be applied to the body of the memory cell MC' and 0 V can be applied to the word lines WL0, WL1 to WLn-1, and WLn. Therefore, data can be erased simultaneously from the memory cells MC of the NAND strings NS1, NS21, and NS22. The figure shows the voltage bias conditions when the stylization operation is performed in the memory element of FIG. In this stylized operation example, one of the memory cells of the mosquito-disposed NAND string NS11 in the first column is programmed. That is, it is assumed that the second NAND$NS disposed in the first column and the NAND and the NAND string N arranged in the second column are prevented from being programmed. 2 and FIG. 3, since the memory cells arranged in the first NAND string NS11 in the first column are programmed, the ground voltage να 13 201110121 is supplied to the first bit connected to the first NAND string NS11. Line BL1. The first NAND string NS21 of the second column is also connected to the first bit line BL1 to which the ground voltage Vss is supplied. Since the second NAND string NS12 arranged in the first column is prevented from being programmed', the power supply voltage Vcc is supplied to the second bit line BL2 connected to the second NAND string NS12. The second NAND string NS22 of the second column is also connected to the second bit line BL2 to which the power supply voltage Vcc is supplied. Since the first NAND string NS11 of the first column is programmed, the turn-on voltage is supplied to the first string selection line SSL1 and the second string selection line SSL2 connected to the first NAND string NS11. The turn-on voltage may be a voltage for turning on the first string selection transistor TS1 and the second string selection transistor TS2 of the first NAND string NS11. For example, the turn-on voltage can be the supply voltage Vcc. The first string selection transistor TS1 and the second string selection transistor TS2 of the second NAND string of the first column are also connected to the first selection line SSL1 and the second selection line SSL2, respectively. Therefore, the first string selection transistor TS1 and the second string selection transistor TS2 of the second NAND string of the first column are turned on. The first NAND string NS21 and the second NAND string NS22 of the second column are prevented from being programmed. For example, the off voltage is supplied to the third string selection line SSL3 and the fourth string selection line SSL4. The turn-off voltage is a voltage for disconnecting the first string selection transistor TS1 and the second string selection transistor TS2 of the first NAND string NS21 and the second NAND string NS22. For example, the disconnect voltage is the ground voltage Vss. The stylized voltage Vpgm and the transfer voltage Vpass are supplied to the word line 201110121 WLO-WLn. For example, the stylized voltage Vpgm is supplied to a word line connected to the selected 5 memory unit. The transfer voltage Vpass is supplied to a word line connected to an unselected memory cell. The stylized voltage Vpgm and the transfer voltage Vpass are, in this embodiment, a high voltage 'e.g., 8 volts or more. Channels are formed in the memory cells of the first NAND string NS21 and the second NAND string NS22 disposed in the second column by the high voltages (vpgm and Vpass) applied to the word lines WL0-WLn. The voltage of the formed channel is boosted by high voltages (Vpgm and Vpass). At this time, the ground voltage Vss is applied to the gates of the second string selection transistors TS2 of the first NAND string Ns2丨 and the second NAND string NS22 arranged in the second column. Therefore, between the gate voltage (eg, the ground voltage Vss) of the second string selection transistor TS2 of the first NAND string NS1 and the second NAND string NS22 and the gate voltage (eg, the boosted channel voltage) The voltage difference can cause gate induced drain leakage (GIDL). Further, the ground voltage Vss is applied to the second bit line BL2 connected to the second NAND string NS22 arranged in the second column. Additional leakage in the second NAND string NS22 may result due to the voltage difference between the bit line voltage (e.g., ground voltage vss) connected to the second NAND string NS22 and the boosted channel voltage. To address the above limitations, a method of controlling the voltage of the _ select line of a memory device in accordance with an embodiment of the inventive concept is provided. @此, can control the leakage current. Figure 4 is a table depicting the results of a method of controlling voltage not according to an embodiment of the inventive concept. Referring to FIGS. 2 and 4, the third voltage V3 is supplied to the 15th 201110121 three-string selection line SSL3. That is, the third voltage V3 is applied to the gates of the first string selection transistors TS1 of the first NAND string NS21 and the second NAND string NS22 arranged in the second column. For example, the third voltage V3 is a voltage for disconnecting the first string selection transistor TS1 of the first NAND string NS21 and the second NAND string NS22. The fourth voltage V4 is supplied to the fourth string selection line SSL4. That is, the fourth voltage V4 is applied to the gates of the second string selection transistors TS2 of the first NAND string NS21 and the second NAND string NS22 arranged in the second column. For example, the fourth voltage V4 is a voltage for disconnecting the second string selection transistor TS2 of the first NAND string NS21 and the second NAND string NS22. When the difference between the fourth voltage V4 of the first NAND string NS21 and the second NAND string NS22 and the boosted channel voltage is reduced, the second string is selected in the first NAND string NS21 and the second NAND string NS22 The gate inductive drain leakage (GIDL) is reduced in TS2. The fourth voltage V4 is set to prevent or reduce the first NAND string NS21 and the second NAND string NS22. The second string selects the GIDL generated in the transistor TS2. For example, the fourth voltage V4 may have a higher level than the ground voltage Vss. For example, the fourth voltage V4 may have a ground voltage Vss and a second string selection The level between the threshold voltages of the transistor TS2. The lower the level of the third voltage V3, the first string selection transistor tsi leaks to the bit line via the first NAnd string § 21 and the second NAND string NS22 The less the charge of BL1, BL2, the level of the third voltage v can be set to prevent or reduce the leakage of the first string selection transistor TS1 via the first NAND string NS21 and the second NAND string 201110121 NS22. In other words, the third voltage V3 may have a level lower than the ground voltage vss. As described above, if The voltage level of the string selection lines (eg, ssu, SSL4) of the NAND strings (eg, NS21, NS22) configured in a different column from the programmed NAND string (eg, NS11) is controlled. Preventing or reducing the leakage that can occur in NAND strings (eg, m21, NS22).. configured in a different column than the programmed NAND string (eg, NS11). Therefore, the enhanced memory component Reliability. Moreover, while maintaining the amount of leakage, that is, maintaining the reliability of the memory element, the level of the voltage supplied to the word lines adjacent to the string selection transistors TS1, TS2 can be raised. The voltage window adjacent to the word lines of the string selection transistors TS1, TS2 can be enhanced while the reliability of the body elements. In Fig. 4, the fourth voltage V4 has been described as being the off voltage. However, the fourth voltage V4 can be The voltage of the second string selection transistor TS2 of the first nand string NS21 and the second NAND string NS22 disposed in the second column is turned on. For example, the fourth voltage V4 may have a higher frequency than the first ναν〇 The second string of NS21 and the second NAND string NS22 selects the threshold voltage of the transistor TS2 For example, the fourth voltage V4 may have a lower level than the transmission voltage Vpass. The fourth voltage V4 may have a level equal to the transmission voltage Vpass. The fourth voltage V4 may have a higher level than the transmission voltage. Figure 5 is a schematic cross-sectional view taken along the direction of the bit line of the non-volatile memory element of Figure 2, in accordance with an embodiment of the inventive concept. Referring to Fig. 5, 17 201110121 string selection closed electrode〗 66 can be connected to the first string selection line SSL1 and the second string selection line via the contact plug ((7) balance plug) i74. The ground selection inter-electrode 162 can be connected to the first ground selection line GSL1 and the second ground selection line GSL2 via the contact plugs 17A, respectively. Figure 6 is a schematic cross-sectional view taken along the bit line square of the non-volatile memory element of Figure 2, in accordance with another embodiment of the inventive concept. For simplicity of description, the NAND string array portion is omitted. Referring to Fig. 6, the ground selection gate electrode 162 is connected to the first ground selection line GSL1 and the second ground selection line GSL2 via contact plugs 17A, 171 at one side of the NAND string array, respectively. Moreover, the control gate electrode 164 is connected to the word line WL0-WLn via the contact plug 172 at one side of the NAND string array, respectively. The series selection lightning pole is connected by the contact plugs 、5, 176 and the second string selection line SSL2, respectively. As an example, the string selection lines SSL1, SSL2, the word lines WLO-WLn, and the ground selection lines GSL1, GSL2 may be formed on the same layer. For example, string select lines SSU, SSL2, word lines WLO-WLn, and ground select lines GSL1, GSL2 may be formed in the metal layer. For example, the string selection lines SSL1, SSL2, the word lines WLO-WLn, and the ground selection lines gsLI, GSL2 may be formed in the metal germanium layer or the metal 1 layer. Figure 7 is a schematic cross-sectional view taken along the direction of the bit line of the non-volatile memory element of Figure 2, in accordance with yet another embodiment of the inventive concept. Comparing the schematic cross-sectional view of Fig. 7 with the schematic cross-sectional view of Fig. 6, in Fig. 7, the first _ selection line SSL1 and the second string selection line SSL2 are formed in different layers. As an example, the first string selection line SSL1 is formed in a layer above the layer in which the second string selection line 201110121 SSL2 is formed. For example, the first string selection line SSL1 is formed on the metal 1 layer. The second string selection line SSL2 is formed on the metal ruthenium layer. Figure 8 is a schematic cross-sectional view taken along the direction of the bit line of the non-volatile suffix element of Figure 2, in accordance with another embodiment of the inventive concept. Comparing the unintentional cross-sectional view of FIG. 8 with the schematic cross-sectional view of FIG. 7, in FIG. 8, word lines WL (MVLn, ground selection lines GSL1, GSL2, and first string selection line SSL1 are formed in the same layer. For example, words The line nwLn, the ground selection line GSU, the GSL2, and the first string selection line are formed in the metal layer 1. The second string selection line SSL2 is formed in a layer below the first string selection line SSL1. For example, the second selection line SSL2 Figure 9 is a schematic cross-sectional view taken along the direction of the bit line of the non-volatile memory element of Figure 2. In accordance with another embodiment of the inventive concept, a schematic cross-sectional view of Figure 9 is compared Figure 8 is a schematic cross-sectional view, in Figure 9, the ground selection gate electrode 162 is connected to a single ground selection line GS1. That is, the ground selection transistors TGI, TG2 are connected in common with the ground selection line GSL. The first string selection line SSL1 The word line WL0_WLn and the ground selection line GSL are formed in the same layer. For example, the first string selection line SSL1, the sub-line WLO-WLn, and the ground selection line gsl are formed in the metal layer 1. The second string selection line SSL2 is formed. Below the first string selection line SSL1 For example, the second selection line SSL2 is formed in the metal germanium layer. Fig. 10 is a circuit diagram of a non-volatile memory element according to another embodiment of the inventive concept, and the memory element shown in Fig. 2. The charge storage layer is provided for the selection transistors TS1, TS2, TGb TG2 (similar to the memory cell) of the memory device shown in Fig. 10. That is, the transistor 19 201110121 TSl 'TS2, TGI, TG2 and The memory cells have the same structure. As an example, the electrode storage layer provided to the selection transistors TSH TS2, TGI, TG2 and the memory cells may be a charge trap layer. FIG. 11 is a diagram illustrating the charge iayer. A circuit diagram of a non-volatile δ-remembrance τ of a further embodiment of the concept. The non-volatile memory component of FIG. 11 further includes a string selection line SSL1 to the non-volatile memory component of FIG. A dummy dummy line dw1 between SSL4 and the normal wordline nip to WLn. In an embodiment, a dummy transfer voltage can be applied to the dummy word line DWL during the stylization operation. For example, dummy transfer Voltage level Below the level of the normal transfer voltage. In an embodiment, _ or more than two dummy word lines may be provided between the string select lines SSL1 to SSL4 and the normal word line to 0WLn. Figure 12 is a diagram illustrating the concept according to the present invention. In another embodiment, the circuit diagram of the non-volatile memory device, the non-volatile memory component of FIG. 12 further includes the ground selection lines GSL1 to GSL4 and the normal word line muscle.虚 to the dummy word line between in = WL. In the - real sleeve towel, you can apply the dummy transmission voltage to the New York DWL in the shouting operation. The word of the virtual money line dwl can be lower than the normal transmission. The level of voltage. In one implementation, two or more dummy word lines may be provided between ground select lines GSL1 through GSL4 and normal word line drains 3 through WLn. Figure 13 is a circuit diagram illustrating a non-volatile memory 70 piece according to another embodiment of the inventive concept. In contrast to the non-volatile memory component of FIG. 1G, the non-volatile memory component of FIG. 13 further includes a first dummy word line DWL1 between string select lines 20 201110121 SSL1 to SSL4 and normal word lines WL0 to WLn, and A second dummy word line dWL2 is located between the ground selection line GSU to GSM and the normal word lines WL0 to WLn. In one embodiment, a dummy transfer voltage can be applied to the first dummy word line DWL1 and the second dummy word line DWL2 during the stylizing operation. For example, the level of the dummy transfer voltage can be lower than the level of the normal transfer voltage. - In an embodiment, two or more dummy word lines may be provided between string select lines SSL1 through SSL4 and normal sub-lines WL0 through WLn. In one embodiment, two or more dummy word lines may be provided between ground select lines GSL1 through GSL4 and normal word lines WL0 through WLn. Figure 2 is a schematic block diagram illustrating a memory tree containing non-volatile memory components in accordance with another embodiment of the inventive concept. See f Η ' NAND cell array 250 can be coupled to core circuit unit 27A. For example, the NAND cell array 25A can include the non-volatile simon elements described with reference to Figures j through 13. The core circuit unit can include control: 271, column decoder 272, row decoder milk, sense amplifier 274, and/or page buffer 275. The logic 271 can be generalized with the column decoder 272, the row decoder 273, and / 275. Column decoder 272 can select line hunger via string
ί : Phi及/或接地選擇線GSL與具有堆疊結構之NAND 250通信。行解喝器273可經由位元線BL與 NAND早元陳歹彳25Ω、s 、 NANDi - 感測放大器274可在信號自 长賴、· ^車列250輸出時與行解碼器273連接，且可在 ^送JL NAND單元陣列2s〇時不與行解碼器273連 201110121 接。 舉例而言，控制邏輯271可將列位址信號傳送至列解 碼器272，且列解碼器272可對列位址信號進行解碼，且 經由串選擇鍊SSL、字線WL及接地選擇線GSL將經解碼 之列位址信號傳送至NAND單元陣列25(^控制邏輯271 可將行位址信號傳送至行解碼器273或頁緩衝器275，且 行解碼器273可對行位址信號進行解碼，且經由位元線BL 將經解碼之行位址信號傳送至單元陣列25〇。 NAND單元陣列250之信號可經由行解碼器273傳送至感 測放大器274且經放大，且在感測放大器274中放大之信 號可經由頁緩衝器275傳送至控制邏輯271。 圖15是根據本發明概念之一實施例之記憶卡4〇〇的 示意圖。參見圖15，記憶卡400可包含形成或維持於外殼 430中之控制器410及記憶體420或類似物。控制器410 及s己憶體420可交換電信號。舉例而言，根據控制器 之命令，控制器410可與記憶體420交換資料。因此，記 憶卡400可在記憶體420中儲存資料，或可自記憶體42〇 輸出資料。 舉例而言，記憶體420可包含參見圖1至圖13描述 之非揮發性記憶體元件。記憶卡400可用作用於各種攜帶 型元件之資料儲存媒體。舉例而言，記憶卡4〇〇可包含多 媒體卡（multimedia card，MMC)或安全數位卡（secure digital card，SD ) 〇 圖16是根據本發明概念之實施例之電子系統5〇〇的 22 201110121 方塊圖。參見圖16 ’電子***可包含處理器51〇、記憶體 晶片520以及輪入/輸出單元53〇，以上組件可藉由使用匯 流排540而執行資料通信。處理器51〇可執行程式且控制 ，子系統5〇〇。輪入/輸出單元53〇可用以輸入或輸出電子 系統500之資料。電子系統500可藉由使用輸入/輸出單元 530與外部元件（例如，個人電腦或網路）連接以與外部 兀件交換資料。舉例而言，記憶體520可包含參見圖i至 圖13描述之非揮發性記憶體元件。 舉例而言，電子系統500可構成需要記憶體520之各 種電子控制器，且可用於例如行動電話、MP3播放器、導 航系統、固態磁盤（s〇lid state disk，)、家用電器岑 似物中。 〆 圖Π是具備包含參見圖1至圖13描述之非揮發性記 憶體元件之非揮發性記憶體設備62〇之記憶體系統6〇〇的 方塊圖。參見圖17，記憶體系統600包含非揮發性記憶體 元件620及控制器61〇。 " 控制器610與主機及非揮發性記憶體元件62〇連接。 回應於來自主機之請求，控制器61〇經組態以存取非揮發 性記憶體元件620。舉例而言，控制器61〇經組態以控制 非揮發性記憶體元件620之讀取、寫入、抹除及背景操作。 控制器610經組態以提供非揮發性記憶體元件62〇與主機 之間的介面。控制器610經組態以操作用於控制非揮發性 記憶體元件620之韌體。 作為實例，控制器610更包含公共已知之組件，諸如 23 201110121 隨機存取記憶體（random access memory，RAM)、處理單 元、主機介面以及記憶體介面。RAM用作處理單元之操作 記憶體、非揮發性記憶體元件620與主機之間的快取記憶 體以及非揮發性記憶體元件620與主機之間的緩衝記憶體 中的至少一者《處理單元控制控制器61〇之總體操作。 主機介面包含用於執行主機與控制器610之間的資料 交換之協定。作為實例，控制器610經組態以經由各種介 面協定中之至少一者與外部元件（例如，主機）通信，所 述介面協定諸如通用串列匯流排（Universal Serial Bust， USB)協定、多媒體卡（mmc)協定、周邊組件互連 (Peripheral Component Interconnection ’ PCI)協定、串列 ΑΤΑ協定、並列ΑΤΑ協定、小型電腦小型介面（Small Computer Small Interface，SCSI)協定、增強小型磁盤介 面（Enhanced Small Disk Interface，ESDI)協定、積體驅 動電子組件（Integrated Drive Electronics，IDE)協定等。 記憶體介面與非揮發性記憶體元件620介面連接。舉例而 言’記憶體介面包含NAND介面或NOR介面。 記憶體系統600可經組態以更包含錯誤校正區塊。錯 誤校正區塊可經組態以偵測自非揮發性記憶體元件620讀 取之資料的錯誤，且校正錯誤。作為實例，可提供錯誤校 正區塊作為構成控制器61〇之組件。 控制器610及非揮發性記憶體元件62〇可整合至單一 半導體元件令。例示性地，控制器61〇及非揮發性記憶體 το件620可整合至單一半導體元件中，構成如參考圖15 24 201110121 描述之記憶卡。舉例而言，控制器610及非揮發性記憶體 元件620可整合至單一半導體元件中構成記憶卡，諸如 卡（PCMCIA，個人電腦記憶卡國際協會）、緊湊型快閃卡 (compact flash card，CF)、智慧犁媒體卡（SM、SMc)、 記憶棒、多媒體卡（MMC、RS-MMC、MMCmicro)、SD 卡（SD、miniSD、microSD、SDHC)、通用快閃儲存元件 (universal flash storage，UFS)或類似物。 控制器610及非揮發性記憶體元件620可整合至單一 半導體元件中’構成固態驅動器（solid state drive，SSD：)。 S S D包含經組態以在半導體記憶體中儲存資料的儲存單 元。在記憶體系統600用作SSD之情況下，與記憶體系統 600連接之主機之操作速度顯著改良。 作為另一實例’可提供記憶體系統600作為構成電子 元件之各種組件中的一者，諸如電腦、攜帶型電腦、超行 動PC ( Ultra Mobile PC，UMPC )、工作站、迷你筆記型電 腦、個人數位助理（Personal Digital Assistant，PDA)、網 路平板電腦（web tablet)、無線電話、行動電話、智慧型 電話、電子書、攜帶型多媒體播放器（PMP)、攜帶型遊戲 機（Playstation Portable ’ PSP)、導航元件、黑盒（black box)、數位相機、數位多媒體廣播（Digital Multimedia Broadcasting ’ DMB)播放器、數位音訊記錄器、數位音 訊播放器、數位圖片記錄器、數位圖片播放器、數位視訊 記錄器、數位視頻播放器、能夠在無線環境中傳輸及/或接 收資訊的元件、構成家庭網路之各種電子元件中的一者、 25 201110121 RHD元件、構成計算系統之各種組件中的一者，或類似 物。 作為實例’非揮發性記憶體元件610或記憶體系統6〇Q 可安裝於各種類型的封裝中。非揮發性記憶體元件61〇或 έ己憶體系統600之封裝的實例可包含封裝上封裝（package on.package，P0P)、球狀柵格陣列（ball grid 町町，BGA)、 日曰片級封裝（chip scale packages，CSP )、塑膠引線晶片載 體（plastic leaded chip carrier，PLCC )、塑膠雙列直插式封 裝（plastic dual in-line package，PDIP)、萬伏而組件中的 晶粒（die in waffle pack)、晶圓形式之晶粒、板上晶片（chip on board，COB)、陶瓷雙列直插式封裝（ceramic dual in_Une package ’ CERDIP)、塑膠公制四扁平包裝（metric quad flat pack ’ MQFP )、薄四扁平包裝（thin quad flat pack，TQFP)、 小型封裝（small outline ’ SOIC )、收縮小型封裝（shrink small outline package，SSOP )、薄型小型封裝（Ain small 〇utline package ’ TSOP )、系統級封裝（system in package，SIP )、 多晶片封裝（multi chip package，MCP)、晶圓級製造封裝 (wafer-level fabricated package，WFP )、晶圓級處理堆疊封 裝（a wafer-level processed stack package，WSP )等等。 圖18是繪示圖17之記憶體系統之應用實例的方塊 圖。參見圖18，記憶體系統700包含非揮發性記憶體元件 720及控制器710。非揮發性記憶體元件720包含多個非揮 發性記憶體晶片。所述多個非揮發性記憶體晶片劃分為多 個群。所述多個非揮發性記憶體晶片之每一群經組態以經 26 201110121 由單一共同通道與控制器710通信。圖18繪示所述多個非 揮發性記憶體晶片經由通道1 (CH1)至通道k (CHk)與 控制器710通信。每一非揮發性記憶體晶片包含參見圖1 至圖13描述之非揮發性記憶體元件。 圖19是包含參見圖18描述之記憶體系統700之計算 系統800的方塊圖。參見圖19，計算系統800包含中央處 理單元（central processing unit，CPU) 810、隨機存取記 憶體（random access memory，RAM) 820、用戶介面 830、 電源840以及記憶體系統700。 記憶體系統700經由系統匯流排850與CPU 810、 RAM820、用戶介面830以及電源840電連接。經由用戶 介面830提供或由CPU 810處理之資料儲存於記憶體系統 7〇〇中。記憶體系統700包含控制器710及非揮發性記憶 體元件720。 雖然圖19繪示非揮發性記憶體元件72〇經由控制器 710與系統匯流排850連接，但非揮發性記憶體元件72〇 可經組態以與系統匯流排850直接連接。 在圖19中，已描述非揮發性記憶體元件7〇〇包含多 個非揮發性記㈣⑼。然而，非揮發性記紐元件7〇〇 可^-個非揮發性記㈣晶片。而且，非揮發性記憶體 =件700包含在此實關中各自具有—时通道 非 揮發性記憶體晶片。 由將===實施例之非揮發性記憶體元件，藉 由將串選擇電晶體之數目設計為至少兩個，與串選擇電晶 27 201110121 體之數目為一個的情況相比，串選擇閘電極可較大地減小 其閘極長度，使得層間介電質之間的空間可被填滿而無任 何空隙。而且，藉由將串選擇電晶體之數目設計為至少兩 個’與串選擇電晶體之數目為一個的情況相比，接地選擇 閘電極可較大地減小其閘極長度，使得層間介電質之間的 空間可被填滿而無任何空隙。此外’藉由調整串選擇電晶 體、&己憶體單元及接地選擇電晶體之閘極長度以及其問電 極之間的間距’可進一步抑制空隙之形成。因此，可增強 串選擇電晶體、記憶體單元及接地選擇電晶體之可靠^。 雖然上述内容已描述了被視為最佳模式之内容及/或 其它較佳實施例，但應瞭解，可在其中作出各種修改且本 發明可以各種形式及實施例來實施，且其可在許多應用中 應用’本文中僅描述了所述應用中的一些應用而已^以下 申請專利範圍既定主張文字上描述之内容及其所有均等 物，包含屬於每一請求項之範圍内的所有修改及變化。 【圖式簡單說明】 自下文結合關作出之詳細描述將更清楚瞭解 明概念之例示性實施例，附圖中： x 圖1是根縣發_念之祕之非揮發航憶體元 之電路圖的第一實施例。 τ 圖2是根據本發明概念之態樣之非揮發性記憶體 之電路圖的第四實施例。 什 圖3繪示當在圖2之記憶體元件中執行程式 的電壓偏置條件。 28 201110121 之實==據本發明概念之態樣之控輸的方法 圖5是自位元線之方向截取之圖2 元件之示意性橫截面_實施例。/輝發I己憶體 圖^是自位元線之方向截取之圖2之非揮發性記情 元件之示意性橫截面圖的另一實施例。 吻 元件St線之方向截取之圖2之非揮發性記憶體 兀仵之不思性橫截面圖的又一實施例。 元件：-8元線之方向截取之圖2之非揮發性記憶體 兀件之不意性截面圖的又一實施例。 圖=自位樣之方向截取之圖2之非揮發性記憶體 兀件之不意性截面圖的又一實施例。 ，10是根據本發明概念之祕之_發性記憶體元 件之電路圖的第五實施例。 圖11是根據本發明概念之態樣之非揮發性記憶體元 件之電路圖的第六實施例。 圖I2是根據本發明概念之態樣之非揮發性記憶體元 件之電路圖的第七實施例。 圖13是根據本發明概念之態樣之非揮發性記憶體元 件之電路圖的第八實施例。 圖14是根據本發明概念之態樣之非揮發性記憶體元 件之另一實施例的方塊圓。 圖15是根據本發明概念之態樣之記憶卡之實施例的 示意圖。 29 201110121 圖16是根據本發明概念之態樣之電子系統之實施例 的方塊圖。 圖Π是具備包含參見圖1至圖13描述之非揮發性記 憶體元件之非揮發性記憶體設備的記憶體系統之實施例的 方塊圖。 圖18是繪示圖π之記憶體系統之應用實例之實施例 的方塊圖β 圖19是包含參見圖18描述之記憶體系統之計算系統 之實施例的方塊圖。 【主要元件符號說明】 162 :接地選擇閘電極 164 :控制閘電極 166:串選擇閘電極 170〜172、174〜176 :接觸插塞 200 :記憶體元件 250 : NAND單元陣列 270 .核心電路單元 271 :控制邏輯 272 :列解碼器 273 :行解碼器 274 :感測放大器 275 :頁緩衝器 400 :記憶卡 410 :控制器 201110121 420 :記憶體 、 430 :外殼 500 :電子系統 510 :處理器 520 :記憶體 530 :輸入/輸出單元 540 :匯流排 600 :記憶體糸統 610 :控制器 620 :非揮發性記憶體元件 700 :記憶體系統 710 :控制器 720 :非揮發性記憶體元件 800 .計算糸統 810 :中央處理單元 820 :隨機存取記憶體 830 :用戶介面 840 :電源 850 :系統匯流排 BL :位元線 BL1 :第一位元線 BL2 :第二位元線 CSL :共源極線 DWL :虛設字線 31 201110121 DWLl :第一虛設字線 DWL2 :第二虛設字線 GSL :接地選擇線 GSL1 :第一接地選擇線 GSL2 :第二接地選擇線 GSL3 :第三接地選擇線 GSL4 :第四接地選擇線 MC :記憶體單元 NS : NAND 串 NS1 卜 NS12、NS2 卜 NS22 : NAND 串 SSL :串選擇線 SSL1 :第一串選擇線 SSL2 :第二串選擇線 SSL3 :第三串選擇線 SSL4 :第四串選擇線 TG1 :第一接地選擇電晶體 TG2 :第二接地選擇電晶體 TS1 :第一串選擇電晶體 TS2 :第二串選擇電晶體 WL :字線 WL0.....WLn :字線 32ί : Phi and/or ground select line GSL communicates with NAND 250 having a stacked structure. The row decanter 273 can be connected to the row decoder 273 via the bit line BL and the NAND early 歹彳 25 Ω, s, NANDi - sense amplifier 274 when the signal is output from the long row, It can be connected to the row decoder 273 at 201110121 when the JL NAND cell array 2s is sent. For example, control logic 271 can transmit the column address signal to column decoder 272, and column decoder 272 can decode the column address signal and via chain select chain SSL, word line WL, and ground select line GSL The decoded column address signal is passed to NAND cell array 25 (^ control logic 271 can transmit the row address signal to row decoder 273 or page buffer 275, and row decoder 273 can decode the row address signal, and The decoded row address signals are transmitted to the cell array 25A via the bit line BL. The signals of the NAND cell array 250 can be transmitted to the sense amplifier 274 via the row decoder 273 and amplified, and amplified in the sense amplifier 274 The signal can be transmitted to control logic 271 via page buffer 275. Figure 15 is a schematic diagram of a memory card 4A in accordance with an embodiment of the present inventive concept. Referring to Figure 15, memory card 400 can be formed or maintained in housing 430. The controller 410 and the memory 420 or the like. The controller 410 and the suffix 420 can exchange electrical signals. For example, the controller 410 can exchange data with the memory 420 according to a command from the controller.The card 400 can store data in the memory 420 or can output data from the memory 42. For example, the memory 420 can include the non-volatile memory elements described with reference to Figures 1 through 13. The memory card 400 can function. For example, the memory card 4 can include a multimedia card (MMC) or a secure digital card (SD). FIG. 16 is an implementation of the concept according to the present invention. Example of an electronic system 5 2011 22 201110121. See Figure 16 'The electronic system can include a processor 51 〇, a memory chip 520, and a wheel input/output unit 53 〇, the above components can be executed by using the bus 540 Data communication. The processor 51 is executable and controlled, and the subsystem 5 is used. The wheel input/output unit 53 can be used to input or output data of the electronic system 500. The electronic system 500 can be used by using the input/output unit 530. External components (eg, a personal computer or network) are connected to exchange data with external components. For example, memory 520 can include non-volatile descriptions as described with reference to Figures i-13 For example, the electronic system 500 can constitute various electronic controllers that require the memory 520, and can be used, for example, in mobile phones, MP3 players, navigation systems, s〇lid state disks, household appliances. 〆图Π is a block diagram of a memory system 6〇〇 having a non-volatile memory device 62〇 including the non-volatile memory elements described with reference to Figures 1 to 13. See Figure 17, memory The body system 600 includes a non-volatile memory component 620 and a controller 61. " The controller 610 is connected to the host and the non-volatile memory element 62A. In response to a request from the host, the controller 61 is configured to access the non-volatile memory component 620. For example, controller 61 is configured to control the reading, writing, erasing, and background operations of non-volatile memory component 620. Controller 610 is configured to provide an interface between non-volatile memory component 62A and the host. Controller 610 is configured to operate a firmware for controlling non-volatile memory component 620. As an example, controller 610 further includes commonly known components such as 23 201110121 random access memory (RAM), processing unit, host interface, and memory interface. The RAM is used as an operation memory of the processing unit, a cache memory between the non-volatile memory element 620 and the host, and at least one of the buffer memory between the non-volatile memory element 620 and the host. The overall operation of the controller 61 is controlled. The host interface includes a protocol for performing data exchange between the host and the controller 610. As an example, controller 610 is configured to communicate with external components (eg, a host) via at least one of various interface protocols, such as a Universal Serial Bust (USB) protocol, a multimedia card. (mmc) protocol, Peripheral Component Interconnection 'PCI protocol, serial port protocol, parallel port protocol, Small Computer Small Interface (SCSI) protocol, enhanced small disk interface (Enhanced Small Disk Interface) , ESDI) agreement, integrated drive electronics (IDE) agreement, etc. The memory interface is interfaced with a non-volatile memory component 620. For example, the 'memory interface' contains a NAND interface or a NOR interface. The memory system 600 can be configured to further include error correction blocks. The error correction block can be configured to detect errors in the data read from the non-volatile memory element 620 and correct the error. As an example, an error correction block can be provided as a component constituting the controller 61. Controller 610 and non-volatile memory component 62 can be integrated into a single semiconductor component. Illustratively, controller 61 and non-volatile memory 620 can be integrated into a single semiconductor component to form a memory card as described with reference to Figures 15 24 201110121. For example, the controller 610 and the non-volatile memory component 620 can be integrated into a single semiconductor component to form a memory card, such as a card (PCMCIA, Personal Computer Memory Card International Association), a compact flash card (CF). ), smart plow media card (SM, SMc), memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), universal flash storage (universal flash storage, UFS) ) or the like. Controller 610 and non-volatile memory component 620 can be integrated into a single semiconductor component to form a solid state drive (SSD:). S S D contains a storage unit configured to store data in a semiconductor memory. In the case where the memory system 600 is used as an SSD, the operating speed of the host connected to the memory system 600 is significantly improved. As another example, the memory system 600 can be provided as one of various components constituting electronic components such as a computer, a portable computer, an Ultra Mobile PC (UMPC), a workstation, a mini notebook computer, and a personal digital device. Personal Digital Assistant (PDA), web tablet, wireless phone, mobile phone, smart phone, e-book, portable multimedia player (PMP), portable game console (Playstation Portable ' PSP) , navigation components, black box, digital camera, digital multimedia broadcasting (DMB) player, digital audio recorder, digital audio player, digital picture recorder, digital picture player, digital video recording Device, digital video player, component capable of transmitting and/or receiving information in a wireless environment, one of various electronic components constituting a home network, 25 201110121 RHD component, one of various components constituting a computing system, Or similar. As an example, the non-volatile memory element 610 or the memory system 6〇Q can be mounted in various types of packages. Examples of the package of the non-volatile memory component 61 or the memory system 600 may include a package on package (P0P), a ball grid array (ball grid, BGA), a sundial film. Chip scale packages (CSP), plastic leaded chip carriers (PLCC), plastic dual in-line package (PDIP), 10,000 volts in the module ( Die in waffle pack), wafer form die, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (metric quad flat pack) ' MQFP ), thin quad flat pack (TQFP), small outline ' SOIC , shrink small outline package ( SSOP ), thin small package ( Tin ) , system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP), wafer level A wafer-level processed stack package (WSP) and the like. Figure 18 is a block diagram showing an application example of the memory system of Figure 17. Referring to Figure 18, memory system 700 includes a non-volatile memory component 720 and a controller 710. Non-volatile memory component 720 includes a plurality of non-volatile memory chips. The plurality of non-volatile memory chips are divided into a plurality of groups. Each of the plurality of non-volatile memory chips is configured to communicate with controller 710 via a single common channel via 26 201110121. Figure 18 illustrates the plurality of non-volatile memory chips in communication with controller 710 via channel 1 (CH1) to channel k (CHk). Each non-volatile memory wafer contains the non-volatile memory elements described with reference to Figures 1 through 13. 19 is a block diagram of a computing system 800 incorporating a memory system 700 as described with reference to FIG. Referring to Figure 19, computing system 800 includes a central processing unit (CPU) 810, a random access memory (RAM) 820, a user interface 830, a power supply 840, and a memory system 700. The memory system 700 is electrically coupled to the CPU 810, the RAM 820, the user interface 830, and the power source 840 via the system bus 850. The data provided via the user interface 830 or processed by the CPU 810 is stored in the memory system 7A. Memory system 700 includes a controller 710 and a non-volatile memory component 720. Although FIG. 19 illustrates the non-volatile memory component 72 being coupled to the system bus 850 via controller 710, the non-volatile memory component 72 can be configured to interface directly with the system bus 850. In Fig. 19, it has been described that the non-volatile memory element 7A contains a plurality of non-volatile notes (4) (9). However, the non-volatile memory element 7 can be a non-volatile (four) wafer. Moreover, the non-volatile memory = 700 includes a time-channel non-volatile memory wafer in each of the actual gates. By selecting the === non-volatile memory element of the embodiment, by designing the number of string selection transistors to be at least two, compared with the case where the number of the string selection transistors 27 201110121 is one, the string selection gate The electrodes can greatly reduce their gate length so that the space between the interlayer dielectrics can be filled without any voids. Moreover, by designing the number of string selection transistors to be at least two 'as compared with the case where the number of string selection transistors is one, the ground selection gate electrode can greatly reduce the gate length thereof, so that the interlayer dielectric The space between them can be filled without any gaps. Further, the formation of voids can be further suppressed by adjusting the gate length of the string selection transistor, the & memory cell and the ground selection transistor, and the pitch between the electrodes. Therefore, the reliability of the string selection transistor, the memory cell, and the ground selection transistor can be enhanced. While the foregoing has described what is considered to be the best mode of the embodiments and the preferred embodiments of the invention, it is understood that various modifications can be made therein and the invention can be practiced in various forms and embodiments, and In the application, the application of the application is only described herein. The following claims are intended to cover all modifications and variations within the scope of the claims. BRIEF DESCRIPTION OF THE DRAWINGS Exemplary embodiments of the concept will be more clearly understood from the following detailed description of the accompanying drawings, in which: Figure 1 is a circuit diagram of the non-volatile aeronautical memory element of the root of the county. The first embodiment. τ Figure 2 is a fourth embodiment of a circuit diagram of a non-volatile memory in accordance with aspects of the inventive concept. Figure 3 illustrates the voltage bias conditions when the program is executed in the memory device of Figure 2. 28 201110121 Reality == Method of Controlling Transmission According to Aspect of the Concept of the Invention FIG. 5 is a schematic cross-sectional view of the element of FIG. 2 taken from the direction of the bit line. / Huifa I Recall Figure 2 is another embodiment of a schematic cross-sectional view of the non-volatile essay element of Figure 2 taken from the direction of the bit line. A further embodiment of the non-volatile memory of Figure 2, taken in the direction of the St line of the kiss element. Element: Non-volatile memory of Figure 2 taken in the direction of the -8 element line. Yet another embodiment of the unintentional cross-sectional view of the element. Fig. = Still another embodiment of the non-volatile memory of the non-volatile memory of Fig. 2 taken in the direction of the sample. 10 is a fifth embodiment of a circuit diagram of an eigen memory element according to the concept of the present invention. Figure 11 is a sixth embodiment of a circuit diagram of a non-volatile memory element in accordance with aspects of the inventive concept. Figure 12 is a seventh embodiment of a circuit diagram of a non-volatile memory element in accordance with aspects of the inventive concept. Figure 13 is an eighth embodiment of a circuit diagram of a non-volatile memory element in accordance with aspects of the inventive concept. Figure 14 is a block circle of another embodiment of a non-volatile memory element in accordance with aspects of the inventive concept. Figure 15 is a schematic illustration of an embodiment of a memory card in accordance with aspects of the inventive concept. 29 201110121 Figure 16 is a block diagram of an embodiment of an electronic system in accordance with aspects of the inventive concept. Figure Π is a block diagram of an embodiment of a memory system having a non-volatile memory device including the non-volatile memory elements described with reference to Figures 1 through 13. Figure 18 is a block diagram showing an embodiment of an application example of the memory system of Figure π. Figure 19 is a block diagram of an embodiment of a computing system including the memory system described with reference to Figure 18. [Description of main component symbols] 162: Ground selection gate electrode 164: Control gate electrode 166: String selection gate electrodes 170 to 172, 174 to 176: Contact plug 200: Memory element 250: NAND cell array 270. Core circuit unit 271 : Control Logic 272: Column Decoder 273: Row Decoder 274: Sense Amplifier 275: Page Buffer 400: Memory Card 410: Controller 201110121 420: Memory, 430: Case 500: Electronic System 510: Processor 520: Memory 530: Input/Output Unit 540: Bus Bar 600: Memory System 610: Controller 620: Non-volatile Memory Element 700: Memory System 710: Controller 720: Non-volatile Memory Element 800. Calculation 810: central processing unit 820: random access memory 830: user interface 840: power supply 850: system bus bar BL: bit line BL1: first bit line BL2: second bit line CSL: common source Line DWL: dummy word line 31 201110121 DWLl: first dummy word line DWL2: second dummy word line GSL: ground selection line GSL1: first ground selection line GSL2: second ground selection line GSL3: third ground selection line GSL4: Fourth grounding option Line MC: Memory unit NS: NAND string NS1 Bu NS12, NS2 Bu NS22: NAND string SSL: String selection line SSL1: First string selection line SSL2: Second string selection line SSL3: Third string selection line SSL4: Fourth String selection line TG1: first ground selection transistor TG2: second ground selection transistor TS1: first string selection transistor TS2: second string selection transistor WL: word line WL0.....WLn: word line 32