TW201104767A - Semiconductor package with NSMD type solder mask and method for manufacturing the same - Google Patents

Semiconductor package with NSMD type solder mask and method for manufacturing the same Download PDF

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Publication number
TW201104767A
TW201104767A TW099113894A TW99113894A TW201104767A TW 201104767 A TW201104767 A TW 201104767A TW 099113894 A TW099113894 A TW 099113894A TW 99113894 A TW99113894 A TW 99113894A TW 201104767 A TW201104767 A TW 201104767A
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TW
Taiwan
Prior art keywords
metal
solder
semiconductor package
metal ball
resist layer
Prior art date
Application number
TW099113894A
Other languages
Chinese (zh)
Other versions
TWI406342B (en
Inventor
Seong-Bo Shim
Young-Jae Lee
Sung-Wuk Ryu
Original Assignee
Lg Innotek Co Ltd
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Application filed by Lg Innotek Co Ltd filed Critical Lg Innotek Co Ltd
Publication of TW201104767A publication Critical patent/TW201104767A/en
Application granted granted Critical
Publication of TWI406342B publication Critical patent/TWI406342B/en

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A method for manufacturing semiconductor package comprising: a first step of forming a solder mask formed with an opening on an insulation substrate; and a second step of firmly adhering a solder paste and a metal ball on the solder mask to mount chips thereon, such that a circuit density of a substrate can be greatly increased by directly printing a solder paste on a solder mask following formation of an opening of the solder mask on a trace and can be applied to a fine bump pitch of less than 100 μ m due to non-existence of bump bridges.

Description

201104767 宍、發明說明： 【發明所屬之技術領域】 本發明主張關於2009年4月30日所申請的南韓專利 案號10-2009-0038392的優先權，並在此以引用的方式併 入本文中，以作為參考。 本發明是有關於一種半導體封裝的製造方法，其能克 服在印刷電路板（Printed Circuit Board，PCB)的覆晶裝設 方法（flip chip mounting method )中之焊上塾 (solder-on-pad，SOP)技術問題，且特別是有關於一種藉 由形成於走線（trace)上之非阻焊限定型（Non Solder Mask Defined，NSMD )結構或阻焊限定型（Solder Mask Defined， SMD)結構内的防焊開口，而能大幅增加基板電路密度之 製程，以直接在防焊層（solder mask)上印刷（print)焊 贫（solder paste)，並能防止凸塊架橋（bump bridge)的產 生，適合精細圖案（fine pattern)。 【先前技術】 隨著電子產業的迅速發展，其著重於微型化 (miniaturization )、多功能（multi-function )、高效能（high performance)、高集成度（high integration)以及大體積， 特別是在半.導體晶片方面，封裝技術已增加其本身的重要 4 201104767 k而·成為一種能最終決定電子系統之電性效能（electrical performance)、可靠度（reliabiHty)、生產率（pr〇ductivity) 以及微型化的核心技術。封裝技術定義出一系列的流程， 其能使最後在晶圓製程中製造完成的每一個晶片能被銷 售0 近來，為了增加每單位體積的裝設放率（M〇unting efficiency) ’多種封裝技術已問世，例如球柵陣列（Ball 〇rid Array，BGA )、晶片尺寸封裝（Chip Size package，csp ) 以及多晶片模組（Multi Chip Module，MCM )半導體封裝 結構，其中透過二個或多個晶片結合於單一封裝結構中， 二個或多個晶片通常會配置於共用基板上的一多晶片模組 (multi-chip module)的半導體封裝中。 最近，用於保護半導體元件免於外部環境傷害的封裝 技術’其為了因應電子農置（electronic device )微型化與 高集成度之發展趨勢’而要求製造出的產品需輕薄短小、 速率高、多功能、效能高以及高密度裝設。 依據以上這些產品要求，已出現一種能將從晶圓 (wafer)而得的裸晶（bare chip)直接結合在基板上的覆 日日裝δ又技術。亦即’以覆晶接合（fjip chip bonding，FCB ) 為基礎的封裝被認為是其中一種典型的晶片尺寸封裝 (chip size package) ’其中半導體晶片不需要使用打線 (wire )’即能電性連接於印刷電路板（printed circuit 201104767 6oard ’ PCB)，因此相較於具有打線的封裝，在外型上可以 縮小’且因為晶片本身被當作成包圍體（enclosure)，所以 包圍體的尺寸與晶片的尺寸相等，而得以降低尺寸大小。 在覆晶接合封裝中，形成一液態底部填充層（underfill layer )，以確保黏著力（c〇hering p0wer )足夠應付貼附在 半導體晶片接塾上的焊料凸塊（s〇lder bump)高度，進而 強化接合效果以及熱傳輸能力（heat transmission capacity)’同時防止熱應力。以覆晶接合為基礎的封裝能 縮短半導體晶片與連接接塾（C〇nnecti〇npad)之間的連接 距離’而有利於電氣特性（electrical pr〇perties)。此外， 由於知球的自我對準效應（self-alignment effect)有利於微 型化與薄型化，所以接合方法會變的簡單。另外還有一個 優點.由於輸入與輸出端子（terminal)配置在晶片底下， 所以訊號的傳輸速率大約比傳統打線方法的封裝快2〇倍。 現在’請參閱圖1與圖2,其說明一種根據焊上墊（SOP) 流程’並透過傳統封裝技術，將一晶片經由焊料而裝設在 接塾上的封裝製程，其中圖1是傳統焊上墊製程的流程 圖’圖2是圖1中詳細的製程示意圖，而圖3是說明在圖 2的步驟S3.中發生問題時的放大示意圖。 首先’載入一已形成並具有阻焊限定型凸塊接墊的基 板（步驟S1 )。在這個步驟si中，形成一防焊層20在一 絕緣基板10,其中防焊層2〇是以阻焊限定型結構而形成， 201104767 並且覆蓋接塾30的預定外部位（externai p〇rti〇n )。部分接 墊30可以形成於連接貫孔(via) 4〇的結構，而貫孔4〇貫穿 絕緣基板1 〇。 接續地’在步驟S2中，防焊層20的上表面上形成一 金屬遮罩（metal mask) 50，而金屬遮罩5〇能做為一種用 於印刷焊膏（solder paste ) 60的遮罩圖案（mask pattern )。 上述印刷的方法可以是刻板印花法（stencil printing method )或其相似的方法。 在步驟S3中，金屬遮罩50是透過剝離（exfoliation) 而移除。印刷焊膏，步驟進展至回焊（reflow)製程（步驟 S4 )以進行壓印製程（c〇ining pr〇cess，即步驟S5 )，以及 黏合半導體晶圓80之步驟S6。半導體晶圓80與焊膏60 的上表面之間的黏合物是藉由形成在半導體晶圓80底面 之部分的晶片凸塊90而形成，其中被黏合的半導體晶圓可 以透過回焊製程（步驟S7)而穩固裝設（步驟S8)。 然而，傳統的焊上墊（SOP)製程卻遭遇到缺點’其 起因於傳統的焊上墊製程本身在製造步驟S2中不能應用 於凸塊間距（bump pitch )過小的製程，其中焊膏是印刷在 金屬遮罩上。關於以上缺點的詳細說明，以下將配合圖3 來敎述。 隨著凸塊間距變的越小越窄，金屬遮罩的厚度及材質 與焊膏的厚度扮演著重要的變數。亦即換句話說’如圖3 201104767 >斤示’，在金屬遮罩50形成在防焊層20的上表面之情況下 中，塗上焊膏60、進行步驟S3中剝離金屬遮罩的製程。 在移除金屬遮罩後，會有焊料留在一些的小區域中，其將 造成焊膏60隨著金屬遮罩剝離而破碎（crumble )，進而堆 積焊料61於焊膏圖案的間隙表面（gap surface )上，繼而 使相鄰的焊膏連結造成凸塊架橋B而導致在產品的不良率 (defect rate )上出現重大缺點。 上述缺點在凸塊間距小於140微米（μιη)會更加惡化， 而且在精細間距（fine pitch)的環境下，使用金屬遮罩的 焊上墊技術會使問題如滾雪球般的加大。 此外，隨著間距的窄縮，金屬遮罩的製程成本以及處 理細微顆粒（finer particle )之焊膏的所需材料之價格會使 焊上墊技術的缺點以指數方式（exponentially )增加。 【發明内容】 「技術問題」 本發明的構想是要解決上述問題，並且提供一種半導 體封裝的製造方法，其藉由走線上的非阻焊限定型或阻焊 限定型結構，以直接在防焊層上印刷一焊膏，而能大幅增 加基板的電路密度，並且適用於精細圖案，以防止凸塊架 橋的產生。 「技術解決手段」 201104767 * 根據本發明的一考量面，本發明提出一種半導體封裝 的製造方法，包括：在一絕緣基板上形成一具有一開口之 一防焊層的一第一步驟；以及在防焊層上穩固黏合一焊膏 與一金屬球，以將晶片裝設在其中的一第二步驟。 在本發明的一些實施例中，第一步驟包括：（a)在絕 緣基板上形成一走線；以及(b)形成具有一個或多個開口 的防焊層，其中走線的相鄰基板的表面被暴露。 在本發明的一些實施例中，第二步驟包括：（c)在防 焊層上印刷焊膏；（d)在開口的焊膏之表面上黏合一金屬 球；（d)在開口的焊膏之表面上黏合一金屬球；以及(e)在 金屬球上黏合一晶圓級的晶片。 使用於穩固黏合的金屬球以及在製造方法中黏合的金 屬球可以是選自於由銅、鎳、錫、铭、金、氮化鈦、銦或 其他由這些金屬的一種或多種結合而成的合金所構成的一 群組，其中穩固黏合的手段為透過回焊接續黏合後的金屬 球來達成。 金屬球的材料由複合層（composite layer)所構成，其 具有一核心，而核心的詳細介紹在於核心是由金屬或塑膠 所製成，而外圍包覆核心的部分是選自於由銅、錄、錫、 鋁、金、氮化鈦、鉛或銦所構成之一群組而形成的單一或 多層膜層，且金屬球可以透過回焊製程而被結合。 金屬球可以淺薄地進行有機材料塗覆（organic material coating)或金屬電鍵（metal plating)的表面處理（surface 201104767 饮eatment)，其中有機材料是有機保焊劑（〇rgank s〇ider Preservation’ OSP)塗層，而金屬電鍍可以採用金、錫、 錄、錯、銀、銦或其他由這些金屬的一種或多種結合而成 的合金所構成的一群、纟且來實現。 透過以上的方法，半導體封裝製造包括以下步驟：一 防焊層設置有-開口，其中絕緣基板上之走線的相鄰基板 之表面被暴露，且焊膏填入開口；以及一金屬球連接於焊 膏以及-晶圓級的-晶片之—晶片凸塊，其中金屬球的直 徑介於20微米〜200微米之間。依據金屬球的一凸塊間距 介於50微米〜200微米之間。 「有利的功效」 其中一有利的功效在於：藉由將焊膏直接印刷在走線 上已形成防焊層開口的防焊層上，基板的電路密度故能大 幅增加，並且因為沒有凸塊架橋的存在，所以能應用於少 於100微米的精細凸塊間距。 另一有利的功效在於：透過使用金屬球來作為基板與 晶片之間的内連線媒介，能解決習知凸塊裂縫的問題，因 而達到物理光學與電性上的優異性能。 又一有利的功效在於：高間隙高度能達到強化可靠度 的功效’且能減少組裝中未填滿（underfill)以及助焊劑去除 程序(flux removing processes)的缺點。 201104767 ί實施方式】 實施例之具有非阻焊限定型防焊層的半導體封裝以及 其製造方法之詳細描述將參照所附之圖式來進行詳細的說 明’其中整篇發明内容中的相似元件符號會參照相似元 件，並且省略對這些元件所作的多餘說明。在以下實施例 的描述中，可以了解，當提及：一元件（element)或一膜 層（film)是位在另一元件或膜層，，上（〇n)，’ ；或是’，連接 於（connected to)或禺接於（coupled to ) ’’另一元件或 膜層時’表示元件或膜層是直接位在其他元件或膜層上； 或是’連接或搞接於其他元件或膜層；或者，可以是位在 元件或膜層之間。 在此表示的基板指的是含括所有能在電子元件 (electronic element)之間傳遞電訊號（electricalsignal) 的基板之概念。舉例而言’本發明的基板可適用於所有使 用覆晶的產品群’例如硬式基板（rigid substrate )、軟式基 板（flex substrate)、LCTT 基板、單面（single surface) / 多面（multi-surface) /多層（multilayer)基板以及半導體 封裝基板（例如：球柵陣列（BGA )、細間距球柵陣列(Fine pitch BGA，FBGA)、帶式球栅陣列（Tape BGA，TBGA)、 晶片尺寸封裝以及其他相似的基板）。以下將以覆晶半導體 封裝·基板作為舉例說明。 為了釐清目的，與本發明相關之技術領域中的已知技 術材料不會進行詳細的描述，以使本發明不會有不必要的 11 201104767 混淆·。因此，用語（term )與片語（phrase )應由整個專利 說明書的内容為基礎來定義。 圖4是一種本發明一實施例之半導體封裝製程的流程 圖。 本發明適用於各種類型之基板内的一電路圖案，例如 阻焊限定型類型（SMD)或非阻焊限定型類型（NSMD)。 本實施例的内容集中於非阻焊限定型類型。 在本實施例的非阻焊限定型類型中，最適合於實施製 程中依序在防焊層形成一開口（ opening )，以使一走線 (trace)與該走線周圍的基板能被暴露出來，一焊膏覆蓋 在防焊層的開口上，一金屬球被黏合以及一晶片被裝設。 請參閱圖5,根據本發明的一種製程將將被更進一步 地詳細說明。 本發明的半導體封裝製程包括：在一絕緣基板（步驟 P1)上形成一非阻焊限定型防焊層；在防焊層上穩固黏合 一焊膏與一金屬球；以及裝設一晶片（步驟P2〜P4)。 步驟P1是在一絕緣基板110上形成非阻焊限定型的一 防焊層120，更具體而言，在絕緣基板110上最好設計出 一走線130區域，以及一防焊層1+20具有至少一個或多個 開口區域（opening area ) 0P ，透過該些區域以暴露出走 線130區域的鄰近基板之表面，其中非阻焊限定型類型涉 及一種當中有一開口區域OP形成在防焊層上的結構，以 使一走線與該走線周圍的一基板被暴露出來。 12 201104767 •在步驟P2中，在防焊層120上覆蓋一層焊膏 使焊膏140可以填入開口區域。 ，以 亦即，在沒有金屬遮罩下，直接在防焊 焊膏，而防焊層以非阻焊卩 P刷一層 A難型形成在H，以辦 加電路密度以及實現焊膏的印刷製程。 a π於f知的方法’因為是在沒有金屬遮 防焊層上進行印刷，所以不會有凸塊架橋產生’進而允ί午 寸的焊膏，藉以能大幅降低製造成本: 獲付的產品品質。還有應注意的是，除了上述直接 印刷方法之外，可以貼合—層分離式賊（sepamedry film)在防焊層上，以更逐漸堆積（a㈣削㈣）防焊層。 在後續的步驟P3中，更佳地，在開口區域〇p内的焊 膏140之表面上黏合一金屬球ls〇，並且在步驟μ中，在 金屬球150上黏合一晶圓級的半導體晶片16(^步驟p3中 的金屬球可以是選自於由金、錫、鎳、鉛、銀、銦或其他 由這些金屬的一種或多種結合而成的合金所構成的一群 組，其中金屬球的外表面可以進行有機材料塗覆（〇rganic material coating)或金屬電鍍（metal plating)的表面處理 (surface treatment )，以防止金屬表面的氧化（oxidation )。 有機材料可以是有機保焊劑（Organic Solder Preservation， 0SP)塗層，而金屬電鍍可以採用金、錫、鎳、鉛、銀與 銦來電鍍。 當然，金屬球的黏合可以是藉由額外的回焊或壓印製 13 201104767 程來接續進行。特別是，壓印製程為選擇性製程，因此， 有鑑於特性變化甚小的金屬球，例如銅球，本發明可以是 省略壓印製程來實現。 圖6纟會示在圖5中增加壓印的一種步驟。所有圖6中 的步驟均與圖5相同，除了壓印金屬球150的上表面的步 驟P32是跟隨在步驟P3之後，同時增加二個步驟，其中步 驟P31是黏合金屬球之後的回焊製程，而步驟P41是經由 黏合一晶片凸塊161與一金屬球150的回焊製程。 在不同的實施例中，金屬球的核心可以是由金屬或塑 膠而製成，其中外圍包覆核心的部分是選自於由銅、鎳、 錫、鋁、金、氮化鈦、鉛或銦所構成之一群組而形成的單 一或多層膜層。 步驟P4定義裝設一晶圓級的半導體晶片160的製程， 而更具體而言，金屬球150能適應通過回焊製程，並透過 回焊製程而與半導體晶片160的一晶片凸塊161結合而穩 固設置。 特別地，在本發明的一實施例中，其中銅球用來作為 金屬球，而銅被用來作為基板與晶片之間的一種内連線 (interconnection )材料，以獲得相對高的間隙高度 (stand-off height )，藉此，一種在電性與物理性上具備優 異特性的可靠結構能更佳穩固。 為了此目的，金屬球最佳的直徑介於20微米〜200微 米，而金屬球的凸塊間距位在50微米〜200微米的範圍内。 14 201104767 • 亦即’在本發明的此實施例中，其中銅球用來作為金 屬球’而經常發生在一般Sn37Pb、或SAC305、SAC305、 Sn0.7Cu凸塊中的凸塊裂縫（bunlp crack )不會產生，進而 強化產品的可靠度（reliability)以及在電性觀點上能具備 優異的特性。 此外’少量的焊料也可以塗覆在基板以及晶圓凸塊 上’解決難以處理的凸塊架橋產生之問題，並能使習知印 刷技術達到精細間距小於1〇〇微米以及焊上墊技術的凸塊 結構。 圖7是根據本發明所緣示的半導.體封裝的剖面示意 圖。 更具體而言，絕緣基板110具備配置有開口區域OP 的一防焊層120，走線130之相鄰基板的一表面從開口區 域〇P暴露出’焊膏14〇填入開口區域〇p，並且配置連接 於焊膏140以及晶圓級之半導體晶片16〇的晶片凸塊ι61 的一金屬球150。特別地，金屬球最好是銅球，而且如上 所述’金屬球可以由各種不同的材料所形成。金屬球的直 控最好是在20微米〜2〇〇微米之間。 本發明的概念以前述實施例呈現及說明如上，而本發 明所屬技術領域中具有通常知識者所作更動與潤飾之等效 替換’在不脫離本發明之精神和範圍内，仍為本發明之專 利保護範圍内。 15 201104767 f產業利用性」 藉由直接在防焊層上印刷一已在走線上形成防焊層開 口之後的焊膏，一基板的一電路密度能而大幅地增加，並 且因為沒有凸塊架橋的存在，所以能應用於少於100微米 的精細凸塊間距，透過使用金屬球來作為基板與晶片之間 的内連線媒介，能解決習知凸塊裂縫的問題，因而達到物 理光學與電性上的優異性能，而高間隙高度能達到強化可 靠度的功效，且能減少組裝製程中未填滿以及助焊劑去除 程序的缺點。 【圖式簡單說明】 圖1、2與3繪示一流程圖與一示意圖用於說明習知技術 中的焊上墊製程以及其缺點。 圖4、5與6說明本發明之一流程圖以及一半導體封裝製程 的示意圖。 圖7是本發明之一半導體封裝的剖面示意圖。 16 201104767 ί主要元件符號說明】 10、 110 絕緣基板 20 ' 120 防焊層 30 接墊 40 貫孔 50 金屬遮罩 60 ' 140 焊膏 61 焊料 80 半導體晶圓 90 > 161 晶片凸塊 130 走線 150 金屬球 160 半導體晶片 Β 凸塊架橋 OP 開口區域 P1〜P4 、 P31 、 P32 、 P41 、 S1〜S8 步驟 17201104767 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 】 】 】 】 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南 南For reference. The present invention relates to a method of fabricating a semiconductor package capable of overcoming a solder-on-pad in a flip chip mounting method of a Printed Circuit Board (PCB). SOP) technical issues, and in particular, a Non Solder Mask Defined (NSMD) structure or a Solder Mask Defined (SMD) structure formed on a trace The solder resist opening can greatly increase the substrate circuit density process to directly print the solder paste on the solder mask and prevent the bump bridge from being generated. Suitable for fine patterns. [Prior Art] With the rapid development of the electronics industry, it focuses on miniaturization, multi-function, high performance, high integration, and large volume, especially in In terms of conductor wafers, packaging technology has increased its own importance. It has become an ability to ultimately determine the electrical performance, reliability (relibiHty), productivity (pr〇ductivity) and miniaturization of electronic systems. The core technology. Packaging technology defines a series of processes that enable each wafer that is finally manufactured in the wafer process to be sold in the near future, in order to increase the M〇unting efficiency per unit volume. Has been introduced, such as Ball 〇 Array (BGA), Chip Size Package (CSP), and Multi Chip Module (MCM) semiconductor package structure, in which two or more wafers are transmitted. In combination with a single package structure, two or more wafers are typically disposed in a multi-chip module semiconductor package on a common substrate. Recently, packaging technology for protecting semiconductor components from external environmental damage, which is required to be manufactured in response to the trend of miniaturization and high integration of electronic devices, needs to be light, short, high, and high. Functional, high performance and high density installation. In accordance with the above product requirements, a δ-technical technique capable of directly bonding a bare chip obtained from a wafer to a substrate has appeared. That is, 'fjip chip bonding (FCB)-based packaging is considered to be one of the typical chip size packages 'where semiconductor wafers do not need to be wired' to be electrically connected On a printed circuit board (printed circuit 201104767 6oard 'PCB), it can be reduced in appearance compared to a package with wire bonding 'and because the wafer itself is treated as an enclosure, the size of the surrounding body and the size of the wafer Equal, but to reduce the size. In a flip chip package, a liquid underfill layer is formed to ensure that the adhesion (c〇hering p0wer) is sufficient to handle the height of the solder bumps attached to the semiconductor wafer contacts. In turn, the bonding effect and the heat transmission capacity are enhanced while preventing thermal stress. The flip-chip bonding-based package can shorten the connection distance between the semiconductor wafer and the connection interface (C〇nnecti〇npad) and contribute to electrical pr〇perties. In addition, since the self-alignment effect of the ball is advantageous for miniaturization and thinning, the bonding method becomes simple. There is also an advantage. Since the input and output terminals are arranged under the wafer, the transmission rate of the signal is about 2 times faster than that of the conventional wire bonding method. Now, please refer to FIG. 1 and FIG. 2, which illustrate a packaging process in which a wafer is mounted on a joint via solder according to a solder pad (SOP) process and through conventional packaging techniques, wherein FIG. 1 is a conventional soldering process. FIG. 2 is a detailed process diagram of FIG. 1, and FIG. 3 is an enlarged schematic view illustrating a problem occurring in step S3. of FIG. 2. First, a substrate which has been formed and has a solder resist-defining bump pad is loaded (step S1). In this step si, a solder resist layer 20 is formed on an insulating substrate 10, wherein the solder resist layer 2 is formed by a solder resist defining structure, 201104767 and covering a predetermined external position of the interface 30 (externai p〇rti〇 n). A part of the pads 30 may be formed in a structure in which a via 4 is connected, and the through holes 4 are penetrated through the insulating substrate 1A. Successively, in step S2, a metal mask 50 is formed on the upper surface of the solder resist layer 20, and the metal mask 5 can be used as a mask for printing solder paste 60. Pattern (mask pattern). The above printing method may be a stencil printing method or the like. In step S3, the metal mask 50 is removed by exfoliation. The solder paste is printed, and the step progresses to a reflow process (step S4) to perform an imprint process (step S5), and a step S6 of bonding the semiconductor wafer 80. The adhesive between the semiconductor wafer 80 and the upper surface of the solder paste 60 is formed by a wafer bump 90 formed on a portion of the bottom surface of the semiconductor wafer 80, wherein the bonded semiconductor wafer can pass through a reflow process (step S7) is firmly installed (step S8). However, the conventional pad-on-pad (SOP) process suffers from the disadvantages of the conventional pad-on-pad process itself, which cannot be applied to the process of too small bump pitch in the manufacturing step S2, in which the solder paste is printed. On the metal cover. A detailed description of the above disadvantages will be described below in conjunction with FIG. As the pitch of the bumps becomes smaller and narrower, the thickness and material of the metal mask and the thickness of the solder paste play an important variable. In other words, in the case of the metal mask 50 being formed on the upper surface of the solder resist layer 20, in the case of the metal mask 50, the solder paste 60 is applied, and the metal mask is peeled off in the step S3. Process. After the metal mask is removed, the solder remains in a small area, which will cause the solder paste 60 to crumble as the metal mask peels off, thereby depositing the solder 61 on the gap surface of the solder paste pattern (gap) On top of the surface, the adjacent solder paste is then bonded to cause the bump bridge B to cause a major disadvantage in the defect rate of the product. The above disadvantages are further exacerbated when the bump pitch is less than 140 micrometers (μιη), and the solder pad technology using a metal mask can cause problems such as snowballing in a fine pitch environment. In addition, as the pitch is narrowed, the cost of the metal mask process and the price of the material required to process the solder paste of the fine particles increase the exponentially disadvantages of the solder pad technology. SUMMARY OF THE INVENTION [Technical Problem] The present invention has been made to solve the above problems, and to provide a method of manufacturing a semiconductor package which is directly soldered by a non-resistance-limited or solder resist-limited structure on a trace. A solder paste is printed on the layer to greatly increase the circuit density of the substrate and is suitable for fine patterns to prevent the occurrence of bump bridges. "Technical Solution" 201104767 * According to a consideration of the present invention, the present invention provides a method of fabricating a semiconductor package, comprising: forming a first step of forming a solder resist layer having an opening on an insulating substrate; A second step of firmly bonding a solder paste and a metal ball on the solder resist layer to mount the wafer therein. In some embodiments of the invention, the first step comprises: (a) forming a trace on the insulating substrate; and (b) forming a solder mask having one or more openings, wherein the adjacent substrate of the trace The surface is exposed. In some embodiments of the invention, the second step comprises: (c) printing a solder paste on the solder mask; (d) bonding a metal ball on the surface of the open solder paste; (d) solder paste at the opening Bonding a metal ball to the surface; and (e) bonding a wafer level wafer to the metal ball. The metal ball used for the stable adhesion and the metal ball bonded in the manufacturing method may be selected from the group consisting of copper, nickel, tin, indium, gold, titanium nitride, indium or the like, or a combination of one or more of these metals. A group of alloys in which the means of solid adhesion is achieved by reflowing the bonded metal balls. The material of the metal ball is composed of a composite layer, which has a core, and the core is detailed in that the core is made of metal or plastic, and the part of the peripheral cladding core is selected from copper, recorded. A single or multi-layer film formed by grouping of tin, aluminum, gold, titanium nitride, lead or indium, and the metal balls can be bonded through a reflow process. The metal ball can be superficially subjected to an organic material coating or a metal plating surface treatment (surface 201104767 drinking placement), wherein the organic material is an organic soldering agent (〇rgank s〇ider Preservation' OSP) The layer, and the metal plating can be realized by a group of gold, tin, nickel, silver, indium or other alloys formed by combining one or more of these metals. Through the above method, the semiconductor package manufacturing includes the following steps: a solder mask is provided with an opening, wherein a surface of an adjacent substrate on the insulating substrate is exposed, and a solder paste is filled in the opening; and a metal ball is connected to Solder paste and wafer-level-wafer bumps in which the metal spheres are between 20 microns and 200 microns in diameter. The pitch of a bump according to the metal ball is between 50 micrometers and 200 micrometers. "Effective effect" One of the advantageous effects is that the circuit density of the substrate can be greatly increased by directly printing the solder paste on the solder resist layer on which the solder resist layer is formed on the trace, and since there is no bump bridging It exists, so it can be applied to fine bump pitches of less than 100 microns. Another advantageous effect is that by using a metal ball as an interconnecting medium between the substrate and the wafer, the problem of the conventional bump crack can be solved, thereby achieving excellent physical and electrical properties. Yet another advantageous effect is that a high gap height can achieve the effect of enhancing reliability' and can reduce the disadvantages of underfill and flux removal processes in the assembly. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A detailed description of a semiconductor package having a non-solder resistive type solder resist layer and a method of manufacturing the same will be described in detail with reference to the accompanying drawings, in which Reference will be made to similar elements and redundant description of these elements will be omitted. In the description of the following embodiments, it can be understood that when it is mentioned that an element or a film is located on another element or film layer, (〇n), '; or ', "connected to" or "coupled to" ''another element or layer' means that the element or layer is directly on the other element or layer; or 'connected or connected to other element' Or a film layer; or, it may be between the element or the film layer. The substrate referred to herein refers to the concept of including all substrates capable of transmitting electrical signals between electronic elements. For example, the substrate of the present invention can be applied to all product groups using flip chip, such as a rigid substrate, a flex substrate, an LCTT substrate, a single surface, or a multi-surface. /multilayer substrates and semiconductor package substrates (eg, ball grid array (BGA), fine pitch ball grid array (Fine pitch BGA, FBGA), strip ball grid array (Tape BGA, TBGA), wafer size package, and others) Similar substrate). The flip chip semiconductor package and substrate will be described below as an example. For the purpose of clarification, the technical material in the technical field related to the present invention will not be described in detail so that the present invention will not be unnecessarily obscured. Therefore, the terms and phrases should be defined based on the content of the entire patent specification. 4 is a flow chart showing a semiconductor package process in accordance with an embodiment of the present invention. The present invention is applicable to a circuit pattern in various types of substrates, such as a solder mask limited type (SMD) or a non-solder resist defined type (NSMD). The content of this embodiment focuses on the non-resistance limited type. In the non-resistance limiting type of the embodiment, it is most suitable to form an opening in the solder resist layer in order to enable a trace and a substrate around the trace to be exposed. Out, a solder paste is placed over the opening of the solder mask, a metal ball is bonded and a wafer is mounted. Referring to Figure 5, a process in accordance with the present invention will be described in further detail. The semiconductor package process of the present invention comprises: forming a non-solder resist-defining solder mask on an insulating substrate (step P1); firmly bonding a solder paste and a metal ball on the solder resist layer; and mounting a wafer (step P2~P4). Step P1 is to form a solder resist layer 120 of a non-resistance soldering type on an insulating substrate 110. More specifically, a trace 130 region is preferably formed on the insulating substrate 110, and a solder resist layer 1+20 is formed. Having at least one or more opening areas 0P through which the surface of the adjacent substrate of the area of the trace 130 is exposed, wherein the non-resistance limiting type relates to an open area OP formed on the solder resist layer The structure is such that a trace is exposed with a substrate around the trace. 12 201104767 • In step P2, the solder resist layer 120 is covered with a layer of solder paste so that the solder paste 140 can be filled into the open area. That is, in the absence of a metal mask, directly in the solder paste, and the solder resist layer is brushed with a non-resistance 卩P. A hard type is formed in H to handle the circuit density and realize the solder paste printing process. . a π in the method of knowing 'because it is printed on the metal-free solder mask, so there is no bump bridge to produce 'and then allow the solder paste, which can greatly reduce the manufacturing cost: the paid product quality. It should also be noted that in addition to the above direct printing method, a seperastic film may be attached to the solder resist layer to gradually build up (a (four) cut (4)) solder resist layer. In a subsequent step P3, more preferably, a metal ball ls is adhered to the surface of the solder paste 140 in the opening region 〇p, and in the step μ, a wafer-level semiconductor wafer is bonded to the metal ball 150. 16 (^ the metal ball in step p3 may be selected from the group consisting of gold, tin, nickel, lead, silver, indium or other alloys formed by combining one or more of these metals, wherein the metal ball The outer surface may be subjected to surface treatment of 〇rganic material coating or metal plating to prevent oxidation of the metal surface. The organic material may be an organic soldering agent (Organic Solder) Preservation, 0SP) coating, while metal plating can be plated with gold, tin, nickel, lead, silver and indium. Of course, the bonding of metal balls can be continued by additional reflow or stamping 13 201104767 In particular, the imprint process is a selective process, and therefore, in view of a metal ball having a very small change in characteristics, such as a copper ball, the present invention can be realized by omitting an imprint process. A step of increasing the imprint is shown in Fig. 5. All the steps in Fig. 6 are the same as in Fig. 5 except that the step P32 of embossing the upper surface of the metal ball 150 follows the step P3 while adding two steps, wherein the steps are P31 is a reflow process after bonding the metal balls, and step P41 is a reflow process by bonding a wafer bump 161 and a metal ball 150. In different embodiments, the core of the metal ball may be made of metal or plastic. The portion in which the peripheral cladding core is formed is a single or multi-layered film layer selected from the group consisting of copper, nickel, tin, aluminum, gold, titanium nitride, lead or indium. The process of mounting a wafer level semiconductor wafer 160, and more specifically, the metal ball 150 can be adapted to be stabilized by a reflow process and by a wafer bump 161 of the semiconductor wafer 160 through a reflow process. In particular, in an embodiment of the invention wherein a copper ball is used as a metal ball and copper is used as an interconnect material between the substrate and the wafer to achieve a relatively high gap height. (stand-off height), whereby a reliable structure with excellent electrical and physical properties can be better stabilized. For this purpose, the best diameter of the metal sphere is between 20 micrometers and 200 micrometers, and the metal sphere The bump pitch is in the range of 50 μm to 200 μm. 14 201104767 • That is, in this embodiment of the invention, in which the copper ball is used as a metal ball, it often occurs in general Sn37Pb, or SAC305, SAC305. The bump crack in the Sn0.7Cu bump does not occur, thereby enhancing the reliability of the product and having excellent characteristics from the viewpoint of electrical properties. In addition, 'a small amount of solder can also be applied to the substrate and the bumps on the wafer' to solve the problem of difficult-to-handle bump bridges, and to enable the conventional printing technology to achieve a fine pitch of less than 1 μm and solder pad technology. Bump structure. Figure 7 is a cross-sectional schematic view of a semiconductor package in accordance with the teachings of the present invention. More specifically, the insulating substrate 110 includes a solder resist layer 120 in which the opening region OP is disposed, and a surface of the adjacent substrate of the trace 130 exposes the solder paste 14 from the opening region 〇P to fill the opening region 〇p, And a metal ball 150 connected to the solder paste 140 and the wafer bumps 6161 of the semiconductor wafer 16 of the wafer level is disposed. In particular, the metal balls are preferably copper balls, and as described above, the metal balls can be formed from a variety of different materials. The direct control of the metal balls is preferably between 20 microns and 2 microns. The concept of the present invention is presented and described above in the foregoing embodiments, and the equivalents of the modifications and refinements made by those of ordinary skill in the art of the present invention are still in the patents of the present invention without departing from the spirit and scope of the present invention. Within the scope of protection. 15 201104767 fIndustry Utilization" By directly printing a solder paste on the solder resist layer after the solder mask opening has been formed on the trace, a circuit density of a substrate can be greatly increased, and since there is no bump bridging Existence, so it can be applied to the fine bump pitch of less than 100 microns. By using the metal ball as the interconnecting medium between the substrate and the wafer, the problem of the conventional bump crack can be solved, thus achieving physical optics and electrical properties. Excellent performance, high gap height can enhance the reliability of the reliability, and can reduce the shortcomings of the assembly process and the flux removal process. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1, 2 and 3 illustrate a flow chart and a schematic diagram for explaining the solder pad process and its disadvantages in the prior art. 4, 5 and 6 illustrate a flow chart of the present invention and a schematic diagram of a semiconductor package process. Figure 7 is a cross-sectional view showing a semiconductor package of the present invention. 16 201104767 ί Main component symbol description] 10, 110 Insulating substrate 20 '120 Solder mask 30 Pad 40 Through hole 50 Metal mask 60 '140 Solder paste 61 Solder 80 Semiconductor wafer 90 > 161 Wafer bump 130 Trace 150 Metal Ball 160 Semiconductor Wafer 凸 Bump Bridge OP Opening Areas P1 to P4, P31, P32, P41, S1~S8 Step 17

Claims (1)

201104767 七、申請專利範園： 1. 一種半導體封裝的製造方法，包括： 防焊層的第 在一絕緣基板上形成具有一開口之 一步驟；以及 你皤卩万坪層 2. 設多個晶片在其中的第二步驟广、'屬球’以展 1項所述之半導體封裝的製造方 /、中該弟一步驟包括： (a)在該絕緣基板上形成一走線；以及 該走Π?!·有一個或多個開口的該防焊層，其中 β、”、才目鄰基板的-表面從該開口暴露出。 :申：：利範圍第2項所述之半導體封裝的製造方 法’其中該第二步驟包括： (C)在该防焊層上印刷該焊膏； 球及在該開口的該烊膏之—表面上黏合一金屬 ()在》亥金屬球上黏合一晶圓級的晶片。 :申：專利範圍第3項所述之半導體封裝的製造方 暮’其中該步驟（c)包括使用一乾膜或直接印刷該焊 月以在該防焊層上形成一焊膏。 =請專㈣_丨至4項中的任—項所述之半導體 :的製造方法’其中在該防焊層上穩固黏合該金屬 ;、X步驟包括回焊該金屬球，而該金屬球選自於由 18 201104767 鲖、鎳、錫、鋁、金、翁 的一種或多種姓〜心人1姻或其他由這些金屬 6 ^由。而成的合金所構成的一群組。 .如申清專利範園第1至4項中的# 5 封穿的制m 4 頁中的任—項所述之半導體 玫二：仏/、、令在該防焊層上穩固黏合該金屬 球的该步驟包括回焊該金屬 銅生屬球*該金屬球選自於由 其中該金屬球二化鈦、錯所構成的-群組， 7. .° ; /、 核心，其是由金屬或塑膠而製成。 申利範圍第5項所述之半導體封裝的製造方 :表=金屬球進行-有機材料塗覆或-金屬電鐘 9, =申：：利範圍第7項所述之半導體封褒的製造方 田/中該有機材料是有機保焊劑，而該金屬電鑛採 盈 '錫、鎳、錯、銀、銦或其他由這些金屬的一種 或夕種結合而成的合金所構成的一群組來實現。 一種半導體封裝，包括： -防焊層配置有一開口，在一絕緣基板上的一走 線之-相鄰基板的—表面從該開口暴露出，而一焊膏 填入該開口；以及 月 一金屬球，連接於該焊膏以及一晶圓級的一晶片 之一晶片凸塊，其中該金屬球的直徑是在2〇微:至 200微米之間。 10.如申請專利範圍第9項所述之半導體封裝，其中根據 該金屬球，一凸塊間距是在5〇微米至2〇〇微米之間。 19201104767 VII. Application for Patent Park: 1. A method of manufacturing a semiconductor package, comprising: forming a step of forming an opening on a first insulating substrate of a solder resist layer; and forming a plurality of wafers In the second step of the method, the manufacturing process of the semiconductor package described in the 'Balls' is disclosed in the following: (a) forming a trace on the insulating substrate; and the walking The solder resist layer having one or more openings, wherein the surface of the substrate adjacent to the substrate is exposed from the opening. The manufacturing method of the semiconductor package described in claim 2: The second step includes: (C) printing the solder paste on the solder resist layer; bonding a metal to the surface of the paste on the surface of the paste (a) bonding a wafer on the metal ball The wafer of the semiconductor package described in claim 3, wherein the step (c) comprises using a dry film or directly printing the solder moon to form a solder paste on the solder resist layer. = Please use the semiconductor described in (4) _ 丨 to 4 The manufacturing method 'where the metal is firmly bonded to the solder resist layer; the X step includes reflowing the metal ball, and the metal ball is selected from the group consisting of 18 201104767 鲖, nickel, tin, aluminum, gold, and Or a group of multiple surnames ~ heart 1 marriage or other alloys made of these metals. ^ ########################### The semiconductor module of any one of the above-mentioned items, wherein the step of firmly bonding the metal ball on the solder resist layer comprises reflowing the metal copper ball * the metal ball is selected from the group consisting of The metal ball is made of titanium dioxide, a group formed by a fault, 7. . . ; /, a core, which is made of metal or plastic. The manufacturer of the semiconductor package described in claim 5: Table = metal ball - organic material coating or - metal electric clock 9, = Shen:: the manufacturing of the semiconductor package described in item 7 of the benefit range, the organic material is an organic soldering agent, and the metal electric ore采盈's tin, nickel, erroneous, silver, indium or other alloy composed of one or a combination of these metals A group is implemented. A semiconductor package comprising: - a solder resist layer is provided with an opening, a trace on an insulating substrate - the surface of an adjacent substrate is exposed from the opening, and a solder paste is filled in the And a moon metal ball connected to the solder paste and a wafer bump of a wafer level, wherein the metal ball has a diameter of between 2 micrometers and 200 micrometers. The semiconductor package of claim 9, wherein a bump pitch is between 5 Å and 2 Å according to the metal ball.
TW099113894A 2009-04-30 2010-04-30 Semiconductor package with nsmd type solder mask and method for manufacturing the same TWI406342B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI579096B (en) * 2011-03-29 2017-04-21 松下知識產權經營股份有限公司 Solder transferring substrate, manufacturing method of solder transferring substrate, and solder transferring method
TWI655745B (en) * 2016-08-24 2019-04-01 Center For Advanced Meta-Materials Method for transferring micro components and micro device substrate produced by the method

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102012111358A1 (en) * 2012-11-23 2014-05-28 Osram Opto Semiconductors Gmbh Method for separating a composite into semiconductor chips and semiconductor chip
CN105093853B (en) * 2015-09-02 2017-06-23 广东海圣科技有限公司 Automatic anti-welding exposure desk frame module and exposure machine
KR102094014B1 (en) 2018-09-20 2020-03-27 주식회사 지엔테크 Soldering apparatus for PCB and process method

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100336575B1 (en) * 2000-06-28 2002-05-16 박종섭 Solder ball of semiconductor package and method of fabricating the same
TWI307547B (en) * 2003-06-11 2009-03-11 Phoenix Prec Technology Corp Method for fabricating substrate with plated metal layer over pads thereon
TWI234258B (en) * 2003-08-01 2005-06-11 Advanced Semiconductor Eng Substrate with reinforced structure of contact pad
US7377032B2 (en) * 2003-11-21 2008-05-27 Mitsui Mining & Smelting Co., Ltd. Process for producing a printed wiring board for mounting electronic components
TWI295550B (en) * 2005-12-20 2008-04-01 Phoenix Prec Technology Corp Structure of circuit board and method for fabricating the same
US7652374B2 (en) * 2006-07-31 2010-01-26 Chi Wah Kok Substrate and process for semiconductor flip chip package
TWI375307B (en) * 2007-07-26 2012-10-21 Flip chip package structure and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI579096B (en) * 2011-03-29 2017-04-21 松下知識產權經營股份有限公司 Solder transferring substrate, manufacturing method of solder transferring substrate, and solder transferring method
TWI655745B (en) * 2016-08-24 2019-04-01 Center For Advanced Meta-Materials Method for transferring micro components and micro device substrate produced by the method

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KR20100119328A (en) 2010-11-09

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