TW201101024A - SAS back plate testing device - Google Patents

SAS back plate testing device Download PDF

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Publication number
TW201101024A
TW201101024A TW98120744A TW98120744A TW201101024A TW 201101024 A TW201101024 A TW 201101024A TW 98120744 A TW98120744 A TW 98120744A TW 98120744 A TW98120744 A TW 98120744A TW 201101024 A TW201101024 A TW 201101024A
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Taiwan
Prior art keywords
sas
test
control
physical layer
command
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TW98120744A
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Chinese (zh)
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Quan-Jie Zheng
Chih-Jen Chin
Tom Chen
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Inventec Corp
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Priority to TW98120744A priority Critical patent/TW201101024A/en
Publication of TW201101024A publication Critical patent/TW201101024A/en

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Abstract

A SAS back plate testing device is adapted to test a SAS back plate with a plurality of SAS connection port. The SAS back plate testing device includes a control module for sending a control command, a terminal module, and a signal return module. The terminal module includes a physical layer IC and a control unit. The control unit receives the control command and let the physical layer IC send a test signal to the SAS back plate. The signal return module is electrically connected with the SAS back plate, and returns back the test signal received form the SAS back plate. After receiving the test signal turned by the signal return module, the SAS back plate returns the received test signal to the physical layer IC. Then the physical layer IC compares the original test signal and the test signal received from the SAS back plate, and records the comparing result.

Description

201101024 六、發明說明: 【發明所屬之技術領域】 本發明係有關於一種SAS背板的測試裝置’特別是一種不需 使用實體SAS裝置即能進行SAS背板測試的裝置。 【先前技術】 SAS介面係為新一代的小電腦系統介面(Small Computer System Interface,SCSI)的標準,且為繼並行 SCSI 介面(Parallel SCSI) 之後所開發出的全新介面。SAS介面可以提供多點連接,並且在 最新的SAS3.0的標準中,資料能以6Gbps(每秒十億位元)的速度 雙向傳輸。此外’ SAS介面透過縮小連接線的設計,而具有減少 所佔用的系統内部空間的優點。SAS介面並可向下相容,例如可 與串列尚技術配置(Serial Advanced Technology Attachment,SATA) 硬碟連接。 请參考「第1圖」,其係為習知之SAS背板的測試裝置之結 構不思圖。SAS背板22上具有SAS連接埠24,SAS裝置26則分 別透過SAS連接埠24與SAS背板22相連接,而伺服端20亦電 性連接於SAS背板22。伺服端2G巾的酬程式經由SAS背板而 對SAS裝置26進行存取操作,藉由對SAS裝置%的讀寫以測試 SAS背板22使否可以正常工作。 而此種來戦SAS冑板的方法於每次測試時,均麵閉測 4裝置的電私麵拆裝SAS背板及Μ裝置等。由於每次測試 都須要義電源、重喊置、再重新開啟賴,十分耗費時間。 201101024 »· 再者,嫩物崎置後,偏議作細均顧新啟動。 啟動作«統會花費額外的時間,而造成整體的測試時間隨之延 長,使得戦效率低落。此外,此種戦方法轉備多個實體的 SAS裝置。且若使用SAS硬碟,則由於硬碟具有存取次數的壽命 限制使付此種K裝置所需的成本被提高。在欲測試較高階的 SAS面板(例如SAS3.0)時,舊有的s辦置可能無法繼續使用, 對於舊裝置的汰舊換新亦使得此方法具有成本過高的問題。 基於上述,先前技術之測試SAS背板的裝置,具有測試方法 不便而造細試賴冗長,以及所需設備成本高昂等問題。 【發明内容】 鑑於上制題,本發明之目的在於提供—種sas背板的測試 裝置’能以-終賴組模擬SAS裝置,使得此低成本的測試裝置 快速地完成SAS背板之測試。 ) A 了達成上述之目的,本發明提供—種SAS f板的測試裝 置,適於測試- SAS背板,而SAS f板具有複數個SAS連接淳。 其SAS背板測試裝置包括一控麵組,終端模組,以及一信號回 送核組。控制模組制以發送—控制命令。終端模組包括:一物 理層積體電路’電性連接於SAS連接埠其中之―;以及一控制元 件。控制兀件係承接控制命令並令物理層積體電路發送一測試信 旎予SAS背板,而測試信號係為—模擬SAS裝置之訊號。信號回 送模組係電性連結於SAS背板,並把來自於SAS背板的測試信號 回送給SAS背板。SAS背板於接收回送的測試信號後,並把回送 201101024 的測武仏號傳送予物理層積體電路。物理層積體電路把回送的測 試信號與發送的測試信號進行比對後,記錄一比對結果。 根據本發明之一實施例,上述比對結果係以一指示燈表示。 此外,SAS背板的測試裝置另包含一信號回送模組。控制命令包 含一頻率設定命令,控制元件接收到頻率設定命令時,令物理層 積體電路依據頻率設定命令設定測試信號的頻率。 根據本發明之另-實施例,測試裝置包含另一終端模組,而 另一終端模組的控制元件承接終賴組的控制元件的控制命令。 控制命令使得另-終端餘之物理層雜f路發送、以及接收測 试信號’並且由另—終賴組之物理層频電路記錄比對結果。 _此外’控制命令另包含—定址命令。定址命令係令這些控制 元件依據定址命令設定這些控制元件之位址。_命令另更包含 回傳命令’回傳命令係令這些控制元件回傳這些比對結果。 基於上述’根縣發明鱗賴組槪SAS «置與SAS背板 ,相資料’而終端模組亦可自行產生測試資料並計算比對結果。 是以上述的實_可以減少SAS f㈣職裝朗成本,並大幅 減低測試所需的時間。 /下在實施方式中詳細敘述本發明之詳細特徵以及優點,其 心足以使任何㈣蝴技藝者了解本發明之技舶容並據以實 二且根據本說明書所揭露之内容、申請專利範圍及圖式,任何 无、習相關技藝者可姆地理解本㈣蝴之目的及優點。 201101024 以下敘述之關於本發明的詳細特徵以及優點,其内容足以使 任何熟習相關技藝者了解本發明之技術内容並據以實施,且根據 本說明書所揭露之内容、申請專利範圍及圖式,任何熟習相關技 藝者可輕易地理解本發明相關之目的及優點。 請同時參照「第2圖」與「第3圖」,其分別為根據本發明 之SAS背板的測試裝置之電路方塊示意圖,以及終端模組之電路 方塊不意圖。本發明之SAS背板的測試裝置適用於測試一 SAS背 〇板22 ’且SAS背板具有複數個SAS連接埠24。SAS背板的測試 裝置包括-控制模組3 2、至少一終端模、组3 4以及一信號回送模組 %,其中終端模組34包括一物理層積體電路342卩及一控制元件 344。 根據本發狀—實_,控制餘32可岐但不限於電腦主 機、伺服器、或是單晶片控制器。控制模組32用以發出一控制命 令以控管整個測試流程。終端模組34另可包含一連接介面祕, ❹用以電性連接於控制模組32。此電性連接可以是但不限於管理數 ««Tώ 1 ^#(Management Data Input/Output, MDIO) 〇 ^ ^ 使不藉由連接介面346’控制模組32與終端模組34之間仍可以例 如烊接電線的方式相連。 前述㈣命令係由控纖組32發出給終端池%,翔容可 試前的配置設^域是對於終端模組34的指令。對 Γ測試置之前,控制模組32可根據不_測試目 、可包括一頻率設定命令,則控制模組32藉由下達頻 201101024 率設定命令來指定終端模組34與SAS背板22間的資料傳輸速 率。舉例來說,欲模擬測試在SAS10規格下SAS連接蜂24的傳 輸情況時’頻率設定命令的内容可被設為丨5卿;碰以SA咖 規格進行職時,鮮蚊命令_容可被設為犯咖。在必要 的情況之下’此鮮設定命令有可能為聰咖。 而控制命令另可包括—啟動命令。則控制模組Μ對終端模組 34設定完配置之後’發送啟動命令以令終端模组%㈣始執行對 SAS背板22的測試。 終端模組34藉由SAS連接埠24連接於sAS背板22,並以 MDIO與控麵組32電性相連。終端模組34係用以模擬SAs 裝置26以測5式與SAS背板22之間的物理層(phySicai iayer)的資 料傳輸狀況。前述SAS裴置可以是但不限於SAS硬碟。 終端模組34包括物理層積體電路342以及控制元件3糾,其 中物理層積體電路342係電性連接於SAS連接埠24其中之一), 並產生測s式彳§號後傳SAS背板22。根據本發明,物理層積體電 路342可以是一固定頻率發送物理層信號之積體電路或是能在被 設定後以不同頻率發送物理層信號之積體電路,例如但不限於是 TI的TLK3101 ’最高可達3.125G,TLK2541最高可達2.6G,或 是BroadCom BCM8073最高可達l〇G。前述測試信號係模擬一 SAS裝置的訊號。物理層積體電路342所產生的測試訊號的内容 可以例如是交錯式的序列(例如〇1〇101...)或是隨機亂數的序列201101024 VI. Description of the Invention: [Technical Field] The present invention relates to a test apparatus for a SAS backplane', particularly a device capable of performing SAS backplane testing without using a physical SAS device. [Prior Art] The SAS interface is a new generation of Small Computer System Interface (SCSI) standard and is a new interface developed after the parallel SCSI interface (Parallel SCSI). The SAS interface provides multipoint connectivity, and in the latest SAS 3.0 standard, data can be transmitted bidirectionally at 6 Gbps (billion bits per second). In addition, the 'SAS interface has the advantage of reducing the internal space occupied by the system by reducing the design of the connection line. The SAS interface is backward compatible, for example, it can be connected to a Serial Advanced Technology Attachment (SATA) hard drive. Please refer to "Figure 1" for the structure of the test device of the conventional SAS backplane. The SAS backplane 22 has a SAS port 24, and the SAS device 26 is connected to the SAS backplane 22 via a SAS port 24, and the servo 20 is also electrically coupled to the SAS backplane 22. The servo program of the server 2G accesses the SAS device 26 via the SAS backplane, and the SAS backplane 22 can be tested for normal operation by reading and writing the SAS device %. In this method, the SAS slab is used to disassemble the SAS backplane and the sputum device on each side of the device. Since each test requires power, screaming, and re-opening, it takes a lot of time. 201101024 »· In addition, after the tenderness of the object, the bias is negotiating for a new start. It takes extra time to start the work, and the overall test time is extended, making the efficiency low. In addition, this method of transposition is performed on SAS devices of multiple entities. And if a SAS hard disk is used, the cost required to pay such a K device is increased because the hard disk has a life limit of the number of accesses. When you want to test a higher-order SAS panel (such as SAS3.0), the old s office may not be able to continue to use, and the replacement of the old device also makes this method costly. Based on the above, the prior art device for testing the SAS backplane has problems such as inconvenience in testing methods, lengthy trials, and high equipment costs. SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a test device for a sas backplane capable of simulating a SAS device in a final assembly, enabling the low-cost test device to quickly complete the SAS backplane test. A. To achieve the above object, the present invention provides a test apparatus for a SAS f board suitable for testing - a SAS backplane, and a SAS f board having a plurality of SAS ports. The SAS backplane test device includes a control plane group, a terminal module, and a signal return core group. The control module is configured to send-control commands. The terminal module includes: a physical layered circuit 'electrically connected to the SAS port'; and a control element. The control component takes control commands and causes the physical layer integrated circuit to send a test signal to the SAS backplane, and the test signal is the signal that simulates the SAS device. The signal return module is electrically connected to the SAS backplane and sends test signals from the SAS backplane to the SAS backplane. After receiving the returned test signal, the SAS backplane transmits the test signal of the loopback 201101024 to the physical layer integrated circuit. The physical layer integrated circuit compares the returned test signal with the transmitted test signal and records a comparison result. According to an embodiment of the invention, the comparison result is represented by an indicator light. In addition, the test device of the SAS backplane further includes a signal return module. The control command includes a frequency setting command, and when the control component receives the frequency setting command, the physical layer circuit sets the frequency of the test signal according to the frequency setting command. According to a further embodiment of the invention, the test device comprises a further terminal module, and the control element of the further terminal module takes over the control commands of the control elements of the final group. The control command causes the remaining physical layer of the other terminal to transmit and receive the test signal' and the alignment result is recorded by the physical layer frequency circuit of the other terminal group. _In addition, the control command additionally includes an address command. The addressing command causes these control elements to set the addresses of these control elements in accordance with the addressing command. The _ command also includes a return command. The return command causes these control elements to return these alignment results. Based on the above-mentioned 'Ganxian invention scales 槪 group SAS «set and SAS backplane, phase data' and the terminal module can also generate test data and calculate the comparison results. Therefore, the above actual _ can reduce the cost of SAS f (four) job and reduce the time required for testing. The detailed features and advantages of the present invention are described in detail in the embodiments, which are sufficient to enable any skilled person to understand the scope of the present invention and the scope of the application and the scope of the claims. Schema, any person who is not involved in the relevant art can understand the purpose and advantages of this (4) butterfly. 201101024 The detailed features and advantages of the present invention described in the following are sufficient for any person skilled in the art to understand the technical contents of the present invention and to implement it, and according to the content, patent application scope and drawings of the present specification, The objects and advantages associated with the present invention will be readily understood by those skilled in the art. Please refer to both Fig. 2 and Fig. 3, which are circuit block diagrams of the test apparatus of the SAS backplane according to the present invention, and the circuit blocks of the terminal module are not intended. The test apparatus of the SAS backplane of the present invention is suitable for testing a SAS backplane 22' and the SAS backplane has a plurality of SAS ports 24. The test device of the SAS backplane includes a control module 32, at least one terminal module, a group 34, and a signal loopback module %. The terminal module 34 includes a physical layer circuit 342 and a control component 344. According to the present invention, the control 32 can be controlled, but not limited to a computer host, a server, or a single chip controller. Control module 32 is used to issue a control command to control the entire test process. The terminal module 34 can further include a connection interface for electrically connecting to the control module 32. The electrical connection may be, but is not limited to, the management number ««Tώ 1 ^# (Management Data Input/Output, MDIO) 〇 ^ ^ so that the control module 32 and the terminal module 34 are still not connected by the connection interface 346' For example, the way in which the wires are connected is connected. The foregoing (4) command is issued by the control fiber group 32 to the terminal pool %, and the configuration field before the test is the command of the terminal module 34. Before the test is set, the control module 32 can include a frequency setting command according to the non-testing target, and the control module 32 specifies the terminal module 34 and the SAS backplane 22 by using the sending frequency 201101024 rate setting command. Data transfer rate. For example, to simulate the transmission of the SAS connection bee 24 under the SAS10 specification, the content of the frequency setting command can be set to 丨5 qing; when the SA coffee specification is used, the fresh mosquito command _ can be set. For committing coffee. If necessary, this fresh setting order may be Cong. The control command may additionally include a start command. Then, the control module 发送 sends the start command after the terminal module 34 is configured to enable the terminal module to perform the test on the SAS backplane 22. The terminal module 34 is connected to the sAS backplane 22 via a SAS port 24 and is electrically connected to the control panel 32 by MDIO. The terminal module 34 is used to simulate the SAs device 26 to measure the physical transmission status of the physical layer (physicai iayer) between the type 5 and the SAS backplane 22. The aforementioned SAS device may be, but not limited to, a SAS hard disk. The terminal module 34 includes a physical layer integrated circuit 342 and a control element 3, wherein the physical layer integrated circuit 342 is electrically connected to one of the SAS ports 24, and generates a measurement s § § followed by a SAS back Board 22. According to the present invention, the physical layer integrated circuit 342 may be an integrated circuit for transmitting a physical layer signal at a fixed frequency or an integrated circuit capable of transmitting a physical layer signal at a different frequency after being set, such as but not limited to TI's TLK3101. 'Up to 3.125G, TLK2541 up to 2.6G, or BroadCom BCM8073 up to l〇G. The aforementioned test signal simulates the signal of a SAS device. The content of the test signal generated by the physical layer integrated circuit 342 may be, for example, an interleaved sequence (e.g., 〇1〇101...) or a sequence of random random numbers.

(例如偽隨機二進制序列,pseud〇 Random Binary Sequence,PRBS 2U-1)。物理層積體電路342以控制模組32所指定的傳輸速率把 201101024 測试彳§號發送給SAS背板,而終端模組34模擬SAs枣置2、 行傳輸時,所簡達到的傳輸速度取決於物理層積_路=^ 能力。本實施例使用的職削所能達到的最高傳輸頻率高= lOGbps ’足以充分支援sas3.0標準的6Gbps。 " 物理層積體電路342並以控制模組%所指定的傳輸 SAS背板22所傳回的測試信號,且比對發送的測試信號盘回送 的測試信號,並記錄-比對結果。由於物理層積體電路342可自 〇仃產生賴錢並崎測試結果,是贿纏組32下達啟動会 令後並不需再做與SAS f板測試相關的運算。換言之,控制模^ 32在下達啟動命令後直_試結果產生讀,均可自由執行盆他 工作。 終端模組34的控制元件344係用以控管終端模組34之運作。 控制70件344在承接控麵組32所發出的控制命令後,再傳達 控制命令的内容給物理層積體電路342。例如使得物理層積體電 〇路342改變收發測試信號的頻率,或是發送測試信號予SAS背板 以執行測試的動作。控制元件344亦紀錄終端模組%的狀態, =如終端模組34的電·態是侧啟,或是終端模組34是否已 元成SAS背板的測試動作。 域回送觀38 _时SAS雜22把職信號回送給物 理層積體電路342。回送模組38係電性連結於SAS背板22,並 a來自於SAS者板22的測試信號回送給SAS背板22。因此SAS ^板22 _物理層積體電路342所發送的測試信號後,把測試 喊傳、、、α回送模組% ,再把回送模組%所傳回的測試信號傳送 9 201101024 給物理層積體電路342。又,回送模組38可以是但不限定是一擴 充介面卡(Interface Card,I/F Card)。 而控制模組32為了取得比對結果,控制命令另可包括一回傳 命令。回傳命令係令控制元件344回傳比對結果。控制模組& 獲得比對結果後便可紀錄SAS背板的測試結果,亦可進一步地對 測試結果進行分析,例如產品的良率等。 此外’比對結果亦能以一指示燈36表示。例如使指示燈% 顯示為綠色代表測試成功。其意指物理層積體電路342所發出的 測龜號與由SAS背板22所回送的測試信號經比對後相同,即 表示此終端模組34電性相連的SAS連接埠24傳輸正常。相對 的’若比對結果為测試失敗時,指示燈36醜示為紅色。而指 示燈36另可表示終端模組34職的狀態,例如測試中可閃燦^ 色,而指示燈36熄滅則表示終端模組34為待機中。 除了測試SAS背板Μ的SAS連接琿%的傳輸狀況,控制模 組32亦可藉由控制命令等測試SAS f板22上的發光二極體 (LightEmittingDiode,LED博SAS背板可能需要被檢驗的項目。 根據本發明之另-實施例,SAS背板的測試裝置包含另一終 端模組34,。另一終端模組34,電性連接於Sas背板22上的另 一 SAS連接棒24,,且終端模組34與另一終端模組34,之間透過 連接介面346以MDl〇相連。換言之,終端模組%與另一終端 模組34’以串聯的形式相連結。 '' 另一終端模組34,的控制元件342,係承接終端模組34的控制 兀件342的控制命令,控制命令使得另一終端模組料,之物理層 201101024 積體電路342’發送、以及接收測試信號,並由另一終端模組糾, 之物理層積體電路342,記錄比對結果。更詳細的說,控制元件M2 收到控制命令後除了把控制命令轉給物理層積體電路M2之外, 並把控制命令_傳給㈣元件祀,。控制元件如,祕收測試 命令^轉給物理層積體電路342,,以令物理層積體電路M2,對 SAS背板22進行測試。此外,終端模組%與另一終端模組从 可依序執行測試程序,但亦可同時進行。(eg pseudo-random binary sequence, pseudo〇 Random Binary Sequence, PRBS 2U-1). The physical layer integrated circuit 342 sends the 201101024 test number to the SAS backplane at the transmission rate specified by the control module 32, and the terminal module 34 simulates the transmission speed of the SAs when the transmission is performed. Depends on the physical layer _ road = ^ capacity. The highest transmission frequency achievable by the job-cutting used in this embodiment = lOGbps' is sufficient to fully support the 6 Gbps of the sas3.0 standard. " The physical layer integrated circuit 342 transmits the test signal returned by the SAS backplane 22 as specified by the control module %, and compares the test signal sent back by the transmitted test signal disc, and records the comparison result. Since the physical layer integrated circuit 342 can automatically generate the results of the test, it is not necessary to perform the calculation related to the SAS f board test after the brigade group 32 is issued. In other words, the control module 32 can directly perform the potting work after the start command is issued. The control element 344 of the terminal module 34 is used to control the operation of the terminal module 34. The control 70 piece 344 transmits the content of the control command to the physical layer integrated circuit 342 after receiving the control command issued by the control group 32. For example, the physical layer integrated circuit 342 changes the frequency of transmitting and receiving test signals, or sends a test signal to the SAS backplane to perform the test. The control component 344 also records the status of the terminal module %, if the power state of the terminal module 34 is side-to-side, or whether the terminal module 34 has been tested as a SAS backplane. The domain feedback view 38 _ SAS hybrid 22 job signal is sent back to the physical layer integrated circuit 342. The loopback module 38 is electrically coupled to the SAS backplane 22, and a test signal from the SAS panel 22 is sent back to the SAS backplane 22. Therefore, after the test signal sent by the SAS ^ board 22 _ physical layer integrated circuit 342, the test is transmitted, and the α is sent back to the module %, and then the test signal returned by the loopback module % is transmitted to the physical layer. Integrated circuit 342. Moreover, the loopback module 38 can be, but is not limited to, an interface card (I/F Card). In order to obtain the comparison result, the control module 32 may further include a backhaul command. The return command causes control component 344 to return the alignment result. The control module & can obtain the results of the comparison and record the test results of the SAS backplane, and further analyze the test results, such as the yield of the product. In addition, the results of the comparison can also be indicated by an indicator light 36. For example, if the indicator % is displayed in green, the test is successful. It means that the measured turtle number issued by the physical layer integrated circuit 342 is the same as that of the test signal sent back by the SAS backplane 22, that is, the SAS connection port 24 electrically connected to the terminal module 34 is normally transmitted. The relative indicator ugly is red when the result of the comparison is that the test failed. The indicator light 36 can also indicate the status of the terminal module 34, for example, the test can be flashed, and the indicator light 36 is off, indicating that the terminal module 34 is in standby. In addition to testing the transmission status of the SAS port 珲% of the SAS backplane, the control module 32 can also test the LEDs on the SAS f board 22 by means of control commands, etc. (Light Emitting Diode, LED Boss SAS backplane may need to be inspected According to another embodiment of the present invention, the test device of the SAS backplane includes another terminal module 34. The other terminal module 34 is electrically connected to another SAS connection bar 24 on the Sas backplane 22, And the terminal module 34 and the other terminal module 34 are connected by MD1〇 through the connection interface 346. In other words, the terminal module % is connected in series with another terminal module 34'. '' The control component 342 of the terminal module 34 is a control command for receiving the control component 342 of the terminal module 34, and the control command causes the physical layer 201101024 integrated circuit 342' of another terminal module to send and receive the test signal. And the physical layer integrated circuit 342 is corrected by another terminal module, and the comparison result is recorded. In more detail, after receiving the control command, the control element M2 transfers the control command to the physical layer integrated circuit M2. And pass the control command _ to the (four) component The control element, for example, the secret test command ^ is transferred to the physical layer integrated circuit 342 to cause the physical layer integrated circuit M2 to test the SAS backplane 22. In addition, the terminal module % and another terminal module The test procedure can be executed sequentially, but it can also be performed simultaneously.

為了更加詳細的掌控測試的結果,控制命令另可包括—定址 命令。定址命令係令控制元件344以及另一控制元件,依據定 址命令個別設位址。如此—來,#發生測試失敗時,控制模 、、且32便可赠被傳回義轉知錯誤發纽終端触%亦咬玖 端模組34,。且藉由定址命令與回傳命令,控制模組如更能令控 制元件344以及另-控制元件344’回傳個別的比對結果。與終= 模組34同樣地,比對結果亦能以一指示燈%,表示。 於上述實施财可知,根縣發明之SAS背_峨裝置内 可包含複數雜端模組Μ,其分顺同—SAS f板a _不同 SAS連接埠24電性連接,且多個終端餘M之恥以串聯的方 式連接。控制元件344承接控制命令後把控制命令再傳給其他的 終端模組34,並侧依據㈣命令行動。而控倾_ 端模組34的位址進行區別。 ς 請參照「第4圖」’其係為根據本發明之SAS背板測試方法 之流程示意圖。由圖可以知悉,測試的流程包括步驟柳:控制 模組32列舉(enumerate)連接中的終端模組34的個數;步驟撕 201101024 :===__職值;步物:判斷是否使 S90 '驟腳.蚊預舰置值轉截組34 ;步称 ==殊:置值予终端模組34;步物:令终端模组 .細軸序;㈣sm :觸㈣彳試完所妹終端模組 ,以及步驟S120 :令終端模組34回傳比對結果。 ;步驟s5〇中’控制模組以列舉的方式搜尋與⑽背板μ 連接中的終端模組34的健,並於步驟_中檢查搜尋到的終端 模組34的個數是否與事先設定的欲測試個數。若以列舉的方式找 出的連接中的終端模組34健與設紐不合,則重新列舉搜尋。 若個數正破,則步驟S70判斷是否使用預設配置值於終端模短 控制额32謂不義f職織林_崎。例如欲對 不同的SAS連接埠24測試不同的傳輸頻率時,即可下達定址命令 與頻率指定命令以指定不同的傳輸頻率給每-個終端模組34。故 依據不冋的需求,控制模組32可在步驟S8〇對終端模組从指定 預設的配置,亦可在步驟S%指定特別的配置。 /依據控制模組32所指定的配置,終端模組34於步驟麵中 執行測試程序。請同時參照「第5 ®」,其係為根據本發明之SAS 背板测4方法之步驟81〇〇之流程示意圖。由圖可知,測試流程中 包括步驟SKU :物理層積體電路342產生測試信號;步驟麗: 物理層積體電路342發送測試信號給SAS背板22 ;步驟si〇3 : SAS背板22由SAS連接崞24 _測試信號後傳給回送模組38 ; 步驟S1G4 .回送觀38把測試職傳回給sas背板η ;步骤 201101024 SK)5 : SAS背板22透過SAS連接埠24把測試信號傳回給物理層 賴電路342 ;步驟S106 :物理層積體電路3幻接收傳回來的測 試信號;以及步驟S107 :物理層積體電路342比對回送的測試信 虎與發送的測試信號’紀錄比對結果。 於步驟腫中’首先物理層積體電路%產生測試信號,並 於步驟⑽中把測試信號藉由SAS連接埠%發送給_背板 22。則於步驟麗’ SAS背板22 _職錢後傳送給回送模 〇組38,而回送模組38於步驟漏直接將收到的測試信號再傳回 給SAS背板22。SAS背板22收到由回送模組%所傳來的測試信 號後’於步驟娜透過SAS連鱗24把測試信號_給物理層 =體電路342,並且_層積體電路342於步驟遍中接收由⑽ 背板22所傳回的測試信號。In order to control the results of the test in more detail, the control command may additionally include an address command. The addressing command causes the control element 344 and another control element to individually set an address in accordance with the addressing command. So, come, # When the test fails, the control module, and 32 can be sent back to the right and the wrong terminal is also touched. And by the addressing command and the return command, the control module can further cause the control component 344 and the other control component 344' to return the individual comparison results. As with the final = module 34, the comparison result can also be represented by an indicator light %. As can be seen from the above implementation, the SAS back_峨 device invented by Gen County can include a plurality of miscellaneous modules, which are compliant with each other—SAS f board a _ different SAS ports 电 24 electrical connections, and multiple terminals M The shame is connected in series. The control component 344 receives the control command and then transmits the control command to the other terminal module 34, and acts according to the (4) command. The address of the control _ terminal module 34 is distinguished. ς Refer to “Fig. 4”, which is a schematic flow chart of the SAS backplane test method according to the present invention. As can be seen from the figure, the test process includes steps: the control module 32 enumerates the number of terminal modules 34 in the connection; the step tears 201101024: ===__ job value; step: determine whether to make S90 'Steps. Mosquito pre-ship set-turn group 34; step name == special: set to terminal module 34; step: order terminal module. fine axis order; (four) sm: touch (four) 彳 test the sister terminal The module, and step S120: cause the terminal module 34 to return the comparison result. In step s5, the control module searches for the health of the terminal module 34 in the (10) backplane μ connection in an enumerated manner, and checks whether the number of the searched terminal modules 34 is set in advance in step _ Want to test the number. If the terminal modules 34 in the connection that are found in the enumerated manner do not match the settings, the search is re-listed. If the number is broken, step S70 determines whether the preset configuration value is used in the terminal mode control amount 32 is untrue. For example, if different SAS ports 24 are to be tested for different transmission frequencies, the address command and the frequency designation command can be issued to specify different transmission frequencies for each terminal module 34. Therefore, according to the unsatisfactory requirements, the control module 32 can specify a preset configuration for the terminal module in step S8, and can also specify a special configuration in step S%. / According to the configuration specified by the control module 32, the terminal module 34 executes the test program in the step plane. Please also refer to "5th Edition", which is a schematic diagram of the process of step 81 of the SAS backplane measurement method according to the present invention. As can be seen from the figure, the test flow includes a step SKU: the physical layer integrated circuit 342 generates a test signal; the step: the physical layered circuit 342 sends a test signal to the SAS backplane 22; step si〇3: the SAS backplane 22 is composed of SAS The connection 崞24_ test signal is transmitted to the loopback module 38; step S1G4. The return view 38 transmits the test job back to the sas backplane η; step 201101024 SK)5: the SAS backplane 22 transmits the test signal through the SAS connection 埠24 Returning to the physical layer circuit 342; step S106: the physical layer integrated circuit 3 phantom receiving the transmitted test signal; and step S107: the physical layer body circuit 342 comparing the feedback test letter with the transmitted test signal 'record comparison result. In the step swollen, the first physical layer integrated circuit % generates a test signal, and in step (10), the test signal is sent to the backplane 22 by the SAS connection 埠%. Then, the step ’ ' SAS back board 22 _ job money is transmitted to the return mode group 38, and the loopback module 38 directly transmits the received test signal back to the SAS back board 22 in the step leakage. After receiving the test signal transmitted by the loopback module %, the SAS backplane 22 passes the test signal _ to the physical layer = body circuit 342 through the SAS squaring 24, and the _layered body circuit 342 is in the step The test signal transmitted by the (10) backplane 22 is received.

^藉由上述-連串的傳輸過程,模擬以終端模組%代替MS 〇裝置26的存取,吨彌輸的_戦sas連接埠μ使否 可以,常存取。因此最後於步驟sl〇7,物理層積體電路%把由 SAS背板朗補職信號與本身發送的職信舰行比對,並 把比對結果紀錄下來。 藉由定址’各個終端敎34可依序朗時對各個sas連接璋 24進=職信號的傳輸。控制模組%於步驟漏树認是否所 有終端拉組34均測試完畢,並可於步驟si2〇中下達回傳命令, 、长各個終端模組34日傳比對結果。而藉由指示燈%,即使不 把比對結果回傳,亦能表示出SAS背板的測試結果。 13 201101024 據本發明之SAS背板的測試裝置,可使用終端裝置模擬SAS 裝置,而能此終端模組夠自行產生測試信號並產生比對結果,進 行與SAS f板間的資料傳輸的測試。由於測試時不需要使用到 SAS裝置與主機或伺服器,亦不需等待作㈣統重新啟動,故能 以低成本的裝置達到快速測試SAS背板的目的。此外,即使將來 欲測試的SAS她之匯流排解規格提高,僅需置換具有對應頻 率的物理層積體電路亦可對應。 雖然本發_前述之較佳實施_露如上,然其並非用以限 定本發明,任何熟習相像技藝者,在不脫離本發明之精神和範圍 内’當可作些許之更域獅,因此本發明之翻賴範圍須視 本說明書所附之申請專利範圍所界定者為準。 、 【圖式簡單說明】 第】圖所示為習知之SAS背板的測試裝置之結構示意圖; _第2 _示為根據本發明之SAS f板_試裝置之電路方塊 第3圖所福根據本發明之終端模組之電路方塊示意圖; 圖;^圖所示為根據本發明之SAS背板測試方法之流程示意 =所_據她之SAS _試方法之步驟獅 之流程不意圖。 【主要元件符號說明】 20 伺服端 14 201101024^ By the above-mentioned series of transmission processes, the simulation replaces the access of the MS device 26 with the terminal module %, and the _戦sas connection 埠μ of the ton is enabled, and can be accessed frequently. Therefore, finally, in step sl7, the physical layer integrated circuit % compares the SAS backplane remake signal with the letter ship sent by itself, and records the comparison result. By addressing 'each terminal' 34, the transmission of each SAS connection signal can be performed in sequence. The control module % checks whether all the terminal pull groups 34 have been tested in the step, and can issue a return command in step si2, and the long terminal modules 34 transmit the comparison result. With the indicator light %, the test result of the SAS backplane can be indicated even if the comparison result is not returned. 13 201101024 According to the test device of the SAS backplane of the present invention, the terminal device can be used to simulate the SAS device, and the terminal module can generate the test signal by itself and generate the comparison result, and perform the test of data transmission with the SAS f board. Since the test does not need to use the SAS device and the host or the server, and does not need to wait for (4) to restart, it can achieve the purpose of quickly testing the SAS backplane with a low-cost device. In addition, even if the SAS to be tested in the future is improved in the size of the bus, the physical layer integrated circuit having the corresponding frequency can be replaced. Although the present invention has been described above, it is not intended to limit the present invention, and any skilled person can make a few more lions without departing from the spirit and scope of the present invention. The scope of the invention must be determined by the scope of the patent application attached to this specification. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic structural view of a conventional SAS backplane test apparatus; _2_ is shown in FIG. 3 of the circuit block of the SAS f-board according to the present invention. The circuit block diagram of the terminal module of the present invention; FIG. 1 is a schematic flow chart of the SAS backplane test method according to the present invention== According to her SAS_test method, the process of the lion is not intended. [Main component symbol description] 20 Servo terminal 14 201101024

22 SAS背板 24 SAS連接埠 24, SAS連接埠 26 SAS裝置 32 控制模組 34 終端模組 34, 終端模組 342 物理層積體電路 342, 物理層積體電路 344 控制元件 344, 控制元件 346 連接介面 36 指示燈 36, 指不燈 38 回送模組 1522 SAS backplane 24 SAS port 24, SAS port 26 SAS device 32 control module 34 terminal module 34, terminal module 342 physical layer circuit 342, physical layer circuit 344 control element 344, control element 346 Connection interface 36 indicator light 36, refers to no light 38 loopback module 15

Claims (1)

201101024 七、申請專利範圍: 1. 種序列式小型電腦系統介面(Serial Attached Small Computer System Interface ’ SAS)背板的測試裝置,適用於測試一 SAS 月板’該者板具有複數個SAS連接埠,該測試裝置包括·· 一控制模組,用以發送一控制命令; 一終端模組,包括: 一物理層積體電路’電性連接於該些SAS連接埠其中之 一;以及 一控制元件,係承接該控制命令並令該物理層積體電路 發送一測试彳§號予該SAS背板,該測試信號係為一模擬 SAS裝置之訊號;以及 一信號回送模組,電性連結於該SAS背板,並把來自於該 SAS背板的該測試信號回送給該sAS背板,該SAS背板於接 收該回送的測試信號後,並把該回送的測試信號傳送予該物理 層積體電路,該物理層積體電路把該回送的測試信號與該發送 的測試信號進行比對後,記錄一比對結果。 2. 如請求項1所述之SAS背板的測試裝置’其中該比對結果係以 一指示燈表示。 3. 如請求項1所述之SAS背板的測試裝置’其中該控制命令包含 一頻率設定命令,該控制元件接收到該頻率設定命令時,令該 物理層積體電路依據該頻率設定命令設定該測試信號的頻率。 4. 如請求項1所述之SAS背板的測試裝置’其中該測試裴置包含 16 201101024 另一該終端模組,另一兮故 ‘ 通終埏模組的該控制元件係承接該終端 杈、、且的該控制兀件的該控制命令,該控制命令使得另一該終端 模組之該物理層積體魏發送、以及接收該測試信號並由另一 該終端模組之該物理層積體電路記錄該比對結果。 5·如叫求項4所述之SAS背板的測試裝置,其中該控制命令包含 一定址命令,該定址命令係令該些控制元件依據該定址命令設 定該些控制元件之位址。 ❹ 6.如請求項5所述之SAS背板的測試裝置’其中該控制命令包含 一回傳命令,該回傳命令係令該些控制元件把該些比對結果傳 .送給該控制模組。 17201101024 VII. Patent application scope: 1. The serial attached small computer system interface (SAS) backplane test device is suitable for testing a SAS moon board. The board has a plurality of SAS ports. The test device includes: a control module for transmitting a control command; a terminal module comprising: a physical layer integrated circuit electrically connected to one of the SAS ports; and a control component, Receiving the control command and causing the physical layer integrated circuit to send a test 彳§ to the SAS backplane, the test signal is a signal of an analog SAS device; and a signal returning module electrically connected to the The SAS backplane sends the test signal from the SAS backplane to the sAS backplane. After receiving the loopback test signal, the SAS backplane transmits the loopback test signal to the physical layer. The circuit, the physical layer integrated circuit compares the returned test signal with the transmitted test signal, and records a comparison result. 2. The test apparatus of the SAS backplane as described in claim 1 wherein the comparison result is indicated by an indicator light. 3. The test device of the SAS backplane according to claim 1, wherein the control command includes a frequency setting command, and when the control component receives the frequency setting command, the physical layer circuit is configured according to the frequency setting command. The frequency of the test signal. 4. The test device of the SAS backplane according to claim 1, wherein the test device comprises 16 201101024 another terminal module, and the other control component of the terminal module is to receive the terminal. And the control command of the control component, the control command causes the physical layer of another terminal module to send and receive the test signal and the physical layer of another terminal module The body circuit records the alignment result. 5. The test apparatus of the SAS backplane of claim 4, wherein the control command includes an address command, the addressing command causing the control elements to set addresses of the control elements in accordance with the addressing command. 6. The test apparatus of the SAS backplane of claim 5, wherein the control command includes a return command, the return command causes the control elements to transmit the comparison results to the control module group. 17
TW98120744A 2009-06-19 2009-06-19 SAS back plate testing device TW201101024A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI475381B (en) * 2011-04-22 2015-03-01 Hon Hai Prec Ind Co Ltd Sas interface output signal detection device
US10041999B2 (en) 2016-12-13 2018-08-07 Via Technologies, Inc. Interface chip and test method therefor
US10209302B2 (en) 2015-04-22 2019-02-19 Via Technologies, Inc. Interface chip and built-in self-test method therefor
US10896107B1 (en) * 2020-06-15 2021-01-19 Inventec (Pudong) Technology Corporation Backplane testing system and method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI475381B (en) * 2011-04-22 2015-03-01 Hon Hai Prec Ind Co Ltd Sas interface output signal detection device
US10209302B2 (en) 2015-04-22 2019-02-19 Via Technologies, Inc. Interface chip and built-in self-test method therefor
US10041999B2 (en) 2016-12-13 2018-08-07 Via Technologies, Inc. Interface chip and test method therefor
TWI633777B (en) * 2016-12-13 2018-08-21 威盛電子股份有限公司 Interface chip and test method therefor
US10896107B1 (en) * 2020-06-15 2021-01-19 Inventec (Pudong) Technology Corporation Backplane testing system and method thereof

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