201044787 六、發明說明： 【發明所屬之技術領域】 本發明係關於-種升壓位準移位電路（1〇w七姆^ shift Circuit)及其控制方法，尤指—種應用在升壓電路 (bootstrap)中的升壓位準移位電路及其控制方法。 【先前技術】 • 許多電壓轉換器和音頻放大器使用橋式電路(bridge circuit)將能量由電壓源傳送至負載側。橋式電路通常包含 〇 ㊉個連接於電壓源與接地參考端之間的功率開關元件。連 接於電壓源的功率開關元件通常稱為上橋（high side)開關 元件，而連接於接地地端的功率開關元件通常稱為下橋 —-side)開關元件。上橋開關元件和下橋開關元件的共接 點連接至-輸出端以供應電流至負載側。上橋開關元件和 T制關元件交替地導通，使得輸出電愿在電壓源或接地 v 參考端擺動。上橋開關元件和下橋開關元件通常以電晶體 Q 實施。為了使上橋開關元件完全地導通，閘極驅動電磨必 須超過汲極驅動電壓，其在上橋開關元件導通時係連接至 電應源。閘極驅動電遷由位於積體電路（integrated circuh) 内部的核心電路（core circuit)經由驅動電路所產生。核心 電路的工作電壓，基於功率消耗的考量，一般都低於供電 給功率開關元件的電壓源。在現今VLSI技術中，核心電路 的工作電壓大約可低至〇9¥至12V，而系統中的電壓源一 般是5V或12V。因此，有必要在驅動電路中使用一升壓位 準移位電路（l〇w_to_hig}l level shift circuit)，將核心電路的 201044787 輸出信號由低電壓位準轉換至高電壓位準β 在積體電路中，工作於5V/12V的元件傳統上稱為厚氧化 層兀件，而工作在1.2V的元件傳統上稱為薄氧化層元件。 厚氧化層元件和薄氧化層元件的差別在於氧化層的厚度。 厚氧化層元件在製造過程中通常需要額外的光罩，其增加 _ 了製程的難度、製造的時間和成本。為了在功率開關元件 的驅動電路中也能使用薄氧化層元件，有些電路採用一升 Θ 壓電路（bootstrap)來驅動功率開關元件的閘極。 現參照圖1，該圖描繪一橋式電路11〇及一驅動電路1〇〇。 該驅動電路100包含一位準移位電路1〇1、一緩衝級電路 102、一充泵二極體1〇3和一靴帶式電容1〇4<>該橋式電路ιι〇 包含串聯於一高電壓源PVDD及一接地參考端之間之一上 橋開關元件113及一下橋開關元件丨丨扣該上橋開關元件丨！ 3 及該下橋開關元件114通常以電晶體實施，有時該下橋開關 ' 元件U4可以功率二極體替代。該上橋開關元件113和該下 〇 橋開關兀件U4的共接點連接至一輸出端νουτ以供應負載 側電力。當來自於核心電路（未繪出）的信號CRL為一邏 輯〇信號（接地電位）時，該驅動電路100會藉由控制功率開 關元件之相對應閘極，使得上橋開關元件i i 3截止和下橋開 關元件114導通。該動作會強制使輸出端ν〇υτ接地。因此， 一偏壓源VB會經由該充泵二極體1〇3對該靴帶式電容1〇4 充電。當信號CRL為一邏輯1信號（LVDD)時，該驅動電路 100會使传上橋開關元件113導通和下橋開關元件上丨4截 止’進而提尚該輸出端V0UT至一高電壓源pvdd。因為靴 201044787 帶式電容104之下板係連接至該輸出端ν〇υτ，且該靴帶式 電容104已經被充電至Vb (假設二極體1〇3為一理想二極 體），因此該靴帶式電容104之上板電壓會等於Vb+pvdd。 綜合上述’該靴帶式電容1〇4之上板電壓，即一浮動電塵 VB〇〇T，在上橋開關元件113截止時的穩態值為Vb，而在上 橋開關元件113導通時之穩態值為Vb+pvdd。當信號CRL . 為邏輯0信號時，該位準移位電路1〇1會將信號CRL的電壓 ❹ 位準轉換為仍維持於接地位準之信號(：11]9[，其代表足以關 閉上橋開關元件113的邏輯〇信號。當信號CRL為邏輯丨信號 時，該位準移位電路1〇1會將信號CRL的電壓位準從LVDD 轉換為電壓位準為VB+PVDD之信號CRH，其代表可導通上 橋開關元件113的邏輯1信號。信號Crh在經過至少一個反 相器所組成的驅動級電路102傳遞後會輸出UG信號，藉以 驅動上橋開關元件113。 • 請參考圖2 ’ 一習知位準移位電路101包含一由次高電壓 ◎ 源LVDD供電的反相器201，一串聯於該高電壓源pVDD的 電阻202及一控制電晶體203。當信號CRX為邏輯〇信號時， 該控制電晶體203導通而使得輸出信號crh連接至接地參 考端。當信號CRL為邏輯1信號時，該電晶體203截止而使 得輸出信號CRH經由該電阻202連接到該高電壓源 PVDD。該習知電路的缺點之一是高壓應用中的高切換損 失’因為該控制電晶體203的波極會連接至pvdd，其必須 為厚氧化層元件。厚氧化層元件具有較大的寄生電容，因 此會延遲驅動信號UG的上升時間而造成較大的切換損 201044787 失。另一方面，當該控制電晶體203導通時，在該電阻2〇2 上會有直流導通損失，所以該位準移位電路並不適合高壓 及高速的應用》 參考圖3，其繪示另一習知位準移位電路1〇1之示意圖。 該電路由一電晶體306及一電晶體3〇7形成一拴鎖（^化^架 構。該拴鎖架構係由一電晶體301及302所觸發，其閘極端 個別地耦接至信號CRL及其反相信號。一電晶體3〇4及一電 晶體305用來個別地限制該電晶體3〇1及該電晶體3〇2之汲 〇 極電壓。該習知位準移位電路在穩態時並不會有任一電晶 體導通，因此不會有直流導通損失。然而在信號CRL由低 位準切換為尚位準時，該電晶體3〇1、3〇4和3〇6會同時地導 通而造成切換損失和傳遞延遲。為了克服上述缺點，在美 國專利號US6,476,672内藉由***放電（discharge)和預充電 (precharge)信號在原有的設定（set)與重設（reset)信號之間 - 來加以改善。然而，該電路需要一個可執行信息交換程序 〇 (handshaking Procedure)的有限狀態機（finite state machine) 藉以產生所需的相位，因此將無可避免地增加驅動電路的 成本及複雜度。 【發明内容】 本發明之目的係提供一種升壓位準移位電路，其經配置 於一升壓電路中，藉以驅動橋式電路中的功率開關元件。 該升壓電路包含一靴帶式電容（bootstrap capacitor)和一充 泵二極體（charge pump diode)，以提供一浮動電壓。該橋 式電路包含一上橋開關元件和一下橋開關元件，而該浮動 7 201044787 電麗係用來驅動該上橋開關元件的間極。如此—來，該功 率開關元件的驅動電路可使用薄氧化層元件以降低製造時 間及成本°該位準移位電路係用來轉換低電壓位準的輸入 k號至該驅動電路中高電壓位準的驅動信號，藉以控制該 上橋開關元件的開關狀態。 本發明之另一目的係提供一種升壓位準移位方法，其可 , 使用於升壓電路中。該升壓電路係用來產生一浮動電壓， 藉以驅動功率開關元件。該位準移位方法係用來將低電壓 位準的輸入信號轉換至高電壓位準的輸出信號，藉以控制 功率開關元件的開關狀態。 本發明之一實施例之升壓位準移位電路包含一轉換電 路、一提昇電路、一下拉電路及一邏輯電路。該轉換電路 係接收一輸入信號而產生一控制信號，其中該輸入信號的 邏輯位準係相對於一第一電壓。該提昇電路係依據該浮動 • 電壓在一上橋開關元件導通時的上昇量，藉以提高該控制 〇 仏號之電壓至一第二電壓位準。該下拉電路係依據該浮動 電壓在一下橋開關元件導通時的下降量，藉以降低該控制 信號之電壓至接地電位。該邏輯電路係接收該控制信號而 產生一輸出信號以控制該上橋開關元件，其中該輸出作辦· 的邏輯位準係相對於一第二電壓位準。該第二電壓位準大 於該第一電壓位準。 本發明之一實施例之升壓位準移位方法，包含下列步 驟：接收一輸入信號，其中該輸入信號之邏輯位準係相對 於一第一電壓；根據該輸入信號，產生一控制信號；藉由 201044787 該控制信號控制一上橋開關元件的開關狀態；依據該浮動 電壓在該上橋開關元件導通時的上升量，提高該控制信號 之電壓位準至一第二電壓；以及依據該浮動電壓在下橋開 關元件導通時的下降量，降低該控制信號之電壓至一接地 電位。 【實施方式】 圖4的方塊圖是圖1中所示的位準移位電路1〇1之一實施 例。參考圖4 ’該位準移位電路4〇〇包含一轉換電路4(n、一 0 提昇電路402、一下拉電路403和一邏輯電路404。該轉換電 路401係用以接收來自於核心電路（未繪出）的信號CRl， 該核心電路由次高電壓源LVDD所供電。該提昇電路4〇2係 依據該浮動電壓VB00T在上橋開關元件丨13導通時的上升 里，而提尚該轉換電路401的輸出節點TR之電壓，這使得 輸出節點TR的電壓從低位準切換至高位準時能持續地跟 • 隨浮動電壓Vboot的變化。該下拉電路403係依據該浮動電 〇 壓Vboot在下橋開關元件114導通時的下降量，而減少該轉 換電路401的輸出節點TR之電壓，這使得輸出節點tr的電 壓從高位準切換至低位準時能持續地跟隨浮動電壓Vb〇〇t 的變化。該邏輯電路404係接收該輸出節點TR之信號，並 輸出上橋開關元件113之閘極驅動信號UG。 圖5是圖4中所示的位準移位電路4〇〇之更詳細電路圖。上 述轉換電路401包含一反相器501、一第一電晶體5〇2、一第 二電晶體505、一第一組件5〇3、一第二組件5〇4以及一第三 組件514，其互連如圖所示。該第一組件5〇3具有一第一端 201044787 及一第二端。在本實施例中，該第一組件503可以使用一二 極體5丨3實現。當使用該二極體513時，該二極體513之陽極 連接至該第一電晶體5〇2之汲極，而陰極連接至該轉換電路 401之輸出節點TR。在其他實施例中，該組件503可以使用 二極體連結（diode-connected)之電晶體（未繪出）實現。圖201044787 VI. Description of the Invention: [Technical Field] The present invention relates to a boost level shift circuit and a control method thereof, and particularly to a boost circuit The boost level shift circuit in (bootstrap) and its control method. [Prior Art] • Many voltage converters and audio amplifiers use a bridge circuit to transfer energy from a voltage source to the load side. The bridge circuit typically contains 〇 ten power switching elements connected between the voltage source and the ground reference. A power switching element connected to a voltage source is commonly referred to as a high side switching element, and a power switching element connected to a grounded ground is commonly referred to as a lower side switching element. A common junction of the upper bridge switching element and the lower bridge switching element is connected to the -output terminal to supply current to the load side. The upper bridge switching element and the T-switching element are alternately turned on so that the output power swings at the voltage source or ground v reference. The upper bridge switching element and the lower bridge switching element are typically implemented with a transistor Q. In order for the upper bridge switching element to be fully turned on, the gate drive electric grinder must exceed the drain drive voltage, which is connected to the electrical source when the upper bridge switch element is turned on. The gate drive relocation is generated by a core circuit located inside the integrated circuit (circular) via a drive circuit. The operating voltage of the core circuit, based on power consumption considerations, is generally lower than the voltage source that supplies power to the switching components. In today's VLSI technology, the operating voltage of the core circuit can be as low as ¥9¥ to 12V, and the voltage source in the system is typically 5V or 12V. Therefore, it is necessary to use a boost level shift circuit (l〇w_to_hig}l level shift circuit) in the driving circuit to convert the 201044787 output signal of the core circuit from a low voltage level to a high voltage level β in an integrated circuit. Among the components operating at 5V/12V are traditionally referred to as thick oxide layers, while components operating at 1.2V are traditionally referred to as thin oxide layers. The difference between the thick oxide layer element and the thin oxide layer element is the thickness of the oxide layer. Thick oxide elements typically require additional masks during the manufacturing process, which increases the difficulty of the process, the time and cost of manufacturing. In order to use thin oxide layer elements in the driving circuit of the power switching element, some circuits use a one-liter bootstrap to drive the gate of the power switching element. Referring now to Figure 1, there is depicted a bridge circuit 11A and a drive circuit 1A. The driving circuit 100 includes a quasi-displacement circuit 1〇1, a buffer stage circuit 102, a charge pump diode 1〇3, and a bootstrap capacitor 1〇4<> the bridge circuit ιι〇 includes a series connection The upper bridge switching element 113 and the lower bridge switching element are coupled to the upper bridge switching element 之一 between a high voltage source PVDD and a ground reference terminal! 3 and the lower bridge switching element 114 is typically implemented in a transistor, and sometimes the lower bridge switch 'component U4 can be replaced by a power diode. The common junction of the upper bridge switching element 113 and the lower bridge switch element U4 is connected to an output terminal νουτ to supply load side power. When the signal CRL from the core circuit (not shown) is a logic chirp signal (ground potential), the driving circuit 100 turns off the upper bridge switching element ii 3 by controlling the corresponding gate of the power switching element. The lower bridge switching element 114 is turned on. This action forces the output ν〇υτ to be grounded. Therefore, a bias source VB charges the shoe-type capacitor 1〇4 via the charge pump diode 1〇3. When the signal CRL is a logic 1 signal (LVDD), the driving circuit 100 turns on the pass-up switching element 113 and the lower-side switching element 丨4 to turn off the output terminal VOUT to a high voltage source pvdd. Because the boot 201044787 band capacitor 104 is connected to the output terminal ν〇υτ, and the bootband capacitor 104 has been charged to Vb (assuming the diode 1〇3 is an ideal diode), The upper plate voltage of the bootstrap capacitor 104 will be equal to Vb+pvdd. Combining the above-mentioned board-type capacitor 1〇4 upper board voltage, that is, a floating electric dust VB〇〇T, the steady-state value when the upper bridge switching element 113 is turned off is Vb, and when the upper bridge switching element 113 is turned on. The steady state value is Vb+pvdd. When the signal CRL. is a logic 0 signal, the level shifting circuit 1〇1 converts the voltage ❹ level of the signal CRL into a signal (:11]9[, which is sufficient to turn off the signal, which is still maintained at the ground level. The logic 〇 signal of the bridge switching element 113. When the signal CRL is a logic 丨 signal, the level shifting circuit 1〇1 converts the voltage level of the signal CRL from LVDD to a signal CRH whose voltage level is VB+PVDD, It represents a logic 1 signal that can turn on the upper bridge switching element 113. The signal Crh outputs a UG signal after being transmitted through the driver stage circuit 102 composed of at least one inverter, thereby driving the upper bridge switching element 113. • Please refer to FIG. A conventional level shifting circuit 101 includes an inverter 201 powered by a second highest voltage source LVDD, a resistor 202 connected in series with the high voltage source pVDD, and a control transistor 203. When the signal CRX is a logic 〇 When the signal is received, the control transistor 203 is turned on to connect the output signal crh to the ground reference terminal. When the signal CRL is a logic 1 signal, the transistor 203 is turned off and the output signal CRH is connected to the high voltage source PVDD via the resistor 202. The learned electricity One of the disadvantages of the circuit is the high switching loss in high voltage applications 'because the wave of the control transistor 203 is connected to pvdd, which must be a thick oxide layer component. The thick oxide layer component has a large parasitic capacitance and therefore is delayed The rise time of the drive signal UG causes a large switching loss of 201044787. On the other hand, when the control transistor 203 is turned on, there is a DC conduction loss on the resistor 2〇2, so the level shift circuit is Not suitable for high-voltage and high-speed applications. Referring to Figure 3, there is shown a schematic diagram of another conventional level shifting circuit 101. The circuit is formed by a transistor 306 and a transistor 3〇7. The architecture is triggered by a transistor 301 and 302, the gate terminals of which are individually coupled to the signal CRL and its inverted signal. A transistor 3〇4 and a transistor 305 are used to individually limit The transistor 3〇1 and the drain voltage of the transistor 3〇2. The conventional level shifting circuit does not have any transistor conduction during steady state, so there is no DC conduction loss. When the signal CRL is switched from a low level to a good position The transistors 3〇1, 3〇4, and 3〇6 are simultaneously turned on to cause switching loss and transfer delay. To overcome the above disadvantages, by inserting and discharging in U.S. Patent No. 6,476,672 The (precharge) signal is improved between the original set and the reset signal. However, the circuit requires a finite state machine that can perform a handshaking procedure. In order to generate the required phase, the cost and complexity of the drive circuit will inevitably increase. SUMMARY OF THE INVENTION An object of the present invention is to provide a boost level shift circuit that is configured in a boost circuit to drive a power switching element in a bridge circuit. The boost circuit includes a bootstrap capacitor and a charge pump diode to provide a floating voltage. The bridge circuit includes an upper bridge switching element and a lower bridge switching element, and the floating 7 201044787 is used to drive the interpole of the upper bridge switching element. In this way, the driving circuit of the power switching element can use a thin oxide layer component to reduce manufacturing time and cost. The level shifting circuit is used to convert the input voltage of the low voltage level to the high voltage level in the driving circuit. The driving signal is used to control the switching state of the upper bridge switching element. Another object of the present invention is to provide a boost level shifting method which can be used in a booster circuit. The boost circuit is used to generate a floating voltage to drive the power switching elements. The level shifting method is used to convert a low voltage level input signal to a high voltage level output signal to control the switching state of the power switching element. The boost level shifting circuit of one embodiment of the present invention includes a switching circuit, a boosting circuit, a pull-down circuit, and a logic circuit. The conversion circuit receives an input signal to generate a control signal, wherein the logic level of the input signal is relative to a first voltage. The boosting circuit is configured to increase the voltage of the control 仏 至 to a second voltage level according to the rising amount of the floating voltage when an upper switching element is turned on. The pull-down circuit reduces the voltage of the control signal to the ground potential according to the falling voltage of the floating voltage when the lower bridge switching element is turned on. The logic circuit receives the control signal to generate an output signal to control the upper bridge switching element, wherein the output logic level is relative to a second voltage level. The second voltage level is greater than the first voltage level. The boost level shifting method of an embodiment of the present invention comprises the steps of: receiving an input signal, wherein a logic level of the input signal is relative to a first voltage; and generating a control signal according to the input signal; Controlling the switching state of an upper bridge switching component by the control signal according to 201044787; increasing the voltage level of the control signal to a second voltage according to the rising amount of the floating voltage when the upper bridge switching component is turned on; and according to the floating The amount of voltage drop when the lower bridge switching element is turned on reduces the voltage of the control signal to a ground potential. [Embodiment] The block diagram of Fig. 4 is an embodiment of the level shift circuit 1〇1 shown in Fig. 1. Referring to FIG. 4, the level shift circuit 4 includes a conversion circuit 4 (n, a 0 boost circuit 402, a pull-down circuit 403, and a logic circuit 404. The conversion circuit 401 is for receiving from the core circuit ( The signal CR1 is not drawn, and the core circuit is powered by the second highest voltage source LVDD. The boosting circuit 4〇2 is based on the rise of the floating voltage VB00T when the upper bridge switching element 丨13 is turned on, and the conversion is provided. The voltage of the output node TR of the circuit 401, which causes the voltage of the output node TR to continuously change from the low level to the high level. The pull-down circuit 403 is based on the floating voltage Vboot at the lower bridge switch. The amount of drop when the element 114 is turned on reduces the voltage of the output node TR of the conversion circuit 401, which causes the voltage of the output node tr to continuously follow the change of the floating voltage Vb〇〇t when switching from a high level to a low level. The circuit 404 receives the signal of the output node TR and outputs the gate drive signal UG of the upper bridge switching element 113. Fig. 5 is a more detailed circuit of the level shift circuit 4 shown in Fig. 4. The conversion circuit 401 includes an inverter 501, a first transistor 5〇2, a second transistor 505, a first component 5〇3, a second component 5〇4, and a third component 514. The first component 5〇3 has a first end 201044787 and a second end. In this embodiment, the first component 503 can be implemented using a diode 5丨3. When the diode 513 is used, the anode of the diode 513 is connected to the drain of the first transistor 5〇2, and the cathode is connected to the output node TR of the conversion circuit 401. In other embodiments, Component 503 can be implemented using a diode-connected transistor (not shown).
❹ 5所示的第二組件504可作為一箝位電路（ciamp circu⑴。在 本實施例中，該第二組件5〇4可以使用一電晶體5〇0實現。 當使用該電晶體500時，該電晶體500的閘極連接至該輸出 端V0UT ’源極連接至該轉換電路4〇1之輸出節點tr ,且沒 極連接至該第二電晶體505的的汲極。在其他實施例中，該 第二組件504可以使用一個以上串聯連接的二極體（未繪 出）實現，藉以限制輸出節點TR的電壓擺幅。圖5所示的 第三組件514可作為一箝位電路。在本實施例中，該第三組 件514可以使用一電晶體515實現。當使用該電晶體515時， 其閘極連接至CRL的反相信號，源極連接至接地參考端， 且汲極連接至該第一電晶體502的汲極。在其他實施例中， 該第三組件514可以使用一二極體（未繪出）實現，該二極 體之陰極連接至該第一電晶體502之汲極，而陽極連接至接 地參考端，藉以限制該第一電晶體502的汲極端電壓擺幅。 參照圖5,該轉換電路401中的第一電晶體5〇2的閘極連接 至CRL的反相信號，其源極連接至次高電壓源LVdd，且其 汲極連接至該第一組件503的第一端。該第二電晶體5〇5的 閘極連接至CRL的反相信號，其源極連接至接地參考端， 且其汲極連接至該第二組件504的第二端。 201044787 該位準移位電路400之驅動電路404包含一第一反相器 507及一第二反相器5丨〇。在本實施例中，該第一反相器5〇7 係由一P型電晶體508及電晶體5〇9所組成，而該第二 反相器510係由一 p型電晶體511及一 n型電晶體512所組 成。在其他實施例中’該第一反相器507及該第二反相器51〇 可以使用串聯連接於該浮動電壓Vb〇〇t和該輸出端ν〇υτ2 間的一 Ρ型電晶體及一電阻，或以一電阻及一 Ν型電晶體實 現。The second component 504 shown in FIG. 5 can be used as a clamp circuit (ciamp circu(1). In the present embodiment, the second component 5〇4 can be realized by using a transistor 5〇0. When the transistor 500 is used, The gate of the transistor 500 is connected to the output terminal VOUT 'the source is connected to the output node tr of the conversion circuit 4〇1, and the pole is connected to the drain of the second transistor 505. In other embodiments The second component 504 can be implemented using more than one diode (not shown) connected in series to limit the voltage swing of the output node TR. The third component 514 shown in FIG. 5 can function as a clamp circuit. In this embodiment, the third component 514 can be implemented using a transistor 515. When the transistor 515 is used, its gate is connected to the inverted signal of the CRL, the source is connected to the ground reference terminal, and the drain is connected to The drain of the first transistor 502. In other embodiments, the third component 514 can be implemented using a diode (not shown), and the cathode of the diode is connected to the first transistor 502. Extreme, and the anode is connected to the ground reference to limit The 汲 extreme voltage swing of the first transistor 502. Referring to FIG. 5, the gate of the first transistor 5〇2 in the conversion circuit 401 is connected to the inverted signal of the CRL, and the source thereof is connected to the second highest voltage source LVdd. And its drain is connected to the first end of the first component 503. The gate of the second transistor 5〇5 is connected to the inverted signal of the CRL, the source thereof is connected to the ground reference terminal, and the drain is connected The second end of the second component 504. The driving circuit 404 of the level shifting circuit 400 includes a first inverter 507 and a second inverter 5A. In this embodiment, the first An inverter 5〇7 is composed of a P-type transistor 508 and a transistor 5〇9, and the second inverter 510 is composed of a p-type transistor 511 and an n-type transistor 512. In other embodiments, the first inverter 507 and the second inverter 51 〇 may use a 电-type transistor and a cascode connected in series between the floating voltage Vb 〇〇 t and the output terminal ν 〇υ τ 2 The resistor is either implemented as a resistor and a 电-type transistor.
D 在本實施例中，該位準移位電路101之提昇電路402包含 一第二電晶體506和一電阻516。該第三電晶體506之源極連 接至該浮動電壓Vb〇〇t ’其汲極連接至該電阻516之第一 端，而其閘極則連接至該第一反相器5〇7的輸出端。該電阻 5 16之第二端係連接至該輸出節點711。在其他實施例中， 該提昇電路402包含一第三電晶體5〇6,其汲極連接至該輸 • 出節點TR。在本實施例中，該位準移位電路4〇〇之下拉電 〇 路403包含一第四電晶體52丨和一電阻517 »該第四電晶體 521之源極連接至該輸出端ν〇υτ，其丨及極連接至該電阻η? 之第一端，而其閘極則連接至該第一反相器5〇7的輸出端。 該電阻517之第二端係連接至該輸出節點丁汉。在其他實施 例中，該下拉電路4〇3包含一第四電晶體521，其汲極連接 至該輸出節點TR。 當信號CRL為邏輯〇時，CRL的反相信號會導通該第二電 日日體505。當該第二電晶體5〇5導通時，該輸出節點會連 接到接地參考端。接著，TR的信號在經過該第一反相器507 11 201044787 及該第二反相器510後會輸出信號CRH。該信號CRH的電壓 位準等於輸出端V0UT之電壓位準（此時為接地），因此該 上橋開關元件113為截止的狀態。當信號CRL的電壓從低位 準切換至高位準時，CRL的反相信號首先會導通第一電晶 體502，從而提高TR上的電壓至LVDD，而下拉電路403中 的電阻517則用來限制電晶體502的貫通電流（shoot-through current) 。 接著， TR的信號 在經過 該第一 反相器 507 後導通該第三電晶體506，且在經過該第二反相器510後輸 出該信號CRH。該信號CRH的電壓位準會上昇至浮動電壓 VB00T之電壓位準，這使得上橋開關元件113進入導通狀 態。隨著上橋開關元件113的導通，輸出端VOUT的電壓開始 上昇，VB00T亦隨之上昇。該輸出節點TR透過第三電晶體 506會持續地跟隨VB00T的變化，這使得該第一反相器507 及第二反相器510可以保持正確的邏輯位準。最後，對應於 信號CRL的邏輯1位準，信號CRH上的電壓會等於 VB+PVDD，這可以使得上橋開關元件113完全地導通。圖5 所示的該第一組件503是用來阻止當第一電晶體502導通且 輸出節點TR上昇至浮動電壓VB00T時，從VB00T流向LVDD 的逆向電流。 當信號CRL的電壓從高位準切換至低位準時，CRL的反 相信號首先會導通第二電晶體505，從而降低TR上的電 壓，而提昇電路402中的電阻516則用來限制電晶體505的貫 通電流。接著信號TR在經過該第一反相器507後導通該第 四電晶體521，且在經過第二反相器5 10後輸出信號CRH。 12 201044787 該信號CRH的電壓位準會從浮動電壓Vb〇〇t下降至輸出端 v0UT之電壓位準，這使得上橋開關元件113進入截止狀態。 接著，下橋開關元件114開始導通，輸出端ν〇υτ被連接至接 地參考端，因此該電壓下降。由於該第四電晶體521為導通 狀態，這使得輸出節點TR的電壓會跟隨輸出端ν〇υτ的電壓 下降量。最終，對應於信號Crl的邏輯〇位準，信號crh上 的電壓會接近接地參考端電壓。此外，為了避免連接於TR 的任一 P型電晶體，例如本實施例中的電晶體5〇8，其閘極 -源極間電壓差過大而損害閘極氧化層；或者為了避免連接 於TR的任一 N型電晶體，例如本實施例中的電晶體5〇9,其 閘極-汲極間電壓差過大而損害閘極氧化層，該第二組件 5 04會置於該第二電晶體5 〇5的没極與tr之間。該第二組件 504在本實施例中係以一p型電晶體5〇〇實現，其互連如圖 所示。另一方面，當TR上的電壓隨著輸出端ν〇υτ的電壓下 降時，由於雜散電容的耦合效應，該第一電晶體5〇2的汲極 〇 端可能會出現負電壓，因此，一連接於該汲極端與該接地 參考端之間的第三組件514,其作為一箝位電路，可防止負 電壓的發生。該第二組件514在本實施例中係以一 ν型電晶 體515實現’其互連如圖所示。 圖6是圖4中所示的位準移位電路4〇〇之另一更詳細電路 圖。在圖6中，提昇電路4〇2包含一 ρ型電晶體6〇()、一電容 器604以及一脈衝信號產生電路6〇1。該ρ型電晶體6〇〇的源 極連接至該浮動電壓VBG()T ’其閘;^連接至該脈衝信號產生 電路601的輸出端\，而其汲極連接至該轉換電路4〇1的輸 13 201044787 出節點TR。在其他實施例中，該P型電晶體600係經由一電 阻串聯連接至輸出節，藉以限制該轉換電路4〇1中的 第二電晶體5G5之貫通電流。該電容請4係連接至輸出節 點TR與V0UT之間。該脈衝信號產生電路6〇1係接收上橋開 關元件113之閘極驅動信號UG或是下橋開關元件114之閘 極驅動佗號並產生一脈衝信號\，其用來推動該p型電晶體 600之閘極。該脈衝信號產生電路6〇1包含一反及閘6〇2及一 含有奇數個反相器之反相器鏈（inverter chain)6〇3。如前所 〇 述，當輸入信號CRL由低位準切換成高位準時，閘極驅動 信號UG會開始上升。該脈衝信號產生電路6〇1係根據^^信 號的上昇邊緣（rising edge)產生該脈衝信號81，使得該？型 電晶體600導通。當該P型電晶體6〇〇導通時，輸出節點tr 的電壓會跟隨浮動電壓乂的町的變化，這使得邏輯電路中的 第一反相器507及第二反相器51〇可以保持正確的邏輯位 準。當該脈衝信號S1結束時，該電容器604則用來保持TR ❹ 上的電壓等於該浮動電壓Vboot。如此一來，TR上的電壓 從低位準切換至高位準時都能持續地跟隨該浮動電壓 Vboot 0 圖7是圖4中所示的位準移位電路4〇〇之另一更詳細電路 圖。在圖7中，該提昇電路402包含了一 p型電晶體7〇1、一 電阻702、一電容器703及一電容器704。該電容器7〇3和該 電阻702之共接點為N!。該p型電晶體7〇1的源極連接至該 浮動電壓VBOOT，其閘極連接至接點Nl，而其汲極連接至該 轉換電路401的輸出郎點TR。在其他實施例中，該p型電晶 14 201044787 體701係經由一電阻串聯連接至輸出節點Tr，藉以限制該 轉換電路401中的第二電晶體5〇5之貫通電流。該電容器7〇3 係連接於該輸出節點TR與一偏壓源VDC之間，該偏壓源VDC 可以為上述次高電壓源LVDD ^該電容器704係連接於該輸 出節點TR與任一電壓源之間，該電壓源在本實施例為一輸 出端電壓V0UT。該電阻7〇2係連接至Vboot^N!之間。如前 所述，當輸入信號CRL由低位準切換成高位準時，該浮動 D 電M VB00T會開始上昇。上昇的vB00T經由該電阻702限制了 該電容器703的充電電流，因此延緩了 Nl的上昇時間。在 延緩的時間内，該P型電晶體7〇1的閘極-源極間產生壓差， 使知該P型電晶體701為導通的狀態，因此TR上的電壓會跟 隨浮動電壓VB00T的變化。當Nl上的電壓到達乂的的後，該 P型電晶體701為截止狀態，而該電容器704則用來保持TR 上的電壓等於浮動電壓VB〇〇T。本實施例中的提昇電路402 亦可配合如圖5所示的第三電晶體5〇6，或者，第三電晶體 〇 506串聯該電阻516而加以實施。此時，該電容器7〇4不一定 要包含在該提昇電路402中。 本發明之技術内容及技術特點揭示如上，然而熟悉本項 技術之人士仍可能基於本發明之教示及揭示而作種種不背 離本發明精神之替換及修飾。因此，本發明之保護範圍應 不限於實施例所揭示者，而應包含各種不背離本發明之替 換及修飾’並為以下之申請專利範圍所涵蓋。 【圖式簡單說明】 圖1顯示應用一習知驅動電路來控制一橋式電路之示意 15 201044787 圖； 圖2顯示一習知升壓位準移位電路； 圖3顯示另一習知升壓位準移位電路； 圖4顯示本發明之升壓位準移位電路之一實施例的方 塊圖， 圖5顯示本發明之升壓位準移位電路之一實施例； 圖6顯示係本發明之升壓位準移位電路之另一實施例；以 及 Ο 圖7顯示本發明之升壓位準移位電路之又一實施例。 【主要元件符號說明】 Ο 100 102 103 113 CRL PVDD Vboot 驅動電路 驅動級電路 充泵二極體 上橋開關元件 輸入電壓 高電壓源 浮動電壓In the present embodiment, the boost circuit 402 of the level shifting circuit 101 includes a second transistor 506 and a resistor 516. The source of the third transistor 506 is connected to the floating voltage Vb〇〇t', the drain of which is connected to the first end of the resistor 516, and the gate thereof is connected to the output of the first inverter 5?7 end. The second end of the resistor 5 16 is coupled to the output node 711. In other embodiments, the boost circuit 402 includes a third transistor 5〇6 with its drain connected to the output node TR. In this embodiment, the pull-down circuit 403 of the level shifting circuit 4 includes a fourth transistor 52A and a resistor 517. The source of the fourth transistor 521 is connected to the output terminal. Υτ, the 丨 and the pole are connected to the first end of the resistor η?, and the gate is connected to the output of the first inverter 5〇7. The second end of the resistor 517 is connected to the output node Dinghan. In other embodiments, the pull-down circuit 4〇3 includes a fourth transistor 521 with its drain connected to the output node TR. When the signal CRL is logic ,, the inverted signal of the CRL turns on the second electric day body 505. When the second transistor 5〇5 is turned on, the output node is connected to the ground reference terminal. Then, the signal of the TR outputs a signal CRH after passing through the first inverter 507 11 201044787 and the second inverter 510. The voltage level of the signal CRH is equal to the voltage level of the output terminal VOUT (in this case, ground), so the upper bridge switching element 113 is turned off. When the voltage of the signal CRL is switched from the low level to the high level, the inverted signal of the CRL first turns on the first transistor 502, thereby increasing the voltage on the TR to LVDD, and the resistor 517 in the pull-down circuit 403 is used to limit the transistor. 502 shoot-through current. Then, the signal of TR turns on the third transistor 506 after passing through the first inverter 507, and outputs the signal CRH after passing through the second inverter 510. The voltage level of the signal CRH rises to the voltage level of the floating voltage VB00T, which causes the upper bridge switching element 113 to enter an on state. As the upper bridge switching element 113 is turned on, the voltage at the output terminal VOUT starts to rise, and VB00T also rises. The output node TR through the third transistor 506 will continuously follow the change of VB00T, which allows the first inverter 507 and the second inverter 510 to maintain the correct logic level. Finally, corresponding to the logic 1 level of the signal CRL, the voltage on the signal CRH will be equal to VB + PVDD, which can cause the upper bridge switching element 113 to be fully turned on. The first component 503 shown in FIG. 5 is for preventing a reverse current flowing from VB00T to LVDD when the first transistor 502 is turned on and the output node TR rises to the floating voltage VB00T. When the voltage of the signal CRL is switched from a high level to a low level, the inverted signal of the CRL first turns on the second transistor 505, thereby lowering the voltage on the TR, and the resistor 516 in the boost circuit 402 is used to limit the transistor 505. Through current. The signal TR then turns on the fourth transistor 521 after passing through the first inverter 507, and outputs a signal CRH after passing through the second inverter 510. 12 201044787 The voltage level of this signal CRH will drop from the floating voltage Vb〇〇t to the voltage level of the output terminal v0UT, which causes the upper bridge switching element 113 to enter the off state. Next, the lower bridge switching element 114 begins to conduct, and the output terminal ν 〇υ τ is connected to the ground reference terminal, so the voltage drops. Since the fourth transistor 521 is in an on state, this causes the voltage of the output node TR to follow the voltage drop of the output terminal ν 〇υ τ. Finally, corresponding to the logic 〇 level of the signal Cr1, the voltage on the signal crh will approach the ground reference voltage. In addition, in order to avoid any P-type transistor connected to the TR, such as the transistor 5〇8 in this embodiment, the gate-source voltage difference is too large to damage the gate oxide layer; or to avoid connection to the TR Any of the N-type transistors, such as the transistor 5〇9 in this embodiment, has a gate-drain voltage difference that is too large to damage the gate oxide layer, and the second component 504 is placed in the second electrode. The crystal 5 〇 5 between the pole and tr. The second component 504 is implemented in the present embodiment as a p-type transistor 5A, the interconnection of which is illustrated. On the other hand, when the voltage on the TR decreases with the voltage of the output terminal ν 〇υ τ, a negative voltage may appear at the drain terminal of the first transistor 5 〇 2 due to the coupling effect of the stray capacitance, therefore, A third component 514 coupled between the drain terminal and the ground reference terminal acts as a clamping circuit to prevent the occurrence of a negative voltage. The second component 514 is implemented in the present embodiment by a ν-type electrical crystal 515 whose interconnection is as shown. Fig. 6 is another more detailed circuit diagram of the level shift circuit 4 shown in Fig. 4. In Fig. 6, the boosting circuit 4〇2 includes a p-type transistor 6〇(), a capacitor 604, and a pulse signal generating circuit 6〇1. The source of the p-type transistor 6A is connected to the floating voltage VBG()T', the gate thereof is connected to the output terminal of the pulse signal generating circuit 601, and the drain thereof is connected to the conversion circuit 4〇1 Lost 13 201044787 out node TR. In other embodiments, the P-type transistor 600 is connected in series to the output section via a resistor to limit the through current of the second transistor 5G5 in the conversion circuit 4〇1. Connect this capacitor to the output node TR and VOUT. The pulse signal generating circuit 6〇1 receives the gate driving signal UG of the upper bridge switching element 113 or the gate driving signal of the lower switching element 114 and generates a pulse signal\, which is used to push the p-type transistor. The gate of 600. The pulse signal generating circuit 6〇1 includes a reverse gate 6〇2 and an inverter chain 6〇3 having an odd number of inverters. As described above, when the input signal CRL is switched from the low level to the high level, the gate drive signal UG starts to rise. The pulse signal generating circuit 6〇1 generates the pulse signal 81 based on the rising edge of the ^^ signal, so that the pulse signal 81 is made? The type transistor 600 is turned on. When the P-type transistor 6 turns on, the voltage of the output node tr follows the change of the floating voltage ,, which makes the first inverter 507 and the second inverter 51 逻辑 in the logic circuit remain correct. The logical level. When the pulse signal S1 ends, the capacitor 604 is used to maintain the voltage on TR 等于 equal to the floating voltage Vboot. In this way, the voltage on the TR can be continuously followed by the floating voltage from the low level to the high level. Vboot 0. Fig. 7 is another more detailed circuit diagram of the level shifting circuit 4 shown in Fig. 4. In Fig. 7, the boosting circuit 402 includes a p-type transistor 〇1, a resistor 702, a capacitor 703, and a capacitor 704. The common junction of the capacitor 7〇3 and the resistor 702 is N!. The source of the p-type transistor 7〇1 is connected to the floating voltage VBOOT, the gate thereof is connected to the junction N1, and the drain thereof is connected to the output point TR of the conversion circuit 401. In other embodiments, the p-type transistor 14 201044787 body 701 is connected in series to the output node Tr via a resistor, thereby limiting the through current of the second transistor 5〇5 in the conversion circuit 401. The capacitor 7〇3 is connected between the output node TR and a bias source VDC, and the bias source VDC can be the second highest voltage source LVDD. The capacitor 704 is connected to the output node TR and any voltage source. In the present embodiment, the voltage source is an output terminal voltage VOUT. The resistor 7〇2 is connected between Vboot^N!. As described above, when the input signal CRL is switched from the low level to the high level, the floating D electric M VB00T will start to rise. The rising vB00T limits the charging current of the capacitor 703 via the resistor 702, thus delaying the rise time of N1. During the delay time, a voltage difference is generated between the gate and the source of the P-type transistor 7〇1, so that the P-type transistor 701 is turned on, so the voltage on the TR will follow the change of the floating voltage VB00T. . When the voltage on N1 reaches 乂, the P-type transistor 701 is turned off, and the capacitor 704 is used to keep the voltage on TR equal to the floating voltage VB 〇〇T. The boosting circuit 402 in this embodiment may also be implemented in conjunction with the third transistor 5〇6 as shown in FIG. 5, or the third transistor 506 may be connected in series with the resistor 516. At this time, the capacitor 7〇4 is not necessarily included in the boosting circuit 402. The technical content and technical features of the present invention are disclosed above, but those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be construed as not limited by the scope of the invention, and the invention is intended to be BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a schematic diagram of a conventional driver circuit for controlling a bridge circuit. 15 201044787; FIG. 2 shows a conventional boost level shift circuit; FIG. 3 shows another conventional boost level shift circuit. 4 is a block diagram showing an embodiment of a boost level shifting circuit of the present invention, FIG. 5 is an embodiment of a boost level shifting circuit of the present invention; and FIG. 6 is a boosting bit of the present invention. Another embodiment of a quasi-shift circuit; and Figure 7 shows yet another embodiment of the boost level shift circuit of the present invention. [Main component symbol description] Ο 100 102 103 113 CRL PVDD Vboot drive circuit Drive stage circuit Charge pump diode Upper bridge switching element Input voltage High voltage source Floating voltage
101 110 104 114 LVDD VB 位準移位電路 橋式電路 靴帶式電容 下橋開關元件 次高電壓源 偏壓源 CRH 輸出信號101 110 104 114 LVDD VB Level Shift Circuit Bridge Circuit Boot Band Capacitor Lower Bridge Switch Element Secondary High Voltage Source Bias Source CRH Output Signal
V OUT UG 輸出端 会橋開關*件驅動信 201 203 反相器 #制電晶體 N型電晶體 202 電阻 301 N型電晶體 303 反相器 16 302 201044787V OUT UG Output Bridge Switch* Driver Letter 201 203 Inverter #晶晶晶晶晶晶 202 电阻 301 N-type transistor 303 Inverter 16 302 201044787
304 - -307 P型電晶體 400 位準移位電路 401 轉換電路 402 提昇電路 403 下拉電路 404 邏輯電路 TR 共接點 500 P型電晶體 501 反相器 502 P型電晶體 503 第一組件 504 第二組件 505 N型電晶體 506 P型電晶體 507 第一反相器 508 P型電晶體 509 N型電晶體 510 第二反相器 511 P型電晶體 512 N型電晶體 513 二極體 514 第三組件 515 N型電晶體 516〜517電阻 521 N型電晶體 600 P型電晶體 601 脈衝信號產生電路 602 反及閘 603 反相器鏈 604 電容器 Si 脈衝信號 701 P型電晶體 702 電阻 703 第一電容器 704 第二電容器 Νι 節點 Vdc 偏壓源 17304 - -307 P-type transistor 400-bit shift circuit 401 conversion circuit 402 boost circuit 403 pull-down circuit 404 logic circuit TR common contact 500 P-type transistor 501 inverter 502 P-type transistor 503 first component 504 Two components 505 N-type transistor 506 P-type transistor 507 First inverter 508 P-type transistor 509 N-type transistor 510 Second inverter 511 P-type transistor 512 N-type transistor 513 Diode 514 Three components 515 N-type transistor 516~517 resistor 521 N-type transistor 600 P-type transistor 601 pulse signal generation circuit 602 reverse gate 603 inverter chain 604 capacitor Si pulse signal 701 P-type transistor 702 resistance 703 first Capacitor 704 second capacitor Νι node Vdc bias source 17