201044052 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種觸控面板 面板之訊號讀出線的設置。 寻別有關於一種觸控 【先前技術】 傳統的觸控面板可分為電容 容式觸控面板是利用摘測手斤 電阻式感應，電 生的電容來判定手指觸碰的^ 與感應電極之間產 互相接觸而短路，利用= f籌之電極 性連接，並、日日體與按壓感測結構電 取拉厥式 讀出線與感測薄膜電晶體連接，以接 取按麗感測訊號，進而判定手指按壓的位置" 請參閱第1圖，並#顯干值1 面示意圖，且呈右㈣傳統的電阻式觸控面板之平 兩條相鄰的筆直資料素區18，次畫素區1S係由 定義，每個次條相鄰的筆直掃描線II所 =1==_感測_，其係 測薄膜電4 ：f而觸控面板中同—行的感 號至積體=係由㈣讀出線14連接，以傳遞感測訊 (筆吉 電阻式觸控面板中，訊號讀出線14為直線型 曰直）的導電線（或稱沒有f曲的導電線），因此顯示薄膜 :體12文到訊號讀出線14的阻擋，只能設置在資料線1〇 、同側無法5又置成左右交錯（zigzag)的配置，使得傳統 201044052 的電阻式觸控面板無法採用點反轉（dot inversion)的驅動方 式，無法達到省電的功效。 因此，業界亟需一種觸控面板，其可以克服上述問題， 達到省電的功效。 【發明内容】 本發明係提供一種觸控面板，具有複數個晝素區，包 括：第一基板，第一導電層設置於第一基板上，第一導電 層係作為閘極及掃描線；第二導電層設置於第一導電層之 〇 上，第二導電層係作為源極和汲極以及資料線，其中資料 線與掃描線交錯形成該些晝素區；第三導電層設置於第二 導電層之上，第三導電層係作為共用電極；晝素電極設置 於第三導電層上，其中晝素電極具有一主要區塊及至少一 與該主要區塊電性絕緣的次要區塊，主要區塊位於各晝素 區中，次要區塊覆蓋第二導電層之一部份與第三導電層之 一部份；以及彎曲的訊號讀出線，其在同一行且相鄰的二 個晝素區中具有不同的彎曲方向，其中由上視方向觀之， Q 彎曲的訊號讀出線係由第一、第二及第三導電層與晝素電 極之次要區塊互相連接形成，且其中第一導電層經由一第 一導通孔與第二導電層電性連接，晝素電極之次要區塊經 由第二導通孔分別與第二導電層及第三導電層電性連接。 此外，本發明又提供一種觸控面板，包括：第一基板， 第一圖案化導電層設置於第一基板上，其中第一圖案化導 電層包含：複數條掃描線延著第一方向排列，複數個串聯 的第一導電電極，以及複數個各自獨立的第二導電電極。 第二圖案化導電.層設置於第一基板上且位於第一圖案 化導電層上方，其中第二圖案化導電層包含：複數條資料 5 201044052 線延著第二方向排列，與該些掃描線交錯而構成複數個晝 素區群級’其中每個晝素區群組至少包含第一晝素區、第 二晝素區、第三晝素區及第四晝素區；至少一第一源/汲極 對設置於每個晝素區中，且每個源極電性連接於每條資料 線；至少一第三導電電極設置於各第一導電電極之上、各 第一導電電極之上及第一量I區甲升丫议於谷第一守电 電極=上的第三導電電極電性連接於各第一導電電極，·至 少一第一導電線設置於第一晝素區及第三晝素區中，且分 別：：連接位於第一晝素區中之第三導電電極及位於各第 上的第三導電電極;以及至少-第二源/没極 ' 5 —晝素區，第二源極電性連接於另一書素區群 組中的第一導電線。 安另旦素e群 第三圖案化導電層設置於第〜基板上且位於 =層上方，其中第三圖案化導電層包含：至少-第： 導電線平行於該虺掃描線苴中一佟 唆覆宴各眘排列，至少一第三導電 ΐΐΐίΓ的一！份，以及至少-第四導電線設置於 區中的第^，域|第二源極的—部份及位於第一晝素 LT，弟二導電電極的一部份。 層上^素2設置於第—基板上，且位於第三圖案化導電 區中，且盥夂Ϊ素電極包含：畫素電極區塊設置於各晝素 雷極覆f目、ί素區中的各第一及極電性連接；第四導電 第二源極上^連接於第—晝素區中的第三導電電極上及 導電電極之丄以及第五導電線設置於第二晝素區中的第二 三導電電極其中該些第一導電電極、第-導電線、第 、第四導電線與第四導電電極構成一彎曲 (ZlgZag)的^虎讀出'線。 Μ 4曲 201044052 懂，明之上述目的、特徵、及優點能更明顯易 -，以下配合所附圖式，作詳細說明如下： 勿 【實施方式】 魂，提供一種觸控面板，其具有彎曲的訊號讀出 力*夺扭认連接的顯示薄膜電晶體可以利用 i · 工配置’使得觸控面板可採用點反轉(dot 则r贿）的方式驅動，進而達到省電的目的。 Ο 〇 面板Γ ’其係顯示依據本發明—實施例之觸控 ! = 3 圖。觸控面板具有多個次晝素區28，其係 每一個次晝素個Γ-的—掃描線40所定義， ®t ^ 、啕主乂 個顯不溥膜電晶體22。第2 素區二ff圍為一個晝素區群、组30，其包含第一晝 觸^面被内二區32、第三畫素區33及第四晝素區34， 呈ini有夕個晝素區群組3G。在第—畫素區31中 八有至夕一感測薄臈電晶體26， 中之多個感測薄膜電日_ % 订的畫素£群組30 出線24、日日肢26係利用彎曲（zigzag)的訊號讀 兩個金音!^此彎曲的訊號讀出線24在同—行且相鄰的 Η左3中具有不同的f曲方向，因此可以避 i動：的顯示薄膜電晶體22，進而可實現點反轉 制各—蚩9。其中，各個顯示薄膜電晶體22是用以控 二：8_的晝素電極(未標示)之電壓開與關。 〇 第一畫素區32中具有至少一按塵减測结構 連接方之另™晝素區群組中的感測薄膜電晶體％ S電另―、晝素區群組之第一晝素區31中的感測 Μ 25 感測薄膜電晶體26接收來自按壓感測結 構25的喊，並與另—訊號讀出線24電性連接。 7 201044052 由上視方向觀之，此彎曲的訊號讀出線24係由第一導 電層（或稱第一圖案化導電層）241、第二導電層（或稱第二圖 案化導電層）242、第三導電層（或稱第三圖案化導電層）243 及晝素電極（未標示）之次要區塊72互相連接而成。第一導 電層241係作為顯示薄膜電晶體22之閘極和感測薄膜電晶 體26之閘極以及掃描線40，且顯示薄膜電晶體22之閘極 連接至所對應的掃描線40，而感測薄膜電晶體26之閘極 連接至所對應的掃描線40。第二導電層24設置於第一導 電層241之上，其係作為顯示薄膜電晶體22之源/汲極和 感測薄膜電晶體26之源/汲極以及資料線20，且顯示薄膜 電晶體22之源/汲極連接至所對應的資料線20，而感測薄 膜電晶體26之源/汲極連接至所對應的資料線20。第三導 電層243係設置於第二導電層24之上，其係作為共用電極 (common electrode)，而晝素電極則設置於第三導電層243 之上，其具有一主要區塊（未顯示）設置於各次晝素區中， 以及一次要區塊72與主要區塊電性絕緣，次要區塊72覆 蓋第二導電層242的一部份與第三導電層243的一部份。 上述第一導電層241係經由第一導通孔49與第二導電層 242電性連接，而畫素電極之次要區塊72則經由第二導通 孔62分別與第二導電層242及第三導電層243電性連接。 接著，請參閱第3A至3G圖，其係顯示依據本發明之 一實施例，形成觸控面板之晝素區群組30的各製程平面示 意圖，其中畫素區群組30包含第一晝素區31、第二晝素 區32、第三晝素區33及第四晝素區34。請參閱第3A圖， 首先提供第一基板（未顯示），其例如為透明基板(例如：玻 璃、石英《其它的材料、或上述之組合。）、非透明基板（例 201044052201044052 VI. Description of the Invention: [Technical Field] The present invention relates to the setting of a signal readout line of a touch panel panel. Finding a touch is a kind of touch [Previous technology] The traditional touch panel can be divided into a capacitive capacitive touch panel, which uses the resistance of the hand-measured sensor, and the capacitance of the electric power to determine the touch of the finger and the sensing electrode. The inter-products are short-circuited by mutual contact, and the electrode connection is made by using f, and the Japanese body and the pressing sensing structure are electrically connected to the pull-type readout line and the sensing film transistor to receive the sensible signal. , and then determine the position of the finger press " Please refer to Figure 1, and #显干值1 face diagram, and the right (four) traditional resistive touch panel flat two adjacent straight pixel area 18, the second painting The 1S system of the prime zone is defined by the vertical scanning line II adjacent to each secondary strip=1==_Sensing_, which measures the thin film 4:f and the same-line sensed to the integrated body in the touch panel = is connected by (4) the readout line 14 to transmit the conductive line (or the conductive line without the f-curve) of the sensing signal (in the pen-sensitive resistive touch panel, the signal readout line 14 is linear straight). Therefore, the display film: the block 12 to the signal readout line 14 can only be set on the data line 1〇, the same side without The method 5 is also configured in a zigzag configuration, so that the conventional 201044052 resistive touch panel cannot be driven by dot inversion, and the power saving effect cannot be achieved. Therefore, there is a need in the industry for a touch panel that can overcome the above problems and achieve power saving effects. The present invention provides a touch panel having a plurality of halogen regions, including: a first substrate, the first conductive layer is disposed on the first substrate, and the first conductive layer is used as a gate and a scan line; The second conductive layer is disposed on the top of the first conductive layer, and the second conductive layer is used as the source and the drain and the data line, wherein the data line and the scan line are alternately formed to form the halogen regions; the third conductive layer is disposed in the second Above the conductive layer, the third conductive layer is used as a common electrode; the halogen electrode is disposed on the third conductive layer, wherein the halogen electrode has a main block and at least one secondary block electrically insulated from the main block The main block is located in each of the halogen regions, the secondary block covers one of the second conductive layer and one of the third conductive layers; and the curved signal readout line is in the same row and adjacent The two halogen regions have different bending directions, wherein the Q-bending signal readout line is interconnected by the first, second and third conductive layers and the secondary blocks of the halogen electrodes. Formed, and wherein the first conductive layer is via A first via hole is electrically connected to the second conductive layer, and a secondary block of the halogen electrode is electrically connected to the second conductive layer and the third conductive layer via the second via hole. In addition, the present invention further provides a touch panel, comprising: a first substrate, the first patterned conductive layer is disposed on the first substrate, wherein the first patterned conductive layer comprises: a plurality of scan lines are arranged along the first direction, A plurality of first conductive electrodes connected in series, and a plurality of independent second conductive electrodes. The second patterned conductive layer is disposed on the first substrate and above the first patterned conductive layer, wherein the second patterned conductive layer comprises: a plurality of materials 5 201044052 lines are arranged in a second direction, and the scan lines Interlaced to form a plurality of pixel regions, wherein each of the pixel regions includes at least a first halogen region, a second halogen region, a third halogen region, and a fourth halogen region; at least one first source And a drain pair is disposed in each of the pixel regions, and each source is electrically connected to each of the data lines; at least one third conductive electrode is disposed on each of the first conductive electrodes and above each of the first conductive electrodes And the third conductive electrode of the first quantity I zone is electrically connected to each of the first conductive electrodes, and the at least one first conductive wire is disposed in the first halogen region and the first In the triterpenic region, and respectively: connecting a third conductive electrode located in the first halogen region and a third conductive electrode located on each of the first; and at least a second source/dipole '5-alkaline region, The second source is electrically connected to the first conductive line in another group of pixel regions. The third patterned conductive layer is disposed on the first substrate and above the = layer, wherein the third patterned conductive layer comprises: at least - the: conductive line is parallel to the scan line of the scan line The banquets are carefully arranged, at least one of the third conductive ΐΐΐ Γ Γ! And a portion of the at least-fourth conductive line disposed in the region, the second source of the second source, and a portion of the first germanium LT, the second conductive electrode. The layer 2 is disposed on the first substrate, and is located in the third patterned conductive region, and the pixel electrode comprises: the pixel electrode block is disposed in each of the pixel electrodes, Each of the first and second electrical connections; the fourth conductive second source is connected to the third conductive electrode in the first halogen region and the conductive electrode and the fifth conductive line are disposed in the second halogen region The second three conductive electrodes, wherein the first conductive electrodes, the first conductive lines, the fourth conductive lines and the fourth conductive electrodes form a curved (ZlgZag). Μ 4 song 201044052 Understand that the above purposes, features, and advantages can be more obvious - the following is a detailed description of the following drawings: Do not [Embodiment] Soul, provide a touch panel with a curved signal The readout force* can be used to save power by using the i-work configuration to enable the touch panel to be driven by dot inversion (dot). Ο Γ Panel Γ ' shows a touch! = 3 figure in accordance with the present invention. The touch panel has a plurality of sub-tenoxine regions 28, which are defined by each of the sub-prime---scan lines 40, and ® t ^ , 啕 main 显 溥 溥 电 电 22 22 22 22 22 22 22 22. The second element area ff is a morpheous area group, group 30, which includes the first 昼 touch surface, the inner two area 32, the third pixel area 33, and the fourth 昼 区 area 34, Yusu District Group 3G. In the first pixel area 31, the sensation of the thin film transistor 26, the plurality of sensing thin films, the number of pixels, the group of pixels 30, the line 24, and the day and the limb 26 The zigzag signal reads two golden tones! ^ The curved signal readout line 24 has a different f-curve direction in the same row and adjacent Η left 3, so it can avoid the display: The crystal 22, in turn, can realize the dot inversion system - 蚩9. The display thin film transistor 22 is used to control the voltage on and off of the binary electrode (not labeled) of the second: 8_.感In the first pixel region 32, the sensing thin film transistor in the group of the other TM regions having at least one dust-reduction structure connection side, and the first pixel region in the group of the halogen regions Sensing Μ 25 in 31 The sensing film transistor 26 receives a shout from the pressing sensing structure 25 and is electrically coupled to the other signal readout line 24. 7 201044052 The curved signal readout line 24 is formed by a first conductive layer (or first patterned conductive layer) 241 and a second conductive layer (or second patterned conductive layer) 242. The third conductive layer (or the third patterned conductive layer) 243 and the secondary blocks 72 of the halogen electrodes (not labeled) are connected to each other. The first conductive layer 241 functions as a gate of the display film transistor 22 and a gate of the sensing film transistor 26 and the scan line 40, and the gate of the display film transistor 22 is connected to the corresponding scan line 40, and the sense The gate of the thin film transistor 26 is connected to the corresponding scan line 40. The second conductive layer 24 is disposed on the first conductive layer 241 as a source/drain of the thin film transistor 22 and a source/drain of the sensing thin film transistor 26 and the data line 20, and displays the thin film transistor The source/drain of 22 is connected to the corresponding data line 20, and the source/drain of the sensing thin film transistor 26 is connected to the corresponding data line 20. The third conductive layer 243 is disposed on the second conductive layer 24 as a common electrode, and the halogen electrode is disposed on the third conductive layer 243, and has a main block (not shown). The primary block 72 is electrically insulated from the primary block, and the secondary block 72 covers a portion of the second conductive layer 242 and a portion of the third conductive layer 243. The first conductive layer 241 is electrically connected to the second conductive layer 242 via the first via 49, and the secondary block 72 of the pixel electrode is respectively connected to the second conductive layer 242 and the third via the second via 62. The conductive layer 243 is electrically connected. Next, please refer to FIGS. 3A to 3G, which are schematic diagrams showing process planes of the pixel region group 30 forming the touch panel according to an embodiment of the present invention, wherein the pixel region group 30 includes the first pixel. The area 31, the second halogen region 32, the third halogen region 33, and the fourth halogen region 34. Referring to FIG. 3A, a first substrate (not shown) is provided, which is, for example, a transparent substrate (for example, glass, quartz, "other materials, or a combination thereof"), and a non-transparent substrate (for example, 201044052).
如：晶圓、陶瓷、金屬板、不透光之玻璃、不透光之石英、 不透光之聚合物板、其它的材料、或上述之組合。）或軟性 基板(例如：聚丙醯酸酯類、聚碳酸酯、聚苯乙烯、聚醯類、 聚酉旨類、其它的材料、或上述之組合。），在第一基板上形 成第一圖案化導電層310。第一圖案化導電層310包含複 數條掃描線40沿著第一方向X排列，複數個串聯的第一 導電電極241，以及複數個各自獨立的第二導電電極46。 另外，第一圖案化導電層310還作為顯示薄膜電晶體22之 閘極421，以及感測薄膜電晶體26之閘極422。由圖3A 〇 可知，第一圖案化導電層310之所包含的元件，是很明白 的顯示於圖中的各晝素區位置，而不會有任何的疑問或不 能理解的。 請參閱第3B圖，形成半導體層48在顯示薄膜電晶體 22的閘極421上，以及在感測薄膜電晶體26的閘極422 上。接著，請參閱第3C圖，在串聯的第一導電電極241 上形成第一導通孔49。請注意第一導通孔49並非形成於 第一導電電極之材質中，請查看後續之第4C圖，就可明白 〇 之。 請參閱第3D圖，形成第二圖案化導電層320在第一基 板上，且位於第一圖案化導電層310上方，第二圖案化導 電層320包含複數條資料線20沿著第二方向Y排列，與 掃描線40交錯，以形成各晝素區31、32、33及34。第二 圖案化導電層320還包含第一源/汲極對52設置於每個次 晝素區中，且每個第一源/汲極對52電性連接於每條資料 線20。此外，第二圖案化導電層320還包含第三導電電極 50，設置於各第一導電電極241之上、各.第二導電電極46 201044052 之上，以及第一晝素區31中，其中位於各第一導電電極 241之上的第三導電電極50係經由第一導通孔49與各第 一導電電極241電性連接。另外，第二圖案化導電層320 還包含第一導電線242,設置於第一晝素區31及第三晝素 區33中，作為彎曲的訊號連接線24之一部分，其中位於 第一晝素區31中的第一導電線242電性連接於第三導電電 極50，位於第三畫素區33中的第一導電線242電性連接 於位於第一導電電極241之上的第三導電電極50。而且第 一導電線242會與某些條掃描線40交錯。第二圖案化導電 層320還包含第二源/汲極對54,設置於第一晝素區31中， 〇 第二源極電性連接於另一晝素區群組中的第一導電線242。 請參閱第3E圖，形成第三圖案化導電層330於第一基 板之上，且位於第二圖案化導電層320上方，第三圖案化 導電層330包含至少一第二導電線60，平行於掃描線40 的其中一條排列；至少一第三導電線61，覆蓋各資料線20 的一部份；至少一第四導電線243，設置於第一晝素區31 中，且覆蓋於第二源極54的一部份，以及覆蓋於位於第一 晝素區31中的第三導電電極50的一部份，其作為彎曲的 ❹ 訊號連接線24之一部分。 請參閱第3F圖，形成第二導通孔62於各第一汲極52 上、第二源/汲極54上、位於第二源極54之上的第四導電 線243上、位於第三導電電極50的一部份之上的第四導電 線243上，以及位於第一晝素區31中的第三導電電極50 上。請注意第二導通孔62並非形成於第一汲極52之材質 中、第二源/汲極54之材質中、第四導電線243之材質中 及第三導電電極50之材質中，請查看後續之第4A圖與第 . 10 201044052 4D圖，就可明白之。 請參閱第3G圖，形成晝素電極340於第一基板上，並 位於第三圖案化導電層330上方，晝素電極340包含一晝 素電極主要區塊（或稱為晝素電極區塊)70 5設置於各次晝 素區中，且經由第二導通孔62與各次晝素區中的各第一汲 極52電性連接。晝素電極340還包含第四導電電極72, 其係為晝素電極340之次要區塊，與晝素電極之主要區塊 70電性絕緣。晝素電極340之第四導電電極72覆蓋部份 第二源極54上，且經由第二導通孔62與第二源極54電性 ® 連接；再者，第四導電電極72覆蓋另一部份該第二源極上 方的該第四導電線上。此外，第四導電電極72還覆蓋於第 一晝素區31中的部份第三導電電極50上，且經由第二導 通孔62與第三導電電極50電性連接。另外，晝素電極340 還包括第五導電線74,設置於第二畫素區32中的第二導 電電極46之上。必需要說明的是，第五導電線74電性連 接於另一晝素區群組之第一晝素區31中的第二汲極，而於 同一晝素群組時，第五導電線74並不會電性連接至第一晝 ❹ 素區31中第二源極/汲極。此時，第五導電線74就會與某 些資料線20交錯。 上述之第一導電電極241、第一導電線242、第三導電 電極50、第四導電線243以及第四導電電極72構成彎曲 的訊號Ί買出線24。 雖然第3A至3G圖中未繪出各導電層之間的介電層， 然而在第一導電層310與第二導電層之間具有第一介電層 43，在第二導電層320與第三導電層330之間具有第二介 電層45，且在第三導電層330與晝素電極340之間具有第 π 201044052 三介電層47。因此，上述實施例所述之導通孔就是形成或 突穿於上述介電層之材質中。 $ 請參閱第4A圖，其係顯示沿著第3G圖中剖面線A_A, 之觸控面板的局部剖面示意圖’在此僅繪出第—基板上的 結構。首先，在第一基板1〇0上具有第一圖索化導電層421 作為顯示薄膜電晶體22之閘極，接著在第一固案化導電層 421上覆蓋第一介電層（或稱為閘極絕緣層）43，然後在第二 43 _L形成半導體層48 ’半權48可：含未摻雜 的丰導體層482及掺雜的半導體層482。接著， 圖案化導電層52於半導體® 48上，作Ail -- 、千Μ上料顯$薄膜電晶體 第一源/汲極對。接著，在第一源/汲極鮮2上覆罢第 二介電層45(或稱為保護層），並形成第三介電屉二=一 介電層45上，在第二介電層45及第三介電層^中形; 二導通孔62，並形成晝素電極70覆蓋於第三介電層\7上 及第二導通孔62内，使得第一汲極52與畫素電^ ^之主 $區塊電性連接。再者’本發明以底閘型電晶體為實施方 式，但不限於此。於其它實施例中，頂閘型電晶體亦可使 用，二者差別於半導體層48形成於第一基板1〇〇之順序、 閘極形成的順序及介電層之數目。舉例而言，底閘型電晶 體先形成第一圖案化導電層421之閘極後，再覆蓋介電層 β於第一圖案化導電層421及第一基板100上。然後，再 形成半導體層48於閘極上方的介電層43上。頂閘型電晶 體先形成半導體層48於第一基板100上，再覆蓋介電層 43於半導體層48及第一基板100上。然後，再形成第一 圖案化導電層421之閘極於半導體層48上方的介電層43 上。於了頁閘型電晶體時，為了能夠讓第一圖案化導電層421 12 201044052 ”弟—圖案化導電層421上的第二 紐路，除了第二介電層45與第 ^^電層不會發生 匕額外介電層(或稱為内層介電層電二外，會再覆 化導電層421及基板1〇〇上，此時，於第一圖案 ^的第二圖案化導電層位於不同水圖案化導電層421 ^額外介電層，則第一圖 ·^者是’不 ;案化導電層位於同一水平平面上電；:2丄之間極與第二 再依續堆疊所需要的膜層， =隔開且絕 ❹ Ο 弟二介電層45、第三圖案化導 ^圖案化導電層52、 47 ^ A，-A ^ ^ 明參閱第4B圖，其係顯示沿著第 ，板的局部剖面示意圖。在第弟一3=面線Β-Β， :介電層（或稱為閘極騎層Μ3，上具有第 ::圖案化導電層2〇作為 在第， -上形成二二層= 為第保護/ )45。在第二介電層 導電線61上覆罢裳二人θ第一導電線61，然後在第三 要區塊於第三介皿電層層47，亚形成畫素電極7〇之主 請參閱第4c圖θ，i -圖案化導電*第—基板⑽上具有第 上覆蓋第一八二第—導電電極241，在第一導電電極241 層43中形成|筮層（或稱為閘極絕緣層）43，並在第一介電 之第三導電導:孔49 ’然後形成第二圖案化導電層 49内，並心帛覆盘於第一介電層43上及第一導通孔 電極50,4 f 一介電層（或稱為保護層）45覆蓋第三導電 弟圖案化導電層之第一導電電極241經由 13 201044052 弟一導通孔49斑第-圖安推& 性連接。 ’、一，、匕、電層之第三導電電極50電 請參閱第4D圖，苴係顧_ _ 之觸控面板的局部剖面沿；第30圖— 一圖案化導電層422 第一基板100上具有第 第-圖案化導電層422=:薄=體：之閑極，在 層H3，然後形成第二圖以:= 糊極絕緣 上，作為感測薄膜電晶體、26之第%/、及極對介電層43 二介電層（或稱為佴婼弟一源/汲極對，並形成第Such as: wafer, ceramic, metal plate, opaque glass, opaque quartz, opaque polymer plate, other materials, or a combination of the above. Or a flexible substrate (for example, polyacrylic acid ester, polycarbonate, polystyrene, polyfluorene, polyfluorene, other materials, or a combination thereof) to form a first pattern on the first substrate Conductive layer 310. The first patterned conductive layer 310 includes a plurality of scan lines 40 arranged along the first direction X, a plurality of first conductive electrodes 241 connected in series, and a plurality of independent second conductive electrodes 46. In addition, the first patterned conductive layer 310 also functions as a gate 421 for displaying the thin film transistor 22, and a gate 422 for sensing the thin film transistor 26. 3A, the elements included in the first patterned conductive layer 310 are clearly shown in the respective pixel regions in the figure without any doubt or understanding. Referring to Figure 3B, a semiconductor layer 48 is formed over the gate 421 of the display film transistor 22 and on the gate 422 of the sensing film transistor 26. Next, referring to FIG. 3C, a first via hole 49 is formed on the first conductive electrode 241 connected in series. Please note that the first via 49 is not formed in the material of the first conductive electrode. Please refer to the following figure 4C for the following. Referring to FIG. 3D, a second patterned conductive layer 320 is formed on the first substrate and above the first patterned conductive layer 310. The second patterned conductive layer 320 includes a plurality of data lines 20 along the second direction. The arrays are interleaved with the scan lines 40 to form respective pixel regions 31, 32, 33 and 34. The second patterned conductive layer 320 further includes a first source/drain pair 52 disposed in each of the sub-cell regions, and each of the first source/drain pairs 52 is electrically connected to each of the data lines 20. In addition, the second patterned conductive layer 320 further includes a third conductive electrode 50 disposed on each of the first conductive electrodes 241, each of the second conductive electrodes 46 201044052, and the first pixel region 31, wherein The third conductive electrode 50 on each of the first conductive electrodes 241 is electrically connected to each of the first conductive electrodes 241 via the first vias 49 . In addition, the second patterned conductive layer 320 further includes a first conductive line 242 disposed in the first halogen region 31 and the third halogen region 33 as a part of the curved signal connection line 24, wherein the first pixel is located in the first pixel The first conductive line 242 in the region 31 is electrically connected to the third conductive electrode 50, and the first conductive line 242 located in the third pixel region 33 is electrically connected to the third conductive electrode located above the first conductive electrode 241. 50. Moreover, the first conductive line 242 is interleaved with some of the scan lines 40. The second patterned conductive layer 320 further includes a second source/drain pair 54 disposed in the first halogen region 31, and the second source is electrically connected to the first conductive line in the other pixel region group. 242. Referring to FIG. 3E, a third patterned conductive layer 330 is formed on the first substrate and above the second patterned conductive layer 320. The third patterned conductive layer 330 includes at least one second conductive line 60, parallel to One of the scan lines 40 is arranged; at least one third conductive line 61 covers a portion of each data line 20; at least one fourth conductive line 243 is disposed in the first pixel region 31 and covers the second source A portion of the pole 54 and a portion of the third conductive electrode 50 that is disposed in the first pixel region 31 serves as a portion of the curved 讯 signal connection line 24. Referring to FIG. 3F, a second via hole 62 is formed on each of the first drain electrodes 52, on the second source/drain 54 and on the fourth conductive line 243 above the second source 54 at the third conductive line. The fourth conductive line 243 over a portion of the electrode 50 and the third conductive electrode 50 in the first halogen region 31. Please note that the second via hole 62 is not formed in the material of the first drain 52, the material of the second source/drain 54 , the material of the fourth conductive line 243 and the material of the third conductive electrode 50, please check The following figure 4A and paragraph 10 201044052 4D can be understood. Referring to FIG. 3G, a halogen electrode 340 is formed on the first substrate and above the third patterned conductive layer 330. The halogen electrode 340 includes a main block of a halogen electrode (or a halogen electrode block). 70 5 is disposed in each of the halogen regions, and is electrically connected to each of the first drain electrodes 52 in each of the individual halogen regions via the second via holes 62. The halogen electrode 340 further includes a fourth conductive electrode 72, which is a secondary block of the halogen electrode 340, electrically insulated from the main block 70 of the halogen electrode. The fourth conductive electrode 72 of the halogen electrode 340 covers a portion of the second source 54 and is electrically connected to the second source 54 via the second via 62. Further, the fourth conductive electrode 72 covers the other portion. And displacing the fourth conductive line above the second source. In addition, the fourth conductive electrode 72 also covers a portion of the third conductive electrode 50 in the first halogen region 31, and is electrically connected to the third conductive electrode 50 via the second via 62. In addition, the halogen electrode 340 further includes a fifth conductive line 74 disposed above the second conductive electrode 46 in the second pixel region 32. It should be noted that the fifth conductive line 74 is electrically connected to the second drain in the first pixel region 31 of the other pixel region group, and the fifth conductive line 74 is in the same pixel group. It is not electrically connected to the second source/drain in the first pixel region 31. At this time, the fifth conductive line 74 is interleaved with some of the data lines 20. The first conductive electrode 241, the first conductive line 242, the third conductive electrode 50, the fourth conductive line 243, and the fourth conductive electrode 72 constitute a curved signal Ί buyout line 24. Although the dielectric layer between the conductive layers is not depicted in FIGS. 3A to 3G, there is a first dielectric layer 43 between the first conductive layer 310 and the second conductive layer, and a second conductive layer 320 and There is a second dielectric layer 45 between the three conductive layers 330, and a third dielectric layer 47 of the π 201044052 between the third conductive layer 330 and the halogen electrode 340. Therefore, the via holes described in the above embodiments are formed or protruded through the material of the dielectric layer. $ Referring to Fig. 4A, which is a partial cross-sectional view of the touch panel along the section line A_A of Fig. 3G, only the structure on the first substrate is depicted. First, a first patterned conductive layer 421 is provided on the first substrate 110 as a gate of the display thin film transistor 22, and then a first dielectric layer is covered on the first fixed conductive layer 421 (or referred to as a first dielectric layer). The gate insulating layer 43 and then the semiconductor layer 48' is formed at the second 43_L. The half-weight 48 may include an undoped abundance conductor layer 482 and a doped semiconductor layer 482. Next, the patterned conductive layer 52 is patterned on the Semiconductor® 48 for the Ail-, Millennium, and the first source/drain pair of the thin film transistor. Next, a second dielectric layer 45 (or a protective layer) is overlaid on the first source/drain 2, and a third dielectric layer 2 is formed on the dielectric layer 45 in the second dielectric layer. 45 and the third dielectric layer are formed in the middle; the second via hole 62 is formed, and the pixel electrode 70 is formed on the third dielectric layer \7 and the second via hole 62, so that the first drain 52 and the pixel are electrically ^ ^Owner $ block electrical connection. Further, the present invention is a bottom gate type transistor, but is not limited thereto. In other embodiments, a top gate type transistor may also be used, which differs from the order in which the semiconductor layer 48 is formed on the first substrate, the order in which the gates are formed, and the number of dielectric layers. For example, the bottom gate type electric crystal first forms the gate of the first patterned conductive layer 421, and then covers the dielectric layer β on the first patterned conductive layer 421 and the first substrate 100. Then, a semiconductor layer 48 is formed over the dielectric layer 43 above the gate. The top gate type electric crystal first forms a semiconductor layer 48 on the first substrate 100, and then covers the dielectric layer 43 on the semiconductor layer 48 and the first substrate 100. Then, a gate of the first patterned conductive layer 421 is further formed on the dielectric layer 43 above the semiconductor layer 48. In the case of the page gate type transistor, in order to enable the first patterned conductive layer 421 12 201044052 to pattern the second line on the conductive layer 421, except for the second dielectric layer 45 and the second layer An additional dielectric layer (or an inner dielectric layer) will be formed, and the conductive layer 421 and the substrate 1 will be overlaid. At this time, the second patterned conductive layer in the first pattern is different. Water patterned conductive layer 421 ^ additional dielectric layer, then the first figure is 'no; the cased conductive layer is located on the same horizontal plane; 2: between the pole and the second is required to continue stacking Film layer, = separated and absolutely Ο 二 2 dielectric layer 45, third patterned conductive patterned conductive layer 52, 47 ^ A, -A ^ ^ See Figure 4B, which is shown along the A partial cross-sectional view of the plate. In the first brother 3 = the upper line Β-Β, the dielectric layer (or called the gate riding layer ,3, having the ::: patterned conductive layer 2〇 as the first, The second and second layers = the first protection / ) 45. The second dielectric layer 61 is covered on the second dielectric layer conductive line 61, and then the third dielectric layer is in the third dielectric layer 47. For the sub-formation of the pixel electrode, please refer to FIG. 4c, θ, i-patterned conductive*, the first substrate (10) has an upper cover first 182-first conductive electrode 241, and the first conductive electrode 241 layer 43 Forming a 筮 layer (or referred to as a gate insulating layer) 43 and forming a third conductive conductive layer 49 in the first dielectric third conductive via: hole 49 ′, and embossing the first The dielectric layer 43 and the first via electrodes 50, 4 f are a dielectric layer (or referred to as a protective layer) 45 covering the first conductive electrode 241 of the third conductive pattern patterned conductive layer via 13 201044052 The first section of the touch panel of the touch panel is shown in Figure 4D. - a patterned conductive layer 422 having a first - patterned conductive layer 422 on the first substrate 100 =: thin = body: the idle pole, in the layer H3, and then forming a second figure to: = paste insulation, as a sense Measure the thin film transistor, the second % of 26, and the second dielectric layer of the pair of dielectric layers 43 (or a pair of dipoles/bungee pairs, and form the first
CI 形成第三圖宰化導、電/覆盍第二源/汲極對54。接著， 電…：二層第之第二導，線243於部分的第二介CI forms the third map of the smear, electric/covering second source/dip pair 54. Then, electric...: the second of the second layer, the second of the line 243
形成第-導iiil e、 一，I電層45及第四導電線243中 戍弟一導通孔62，然後形 T 覆蓋於第二介電層45和第四導電弟五導電線74 孔62内，其中晝素電極之第五雷’以及第二導通 62分別與第二圖案化 導電線、74、㈣第二導通孔 案化導電層之第四導電後曰—源/沒極對54及第三圖 咬会⑽ 電線43電性連接。 明茶閱第4E圖，其係顯示沿 之觸控面板的按壓❹彳結 抽線M， ❹ inn u a ^ 舟zz> 口』面不意圖。在筮一装此 後形成第二圖案化導電層1 之第mm緣層然 保護細。上述第-、第 電層（或稱為 :、第二介電層…構成按，二== 此外’觸控面板還包括第二基板與第_基板⑽ 14 201044052 對向設置，第二基板200例如為破璃基板，感測間隔物 設置於第二基板200上，其例如為感光性間隔物 spacer)。在感測間隔物201上覆蓋有第一透明導電居2 t〇 並且在感測平台101上覆蓋有第二透明導電層74，其3、 晝素電極之第五導電線，第一及第二透明導電層可為 或多層結構，其材質包含：銦錫氧化物(IT〇)、銦鋅^化， (ΙΖ〇)、鋁鋅氧化物(ΑΖΟ)、鋁錫氧化物(ΑΤ〇)、銦鍺鋅勿 物(IGZO)、其它合適的材質、或上述之組合，兩者於觸$ 〇 面板未受到按壓時具有一間距Ρ，並且於觸控面板受到^ 壓時互相接觸而形成電通路（或稱短路）。此時，觸控面板 訧已完成，其中，二基板内沒有其它物質。再者，若要形 成觸控顯示面板，可將上述之觸控面板外貼於顯示面板之 卜其中’顯示面板結構為第一基板具有主動元件矩陣層， 包含複數個電晶體，第二基板相對應於第一基板，且上述 一基板間具有一間隔以及顯示介質層設置該間隔中。若， 將觸控面板搭配顯示面板之製造過程，而形成内整合式觸 控顯示面板’則在第一基板100與第二基板200之間還包 ^ 含一顯示介質層300，可使觸控面板顯示影像。其中，上 述顯示介質層之材料，包含非自發光材料（例如：液晶材 料、電泳材料、其它合適的材料或上述之組合）、自發光材 料(例如：有機發光材料、無機發光材料、其它合適的材料 或上述之組合）、其它合適的材料或上述之組合。顯示面板 可依顯示介質層之材料包含非自發光面板(例如：液晶顯示 面板、三維顯示面板、電泳顯示面板、藍相顯示面板、水 平切換顯示面板、垂直配向顯示面板、雙面顯示面板、其 匕合適的面板或上述之組合）、自發光面板、其它合適的面 15 201044052 板或上述之組合。 雖然本發明已揭露較佳實施例如上，然其並非用以限 定本發明，任何熟悉此項技藝者，在不脫離本發明之精神 和範圍内，當可做些許更動與潤飾，因此本發明之保護範 圍當視後附之申請專利範圍所界定為準。 f) ❹ 16 201044052 【圖式簡單說明】 第1圖係顯示傳統的電阻式觸控面板之平面示意圖。 第2圖係顯示係顯示依據本發明一實施例之觸控面板 的平面示意圖。 第3A至3G圖係顯示依據本發明之一實施例，形成觸 控面板之晝素區群組的各製程平面示意圖。 第4A至4E圖係分別顯示沿著第3G圖中剖面線 八-八’、3-：8’、(：-(：’、0-0’及£-丑’之觸控面板的剖面示意圖。Forming a first conductive via 62 in the first conductive layer iii1 e, the first electrical layer 45 and the fourth conductive line 243, and then overlying the second dielectric layer 45 and the fourth conductive fifth conductive line 74 in the hole 62 The fifth conductive ray of the halogen electrode and the second conductive electrode 62 respectively and the second patterned conductive line, 74, (four) the second conductive via conductive layer, the fourth conductive back-source/no-pole pair 54 and The three figures bite (10) The wires 43 are electrically connected. Ming tea read Figure 4E, which shows the pressing of the touch panel along the touch panel, M, ❹ inn u a ^ boat zz> mouth is not intended. The first mm layer of the second patterned conductive layer 1 is formed to be finely protected after the first mounting. The first and second electrical layers (or the second dielectric substrate (or the second dielectric layer constituting the second, the second dielectric substrate constituting the second, the second substrate, the second substrate, and the second substrate) For example, the glass substrate is provided, and the sensing spacer is disposed on the second substrate 200, which is, for example, a photosensitive spacer. The sensing spacer 201 is covered with a first transparent conductive layer 2 t and covered on the sensing platform 101 with a second transparent conductive layer 74, 3, a fifth conductive line of the halogen electrode, first and second The transparent conductive layer may have a multi-layer structure, and the material thereof comprises: indium tin oxide (IT〇), indium zinc oxide, (ΙΖ〇), aluminum zinc oxide (ΑΖΟ), aluminum tin oxide (ΑΤ〇), indium. IG 勿 勿 (IGZO), other suitable materials, or a combination thereof, both of which have a spacing 于 when the touch panel is not pressed, and form an electrical path when the touch panel is pressed against each other ( Or short circuit). At this time, the touch panel has been completed, and there is no other substance in the two substrates. Furthermore, if the touch display panel is to be formed, the touch panel may be externally attached to the display panel. The display panel structure has a first substrate having an active device matrix layer, and includes a plurality of transistors, and the second substrate phase Corresponding to the first substrate, and a spacing between the one of the substrates and the display medium layer are disposed in the interval. If the touch panel is combined with the manufacturing process of the display panel to form the inner integrated touch display panel, a display medium layer 300 is further included between the first substrate 100 and the second substrate 200 to enable touch The panel displays the image. The material of the display medium layer comprises a non-self-luminous material (for example, a liquid crystal material, an electrophoretic material, other suitable materials or a combination thereof), a self-luminous material (for example, an organic luminescent material, an inorganic luminescent material, other suitable materials). Materials or combinations thereof, other suitable materials or combinations thereof. The display panel may include a non-self-illuminating panel according to the material of the display medium layer (eg, a liquid crystal display panel, a three-dimensional display panel, an electrophoretic display panel, a blue phase display panel, a horizontal switching display panel, a vertical alignment display panel, a double-sided display panel, and匕 Suitable panels or combinations of the above), self-illuminating panels, other suitable faces 15 201044052 panels or a combination of the above. Although the present invention has been disclosed in its preferred embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached. f) ❹ 16 201044052 [Simple description of the diagram] Figure 1 shows a schematic diagram of a conventional resistive touch panel. Fig. 2 is a plan view showing a touch panel according to an embodiment of the present invention. 3A through 3G are schematic views showing respective process planes of a group of pixel regions forming a touch panel in accordance with an embodiment of the present invention. 4A to 4E are cross-sectional views showing the touch panels of the eight-eighth, 3-:8', (:-(:', 0-0', and £-ugly') sections along the section 3G, respectively. .
【主要元件符號說明】 11、40〜掃描線； 14〜訊號讀出線； 16、26〜感測薄膜電晶體； 24〜彎曲的訊號讀出線； 31〜第一晝素區； 33〜第三晝素區； 310〜第一圖案化導電層； 10、20〜資料線； 12、22〜顯示薄膜電晶體； 15、25〜按壓感測結構； 18、28〜次晝素區； 30〜晝素區群組； 32〜第二晝素區； 34〜第四晝素區； 241〜第一導電電極(第一圖案化導電層）； 46〜第二導電電極(第一圖案化導電層）； 421〜顯示薄膜電晶體之閘極(第一圖案化導電層）； 422〜感測薄膜電晶體之閘極(第一圖案化導電層）; 48〜半導體層； 49〜第一導通孔； 320〜第二圖案化導電層； 242〜第一導電線(第二圖案化導電層）； 50〜第三導電電極(第二圖案化導電層）； 52〜第一源/汲極對(第二圖案化導電層）； 54〜第二源/汲極對(第二圖案化導電層）； 17 201044052 330〜第三圖案化導電層； 60〜第二導電線(第三圖案化導電層）； 61〜第三導電線(第三圖案化導電層）； 243〜第四導電線(第三圖案化導電層）； 62〜第二導通孔； 340〜晝素電極； 70〜畫素電極之主要區塊， 72〜晝素電極之第四導電電極， 74〜晝素電極之第五導電線(第二透明電極層）； 100〜第一基板； 482〜摻雜之半導體層 45〜第二介電層； 200〜第二基板； 203〜第一透明導電層 300〜顯示介直層； X〜第一方向； 481〜未摻雜之半導體層； 43〜第一介電層； 47〜第三介電層； 201〜感測間隔物； 101〜感測平台； P〜間距； Y〜第二方向。 18[Main component symbol description] 11, 40~ scan line; 14~ signal readout line; 16, 26~ sensing thin film transistor; 24~ curved signal readout line; 31~ first pixel area; 33~ Triterpenoid zone; 310~first patterned conductive layer; 10, 20~ data line; 12, 22~ display film transistor; 15, 25~ press sensing structure; 18, 28~ sub-dioxin zone; 30~ a group of halogen regions; 32 to a second halogen region; 34 to a fourth halogen region; 241 to a first conductive electrode (first patterned conductive layer); 46 to a second conductive electrode (first patterned conductive layer) 421~ display the gate of the thin film transistor (first patterned conductive layer); 422~ sense the gate of the thin film transistor (first patterned conductive layer); 48~ semiconductor layer; 49~ first via 320~ second patterned conductive layer; 242~first conductive line (second patterned conductive layer); 50~third conductive electrode (second patterned conductive layer); 52~first source/drain pair a second patterned conductive layer); 54~ a second source/drain pair (a second patterned conductive layer); 17 201044052 330~ a third patterned conductive a layer; 60 to a second conductive line (third patterned conductive layer); 61 to a third conductive line (third patterned conductive layer); 243 to a fourth conductive line (third patterned conductive layer); Two via holes; 340~ quinone electrode; main block of 70~ pixel electrode, fourth conductive electrode of 72~ quinone electrode, fifth conductive line of 74~ quinone electrode (second transparent electrode layer); ~ first substrate; 482 ~ doped semiconductor layer 45 ~ second dielectric layer; 200 ~ second substrate; 203 ~ first transparent conductive layer 300 ~ display dielectric layer; X ~ first direction; 481 ~ undoped Miscellaneous semiconductor layer; 43~first dielectric layer; 47~third dielectric layer; 201~ sensing spacer; 101~ sensing platform; P~ pitch; Y~ second direction. 18