201037444 六、發明說明： 【發明所屬之技術領域】 本發明係一種提昇薄膜電晶體基板之畫素缺陷偵測率的佈局結201037444 VI. Description of the Invention: [Technical Field] The present invention is a layout knot for improving the pixel defect detection rate of a thin film transistor substrate
構，其係特別關於一種利用虛擬資料走線來定位短路缺陷之薄膜電^ 體基板佈局結構。 BB 【先前技術】 在陣列製程(Array process)結束後，係搭配一陣列製程檢測(A「ray test)來檢是薄膜電晶體是否符合需求^舉例來說在八「「办娜中檢測 金屬線(掃描線、資料線、共通電極走線）是否符合需求、電晶體 〇符合需求等等。 當輸入測試f歸，如歸線娜姆_鱗時(SGUrc e line short，SG s_，檢測機的螢幕上會顯示’，十，，字線十字的交錯 即為短路(_所在’定針分方便；如將線與共财極走線出 =^時(source/common line _，sc _)，檢測機的勞幕上亦 會上會顯〇’，跡但是，如掃描_共通雜走線出馳路_· :m〇n line s_，GC s_，檢測機的螢幕上會顯示，，一”字線。目 是在那條字線上出現最低電壓的地方定位，以人眼開始 ❹的解^方^在，耗費人力成本。先前技術對於GC short並未提出有效 =’本發明提出—種提昇薄膜電晶體基板之畫素缺_測率的 怖局，構，以解決上述缺失。 【發明内容】 測率要二的在提供-種提昇薄膜電晶體基板之畫素缺陷偵 效解決先前;術中口 ==GC蝴短路位置，有 本辨明夕η 1 找賴擾，能有效的節省人力成本。 測率的— Ξ的在提供—種提昇薄膜電晶體基板之晝素缺陷摘 〜Ί將虛㈣料走線設置於掃描線與共通電極走線 201037444 之間’當有祕雜時’位於雜職共通電極 訊號(電壓)輸入，電壓通過書素電極it ] f將測"式 陷產生電容時，電容的位置走線触’並與短路缺 糾本=雜供—種料薄膜電晶縣板之畫素__率的佈局 ^構丄其係包純數列第-資料線及複數行第—掃描線，利用複數列 貝料線及複數行第-掃插線定義出複數個晝素(pixe|)，且於每一個 素中形成-個薄媒電晶體，其中薄膜電晶體的閘極係與該第一掃描 線連接，薄膜電晶體的源極及汲極分別與該第 連接。共通電極走線臨近第—掃描線和第—資料走線設置， $線被畫素電極部分覆蓋；虛擬資料走線位㈣第—掃描線與該共 通電極走狀間，且虛姆料纽與該畫素電極連接。 本 /本發明之提昇薄膜電晶體基板之晝素缺陷侧率的佈局結構，其 ^將虛擬資料走線設置於掃财與舰雜走線之間；#有短路缺陷 日·’位於掃描線與共通電極走線之間時’將測試訊號(電壓)輸入，電壓 通過晝素電極與虛擬資料_連接，並與短路缺陷產生電容時，電容 的位置係為缺關位置。能有效並快義定位GC shQrt的短路位置， f效解決先前技術巾，必須以人眼·的隨，能有效的節省人力成 底下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本 發明之目的、技術内容、特點及其所達成之功效。 【實施方式】 為能詳細綱本㈣之提⑽麟晶縣板之晝素缺陷細率的 =結構’睛參照第1圖及第2圖。第彳圖係本發明之提昇薄膜電晶 土板之畫素缺__的佈局結構。本發明之薄膜電晶體基板之畫 二缺陷偵測率的佈局結構包括複數列第一資料線22及複數行第一掃 =線24 °複數列第一資料'線22及複數行第一掃描線24定義出複數個 —素(pixel) ’且於每一個晝素中形成一個薄膜電晶體26，以薄膜電晶 201037444 ‘ 為件，其中係糊'第—金屬層同時形成薄膜電晶體 思门I 第一掃猶22以及共通電極走線38 ;利用-第二金屬 •電晶體26咖2、源極3〇以及第-資料線一22。 tlltZ Tm 32 ^ 34 ^ ° 28 30 # 44作為通道。其中，在本實施例中， 形成第一~描線24、薄膜電晶體26的閘極28以月妓、3餘^：^& 之第一金屬層係鈥鋁鉬合金（Mo/AI/Nd)。 38 曰丘極走線38，係臨近第—諸線22和第—掃描線24設置， ο 來遮___ 的好ίΐΓ财’共通電極走線38係以“u，，字型設置，如此設計 綠初處if =提_σ率。在本發_其他實_中，共通電極走 為均等變H口？型設置。此等共通極走線38的形狀變化，應 為均尋變化或修飾，理應屬於於本發明之同一技術思想。 虛擬資料走線40位於第一掃描線24與共通電極走線38之 ^虛擬資料走線40與畫素電極34連接。在本實施例中，在同一 中，有兩條虛擬資料走線40，且兩條虛擬資料走線4〇均介於' 〇 通電極走線38之間。其中兩條虛擬資料走線4〇 :42數目並不相同’接觸窗42的數目越多，虛擬資料走線4〇 f電極34的紐連接錢賴高，树批虛㈣料纽4q之接 匈42的數目並不限制，依照需求而有所不同。 繼續說明第1圖中’虛擬資料走線4〇的設置，請一併參2 圖’第2圖係第1圖之部分剖面圖。於第2圖中，包括薄膜 板50，介電層52位於薄膜電晶體玻璃基板上，在本實施例中== 52係由閘極絕緣層和保護層構成。接觸窗42形成於介電層52上，: 素電極34設置在介電層52之上，並通過該接觸窗42與虛擬^ 線40相接觸’以達成電性連接。畫素電極34則位於介電層52上 需要測試時，可透過晝素電極34、接觸t42與虛擬資料走線4接 5 201037444 請一併參照第3圖及第4圖，第3圖係者太 板有缺陷時的示意圖。第4難第3圖之部分立彳關；膜電晶體基 如前所述，本發明之薄膜電晶體基板5〇 _複數 22及複數行第-掃猶24。複數列第—資料線&及複赠第== 線24定義出複數個畫素(ρ_ ’且於每一個畫素中形成 體26，以薄膜電晶體26作為開關元件，其中係 時形成顧電晶體26的閉極28、第一掃晦線&以及共 38 ;利用一第二金屬層同時形成薄膜電晶體％的沒極32、源極 以及第-資料線22。薄膜電晶體26 _極32與畫素電極連接。 在閘極28與源極30及沒極32之間係有—非晶石夕々44 中，在本實施例中，形成第-掃描線24、薄膜電晶體况的閑極28以 及共通電狱線38之第-金屬層係_齡金（M副_)。 共通電極走線38 ’佩近第—資料線22和第_掃描線24設置， ^共通電極走線38被畫素電極34部分覆蓋，魏雜走線38係用 晝u^i34週緣通過之光線。在本實施例中，共通電極走線 係以U子型設置，如此設計的好處在於可以提高開口率。在本 發明的其他實施例中’共通_走線38亦可以‘‘口，，字型設置。此等 電和走線38的开〉狀變化，應為均等變化或修飾，理應屬於於本發 明之同一技術思想。 、 虛，資料走線4G位於第-掃描線24與共通電極走線％之間， 資料走線4〇與晝素電極34連接。在本實施例中，在同—個_ 兩條虛擬資料走線，且兩條虛擬資料走線均介於第一掃 ^22i與共通電極走線38之間。其中兩條虛擬資料走線4〇的接觸 目並不相同，接觸窗42的數目越多，虛擬資料走線40與畫 二，34❸電性連接強度就越高’本發明之虛擬資料走線40之接觸 窗42的數目並不關，依照f求而麵不同。 接觸 4 |^| =之部份局部放大之剖視圖包括一介電層52，介電層52位 ' 、電曰曰體破螭基板上，在本實施例中介電層52係由閘極絕緣層和 201037444 • 保$層構成。介電層52包覆該虚擬資料走線40, -接觸窗42形成於 该介電層52上，晝素電極34設置在所述的介電層&之上，並通過 該接觸142與輯的虛擬資料魏4()減觸，以賴紐連接。晝 素電極34則位於介電層52上，需要測試時，可透過畫素電極34、接 觸窗42與虛擬資料走線4〇連接。 請一併參照第4圖所示，當薄膜電晶體基板50中之介電層中52 具有一缺陷46位於該第一掃描線24與共通電極走線38之間時，將 一電壓輸人’電壓通獅4素電極34與該虛擬資料走線4G連接，並 與缺陷46產生電容48時，電容48的位置係為缺陷46的位置。藉由 ^ 述方式、本發明之提昇薄膜電晶體基板之晝素缺陷Y貞測率的佈局結 構能有效並快速的定位GCsh〇rt的短路位置，有效解決先前技術中， 必須以人眼尋找的困擾，能有效的節省人力成本。 唯以上所述者，僅為本發明之較佳實施例而已，並非用來限定本 發明實施之範®。故即凡鉢發明_魏麟狀雜、構造、特徵 及精神所為之鱗變化或修飾，均應包括於本發明之_請專利範圍内。 【圖式簡單說明】 第1圖係本發明之一實施例之提昇薄膜電晶體基板之晝素缺陷偵測率 的佈局結構。 ®第2圖係本發明之—實施例之部分放大示意圖。 第3圖係本發明之另__實_之提昇薄膜電晶體基板之晝素缺陷侧 率的佈局結構。 第4圖係本發明之另一實施例之部分放大示意圖。 【主要元件符號說明】 22第一資料線 24第一掃描線 26薄膜電晶體 28閘極 7 201037444 30源極 32汲極 34晝素電極 36儲存電容 38共通電極走線 40虛擬資料走線 42接觸窗 44非晶矽層 46缺陷 48電容 50薄膜電晶體玻璃基板 52介電層The structure is particularly related to a thin film electrical substrate layout structure for locating short defects using dummy data traces. BB [Prior Art] After the Array process is finished, it is combined with an array process test (A "ray test" to check whether the film transistor meets the requirements. For example, in the "8" (Scan line, data line, common electrode trace) Whether it meets the requirements, the transistor 〇 meets the requirements, etc. When the input test f is returned, such as the return line nam _ scale (SGUrc e line short, SG s_, detector The screen will display ', ten, the intersection of the word line cross is short circuit (_ where 'fixed pin is convenient; if the line and the common wealth line out = ^ (source/common line _, sc _), The screen of the inspection machine will also appear on the screen, but the traces, such as the scan _ common miscellaneous lines, _· :m〇n line s_, GC s_, will be displayed on the screen of the detector, one Word line. The purpose is to locate the place where the lowest voltage appears on the word line, and the solution is started by the human eye. It costs labor costs. The prior art has not been effective for GC short = 'proposed by the present invention' The thin film transistor substrate has a lack of metrics, which is used to solve the above-mentioned defects. SUMMARY OF THE INVENTION The measurement rate is two in the provision of a thin film transistor substrate for the detection of pixel defects in the previous solution; intraoperative mouth == GC butterfly short-circuit position, there is a sensation of η 1 to find the reliance, can effectively save Labor cost. Measured - Ξ 在 在 提供 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升 提升Located in the common electrode signal (voltage) input, the voltage through the pixel electrode it] f will be measured " type trapping capacitance, the position of the capacitor touches the line and the short circuit is missing the correct version = miscellaneous supply - seed film The layout of the __ rate of the Jingxian plate 丄 丄 丄 丄 丄 丄 丄 丄 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯 纯a pixe|, and forming a thin dielectric transistor in each of the elements, wherein a gate of the thin film transistor is connected to the first scan line, and a source and a drain of the thin film transistor are respectively connected to the first The common electrode trace is adjacent to the first scan line and the first data trace The $ line is partially covered by the pixel electrode; the dummy data trace position (4) is between the scan line and the common electrode, and the dummy material is connected to the pixel electrode. The present invention is a lift thin film transistor substrate The layout structure of the defect side rate of the halogen element, which sets the virtual data trace between the sweeping and the ship miscellaneous line; #有短断缺日·'When the scan line is between the scan line and the common electrode trace' will test Signal (voltage) input, the voltage is connected to the dummy data through the halogen electrode, and when the capacitor is generated with the short defect, the position of the capacitor is the missing position. The short position of the GC shQrt can be effectively and quickly located, and the f effect is solved. The technical towel must be effectively saved by the human eye, and can be effectively explained by the specific embodiment with the accompanying drawings, when it is easier to understand the purpose, technical content, characteristics and achievement of the present invention. The effect. [Embodiment] For the detailed outline (4), refer to Figs. 1 and 2 for the structure defect of the ruthenium defect of the Linjing County plate. The second drawing is a layout structure of the lithographic defect of the lifted film electromorphic plate of the present invention. The layout structure of the defect detection rate of the thin film transistor substrate of the present invention comprises a plurality of columns of first data lines 22 and a plurality of rows of first scan = line 24 ° plural columns of first data 'line 22 and a plurality of lines of first scan lines 24 defines a plurality of pixels - and forms a thin film transistor 26 in each of the halogens, and the thin film electrocrystal 201037444' is used as a piece, wherein the metal layer of the paste is simultaneously formed into a thin film transistor. The first sweeping 22 and the common electrode trace 38 are utilized; the second metal transistor 22, the source 3 〇, and the first-data line 22 are utilized. tlltZ Tm 32 ^ 34 ^ ° 28 30 # 44 as a passage. In the present embodiment, the first to trace 24, the gate 28 of the thin film transistor 26 is formed by a first metal layer of ruthenium aluminum molybdenum alloy (Mo/AI/Nd). ). 38 曰 极 极 38 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , At the beginning of the green, if = _ σ rate. In this _ other real _, the common electrode is set to the equal-change H port type setting. The shape change of these common pole traces 38 should be changed or modified. The virtual data trace 40 is located between the first scan line 24 and the common electrode trace 38 and is connected to the pixel electrode 40. In this embodiment, in the same There are two virtual data traces 40, and the two virtual data traces 4〇 are between the 'pass-through electrode traces 38. Two of the virtual data traces are 4: 42 are not the same 'contact window The more the number of 42, the virtual data connection 4 〇 f electrode 34 of the new connection money Lai Gao, the tree is imaginary (four) material 4 4 of the number of the connection to Hungary 42 is not limited, according to the needs vary. Continue to explain the first In the figure, the setting of 'virtual data trace 4〇, please refer to 2 Fig. 2' is a partial cross-sectional view of Fig. 1 2, comprising a film plate 50, the dielectric layer 52 is on the thin film transistor glass substrate, in this embodiment == 52 is composed of a gate insulating layer and a protective layer. The contact window 42 is formed on the dielectric layer 52. The element electrode 34 is disposed on the dielectric layer 52 and is in contact with the dummy wire 40 through the contact window 42 to achieve electrical connection. The pixel electrode 34 is located on the dielectric layer 52 and needs to be tested. Connected to the virtual data trace 4 through the halogen electrode 34 and the contact t42. 5 201037444 Please refer to Fig. 3 and Fig. 4 together. Fig. 3 is a schematic diagram of the case where the board is defective. Part 4 of the fourth difficulty彳 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; A plurality of pixels (ρ_ ' are defined and a body 26 is formed in each pixel, and a thin film transistor 26 is used as a switching element, wherein the closed pole 28 of the transistor 26, the first broom line & A total of 38; using a second metal layer to simultaneously form the thin film transistor % of the pole 32, the source and the - data line 22. Thin The transistor 26 _ pole 32 is connected to the pixel electrode. In the amorphous gate 々 44 between the gate 28 and the source 30 and the gate 32, in the present embodiment, the first scan line 24 is formed. The idle pole 28 of the thin film transistor state and the first metal layer of the common power line 38 are _ age gold (M pair _). The common electrode trace 38 'pepe close to the data line 22 and the _ scan line 24 are set, The common electrode trace 38 is partially covered by the pixel electrode 34, and the Wei trace 38 is the light that passes through the periphery of the 昼u^i34. In this embodiment, the common electrode trace is set by the U sub-type, thus designed. The advantage is that the aperture ratio can be increased. In other embodiments of the invention, the 'common_line 38 may also be '' mouth, font set. The change of the electrical and trace 38 should be equal or modified, and should belong to the same technical idea of the present invention. The data trace 4G is located between the first scan line 24 and the common electrode trace %, and the data trace 4 is connected to the halogen electrode 34. In this embodiment, two virtual data lines are routed in the same _, and two virtual data lines are between the first scan 22i and the common electrode trace 38. The contact angles of the two virtual data traces are not the same. The more the number of contact windows 42 is, the higher the virtual data connection 40 and the second and the 34 ❸ electrical connection strength. The virtual data trace 40 of the present invention. The number of contact windows 42 is not closed, and the surface is different according to f. A partially enlarged cross-sectional view of the contact 4 |^| = includes a dielectric layer 52, a dielectric layer 52, and an electrical body on the substrate. In the present embodiment, the dielectric layer 52 is composed of a gate insulating layer. And 201037444 • Guaranteed $ layer composition. a dielectric layer 52 envelops the dummy data trace 40, a contact window 42 is formed on the dielectric layer 52, and a halogen electrode 34 is disposed on the dielectric layer & The virtual data Wei 4 () is touched to connect with Lai. The germanium electrode 34 is located on the dielectric layer 52. When it is required to test, it can be connected to the dummy data trace 4 through the pixel electrode 34 and the contact window 42. Referring to FIG. 4 together, when a dielectric layer 52 in the thin film transistor substrate 50 has a defect 46 between the first scan line 24 and the common electrode trace 38, a voltage is input. When the voltage lion 4 electrode 34 is connected to the dummy data trace 4G and generates a capacitor 48 with the defect 46, the position of the capacitor 48 is the position of the defect 46. By means of the method, the layout structure of the germanium defect Y detection rate of the improved thin film transistor substrate of the present invention can effectively and quickly locate the short-circuit position of the GCsh〇rt, effectively solving the problem in the prior art that must be sought by the human eye. Troubled, can effectively save labor costs. The above is only the preferred embodiment of the present invention and is not intended to limit the implementation of the present invention. Therefore, all changes or modifications to the scales of the invention, such as Wei Lin's miscellaneous, structural, characteristic and spiritual, should be included in the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a layout structure of a defect detection rate of a thin film transistor substrate according to an embodiment of the present invention. ® Figure 2 is a partially enlarged schematic view of an embodiment of the invention. Fig. 3 is a layout structure of the halogen defect side rate of the lifted film transistor substrate of the present invention. Figure 4 is a partially enlarged schematic view of another embodiment of the present invention. [Main component symbol description] 22 first data line 24 first scan line 26 thin film transistor 28 gate 7 201037444 30 source 32 drain 34 halogen electrode 36 storage capacitor 38 common electrode trace 40 virtual data trace 42 contact Window 44 amorphous germanium layer 46 defect 48 capacitor 50 thin film transistor glass substrate 52 dielectric layer