TW201034154A - Integrated circuit micro-module - Google Patents

Integrated circuit micro-module Download PDF

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Publication number
TW201034154A
TW201034154A TW098144884A TW98144884A TW201034154A TW 201034154 A TW201034154 A TW 201034154A TW 098144884 A TW098144884 A TW 098144884A TW 98144884 A TW98144884 A TW 98144884A TW 201034154 A TW201034154 A TW 201034154A
Authority
TW
Taiwan
Prior art keywords
integrated circuit
layer
package
heat
layers
Prior art date
Application number
TW098144884A
Other languages
Chinese (zh)
Other versions
TWI423414B (en
Inventor
Peter Smeys
Peter Johnson
Peter Deane
Reda R Razouk
Original Assignee
Nat Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/390,349 external-priority patent/US7843056B2/en
Priority claimed from US12/479,709 external-priority patent/US7898068B2/en
Priority claimed from US12/643,924 external-priority patent/US7902661B2/en
Application filed by Nat Semiconductor Corp filed Critical Nat Semiconductor Corp
Publication of TW201034154A publication Critical patent/TW201034154A/en
Application granted granted Critical
Publication of TWI423414B publication Critical patent/TWI423414B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Abstract

Various apparatus and methods for improving the dissipation of heat from integrated circuit micro-modules are described. One aspect of the invention pertains to an integrated circuit package with one or more thermal pipes. In this aspect, the integrated circuit package includes multiple layers of a cured, planarizing dielectric. An electrical device is embedded within at least one of the dielectric layers. At least one electrically conductive interconnect layer is embedded within one or more of the dielectric layers. A thermal pipe made of a thermally conductive material is embedded in at least one associated dielectric layer. The thermal pipe thermally couples the electrical device with one or more external surfaces of the integrated circuit package. Various methods for forming the integrated circuit package are described.

Description

201034154 ^ 六、發明說明： 【發明所屬之技術領域】 本發明大體上關於積體電路（Integrated circuit，1C ) 的封裝。更明確地說，本發明是關於積體電路微模組。 【先前技術】 有數種習知的方法用以封裝積體電路（IC )晶粒。某 些封裝技術會創造電子模組用以將多個電子裝置（舉例來 說’積體電路；被動式器件，例如：電感胃、電容器、電 阻盗或是鐵磁材料；…等）併入單一封裝之中。併入一個以 上積體電路晶粒的封裝通常會被稱為多晶片模組。某些多 晶片模組包含—基板或内插板（interposer)以支撐各種器 件；而其它多晶片模組則是利用導線框架、模具或是其它 結構來支撑各種其它封裝器件。 已經有人找出數種多晶片模組封裝技術，舉例來說， 用以利用多個層疊膜或多重堆疊晶片载板將多個互連層整 ❹合成該封裝。雖然用於封裝電子模组的既有排列與方法並 無不妥，不過，仍得繼續努力發展出改良的封裝技術，用 以提供省錢的方式，以便滿足各式各樣不同封裝應用的需 求。 【發明内容】 本發明說明用於改良積 備及方法。本發明的其中一 條導熱管的積體電路封裝。 襄包含多層已固化、平坦化 體電路微模組之散熱的各種設 項觀點是關於一種具有一或多 於此項觀點中’該積體電路封 的介電質。一電氣裝置埋置該 5 201034154 等介電層中的至少其中一者裡面。至少一導電互連層埋置 在該等介電層中的一或多者裡面。一由導熱材料製成的導 熱管埋置在至少一相關聯的介電層裡面。該導熱管熱耦接 該電氣裝置及該積體電路封裝的一或多個外部表面。 在本發明的各種實施例中’該導熱管能夠彎折、分又 及/或延伸在實質不同的方向中。可能會有多條導熱管。特 殊的實施例包含一導熱管，其會排列成用以傳送熱量而不 會傳送電氣資料訊號。該導熱管能夠將該電氣裝置熱耦接 至一或多個散熱片。 本發明的另一實施例是關於一種用於形成具有一或多 條導熱管之積體電路封裝的方法。由一環氧樹脂所製成的 多層會依序被儿積在一基板的上方。至少某些該等環氧樹 脂層會被光微影圖樣化。一電氣裝置擺放在一或多個相關 聯的環氧樹脂層的上方。一導電互連層及一導熱管形成在 一或多個相關聯的環氧樹脂層的上方。該互連層與該導熱 管實質上能夠同時被形成。 【實施方式】 於其中一項觀點中’本發明大體上關於積體電路（IC) 封裝且更明確地說，本發明是關於IC微模組技術。此項觀 點包含由一介電質（其較佳的是可光成像且很容易平坦化） 所製成的多層所構成的微模組。該微模組可能含有各式各 樣的器件，其包含一或多個積體電路、互連層、散熱片、 導體通道、被動式裝置、MEMS裝置、感測器、導熱管' 等。該等各種器件可以各式各樣不同的方式被排列且堆疊 201034154 在該微模組裡面。可以利用各種習知的晶圓層級處理技術 來沉積與處理該微模組的該等層與器件，例如：旋塗技術、 喷塗技術、微影術及/或電鍍技術。本發明的另一項觀點是 關於將多個主動式及/或被動式器件整合成單一、低成本、 高效能封裝的晶圓層級製造技術與結構。 圖1所示的疋根據本發明一實施例的封裝。於圖中所 示的實施例中，-多層式封裝100包含：_基板1〇2、一散 熱片104、複數個堆疊介電質層1〇6、積體電路ιΐ4、被動 式器件（圖中並未顯示）、互連層122、通道125以及外部 接觸觸墊120。散熱片104會被形成在基板.1〇2的上方，而 該等介電質層106則會被堆疊在該散熱片的頂端。必要時， 多個互連層會***設在相鄰的介電質層1〇6之間。該等積 體電路會被埋置在一堆疊的介電質層1〇6裡面，而且可能 會藉由該等互連層122與通冑125之中合宜的線路被電氣 連接至其它器件，舉例來說，其它IC、被動式器件、外部 ❿接觸觸整120、…等。於圖中所示的實施例中，該等積體電 路中的其中一者（114a)會有效地被安置在該散熱片1〇4 之上’以便提供良好的散熱效果。 該等介電質層106可以由任何合宜的介電材料製成。 於各種較佳的實施例中，該等介電質層1〇6是由很容易平 坦化及/或可光成像的材料所製成。於一特殊的較佳實施例 中，該等層是由可光成像、平坦化的su_8所製成，不過， 亦可以使用其它合宜的材料。於某些設計中，用於層1〇6 的介電質在剛被塗敷時的黏稠性很高，接著便會在光微影 201034154 製程期間被分或完全固化。可以利用各式各樣合宜的技 術來塗敷該等層1G6’其包含旋塗技術與噴塗技術。該等各 個介電質層的厚度可以依照特殊應用的需求而廣泛地改 而且不同的層不需要具有相同的厚度（不過，它們亦 可能具有相同的厚度）。 封裝100裡面的積體電路114可以各式各樣的方式來 t J並且可以被擺放在該封裝裡面的幾乎任何位置處。舉 例來說’不同的積體電路114可以被設置在基板102之中、 不同的可光成像層之中及/或相同的層裡面。於各種實施例 中-亥等積體電路114可以被堆叠、並排設置、彼此緊密 相鄰擺放及/或分隔以封裝1〇〇之整體大小為基準的一實質 :離。被設置在不同層之中的積體電路可以直接或部分被 没置在彼此的上方，或|，它們可能會分開俾使它們彼此 不會叠置。積體料m亦可能具有各式各樣不同的形狀 因數、架構以及配置。舉例來說，它們可能會有相對裸晶 粒的形式（舉例來說’未封裂晶粒、覆晶、…等），部分及 /或完全封裝晶粒的形式（舉例來說，BGA、lGa、 … 專）。 封裝HH)裡面的電性互連線同樣可林式各樣不同的 方式來排列。® 1中所示的實施例包含兩個互連（線路） 層122。在不同的施行方式中可能會有更多或較少的互連 層。每-個互連層通常會有至少_條（但是，@常會有許 多條）線路123,它們會被用來在該封裝的不同器件之間幫 助傳送電訊號。該等互連層122通常會被形成在該等 201034154 埋相關聯層的頂端。接著，該線路層會被 =被另—介電質層覆蓋，，該等互連層通常會延 :在：行於該等介電質層且被埋置在該等介電質層裡面的 平面中。 ，、因為該等互連層（以及該封裝的其它可能器件）會被 心成在；|電質層的頂端’所以’會希望該等介電質層106 具有非*平坦且堅硬的表面而可於其上形成其它器件（舉 ❹例來說，線路、被動式器件、·.等）或是可以安置離散器件 (舉例來說’ 1C) 。SU-8特別適用於此應用，因為當利用 習知的旋轉技術與旋塗技術來塗敷時其可輕易地自動平坦 化，而且在被固化之後其會非常的堅硬。更確切地說，經 旋轉的SU-8可以在利用習知的濺鍍技術/電鍍技術於其上 形成高品質的互連層之前被用來形成一堅硬的平坦表面而 ί不需要任何額外的平坦化作用（舉例來說，化學機械研 磨）。可依此方式被塗敷而形成一非常平坦表面的介電材 料在本文中稱為平坦化介電質。 導電通道125會被提供用以電氣連接駐存在該封裝的 不同層處的器件（舉例來說，IC/線路/端子/被動式器件… 等）。該等通道125會被排列成延伸穿過一相關聯的介電 質層106。舉例來說，該等通道125可被用來將來自兩個不 同互連層的線路耦接在一起，將一晶粒或另一器件耦接至 一互連層，將一端子耦接至一線路、晶粒或是其它器件… 等。如下文的更詳細說明’多個金屬化通道可以同時形成’ 因此藉由填充先前已形成在.一相關聯介電質層106之中的 201034154 通道開口便可沉積_相關聯的互連.層ι22。 封裝 可成包含圖1中所示者以外的許多其它類型 置在圖中所示的實施例中，僅顯示數個積體電路和互 連層$㉟封裝100可能還含有幾乎任何數量的主動式 及/或被動式Ί此等主動式及/或被動式裝置的範例包含 電阻器、電容器、磁核心、MEMS裝置、感測器、電池（舉 例來說，囊封鋰電池或其它電池）、積體薄膜電池結構、 電感器、…等。該些襞置可以被設置及/或被堆疊在封裝ι〇〇 裡面的各個位置中。該等器件可能具有事先製造之離散器 件的形式或者可以於現場被形成。用於創造封裝1〇〇之以 微影術為基礎的製程的其中一項優點是可以在分層形成該 封裝期間於現場形成該些與其它器件。也就是，當被事先 製造之後，離散器件幾乎可被擺放在封裝1〇〇裡面的任何 位置，器件還可以利用任何合宜的技術（例如··習知的濺 鍍及/或電鍍）被直接製造在任何的可光成像層1〇6之上。 由於此製程特性的關係，可以達成較優的匹配效果、精確 性以及控制作用，而且可以在各種晶粒及/或基板尺寸（其 包含中型與大型晶粒及/或基板）上達成低應力封裝的效果。 基板102可能是由任何合宜的材料所製成，其包含： 矽、玻璃、鋼、石英、G10-FR4、任何其它FR4家族環氧樹 知、…4 51端視特殊應用的需求而定，該基板可能為導電性、 電絕緣性及/或透光性。於某些實施例中，該基板僅是於製 造期間作為一載板並且因而會在該封裝完成之前被移除。 於其它實施例中，該基板會保留為該封裝的一體成型部 201034154 件。倘若需要的話，·該基板1〇2還可藉由背面研磨技術或 其它合宜的技術於組裝之後進行薄化。又，於其它實施例 中’可能會完全省略該基板。 於某些實施例中，該基板丨〇2可能會整合一或多個感 測器（圖中並未顯示）。此方式可達成整合感測器器件的 目的’而不必進行封裝且不會有通常和要曝露於環境中的 感測器的必要條件相關聯的可靠度問題。感測器可被安置 在基板102的任一側而且可經由被蝕刻的視窗或微管道而 © 被埋置或曝露於環境中。合宜感測器的範例包含，但是並 不受限於：生物感測器、氣體感測器、化學藥劑感測器、 電磁感測器、加速感測器、震動感測器、溫度感測器、濕 度感測器、…等。 其中一種方式是將一感測元件整合至基板I 〇2的背 面。該感測元件可被建立在該基板1 〇2之中一已經從該基 板102的背面被蝕除的深腔穴的内部。舉例來說，該感測 Ο 元件可能是一由多個電鍍Cu指狀物所製成的電容器。該電 . 各器可經由微通道來與該基板102正面的接.觸觸墊相連。 封裝100可被形成在該些接觸觸墊的上方，俾使該電容器 會與封裝100裡面的電裝置及互連層中的至少一部分電氣 耦接。在晶圓背面所產生的腔穴内部的感測元件可能會填 充著氣敏材料並且可能會自動曝露於環境中，而基板1〇2 正面的主動式電路系統則可以利用習知的囊封技術（例 如：下面配合圖5E所討論者）來保護。 封裝100還包含一用於消散内部產生之熱量的系統， 11 201034154201034154 ^ VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention generally relates to the packaging of an integrated circuit (1C). More specifically, the present invention relates to an integrated circuit micromodule. [Prior Art] There are several conventional methods for packaging integrated circuit (IC) dies. Some packaging technologies create electronic modules for incorporating multiple electronic devices (eg, 'integrated circuits; passive devices such as inductive stomachs, capacitors, resistance thieves, or ferromagnetic materials; etc.) into a single package. Among them. A package incorporating more than one integrated circuit die is often referred to as a multi-wafer module. Some multi-chip modules include a substrate or interposer to support various devices; while other multi-chip modules utilize wireframes, dies or other structures to support various other packaged devices. Several multi-wafer module packaging techniques have been identified, for example, to multiplex a plurality of interconnect layers into a package using a plurality of stacked films or multiple stacked wafer carriers. Although there is nothing wrong with the existing arrangement and method for packaging electronic modules, efforts must continue to develop improved packaging techniques to provide a cost-effective way to meet the needs of a wide variety of packaging applications. . SUMMARY OF THE INVENTION The present invention is described for improved preparation and methods. An integrated circuit package of one of the heat pipes of the present invention. The various aspects of the design including the heat dissipation of the multilayer cured, planarized circuit micro-module are related to a dielectric having one or more of the integrated circuit packages. An electrical device embeds at least one of the dielectric layers such as 5 201034154. At least one electrically conductive interconnect layer is embedded in one or more of the dielectric layers. A heat transfer tube made of a thermally conductive material is embedded in at least one associated dielectric layer. The heat pipe is thermally coupled to the electrical device and one or more exterior surfaces of the integrated circuit package. In various embodiments of the invention, the heat pipe can be bent, divided and/or extended in substantially different directions. There may be multiple heat pipes. A particular embodiment includes a heat pipe that is arranged to transfer heat without transmitting electrical data signals. The heat pipe is capable of thermally coupling the electrical device to one or more heat sinks. Another embodiment of the invention is directed to a method for forming an integrated circuit package having one or more heat pipes. A plurality of layers made of an epoxy resin are sequentially stacked on top of a substrate. At least some of these epoxy layers are patterned by light lithography. An electrical device is placed over one or more associated epoxy layers. A conductive interconnect layer and a heat transfer tube are formed over the one or more associated epoxy layers. The interconnect layer and the heat pipe can be formed substantially simultaneously. [Embodiment] In one of the views, the present invention relates generally to integrated circuit (IC) packaging and more specifically to the IC micromodule technology. This view includes a micromodule composed of a plurality of layers made of a dielectric material, which is preferably photoimageable and easily planarized. The micromodule may contain a wide variety of devices including one or more integrated circuits, interconnect layers, heat sinks, conductor vias, passive devices, MEMS devices, sensors, heat pipes', and the like. The various devices can be arranged in a variety of different ways and stacked in 201034154 within the micromodule. The various layers and devices of the micromodule can be deposited and processed using various conventional wafer level processing techniques, such as spin coating techniques, spray coating techniques, lithography, and/or electroplating techniques. Another aspect of the present invention is directed to wafer level fabrication techniques and structures that integrate multiple active and/or passive devices into a single, low cost, high performance package. A package according to an embodiment of the invention is shown in FIG. In the embodiment shown in the figures, the multi-layer package 100 comprises: a substrate 1 〇 2, a heat sink 104, a plurality of stacked dielectric layers 〇6, an integrated circuit ΐ4, and a passive device (in the figure Not shown), interconnect layer 122, via 125, and external contact pads 120. The heat sink 104 will be formed over the substrate .1〇2, and the dielectric layers 106 will be stacked on top of the heat sink. If necessary, a plurality of interconnect layers are interposed between adjacent dielectric layers 1〇6. The integrated circuits are buried in a stacked dielectric layer 1 〇 6 and may be electrically connected to other devices by suitable interconnections of the interconnect layer 122 and the via 125. In other words, other ICs, passive devices, external contact contacts, 120, etc. In the embodiment shown in the figures, one of the integrated circuits (114a) is effectively placed over the heat sink 1〇4 to provide good heat dissipation. The dielectric layers 106 can be made of any suitable dielectric material. In various preferred embodiments, the dielectric layers 1 〇 6 are made of a material that is easily planarized and/or photoimageable. In a particularly preferred embodiment, the layers are made of photoimageable, planarized su_8, although other suitable materials may be used. In some designs, the dielectric used for layer 1〇6 is very viscous when it is just coated, and then is partially or fully cured during the photolithography 201034154 process. The layers 1G6' can be applied using a variety of suitable techniques including spin coating techniques and spray coating techniques. The thickness of the various dielectric layers can vary widely depending on the needs of the particular application and the different layers need not be of the same thickness (although they may also have the same thickness). The integrated circuit 114 within the package 100 can be placed in a variety of ways and can be placed at almost any location within the package. For example, a different integrated circuit 114 can be disposed in the substrate 102, in different photoimageable layers, and/or in the same layer. In various embodiments, the integrated circuits 114 can be stacked, placed side by side, placed closely adjacent each other, and/or separated by a substantial basis based on the overall size of the package. The integrated circuits disposed in the different layers may be placed directly or partially above each other, or |, they may be separated so that they do not overlap each other. The bulk material m may also have a variety of different form factors, configurations, and configurations. For example, they may be in the form of relatively bare grains (for example, 'unsealed grains, flip-chips, etc.), partially and/or completely encapsulated in the form of grains (for example, BGA, lGa) , ... special). The electrical interconnects in the package HH can also be arranged in different ways. The embodiment shown in ® 1 includes two interconnect (line) layers 122. There may be more or fewer interconnect layers in different implementations. Each interconnect layer will typically have at least _ (but, @ often there are) lines 123 that will be used to help transmit electrical signals between different devices in the package. The interconnect layers 122 will typically be formed at the top of the 201034154 buried associated layer. Then, the circuit layer is covered by another dielectric layer, and the interconnect layers are generally extended: in the dielectric layers and embedded in the dielectric layers In the plane. , because the interconnect layers (and other possible devices of the package) will be cored; the top of the dielectric layer 'so' would hope that the dielectric layers 106 have a non-flat and hard surface. Other devices can be formed thereon (for example, lines, passive devices, etc.) or discrete devices can be placed (for example, '1C). SU-8 is particularly suitable for this application because it can be easily automatically planarized when applied by conventional spin technology and spin coating techniques, and it will be very stiff after being cured. More specifically, the rotated SU-8 can be used to form a hard, flat surface prior to forming a high quality interconnect layer thereon using conventional sputtering/electroplating techniques without any additional Flattening (for example, chemical mechanical polishing). A dielectric material that can be coated in this manner to form a very flat surface is referred to herein as a planarizing dielectric. Conductive vias 125 are provided to electrically connect devices resident at different layers of the package (e.g., IC/line/terminal/passive device, etc.). The channels 125 are arranged to extend through an associated dielectric layer 106. For example, the channels 125 can be used to couple lines from two different interconnect layers together, couple a die or another device to an interconnect layer, and couple a terminal to a Lines, dies or other devices...etc. As described in more detail below, 'multiple metallization channels can be formed simultaneously', thus depositing an associated interconnect layer by filling the 201034154 channel opening previously formed in an associated dielectric layer 106. Ip22. The package may be in many other forms than those shown in Figure 1. In the embodiment shown in the figures, only a few integrated circuits and interconnect layers $35 package 100 may also contain almost any number of active And/or passive examples of such active and/or passive devices include resistors, capacitors, magnetic cores, MEMS devices, sensors, batteries (for example, encapsulated lithium batteries or other batteries), integrated films Battery structure, inductors, etc. The devices can be arranged and/or stacked in various locations within the package. These devices may be in the form of discrete devices fabricated in advance or may be formed in the field. One of the advantages of the lithography-based process for creating packages is that these and other devices can be formed in the field during the layered formation of the package. That is, discrete devices can be placed almost anywhere in the package after being fabricated in advance, and the device can be directly applied using any suitable technique (eg, conventional sputtering and/or plating). It is fabricated on any photoimageable layer 1〇6. Due to this process characteristics, superior matching, accuracy, and control can be achieved, and low stress packages can be achieved on a variety of die and/or substrate sizes, including medium and large die and/or substrates. Effect. The substrate 102 may be made of any suitable material, including: germanium, glass, steel, quartz, G10-FR4, any other FR4 family of epoxy trees, ... 4 51 depending on the needs of the particular application, The substrate may be electrically conductive, electrically insulating, and/or light transmissive. In some embodiments, the substrate is only used as a carrier during fabrication and thus will be removed prior to completion of the package. In other embodiments, the substrate will remain as an integral part of the package 201034154. If desired, the substrate 1 2 can also be thinned after assembly by back grinding techniques or other suitable techniques. Again, in other embodiments, the substrate may be omitted altogether. In some embodiments, the substrate 丨〇 2 may incorporate one or more sensors (not shown). This approach can achieve the goal of integrating sensor devices without having to package and without the reliability issues typically associated with the necessary conditions of the sensor to be exposed to the environment. The sensor can be placed on either side of the substrate 102 and can be embedded or exposed to the environment via an etched window or microchannel. Examples of suitable sensors include, but are not limited to, biosensors, gas sensors, chemical sensors, electromagnetic sensors, acceleration sensors, vibration sensors, temperature sensors , humidity sensor, ..., etc. One such way is to integrate a sensing element onto the back side of the substrate I 〇 2 . The sensing element can be built into the interior of the deep cavity of the substrate 1 〇 2 that has been etched away from the back side of the substrate 102. For example, the sense Ο element may be a capacitor made of a plurality of plated Cu fingers. The device can be connected to the contact pad on the front side of the substrate 102 via a microchannel. A package 100 can be formed over the contact pads such that the capacitor is electrically coupled to at least a portion of the electrical devices and interconnect layers within the package 100. The sensing elements inside the cavity created on the back side of the wafer may be filled with gas sensitive material and may be automatically exposed to the environment, while the active circuitry on the front side of the substrate 1〇2 may utilize conventional encapsulation techniques. (For example: as discussed below in conjunction with Figure 5E) to protect. The package 100 also includes a system for dissipating internally generated heat, 11 201034154

其可能包含導熱管與散熱片’例如：散熱片1〇4。此系統在 封裝100的效能上可能會扮演很重要的角色，因為具有高 電力密度和多個埋置裝置的封裝可能會需要有良好的散熱 效果方能正常運作。該等導熱管與散熱片通常會與互連層 12以至i22b實質同時並且利用相同的技術來形成。此等導 熱管能夠穿過及/或迁迴通過一或多個互連層及/或可光成 像層。任何單―、連續的導熱管、線路及/或通道皆能夠在 幾乎任何位置點處岔開伸入多個其它線路及/或通道之中並 且能夠延伸在該封裝裡面一個以上的方向中，例如：橫向 及/或垂直。該等導熱管實際上能夠讓封裝1〇〇裡面的任； 裝置熱搞接位於該封裝⑽外部的__或多個散熱觸塾及/或 •…，不僻。隹圚中所示 實施例中，散熱片ΠΗ會構成—涵蓋範圍實質上匹配於 裝1〇〇之可光成像層的涵蓋範圍的層。或者，封裝⑽ 能包含-或多個散熱片’它們的維度至少部分匹配於上It may include a heat pipe and a heat sink' such as a heat sink 1〇4. This system may play an important role in the performance of package 100, as packages with high power density and multiple buried devices may require good heat dissipation for proper operation. The heat pipes and fins are typically formed substantially simultaneously with interconnect layer 12 and i22b and using the same techniques. The heat transfer tubes are capable of passing through and/or relocating through one or more interconnect layers and/or photoimageable layers. Any single, continuous heat pipe, line, and/or channel can be split into a plurality of other lines and/or channels at almost any point of the location and can extend in more than one direction of the package, such as : Horizontal and / or vertical. The heat pipes can actually allow any of the components in the package to be thermally connected to the outside of the package (10) or a plurality of heat-dissipating contacts and/or .... In the embodiment shown in the drawings, the heat sink ΠΗ will constitute a layer that covers a range substantially matching the coverage of the photoimageable layer. Alternatively, the package (10) can contain - or multiple heat sinks' their dimensions at least partially matched to

或下：主動式裝置（例如：積體電路）的維度。在圖中 示的實施例中，散熱片可能具有形成在該基板 薄板1〇4的形式並且會形成介電質層1〇6的基底。奶： 要的話，積體電路114可以直 倘右 上，如積體電路114(a)所示。 …片層 ^ m i B 次者’可以使用導敎 道（圖中並未顯示）來改良_埋置積7 間的熱路徑，如積體電路 、〜散“、、片 中，該（箄）埤無 Cb)所不。於某些實施 中/ )散熱片或散熱片層會#霞/eh 會稞露纟该封褒的頂端 12 201034154 面或底部表面。於其它實施例中，一基板或其它層可能會 覆蓋該（等）散熱片或散熱片層，俾使該等散熱片充當熱 分散板。該（等）散熱片104可能是由各式各樣合宜的導 體材料（例如：銅）所製成而且可以和互連層相同的方式 來構成。 封裝100的各種實施例可能還會併入各式各樣的其它 特點《舉例來說，封裝100可能會併入高電壓（High Voltage，HV )隔離以及埋置的感應式賈凡尼功能（galvanic capability)。其特點可能是具有無線介面，舉例來說，無 線系統IO的RF天線、EM電力收集（Em肿舊 scavenging) 、EMI敏感性應用的RF屏蔽、等。於各種 實施例中，封裝100可能包含電力管理子系統，舉例來說， 超級充電器（supercharger)、積體式光伏特開關、…等。 :封裝100可以被形成在一晶圓之上並且被囊封，舉例來說， 如圖5E中所不。感測表面與材料可被整合至封裝1 〇〇以及 ❹ 如上面且配合圖CTTx/TA yr yr Tt 圃从至5H、6A至6C及7A至7C所討論的 晶圓的其它處理步驟之中。 接著，將參考圖2來說明根據本發明一實施例，用於 形成積體電路封裝_的晶圓層級方法方法2〇〇的步 驟圖解在® 3Aj_3L之中。方法2⑽的步驟可 及/或以和圖中所千τ门u A 7 所不不同的順序來實施。應該注意 法200中所示的劁兹叮、丨m Α J疋石 程可以用來同時構成圖3A至 中 者以外的許多其它結構。 儿中所不 一開始’在圖2的步驟202中’會利用任何各式各樣 13 201034154 ' i 合宜的技術在基板1〇2的上方形成圖3A的一非必要導體層 104。舉例來說，於濺鍍一晶種層之後進行習知的電鍍便非 常適用。當然’亦可以利用其它合宜的導體層形成技術。 導體層104是充當散熱片並且可以由各種材料製成，例如： 銅或是其它適當的金屬或金屬層堆疊。基板1〇2可能是一 晶圓並且可以由各式各樣合宜的材料製成，例如：矽、 G10-FR4、鋼、玻璃、塑膠 '…等。 在圖3B中，會在該散熱片1〇4的上方沉積一層平坦 化、可光成像的環氧樹脂106 (圖2的步驟2〇4)。這可以 利用各式各樣的技術來完成，例如：旋塗喷塗或片式層 疊（sheet lamination)。在圖中所示的實施例中，環氧樹脂 層106a是SU-8，不過，亦可以使用其它適當的介電材料。 SU-8非常適用於利用習知旋轉塗佈技術的應用。 SU-8有各種優越的特性。其是—高黏稠性、可光成像、 具有化學惰性的聚合物，舉例來說，其能夠在光微影製程 期間曝露於uv輻射時被固化^ su_8會提供大於某些其它 已知光阻的機械強度，可抵抗過度研磨作用，而且在高達 至少300 C的溫度處具有機械性穩定與熱穩定。相對於特定 其它可光成像的材料（例如：BCB〉，其可利用旋塗法彳艮容 易且均勻地平坦化，這使其可輕易地作為一可於其上製造 互連線或疋被動式器件的基底，並且可於其上安置積體電 路或疋其匕被動式器件。其可輕易地被用來創造厚度範園 為1微米至250微米的介電質層，而且可以製造出更薄或 更厚的層。於特殊的實施例中，多個具有大寬高比（舉例 201034154 來說，約5:1或更大）的開口可以被形成在Su_8之中，其 有助於形成具有大寬高比的器件，例如：導體性通道或其 它結構。舉例來說，可以輕易地達成7: i的寬高比。相較於 許多其它材料，利用SU-8層能夠達成更優的控制作用、精 確性以及匹配效果，其能夠造成更高的密度與改良的效 月色。亦可以使用具有上面特徵中一或多者的其它合宜介電 材料來取代SU-8。 在圖2的步驟206中，會利用習知的光微影技術來圖 〇 樣化環氧樹脂層106a。於其中·實施.例中，會使用一光罩 來選擇性地曝光該環氧樹脂層106a中的多個部分。曝光之 後會進行烘烤作業。該些作業能夠讓該環氧樹脂層1〇6a中 已曝光的部分產生交聯。於該光微影製程期間，環氧樹脂 層106a中已曝光的部分可能會被固化、部分被固化（舉例 來說’B階）、或者會相對於未被曝光的部分被改質或硬化， 以幫助稍後移除該環氧樹脂中未被曝光的部分。 ❹ 在圖2與圖3C的步驟208中，該環氧樹脂層i〇6a中 未被曝光的部分會被移除以便在該環氧樹脂層1〇6a中形成 一或多個開口 306。此移除製程可以各式各樣的方式來實 施。舉例來說，可以在一顯影劑溶液中顯影該環氧樹脂層 l〇6a，從而導致該層i〇6a中未被曝光的部分溶解。於進行 顯影作業之後，可能會實施硬烘烤。 在圖2與圖3D的步驟210中，一積體電路n4a會被 擺放在開口 306之中並且被安置在散熱片104之上。該積 體電路114a可以各式各樣的方式來配置。舉例來說，該積 15 201034154 體電路1 l4a可能是一裸晶粒或覆晶晶.粒或者其可能具 . 有BGA、LGA及/或其它合宜的外送接針配置。於圖中所示 的實施例中，積體電路114a的厚度會大於其在一開始被埋 置於其中的環氧樹脂層106a的厚度；不過，於其它實施例 中，該晶粒亦可能和其在一開始被埋置於其中的環氧樹脂 層具有實質上相同或較薄的厚度。積體電路114&的主動面 可以面向上或面向下。於特殊的實施例中，該積體電路n4a 可以利用黏著劑被貼附且被熱耦接至散熱片1〇4。Or lower: The dimensions of active devices (eg, integrated circuits). In the embodiment shown in the drawings, the heat sink may have a substrate formed in the form of the substrate sheet 1 〇 4 and which will form the dielectric layer 1 〇 6. Milk: If desired, the integrated circuit 114 can be straight up, as shown by integrated circuit 114(a). ... slice ^ mi B second' can use the guide channel (not shown) to improve the thermal path between the buried product 7, such as the integrated circuit, ~ scattered ",, in the film, the (箄)埤 No Cb) No. In some implementations /) The heat sink or heat sink layer will #霞/eh will reveal the top surface of the package 12 201034154 face or bottom surface. In other embodiments, a substrate or Other layers may cover the heat sink or heat sink layer such that the heat sink acts as a heat spreader. The heat sink 104 may be of a variety of suitable conductor materials (eg, copper). It is made and can be constructed in the same manner as the interconnect layer. Various embodiments of package 100 may also incorporate a variety of other features. For example, package 100 may incorporate high voltage (High Voltage, HV) Isolated and embedded inductive galvanic capability, which may be characterized by a wireless interface, for example, RF antenna for wireless system IO, EM power collection (Em swageging), EMI sensitivity Applied RF shielding, etc. in various embodiments The package 100 may include a power management subsystem, for example, a supercharger, an integrated photovoltaic switch, etc.: The package 100 may be formed over a wafer and encapsulated, for example Said, as shown in Figure 5E. The sensing surface and material can be integrated into the package 1 and as discussed above and in conjunction with the figure CTTx/TA yr yr Tt 圃 from 5H, 6A to 6C and 7A to 7C Among other processing steps of the wafer. Next, a description will be given of a step of the wafer level method method 2 for forming an integrated circuit package according to an embodiment of the present invention with reference to FIG. 2 in the ® 3Aj_3L. The steps of method 2 (10) can be implemented and/or performed in an order different from that of the thousands of gates u A 7 in the figure. It should be noted that the equations shown in the method 200 can be used simultaneously. Many other structures other than those shown in Fig. 3A are formed. In the beginning, 'in step 202 of Fig. 2', a pattern is formed above the substrate 1〇2 using any of the various techniques 13 201034154'i. A non-essential conductor layer 104 of 3A. For example, splashing It is well suited to carry out conventional plating after plating a seed layer. Of course, other suitable conductor layer forming techniques can also be utilized. The conductor layer 104 acts as a heat sink and can be made of various materials such as copper or other suitable The metal or metal layer is stacked. The substrate 1〇2 may be a wafer and may be made of a variety of suitable materials, such as: 矽, G10-FR4, steel, glass, plastic, etc. In Figure 3B A planarized, photoimageable epoxy 106 is deposited over the heat sink 1〇4 (steps 2〇4 of Figure 2). This can be done using a wide variety of techniques, such as spin coating or sheet lamination. In the embodiment shown in the figures, the epoxy layer 106a is SU-8, although other suitable dielectric materials may be used. SU-8 is ideal for applications that utilize conventional spin coating techniques. The SU-8 has a variety of superior features. It is a highly viscous, photoimageable, chemically inert polymer that, for example, can be cured when exposed to uv radiation during photolithography, and will provide greater than some other known photoresists. Mechanical strength, resistant to excessive grinding, and mechanically stable and thermally stable up to at least 300 C. Relative to certain other photoimageable materials (eg, BCB), which can be easily and uniformly planarized by spin coating, which makes it easy to fabricate interconnects or germanium passive devices thereon. a substrate on which an integrated circuit or a passive device can be placed. It can be easily used to create a dielectric layer having a thickness ranging from 1 micron to 250 microns, and can be made thinner or more Thick layers. In a particular embodiment, a plurality of openings having a large aspect ratio (about 5:1 or greater for example 201034154) can be formed in Su_8, which helps to form a large width High-ratio devices, such as conductive channels or other structures. For example, an aspect ratio of 7: i can be easily achieved. Compared to many other materials, the SU-8 layer can achieve better control. Accuracy and matching effects, which can result in higher density and improved moonlight color. Other suitable dielectric materials having one or more of the above features can be used in place of SU-8. In step 206 of FIG. Will use the light of the known The image technique is used to pattern the epoxy resin layer 106a. In the embodiment, a mask is used to selectively expose portions of the epoxy layer 106a. After the exposure, baking is performed. These operations enable cross-linking of the exposed portion of the epoxy layer 1〇6a. During the photolithography process, the exposed portion of the epoxy layer 106a may be cured and partially cured ( For example, 'B-stage', or may be modified or hardened relative to the portion that is not exposed to help remove portions of the epoxy that are not exposed later. 步骤 At step 208 of Figures 2 and 3C The unexposed portion of the epoxy layer i〇6a is removed to form one or more openings 306 in the epoxy layer 1〇6a. This removal process can be done in a variety of ways. For example, the epoxy resin layer 16a can be developed in a developer solution, thereby causing the unexposed portion of the layer i〇6a to be dissolved. After the development operation, hard baking may be performed. Bake. In step 210 of Figure 2 and Figure 3D, an integrase The path n4a will be placed in the opening 306 and placed over the heat sink 104. The integrated circuit 114a can be configured in a variety of ways. For example, the product 15 201034154 body circuit 1 l4a may be A bare die or flip chip. or it may have a BGA, LGA and/or other suitable external pin configuration. In the embodiment shown in the figures, the integrated circuit 114a will have a thickness greater than The thickness of the epoxy layer 106a that is initially embedded therein; however, in other embodiments, the die may be substantially identical to the epoxy layer in which it was initially embedded or Thinner thickness. The active surface of the integrated circuit 114& can face up or face down. In a particular embodiment, the integrated circuit n4a can be attached with an adhesive and thermally coupled to the heat sink 1〇4.

在積體電路114a已經被設置在開口 3〇6之中且被貼附 Q 至散熱片之後，一第二環氧樹月旨層l〇6b便會被塗敷在該積 體電路114a與該環氧樹脂層1〇6a的上方（圖2的步驟 2〇4) ’如圖3E中所示。和第一環氧樹脂層汪相同，可 以利用任何合宜的方&(例如：旋塗法）來沉積該第二環 氧樹月曰層106b。於圖中所示的實施例中，環氧樹脂層嶋 是位於積體電路114a和環氧樹脂層1〇以的正上方、與積體 電路114a和環氧樹脂層1〇6a緊密相鄰及/或直接接觸積體 電路114a和環氧樹脂層1〇6a;不過，亦可以採用其它排列。❹ 環氧樹脂層祕可能會完全或部分覆蓋積體電路u4a的主 動表面。 入—在環氧樹脂層l〇6b已經被塗敷之後，便可以利用任何 ^且的技術來對其進行圖樣化與顯影（步驟與)， 該等技術通常和用於圖樣化第一環氧樹脂層购為相同的 技術。於圖中所示的實施例令，多個通道開〇 3 12會被形 成在積體電路114a的上方，以便在積體電路心的主動表 16 201034154 所產生的結構如 面上露出I/O輝接觸# (圖中並未顯示） 圖3F中所示。 經形成任何適當的通道開口 3 12之後， %、匕 319便會被沉積在開σ 312和環氧樹脂層106b的上方種= 7二:戶 1:。晶種層319可能是由任何合宜的材料所製成 (其包含由多個依序塗敷的子層（舉例來說，Ti、Cu以及After the integrated circuit 114a has been disposed in the opening 3〇6 and attached Q to the heat sink, a second epoxy layer layer 6b is applied to the integrated circuit 114a and the The upper side of the epoxy resin layer 1〇6a (step 2〇4 of Fig. 2)' is as shown in Fig. 3E. As with the first epoxy layer, the second epoxy tree layer 106b can be deposited using any convenient square & (e.g., spin coating). In the embodiment shown in the figures, the epoxy layer is located directly above the integrated circuit 114a and the epoxy layer 1 , and is closely adjacent to the integrated circuit 114a and the epoxy layer 1〇6a. / or directly contact the integrated circuit 114a and the epoxy layer 1 〇 6a; however, other arrangements may also be employed.环氧树脂 The epoxy layer may completely or partially cover the active surface of the integrated circuit u4a. Into - after the epoxy layer l〇6b has been applied, it can be patterned and developed (steps) using any technique, which is usually used to pattern the first epoxy The resin layer was purchased as the same technology. In the embodiment shown in the figure, a plurality of channel openings 3 12 are formed over the integrated circuit 114a to expose I/O on the surface of the active circuit 16 201034154 of the integrated circuit core. Hui contact # (not shown in the figure) is shown in Figure 3F. After any suitable via opening 3 12 is formed, %, 319 319 will be deposited over the open σ 312 and the epoxy layer 106b = 7 2: Household 1: 1. The seed layer 319 may be made of any suitable material (which includes a plurality of sub-layers that are sequentially coated (for example, Ti, Cu, and

Ti)所組成的堆叠）並且可以利用各式各樣的製程來沉積（舉Ti) is composed of stacks and can be deposited using a variety of processes

例來說’#由在該等外露表面上濺鍵__薄的金屬層）。前 述方式的特點I，被濺鍍的晶種層會有塗佈所有外露表面 (其包含通道開口 312的側壁和底部）的傾向。晶種層319 的沉積亦可能僅限於該等外露表面的一部分。 在圖3H申，一光阻315會被塗敷在晶種層319的上方。 光阻315可能為正向或負向，其會覆蓋晶種層319並且填 充開口 3 12。在目31中，該光阻會被圖樣化且顯影，用以 形成會露出晶種層319的開放區域317。該等開放區域會被 圖樣化反映互連層的所希望的佈局，其包含任何所希望的 導體線路及熱管以及下方的環氧樹脂層1〇6(1))中所希望 的任何通道。於已經形成該等所希望的開放區域之後，該 晶種層中的外露部分接著便會被電鍍，以便形成所希望的 互連層結構。於某些實施例中，在進行電鍍之前會先蝕刻 該晶種層中的一部分（舉例來說，Ti)。於電鍍期間，一電 壓會被施加至晶種層3 19，用以幫助將一導體材料（例如： 銅）電鑛至該等開放區域317之中。在已經形成該互連層 之後’該場域中的光阻3 15和晶種層3 19接著便會被剝除。 17 201034154 因此，互連層122a會被形成在瓖氧樹脂層1〇6b的上 方’如圖3J中所示（步驟212)。前面所述之用以利用金 屬來填充該通道開口的電鍵作業從而便會在該等通道開口 以前所界定的空間中形成金屬通道313。該等金屬通道313 可以被排列成用以電氣耦接積體電路U4a的1/〇觸墊及互 連層122a的對應線路316。因為晶種層319已經被沉積在 開口 3 12的側壁和底部兩者之上，所以，該導體材料實質 上會同時累積在該等側壁和該等底部之上，從而導致開口 312的填充速度會快過該晶種層僅被塗佈在開口 312的底部 ^For example, '# is made of a thin metal layer on the exposed surface. In the feature of the foregoing mode I, the sputtered seed layer has a tendency to coat all exposed surfaces (which include the sidewalls and bottom of the passage opening 312). The deposition of the seed layer 319 may also be limited to only a portion of the exposed surfaces. In FIG. 3H, a photoresist 315 is applied over the seed layer 319. The photoresist 315 may be either positive or negative, which will cover the seed layer 319 and fill the opening 3 12 . In item 31, the photoresist is patterned and developed to form an open region 317 where the seed layer 319 is exposed. These open areas will be patterned to reflect the desired layout of the interconnect layers, including any desired conductor tracks and heat pipes, as well as any desired channels in the underlying epoxy layer 1〇6(1)). After the desired open areas have been formed, the exposed portions of the seed layer are then electroplated to form the desired interconnect layer structure. In some embodiments, a portion of the seed layer (e.g., Ti) is etched prior to electroplating. During electroplating, a voltage is applied to the seed layer 3 19 to help electromineralize a conductor material (e.g., copper) into the open regions 317. After the interconnect layer has been formed, the photoresist 3 15 and the seed layer 3 19 in the field are subsequently stripped. 17 201034154 Therefore, the interconnect layer 122a will be formed above the epoxy resin layer 1〇6b as shown in Fig. 3J (step 212). The previously described keying operations for filling the opening of the passage with metal thereby form a metal passage 313 in the space defined before the opening of the passage. The metal vias 313 can be arranged to electrically couple the 1/〇 pads of the integrated circuit U4a and the corresponding lines 316 of the interconnect layer 122a. Since the seed layer 319 has been deposited on both the sidewalls and the bottom of the opening 312, the conductor material will accumulate substantially simultaneously on the sidewalls and the bottoms, thereby causing the filling speed of the opening 312 to The seed layer is coated only at the bottom of the opening 312 faster ^

圖中雖然並未顯示在環氧樹脂層1〇6a與1〇6b之中；不 過其匕通道亦可能會被形成穿過一或多個環氧樹脂層， 用以器件（舉例來說，線路、被動式裝4、外部接觸觸墊、 1C、…等）耦接在一起。又，於其它排列中可能會在一積 體電路的底部（或其它）表面的一表面與散熱片層之 間形成多條導體通道，以便在即使未制金屬化作業來達 成-電流攜載功能仍可提供一條良好導熱路徑至該散熱 般來說互連層122a會有任何數量的相關聯線路及 金屬通道’並且會以適合用來電氣耦接它們的相關聯封裝 器件的任何方式來繞接該些導體。 要注意的是’本文雖然已經說明-種非常適合在實 相同的時間處於—相關聯的環氧樹脂I iG6上方形成線 :、於其複面形成通道的特殊濺錄/電沉積製程；不過， 該明白的是’亦可以使用各式各樣其它習知或新開發的 18 201034154 程來分開或一起形成該等通道和線路。 在已經形成互連層122a之後，通常會以適合用來形成 額外環氧樹脂層、互連層以及適合用以將適當的器件擺放 於其中或其丨或是於其中或其上形成it當器件的任何順序 重複進行步驟204、206、208、210及/或212，以便形成一 特殊封裝100 ’例如：圖3K中所示的封裝。舉例來說在 圖中所示的實施例中，額外的環氧樹脂層106c至106f會被 0 塗敷在層1〇6b上方（其實際上會在必要時重複進行步驟 204) ^積體電路U4b與U4c會被埋置在環氧樹脂層ίο" ” 1〇6e裡面（步驟206、208以及210)。另一互連層122b 會被形成在頂端環氧樹脂層l〇6f裡面（步驟206、208以及 212)，依此類推。 應該明白的是’封裝1〇〇之中的積體電路和互連層可 以各式各樣的方式來排列，端視特殊應用的需求而定。舉 例來說’在圖中所示的實施例中，某些積體電路的主動面 0 會直接堆疊在彼此的上方（舉例來說，積體電路114a與 U4b )。某些積體電路會被埋置在同一個環氧樹脂層或多 個相同的環氧樹脂層裡面（舉例來說，積體電路114b與 114〇)。積體電路可能會被埋置在和其中埋置著互連層的環 氧樹脂層不同的環氧樹脂層之中（舉例來說，互連層M8a 和積體電路114&與114b)。（「不同的（distinct)」環氧 樹脂層所指的是多層之中的每一層與其它層依序被沉積在 單、有黏著性的塗層之中’如環氧樹脂層i〇6a至106e 的清况。）積體電路可能會被堆疊在彼此的上方及/或彼此 201034154 緊密相鄰。積體電路亦可透過實質上延伸至任何單一積體 電路之最鄰近處或輪廓外面的電氣互連層、通道及/或線路 被電氣麵接（舉例來說，積體電路1丨4b與114c)。 在圖2與圖3L的步驟214中，可能會在封裝1〇〇的頂 表面新增非必要的外部接觸觸墊12〇。該等外部接觸觸墊 120可以被擺放在其它表面之上並且以各式各樣的方式來 形成。舉例來說，可以利用上面所述的技術來圖樣化與顯 影頂端環氧樹脂層l〇6f，用以露出電氣互連層12孔的一部 分。任何合宜的金屬（例如：銅）皆可被電鍍至環氧樹脂 〇 層106f上的孔洞之中，用以形成導體通道與外部接觸觸墊 120。因此，至少某些該等外部接觸觸墊12〇可以電氣耦接 電氣互連層122a至122b及/或積體電路114&至U4c。 封裝100的特徵元件可以各式各樣的方式來修正。舉 例來說，其可能含有更多或較少的積體電路及/或互連層。 其可能還含有多個額外的器件，例如：感測器、mems裝 置、電阻器、電容器、薄膜電池結構、光伏特電池、叩無 線天線及/或電感器。於某些實施例中，基才反1〇2會被隱蔽 〇 或疋棄置基板102可能具有任何合宜的厚度。舉例來說， 範圍在約100至250微米之中的厚度極適用於許多應用之 中。封裝100的厚度可能會廣泛地改變。舉例來說，範圍 在約0.5至1毫米之中的厚度極適用於許多應用之中。電氣 互連層122a與122b的厚度同樣可能會隨著特殊應用的需求 而廣泛地改變。舉例來說，相信約5〇微米的厚度極適用於 許多應用之中。 20 201034154 圖4A所示的是本發明另一實施例的剖面圖。和圖【的 封裝100雷同，圖4A的封裝400包含積體電路4〇1與4〇3, 環氧樹脂層410，以及多個互連層。封襞400還包含在封裝 1 〇〇之中並未顯示的某些額外非必要的特徵元件。 舉例來說，封裝400的特點是積體電路4〇1會熱耦接 散熱片402。在圖中所示的實施例中，散熱片4〇2的某些 維度實質上和被熱耗接裝置的維度雷同。於特殊的實施例 中散熱片402可能會大於或小於其下方裝置。散熱片4〇2 可能會被設置在積體電路4〇1的頂端表面或底部表面之上 及/或直接接觸積體電路401的頂端表面或底部表面。其可 能會直接近接封裝400的一外部表面（如圖中所示之實施 例的If况），或者會透過一或多個熱通道被連接至該外部 表面。政熱片402會熱耦接一導體層，例如：圖j的層1〇4<> 於環氧樹脂層410是由SU-8製成的較佳實施例中，在積體 電路401的正下方若有一散熱片4〇2會特別有幫助，因為 熱量不會完全經由SU-8傳導。 封裝400的特點還有各種被動式器件，例如：電感器 406與408、電阻器404以及電容器406。該些被動式器件 可能位於封裝400裡面的任何環氧樹脂層或位置中。它們 可以利用各式各樣的合宜技術來形成，端視特殊應用的需 求而疋。舉例來說，電感器繞線4丨2以及電感器核心4〗 與41〇b可能是藉由在該等環氧樹脂層41〇中的至少其中一 者上方分別沉積導體材料與鐵磁材料而形成。薄膜電阻器 可此是藉由在該等環氧樹脂層410中的其中一者上方減鍵 21 201034154 或塗敷任何合宜的電阻性枯粗 旺柯枓（例如：矽鉻、鎳鉻及/或鉻 碳化梦）而形成。電容器可3[丄 器了月b疋藉由在被沉積於一或多個 環氧樹脂層上方的金屬板之間夾設一薄的介電質層而形 成。事先製造的電阻器、電感器以及電容器亦可以被擺放 在一或多個環氧樹脂層41n + L ^ 日滑410之上。導體性、鐵磁性以及其 它材料皆能夠利用本技術中已4 广 <又w r匕知的任何合宜方法來沉積， 例如：電鍍法或濺鍍法。Although not shown in the epoxy layers 1〇6a and 1〇6b, the germanium channel may also be formed through one or more epoxy layers for devices (for example, lines) , passive mounting 4, external contact pads, 1C, ..., etc.) are coupled together. Moreover, in other arrangements, a plurality of conductor paths may be formed between a surface of the bottom (or other) surface of the integrated circuit and the heat sink layer to achieve a current carrying function even without metallization. Still providing a good thermal path to the heat dissipation, the interconnect layer 122a will have any number of associated lines and metal channels' and will be wound in any manner suitable for the associated packaged devices used to electrically couple them. The conductors. It should be noted that 'this article has shown that it is very suitable to form a line above the associated epoxy resin I iG6 at the same time: a special splatter/electrodeposition process for forming a channel on its complex surface; however, It is understood that 'all other conventional or newly developed 18 201034154 procedures can also be used to separate or form the channels and lines together. After the interconnect layer 122a has been formed, it is generally suitable to form an additional epoxy layer, an interconnect layer, and a suitable device for placing or embedding a suitable device therein or in or on it. Steps 204, 206, 208, 210, and/or 212 are repeated in any order of the device to form a particular package 100' such as the package shown in Figure 3K. For example, in the embodiment shown in the figures, additional epoxy layers 106c to 106f may be coated with 0 over layer 1 〇 6b (which will actually repeat step 204 if necessary). U4b and U4c will be embedded in the epoxy layer ίο" ” 1〇6e (steps 206, 208, and 210). Another interconnect layer 122b will be formed in the top epoxy layer 16f (step 206). , 208 and 212), and so on. It should be understood that the integrated circuits and interconnect layers in the package can be arranged in a variety of ways, depending on the needs of the particular application. Say 'in the embodiment shown in the figure, the active faces 0 of some integrated circuits are stacked directly above each other (for example, integrated circuits 114a and U4b). Some integrated circuits are buried. In the same epoxy layer or a plurality of identical epoxy layers (for example, integrated circuits 114b and 114A), the integrated circuit may be buried in a ring in which the interconnect layer is buried. Among the different epoxy layers of the oxy-resin layer (for example, the interconnect layer M8a and the integrated circuit 11) 4 & and 114b). ("Different" epoxy layer means that each of the layers and other layers are sequentially deposited in a single, adhesive coating such as epoxy The condition of the resin layers i 〇 6a to 106e.) The integrated circuits may be stacked above each other and/or closely adjacent to each other 201034154. The integrated circuit can also be electrically interfaced through electrical interconnect layers, vias and/or lines that extend substantially to the nearest or outer contour of any single integrated circuit (for example, integrated circuits 1丨4b and 114c) ). In step 214 of Figures 2 and 3L, optional external contact pads 12A may be added to the top surface of the package. The external contact pads 120 can be placed over other surfaces and formed in a variety of ways. For example, the top epoxy layer 106f can be patterned and developed using the techniques described above to expose a portion of the hole in the electrical interconnect layer 12. Any suitable metal (e.g., copper) can be plated into the holes in the epoxy layer 106f to form conductor vias and external contact pads 120. Accordingly, at least some of the external contact pads 12A can be electrically coupled to the electrical interconnect layers 122a-122b and/or the integrated circuits 114& to U4c. The features of package 100 can be modified in a variety of ways. For example, it may contain more or fewer integrated circuits and/or interconnect layers. It may also contain a number of additional devices such as sensors, MEMS devices, resistors, capacitors, thin film cell structures, photovoltaic cells, germanium wireless antennas and/or inductors. In some embodiments, the substrate may be concealed or the substrate 102 may have any suitable thickness. For example, thicknesses ranging from about 100 to 250 microns are well suited for many applications. The thickness of the package 100 may vary widely. For example, a thickness ranging from about 0.5 to 1 mm is well suited for many applications. The thickness of the electrical interconnect layers 122a and 122b may also vary widely as the needs of a particular application. For example, it is believed that a thickness of about 5 microns is well suited for many applications. 20 201034154 Figure 4A is a cross-sectional view showing another embodiment of the present invention. Similar to the package 100 of FIG. 4A, the package 400 of FIG. 4A includes integrated circuits 4〇1 and 4〇3, an epoxy layer 410, and a plurality of interconnect layers. The package 400 also contains some additional non-essential features that are not shown in the package 1 . For example, package 400 is characterized in that integrated circuit 4〇1 is thermally coupled to heat sink 402. In the embodiment shown in the figures, certain dimensions of the fins 4〇2 are substantially the same as those of the heat-sinking device. In a particular embodiment the heat sink 402 may be larger or smaller than the device below it. The heat sink 4〇2 may be disposed on the top or bottom surface of the integrated circuit 4〇1 and/or directly in contact with the top or bottom surface of the integrated circuit 401. It may be directly adjacent to an outer surface of the package 400 (as in the example of the embodiment shown) or may be connected to the outer surface through one or more hot channels. The thermal sheet 402 is thermally coupled to a conductor layer, for example, layer 1 〇 4 <> of Fig. j. In the preferred embodiment in which the epoxy layer 410 is made of SU-8, in the integrated circuit 401 It is especially helpful if there is a heat sink 4〇2 directly below, because heat is not completely conducted through the SU-8. Package 400 is also characterized by various passive components such as inductors 406 and 408, resistor 404, and capacitor 406. The passive devices may be located in any epoxy layer or location within the package 400. They can be formed using a variety of appropriate techniques, depending on the needs of the particular application. For example, the inductor winding 4丨2 and the inductor cores 4 and 41〇b may be formed by depositing a conductor material and a ferromagnetic material respectively over at least one of the epoxy layers 41〇. form. The thin film resistor can be formed by subtracting the key 21 201034154 over one of the epoxy layers 410 or applying any suitable resistive dry ruthenium (eg, chrome, nickel chrome, and/or Chromium carbonization dreams are formed. The capacitor can be formed by sandwiching a thin dielectric layer between metal plates deposited over the one or more epoxy layers. Pre-fabricated resistors, inductors, and capacitors can also be placed over one or more epoxy layers 41n + L ^ day slip 410. Conductor, ferromagnetism, and other materials can be deposited by any suitable method known in the art, such as electroplating or sputtering.

封裝400還包含位於正面表面416之上的非必要BGA 型接觸觸墊410。因為接觸觸墊4i〇的位置的關係，基板 14此夠由各種材料製成，例如：G10-FR4、鋼和玻璃。於 該等接觸觸塾位於背面表面418之上的特殊實施例中，基 板41'可能會是由矽所製成而且特點是具有能夠和該等接 觸觸墊^成電氣連接的貫穿通道。於另—實施例中，該基 ,要疋作為一用於形成該封裝400的建立平台而且最後 所示的疋本發明的另一實施例，其具有圖4A中The package 400 also includes an optional BGA type contact pad 410 over the front surface 416. The substrate 14 is made of various materials such as G10-FR4, steel, and glass because of the positional contact with the contact pads 4i. In a particular embodiment where the contact contacts are located on the back surface 418, the substrate 41' may be made of tantalum and is characterized by a through passage that is electrically connectable to the contact pads. In another embodiment, the substrate is used as a setup platform for forming the package 400 and is finally shown in another embodiment of the present invention having the structure of FIG. 4A

入. 符徵70件。此實施例包含額外的器件，它們包 Q 含.精密可調整式電容器430與電阻器432、微繼電器434、 低成本可組態設定的精密被動式回授網路4刊、FR_4底座 了8以及光伏特電池44〇。電池柳可能會被—層透明材料 ，例如.透明# Su_8 )覆蓋。於其它實施例中，光伏特電 池440可以+ 面來取代：窗型玻璃感測器、無線相位天線 夕歹散熱片或是另一合宜的器件。封裝400可能包含許 夕額外的結構’它們包含：電力電感器陣列、有RF功能的 22 201034154 天線、導熱管以及用於消散爽白扭壯λλλ 敢來自封裝400内部之熱量的外 部觸墊。 外 圖4C與4D所示的是且有 足，、有導熱管的兩個另外實 例。圖4C圖解一封裝479，苴白人 、士丄 再包含一被埋置在多層平担 化、可光成像環氧樹脂480之申的拉胁带Α 〒的積體電路486。多個金 屬互連線484會麵接積體電路偽的主動表面上的焊 些（圖中並未顯示）。積體電路似的背面會被安置在— 導熱管48 8之上，該導埶營句冬 ❹ Ο …、s包含導熱線路488a和導埶通 道488b。導熱管488是由會妥褕伟、*办θ … 疋田嘗女適傳導熱量的任何合宜材 料所製成’例如：銅。如虛、線彻所示，來自積體電路 楊的熱量會傳送通過積體電路梅的背面，在導熱線路 488a附近流動並向上通過導埶 艰导，，、、通道48 8b ’所以，該熱量 會流通至封裝479的外部谓嫂志二 町冲。P頂端表面。圖4B中所示的實施 例可以利用各種技術來芻4，為 耵术裂&例如：配合圖3A至3K:所 討論的技術。 圖4.D所示的是本發明的另一眚故么丨 货刃力貫施例。該實施例包含― 積體電路114a’其底部表面會㈣接導熱管。導熱管 :7〇是由導熱材料（例如：銅）所製成，並且會將熱量從積 體電路ll4a處傳送 封裝100的外部熱流通部位472。對 具有多個積體電路和高雷六齊庚 门電力在度的封裝來說，熱消散可能 答造成問題。能夠耦接封裝100，里面-或多個裝置的導熱 可以讓内部產生的熱被傳輸至封I ι〇〇的一或多個 舉例來說’熱會被傳導遠離積體電 塔114a而流到封裝〗n 100的頂端表面' 底部表面以及多個側 23 201034154 邊表面上的熱流通部位472。 多個散熱片亦可能會被安置在封裝1〇〇的頂端表 面、底部表面、側邊表面及/或幾乎任何外部表面。在圖 中所示的實施例中，舉例來說，位於封裝1〇〇之底部表面 的熱分散板102會熱耦接導熱管47〇並且將熱量消散至封 裝100的整個底部表面區域。於其中一實施例中，封裝 100中的所有導熱管（它們會熱耦接多個埋置的積體電路） 同樣會熱耦接熱分散板102。於此實施例的一變化例中， 某些該等導熱管還會耦接位於該封裝100之頂端表面的 Θ 散熱片。導熱管4 70可以利用和用於製造互連層122雷同 的製程來形成。它們可能會耦接封裝1〇〇裡面的多個被動 式及/或主動式裝置並且能夠延伸在封裝1〇〇裡面的幾乎 任何方向中。在圖中所示的實施例中，舉例來說，導熱管 470會延伸在平行及垂直於由該等可光成像層1〇6所形成 之平面中某些平面的方向中。如圖4C中所示，導熱管470 可能包含穿過一或多個互連層122及/或可光成像層1〇6 的導熱線路470b與470d及/或通道470a與470c。該等導 ❹ 熱管470會被配置成用以散熱、傳導電氣訊號或兩者。於 其中一實施例中，會在相同的環氧樹脂層裡面埋置一用於 傳送電氣訊號的互連層以及一不適合用於傳送電氣訊號 的導熱管* 本發明的另一實施例圖解在圖4E中。封裝排列45 0包 含一被形成在基板456之頂端表面460上的微系統452。微 系統452可能包含多個介電質層、互連層、主動式及/或被 24 201034154 動式器件，並且可能具有配合圖i的封裝1〇〇及/或圖4a 的封裝400所述的任何特徵元件。微系統452及基板456 的頂端表面460會被囊封在鑄模成型材料牝4(其可以由任 何合宜的材料製成，例如：熱固性塑膠）之中。多個金屬 通道458會電氣耦接微系統452底部的外部觸墊（圖中並 未顯不）及基板45 6的底部表面461。該等通道458會終止 於非必要的焊球462處，該等焊球可能是由各種導體材料 製成。舉例來說，焊球462可以被安置在一印刷電路板之 上，用以達成微系統452和各種外部器件之間的電氣連接。 圖5A至5H所示的是用於建立和圖4D之排列45〇雷 同的封裝的晶圓層級製程的剖面圖。圖5八繪製的是一具有 頂端表面502和底部表面504的晶圓5〇〇。圖中僅顯示晶圓 500的一小部分。虛垂直線所示的是已投影的切割線508。 在圖中所示的實施例中，基板5〇〇可能是由各式各樣的合 宜材料所製成，例如：矽。 、在圖Μ中’晶圓500的頂端表面5〇2會被蝕除，用以 形成孔洞506。此蝕刻製程可以利用各式各樣的技術來實 施例如.電漿蝕刻技術。而後，金屬便會被沉積在該等 孔洞之中，用以形成一電氣系統。此沉積可以利用任何合 且的方去來實施’例如：電鍍法。舉例來說，一晶種層（圖 中並未顯不）可能會被沉積在晶圓500的頂端表面502上 方接著，便可以利用—金屬（例如：銅）來電鐘該晶種 層該電鑛製程會在晶圓5〇〇的頂端表面5〇2產生金屬通 道510以及接觸觸墊512。 25 201034154In. 70 characters. This embodiment includes additional devices, including Q. Precision Adjustable Capacitor 430 and Resistor 432, Micro Relay 434, Low-Cost Configurable Precision Passive Feedback Network 4, FR_4 Base 8 and Photovoltaic Special battery 44〇. The battery will probably be covered by a layer of transparent material such as .Transparent # Su_8 . In other embodiments, the photovoltaic cell 440 can be replaced with a +-face glass sensor, a wireless phase antenna, a heat sink or another suitable device. The package 400 may contain additional structures that include: a power inductor array, an RF-enabled 22 201034154 antenna, a heat pipe, and an external contact pad for dissipating the coolening of the interior of the package 400. Figures 4C and 4D show two additional examples of a heat pipe. Figure 4C illustrates a package 479, which includes a built-in circuit 486 embedded in a multi-layered, photoimageable epoxy resin 480. A plurality of metal interconnects 484 are surfaced to the solder on the dummy active surface of the integrated circuit (not shown). The back side of the integrated circuit will be placed over the heat pipe 48 8 , which includes the heat conducting line 488a and the guiding channel 488b. The heat pipe 488 is made of any suitable material that would be suitable for the heat transfer of the females, such as copper. As shown by the virtual line and the line, the heat from the integrated circuit Yang will be transmitted through the back side of the integrated circuit, flowing near the heat conducting line 488a and passing upward through the guide, and the passage 48 8b 'so, the heat It will flow to the outside of the package 479. P top surface. The embodiment shown in Fig. 4B can utilize various techniques for 刍4, for 耵 裂 & for example: in conjunction with Figures 3A through 3K: the techniques discussed. Figure 4D shows another example of the invention. This embodiment includes an "integral circuit 114a' whose bottom surface is (four) connected to the heat pipe. The heat pipe: 7 is made of a heat conductive material (for example, copper), and heat is transferred from the integrated circuit 114a to the external heat flux portion 472 of the package 100. For packages with multiple integrated circuits and high power, the heat dissipation may cause problems. Capable of coupling the package 100, the heat conduction of the inside-or multiple devices allows the internally generated heat to be transferred to one or more of the blocks, for example, 'heat will be conducted away from the integrated circuit tower 114a. The top surface of the package n 100 'the bottom surface and the heat transfer portion 472 on the side surface of the plurality of sides 23 201034154. Multiple fins may also be placed on the top surface, bottom surface, side surfaces, and/or almost any exterior surface of the package. In the embodiment shown in the figures, for example, the heat dispersing plate 102 on the bottom surface of the package 1 is thermally coupled to the heat pipe 47 and dissipates heat to the entire bottom surface area of the package 100. In one embodiment, all of the heat pipes in the package 100, which are thermally coupled to a plurality of embedded integrated circuits, are also thermally coupled to the heat spreader plate 102. In a variation of this embodiment, some of the heat pipes are also coupled to a heat sink located on a top surface of the package 100. The heat pipe 4 70 can be formed using a process similar to that used to fabricate the interconnect layer 122. They may couple multiple passive and/or active devices within the package 1 and can extend in almost any direction within the package. In the embodiment shown in the figures, for example, the heat pipe 470 will extend in a direction parallel and perpendicular to certain planes in the plane formed by the photoimageable layers 1〇6. As shown in FIG. 4C, the heat pipe 470 may include thermally conductive lines 470b and 470d and/or channels 470a and 470c that pass through one or more interconnect layers 122 and/or photoimageable layers 1〇6. The conductive heat pipes 470 are configured to dissipate heat, conduct electrical signals, or both. In one embodiment, an interconnect layer for transmitting electrical signals and a heat pipe unsuitable for transmitting electrical signals are embedded in the same epoxy layer. * Another embodiment of the present invention is illustrated in the drawings. 4E. The package arrangement 45 0 includes a microsystem 452 formed on the top surface 460 of the substrate 456. The microsystem 452 may include a plurality of dielectric layers, interconnect layers, active and/or by 24 201034154, and may have the package 1 of FIG. 1 and/or the package 400 of FIG. 4a. Any feature component. The top surface 460 of the microsystem 452 and substrate 456 will be encapsulated in a molding material crucible 4 (which may be made of any suitable material, such as a thermoset plastic). A plurality of metal vias 458 are electrically coupled to the external contact pads at the bottom of the microsystem 452 (not shown) and the bottom surface 461 of the substrate 45. The channels 458 terminate at unnecessary solder balls 462, which may be made of various conductor materials. For example, solder balls 462 can be placed over a printed circuit board to achieve electrical connections between microsystem 452 and various external components. 5A through 5H are cross-sectional views of a wafer level process for establishing a package of the same arrangement as that of Fig. 4D. Figure 5 shows a wafer 5 having a top surface 502 and a bottom surface 504. Only a small portion of wafer 500 is shown. Shown by the dashed vertical line is the projected cut line 508. In the embodiment shown in the figures, the substrate 5 may be made of a wide variety of suitable materials, such as ruthenium. In the figure, the top surface 5〇2 of the wafer 500 is etched away to form the hole 506. This etching process can utilize a variety of techniques to implement, for example, plasma etching techniques. Metal is then deposited in the holes to form an electrical system. This deposition can be carried out using any combination of 'for example: electroplating. For example, a seed layer (not shown) may be deposited over the top surface 502 of the wafer 500, and then the metal layer (eg, copper) may be used to call the seed layer. The process produces a metal via 510 and a contact pad 512 on the top surface 5〇2 of the wafer 5〇〇. 25 201034154

在圖5D中，微系統513會利用和配合圖2及从至几 所述者雷同的步驟被形成在晶圓⑽的頂端表面502上。 在圖中所示的實施例中，微系統513並不具有被形成在它 們的頂端表面515上的外部接觸觸墊，因為頂端表面SBIn Figure 5D, microsystem 513 is formed on top surface 502 of wafer (10) using the same steps as in Figure 2 and from the same. In the embodiment shown in the figures, the microsystem 513 does not have external contact pads formed on their top end surfaces 515 because the top surface SB

在精後的作業中將會進行包㈣模成型。於另—實施例 中，多個外部接觸觸塾會被形成在頂端表φ 515上，用以 在進行包覆鑄模成型之前達成晶圓層級功能測試。微系統 513在匕們的底部表面517上具有外部接觸觸墊，它們會對 齊晶圓500之頂端表s 5〇2上的接觸觸m2。這有助於在 該等金屬通道510和該等微系統513裡面的 間達成電氣連接。 〒，一 口宜的鑄模成型材料52〇會被塗敷在該 等微系統513以及晶® 5〇〇的頂端表面5〇2上方。該鱗模 成型製程能夠利用各式各樣合宜的技術與材料來實施。結 果’便會形成-已鍀模成型的晶圓結構522。於某些設計 中’禱模成型材料520會完全覆蓋及囊封微***513及/或 整個頂端表面502。鑄模成型材料52〇的塗敷可以為微系統❹ 513提供額外的機械支撐，當微系統513非常龐大時這可能 相當實用。 圖5F所示的是當利用任何各種合宜技術（例如：背面 研磨技術）部分移除晶圓500的底部表面5〇4之後的已鑄 模成型的晶圓結構522。結果，部分的金屬通道5 1〇便會露 出。在圖5G中，焊球524會被塗敷至該等裸露的金屬通道 510部分。在圖5H中，接著便會沿著已投影的切割線5〇8 26 201034154 來卓體化該已禱模成s ^ 风玉的Ba圓結構522，以便創造多個個別 的封裝排列526。該單體朴制叙—p、， 平篮化製程可以利用各式各樣適當的方 法（例如：削切法或雷射切割法）來實施。 圖6A至6C所示的是根據本發明另一實施例用於建立 一封裝的晶圓層級製程的剖面圖。圖6A所示的是已經事先 製造出多個穿孔602的基板600。6B所示的是將金屬沉 積在該等孔洞602之中，用以形成多個金屬通道6〇4。金屬 的/儿積可以利用任何合宜的技術（例如：電鍍技術）來實 施於某些實施例中，該基板600會事先製造出穿孔602 及/或金屬通道604，因而得以省略一或多個處理步驟。在 圖6C中，多個微系統606會利用任何前述的技術被形成在 3亥4金屬通道604與該基板600上方。而後，便可以實施 焊凸作業及單體化，如圖5G與5H中所示。圖中所示的實 施例可能包含和配合圖5A至5H所述者相同的各種特徵元 件。 ❹ 圖7A至7C所示的是根據本發明另一實施例用於建立 封裝的晶圓層級製程的剖面圖。'一開始會先提供一基板 700。多個銅質觸墊702接著會被形成在基板7〇〇的頂端表 面上方。在圖7B中，多個微系統704會利用任何前述的技 術被形成在銅質觸墊702與該基板700上方。該等微系統 7〇4與基板700的頂端表面接著會被囊封在合宜的鑄模成型 材料706之中。接著，在圖7C中，基板700會被完全磨除 或移除。而後，多個焊凸塊便會被貼附至銅質觸墊702。圖 中所示的實施例可能包含和配合圖5A至5H所述者相同的 27 201034154 各種特徵元件。 本發明的額外實施例圖解在圖8至1〇中。該些實施例 是關於會在一基板（舉例來說，矽質基板）裡面埋置一或 多個積體電路的積體電路封裝。埋置積體電路會被一可光 成像的環氧樹脂層覆蓋。一互連層會被形成在該環氧樹脂 層的上方並且會經由該環氧樹脂層中的一或多條通道電氣 耦接該積體電路。 在基板中埋置一或多個積體電路會提供許多優點。舉 例來說，本發明的各實施例皆包含會使用該基板作為散熱 ❹ 片、導電體及/或用於光通訊之媒體的埋置積體電路。當使 用碎質晶圓作為該基板時，埋置積體電路和石夕質基板雷同 的熱膨脹是數能夠有助於降低脫層的風險。於某些施行方 式中，將積體電路埋置在基板中而非環氧樹脂層中能夠幫 助最小化該環氧樹脂層的厚度並且縮減封裝的尺寸。 現在參考圖8A與8B來說明包含具有一或多個埋置積 體電路之基板的積體電路封裝的各種範例。圖8A所示的是 一積體電路封裝800，其包含：一基板8〇4、積體電路8〇2、 q 一環氧樹脂層806以及一互連層812。基板8〇4較佳的是一 矽質晶圓，其很容易藉由現有的半導體封裝設備來處置。 不過，端視封裝800的預期用途而定，可以使用其它合宜 的材料（舉例來說’玻璃、石英、…等）。積體電路8〇2 會被ό又置在該基板8〇4之頂端表面中的腔穴裡面。該 等=體電路802的主動面以及該基板8〇4的頂端表面會被 一環氧樹脂層806覆蓋。該環氧樹脂層8〇6是由一平坦化、 28 201034154 可光成像的環氧樹脂（例如：su_8)所製成。該互連層8i2 會被形成在該環氧樹脂層806的上方。該互連層8i2包含 導體線路812b以及導體通道812a，它們會延伸至該環氧樹 脂層806中的開口請並且會電氣麵接該等積體電路8〇2 之主動面上的1/0觸墊。於不考慮新增更多環氧樹脂層、積 體電路以及電氣器件的各種施行方式中，一介電質層能夠 被塗敷在該互連層812的上方。焊接觸墊可能會被形成在 該封裝800的外面，它們會經由該介電質層之中㈣ 電氣耦接該等積體電路802和該互連層812。 圖8B所示的是本發明的另一實施例其包含在基板 804的上方設置額外的環氧樹脂層、積體電路以及互連層。 該積體電路封裝801包含多個相鄰的環氧樹脂層822、互連 層818以及積體電路816，它們會被堆疊在互連層812、環 氧樹脂層806、積體電路802以及基板8〇4的上方。積體電 路816中的每一者會被設置在該等環氧樹脂層822中的至 Q少其中一者之中。互連層818會被散置在各個積體電路816 與環氧樹脂層822之間。該等互連層818會相互電氣連接 各個積體電路802與816並且讓積體電路8〇2與816電氣 連接被形成在該積體電路封裝801之頂端表面上的1/〇觸墊 824 〇 應該明白的是，圖8A與8B代表的是可以從中產生許 多變化例的特殊實施例。舉例來說，可能會有一個或幾乎 任何數量的積體電路被設置在該基板8〇4的裡面或之上。 該等導體通道與線路的設置、該等腔穴的擺放與維度及/或 29 201034154 該等互連層與環氧樹 同。除此之冰 ”曰層的厚度皆可能和圖中所示者不 RA ^ 所述的任何特徵元件及排列 力J、，·〇 〇圖8A與8B中的幾乎柘彻WL丄 ^ δο , 于任饤觀點或是用來修正圖8Α 與8Β中的幾乎任何觀點。 現在參考圖9Α至9G來續明田 术說明用於形成圖8Α與8Β之積 體電路封裝的示範性方法 万凌在圖9A中會提供一基板902。 於一較佳的實施例中，咭某柘 β 处 Τ这基扳902疋一矽質晶圓，因為這 勺幫助最大化圖9A至9F之操作和既有以半導體晶圓為In the finishing operation, the package (four) molding will be carried out. In another embodiment, a plurality of external contact contacts are formed on the top surface φ 515 for wafer level functional testing prior to cladding molding. The microsystem 513 has external contact pads on their bottom surface 517 that will contact the contact m2 on the top surface s 5〇2 of the wafer 500. This facilitates electrical connection between the metal channels 510 and the microsystems 513. Alternatively, a suitable molding material 52 is applied over the top surface 5〇2 of the microsystem 513 and the crystal® 5〇〇. The scale forming process can be implemented using a variety of suitable techniques and materials. The result will form a patterned wafer structure 522. In some designs, the prayer molding material 520 will completely cover and encapsulate the microsystem 513 and/or the entire tip surface 502. The application of the molding material 52A can provide additional mechanical support to the microsystem 513, which can be quite practical when the microsystem 513 is very bulky. Shown in Figure 5F is a molded wafer structure 522 after partial removal of the bottom surface 5〇4 of wafer 500 using any of a variety of suitable techniques (e.g., backside grinding techniques). As a result, part of the metal passage 5 1 will be exposed. In Figure 5G, solder balls 524 are applied to portions of the bare metal vias 510. In Fig. 5H, the Ba circle structure 522 that has been spliced into s^ wind jade is then classically formed along the projected cut line 5〇8 26 201034154 to create a plurality of individual package arrangements 526. The single-ply, p-, and flat-blanking process can be carried out using a variety of suitable methods (e.g., cutting or laser cutting). 6A through 6C are cross-sectional views showing a wafer level process for establishing a package in accordance with another embodiment of the present invention. Shown in Fig. 6A is a substrate 600 in which a plurality of perforations 602 have been previously fabricated. 6B shows the deposition of metal in the holes 602 to form a plurality of metal vias 〇4. The metal/product can be implemented in some embodiments using any suitable technique (e.g., electroplating techniques) that will previously create perforations 602 and/or metal vias 604, thereby omitting one or more processes. step. In Figure 6C, a plurality of microsystems 606 are formed over the 3well 4 metal vias 604 and the substrate 600 using any of the foregoing techniques. Then, the solder bumping operation and singulation can be performed as shown in Figs. 5G and 5H. The embodiment shown in the figures may contain the same various features as those described in connection with Figures 5A through 5H. 7A to 7C are cross-sectional views showing a wafer leveling process for establishing a package in accordance with another embodiment of the present invention. 'A substrate 700 will be provided first. A plurality of copper contact pads 702 are then formed over the top surface of the substrate 7A. In Figure 7B, a plurality of microsystems 704 are formed over the copper contact pads 702 and the substrate 700 using any of the foregoing techniques. The microsystems 7〇4 and the top surface of the substrate 700 are then encapsulated in a suitable mold forming material 706. Next, in Figure 7C, the substrate 700 will be completely removed or removed. A plurality of solder bumps are then attached to the copper contact pads 702. The embodiment shown in the figures may include the same 27 201034154 various features as those described in connection with Figures 5A through 5H. Additional embodiments of the invention are illustrated in Figures 8 to 1A. These embodiments are directed to integrated circuit packages that embed one or more integrated circuits in a substrate (e.g., a germanium substrate). The buried integrated circuit is covered by a photoimageable epoxy layer. An interconnect layer will be formed over the epoxy layer and electrically coupled to the integrated circuit via one or more of the epoxy layers. Embedding one or more integrated circuits in a substrate provides a number of advantages. For example, various embodiments of the present invention include a buried integrated circuit that uses the substrate as a heat sink, an electrical conductor, and/or a medium for optical communication. When a chip is used as the substrate, the same thermal expansion of the embedded integrated circuit and the stone substrate can reduce the risk of delamination. In some implementations, embedding the integrated circuit in the substrate rather than in the epoxy layer can help minimize the thickness of the epoxy layer and reduce the size of the package. Various examples of integrated circuit packages including substrates having one or more buried integrated circuits will now be described with reference to Figs. 8A and 8B. 8A is an integrated circuit package 800 comprising: a substrate 8〇4, an integrated circuit 8〇2, an epoxy layer 806, and an interconnect layer 812. The substrate 8〇4 is preferably a germanium wafer which is easily handled by existing semiconductor packaging equipment. However, depending on the intended use of the package 800, other suitable materials (e.g., 'glass, quartz, ..., etc.) may be used. The integrated circuit 8〇2 is placed in the cavity in the top surface of the substrate 8〇4. The active surface of the body circuit 802 and the top surface of the substrate 8〇4 are covered by an epoxy layer 806. The epoxy layer 8〇6 is made of a planarized, 28 201034154 photoimageable epoxy resin (eg, su_8). The interconnect layer 8i2 will be formed over the epoxy layer 806. The interconnect layer 8i2 includes a conductor line 812b and a conductor channel 812a that extend to the opening in the epoxy layer 806 and electrically connect to the 1/0 contact on the active surface of the integrated circuit 8〇2. pad. A dielectric layer can be applied over the interconnect layer 812 without regard to various implementations of adding more epoxy layers, integrated circuits, and electrical devices. Solder contact pads may be formed on the outside of the package 800, which electrically couple the integrated circuits 802 and the interconnect layer 812 via the dielectric layer (4). Another embodiment of the present invention, shown in Figure 8B, includes an additional layer of epoxy, integrated circuitry, and interconnect layers disposed over substrate 804. The integrated circuit package 801 includes a plurality of adjacent epoxy layers 822, interconnect layers 818, and integrated circuits 816 which are stacked on the interconnect layer 812, the epoxy layer 806, the integrated circuit 802, and the substrate. Above 8〇4. Each of the integrated circuits 816 is disposed in one of the less than one of the epoxy layers 822. The interconnect layer 818 is interspersed between the respective integrated circuits 816 and the epoxy layer 822. The interconnect layers 818 electrically connect the respective integrated circuits 802 and 816 to each other and electrically connect the integrated circuits 8〇2 and 816 to the 1/〇 contact pads 824 formed on the top surface of the integrated circuit package 801. It should be understood that Figures 8A and 8B represent particular embodiments from which many variations can be made. For example, there may be one or almost any number of integrated circuits disposed on or in the substrate 8〇4. The arrangement of the conductor channels and lines, the placement and dimensions of the cavities, and/or 29 201034154 are the same as the epoxy tree. In addition to this, the thickness of the 曰 layer may be any characteristic element and arrangement force J as described in the figure, and the arranging force J, 〇〇 8 丄 丄 丄 丄 于 于 于 于 于 于Any point of view is used to correct almost any of the views in Figures 8A and 8B. Referring now to Figures 9A through 9G, the exemplary method for forming the integrated circuit package of Figures 8A and 8B is shown in Figure 9A. A substrate 902 is provided. In a preferred embodiment, the 柘β Τ Τ 疋 疋 矽 矽 , , , , , , , , , , , , , 因为 帮助 帮助 帮助 帮助 帮助 帮助 帮助 帮助 帮助 帮助 帮助 帮助 帮助 帮助 帮助 帮助 帮助 帮助 帮助 帮助Wafer is

= <處理設備的相容性。於替代的實施例中，基板902 可能是由各式各樣的材料（其包含：矽、玻璃、鋼、g1〇_fr4、 石英、…等）所製成，端視特殊應用的需求而定。= < Processing device compatibility. In an alternative embodiment, the substrate 902 may be made from a wide variety of materials including: tantalum, glass, steel, g1〇_fr4, quartz, ..., etc., depending on the needs of the particular application. .

在圖9B中’多個腔穴904會被形成在基板902之中。 腔穴904可以利用濕式或電漿蝕刻來形成，不過，亦可以 利用其它合宜的技術。蝕刻製程中所使用的化學藥劑以及 基板902中的矽的結晶結構能夠幫助控制腔穴9〇4之側壁 的角度。舉例來說’已經發現到，的矽晶體結構能夠 幫助更筆直的側壁及/或幫助形成一約略垂直於其對應腔穴 之底部表面的側壁。晶粒貼附黏著劑9〇3會被塗敷至腔穴 9〇4的底部，以便幫助將積體電路906黏著至腔穴904的底 部表面’如圖9C中所示。於一替代的實施例中，在將積體 電路906擺放於該腔穴904中之前，該晶粒貼附黏著劑903 會先以個別的方式或在晶圓層級中被塗敷至積體電路906 的背部表面。端視特殊應用的需求而定，該晶粒貼附黏著 劑可能為導電性或不導電性。於某些實施例中，倆種類型 30 201034154 的黏著劑會同時被使用在相同的封裝之中，俾使其中一個 積體電路會經由其底部表面電氣輪接一導電基板，而另一 個積體電路則會與基板電氣絕緣（下面會討論導 各種應用）。 、在® 9D中’一平坦化、可光成像的環氧樹脂層9〇8會 被沉積在該等腔R 904、該基板9〇2以及該等積體電路_ 的上方。该環氧樹脂層908較佳的是su_8，但是，亦可以 使用其它合宜的材料。該環氧樹脂層能夠延伸在積體電路 906之主動表面的上方及直接接觸該積體電路9〇6的主動表 面並且能夠填入該基板9〇2中的腔穴9〇4之中。如先前所 提，利用可光成像的環氧樹脂（例如：su_8 )的其中一項 優點是相較於其利用光微影技術能夠有更佳的控制程度。 在圖9E中，一或多個開口 91〇會被形成在該環氧樹脂 層908之中。該等開口 91〇能夠以熟習半導體處理領域的 人士已知的各式各樣方式來產生。舉例來說，該環氧樹脂 〇 層908可能會被光微影圖樣化並且可以利用一顯影劑溶液 來溶解部分該環氧樹脂層908。該等開口 910能夠露出被埋 置在該環氧樹脂層908裡面的積體電路906之主動表面上 的I/O觸墊。 圖9F所示的是互連層912之成形，其能夠利用本技術 中已知的各種合宜技術來實施。和配合圖3F至3J所述之步 驟類似的其中一種方式包含：沉積一晶種層與一光阻層； 圖樣化該光阻層；以及電鍍一金屬，用以在該等開口 9 j 〇 中形成導體線路912a和導體通道912b。於各種實施例中， 31 201034154 該互連層912會電氣連接被埋置在基板9〇2之中的多個積 體電路晶粒906。 而後，額外的環氧樹脂層918、積體電路922及/或互 連層916便可被形成在基板9〇2、積體電路9〇6'環氧樹脂 層908以及互連層912的上方。該些層與器件可以各式各 樣的方式來排列，並且可以利用配合圖i至7C所討論的任 何排列與特徵元件來修正圖中所示實施例的任何觀點。舉 例來說，該等一或多個互連層912及/或916可以用來電氣 連接被設置在該基板9〇2裡面的積體電路9〇6以及被埋置❹ 在該等環氧樹脂$ 918裡面的任何或全部積體電路922。適 合或不適合用㈣送電氣訊號料熱管會從該以基板為基 礎的積體電路晶粒906延伸至積體電路封裝921的任何外 部表面。如先前所述，各種被動式裝置與主動式裝置、導 熱管、散熱片、感測器、…等可以被形成或擺放在該積體電 路封裝921的幾乎任何位置中（舉例來說在基板9〇2之 中、在基板902之上、被埋置在環氧樹脂層918之間、…等 該基板902同樣可能會接受背面研磨或是適合用來縮減基 ❹ 板902之厚度的任何其它作業。圖9G所示的是額外的環氧 樹月曰層、互連層以及積體電路被塗敷在基板902、積體電路 906、環氧樹脂層9〇8以及互連層912上方之後的圖之 積體電路封裝的範例。 圖10A至1 〇d中所示的是本發明的額外實施例，每一 個實施例同樣包含一具有一或多個埋置積體電路的基板。 圖1〇A所示的是積體電路封裝ι〇〇〇，其包含：一導電與導 32 201034154 熱基板1002，其具有埋置積體電路1〇〇4 ; 一平坦化可光 成像的環氧樹脂層1〇〇6 ;以及一互連層1〇〇8。積體電路封 裝1000可以利用配合圖9人至9F所述的任何技術來形成。 積體電路1004b會利用導電黏著劑1〇12b被安置在基 板1002中腔穴1〇〇5的底部表面上。因此，積體電路1〇〇仆 會電氣耦接該基板1002及/或能夠利用該基板1〇〇2將熱量 消散至該封裝的外部表面。某些施行方式還包含一積體電 路1〇〇4a ’其會藉由一非導體黏著劑l〇12a與該導體基板 1002產生電氣絕緣。在圖中所示的實施例中雖然僅顯示兩 個積體電路；不過，亦可於該基板1〇〇2裡面設置較少或更 多的積體電路，每一者會分別電氣耦接該基板1〇〇2或是與 該基板1002產生電氣絕緣。 於各種實施例中，基板1〇02可充當一用於達成電氣接 地連接的管線。封裝1000包含一接地互連線1〇2〇,其會被 形成在該環氧樹脂層1006的上方並延伸穿過該環氧樹脂層 ◎ 1006而且會電氣耦接該基板1〇〇2中的一接地接觸區 1014。接地互連線1020是由一導電材料（例如：銅）製成， 而且至少部分在該互連層1008的形成期間便可能已經形 成，如先前配合圖9F所述。 基板1002争的接地接觸區1014及基板1〇〇2的其它部 分皆由矽製成並且會被摻雜以改良它們的導電性。為有助 於基板1002和接地互連線1020之間的電氣連接，該接地 接觸區1014的摻雜濃度實質上會高於該基板1〇〇2中的一 或多個其它部分。於各種施行方式中，該基板1〇〇2是由p 33 201034154 . 型半導體材料所製成而該接地接觸區1014則是一 p++摻雜 區；不過’亦可以利用熟習本技術的人士已知的任何合宜 材料及/或濃度來摻雜該基板1002和該接地接觸區1014。 因此，當該接地互連線1020被電氣接地的話，該積體電路 1004b、該基板1002以及該接地接觸區ι〇14會電氣耦接該 接地互連線1020並且同樣會被電氣接地。 圖10B提供根據本發明其中一實施例的圖10A的區域 1010的放大圖。該圖包含具有下面的基板1〇〇2 :接地接觸 區1014、層間介電質1〇16、鈍化層1〇18、導電插塞1022、 © 電氣互連線1024與1020、環氧樹脂層1〇〇6以及接地互連 線1020。熟習半導體製造領域的人士已知的各項技術皆可 被用來沉積、圖樣化及/或顯影層間介電質10丨6與鈍化層 1018，並且形成插塞1022與電氣互連線1〇24。插塞1022 與電氣互連線1024可能是由各種合宜的導電材料所製成’ 其分別包含鎢與鋁。環氧樹脂層1 〇〇6與互連線1 〇2〇可以 利用各種技術來形成，其包含配合圖9D至9F所述的技術。 用於形成圖10B之層間介電質1〇16與鈍化層1〇18的 Ο 技術能夠被整合至用於形成圖l〇A之腔穴1〇〇5的技術之 中。舉例來說，在腔穴1005之成形期間，層間介電質ι〇16 會被沉積跨越基板1〇〇2的頂端表面1〇〇3。該層間介電質會 被圖樣化與蝕刻，不僅用以產生該等插塞1 〇22的空間，還 會用以形成一光罩以便形成基板1〇〇2中的腔穴ι〇〇5。此種 方式能夠幫助減少用於製造積體電路封裝1〇〇〇的處理步驟 的數量。 34 201034154 本發明的另一實施例圖解在圖1〇c之中。圖10C包含 一積體電路封裝1〇3〇’其在一基板的兩面之上會形成積體 電路、平坦化可光成像環氧樹脂層以及互連層。在圖中所 示的實施例中，積體電路1〇36、環氧樹脂層1〇4〇以及互連 層1038會被形成在基板1〇32的頂端表面1〇34的上方積體 電路1042、環氧樹脂層1〇44以及互連層1〇46會被形成在 基板1032的反向底部表面ι〇46的上方。用以形成該積體 電路封裝1030的其中一種方式是在該基板1〇32的頂端表 〇 面與底部表面兩者之上套用配合圖9A至9F所討論的各項 技術。 積體電路封裝1030的一種特殊施行方式包含排列多個 積體電路’以便經由一透光基板以光學方式來彼此進行通 訊。在圖中所示的實施例中，舉例來說，積體電路l〇36a 與1042a會相互上下對齊並且包含多個光學裝置，例如：雷 射二極體、光學偵測器、…等（又，在另一實施例中，可以 使用多個光學裝置（例如：光學感測器、光學偵測器、雷 射二極體、…等）來取代積體電路l〇36a及/或1〇42a)。該 基板中至少介於積體電路1〇36&與1042a之間的部分1〇34 為透光性並且會被排列成用以允許在積體電路1〇36a與 1042a之間進行光學通訊。該透光基板可能是由各種材料製 成，其包含玻璃與石英。某些施行方式包含一完全由單一 透光材料所製成及/或具有均勻組成的基板1 〇32。 另一種方式包含一由矽製成的基板1032。該矽質基板 1032能夠電氣絕緣該等積體電路i〇36a與1〇42a ;但是舉 35 201034154 例來說，卻會讓& μ u ^ |賞m匕們利用紫外光（其能夠行進通過 光學方式進行通訊。 又，本發明的另—實施例圖解在圖10D之中。圖1〇D 所不的疋一積體電路封裝ι〇5〇，其具有用以減輕被埋置在 封裝基板1052裡面的—或多個積體電路1〇54之上的應力 特徵元件。積體電路封裝1〇5〇包含一具有下面的基板 1〇52·腔穴1060、積體電路1054、可光成像環氧樹脂層1〇56 以及互連層1〇58。每一個腔穴1〇6〇於該腔穴1〇6〇的一側 壁1064及該積體電路1054之間皆包含一空氣間隙1062。 © 於測試與操作期間，該積體電路1054與封裝1〇5〇會 進行溫度循環作業。溫度提高可能會導致該積體電路 1054 與該封裝1050中的其它器件膨脹。倘若該積體電路1〇54 被囊封在有彈性的材料之中的話，此膨漲作用便可能會在 該積體電路1054上強加額外的應力。空氣間隙1〇62能夠 提供空間給該積體電路1〇54膨脹，並且從而有助於降低此 應力。據此，環氧樹脂層1056雖會覆蓋腔穴1060，但實質 上卻不會延伸至腔穴1060之中。 ❹ 有各種方式可以被用來形成積體電路封裝1050的特徵 元件。舉例來說，在基板1052中形成腔穴1060以及在腔 穴1060之中擺放積體電路1〇54可以如先前配合圖9A至9C 所述般來實施。而後，便可以塗敷一層事先製造的可光成 像環氧樹脂（例如：SU-8)，俾使其會覆蓋該等腔穴1060 及該基板1052 ^於各種實施例中，該環氧樹脂層1056並不 是被喷塗和旋塗在該等腔穴1060的上方，而是被層疊在基 36 201034154 板1〇52之上。此方式有助於保留每-個積體電路1054和 對應腔八1060之側壁1〇64之間的空氣間隙。接著， 在環氧樹脂層1056和互連層1〇58之令形成開口便能夠以 穿配^圖9EJL 9F所述之作業雷同的方式般來進行。舉例 來說，可以利用光微影術來圖樣化該環氧樹脂層1〇56，其 會導致該環氧樹脂層1056中的一部分的固化及/或移除。 雖然本文已經詳細說明本發明的；不過，應該明白的 可以許多其匕形式來施行本發明，其並不會脫離本 ❹發明的精神或範嘴。舉例來說，本文所述之各種實施例有 時候雖然會圖解特有及不同的特徵元件；不過，本發明卻 涵蓋各式各樣積體電路封裝，它們可能各自含有本文所述 之特徵元件的幾乎任何組合並且是利用本文所述之製程的 幾乎任何組合所形成。以包含一或多個埋置積體電路8〇2 的圖8A的積體電路封裝80〇的基板8〇4作為範例，其可能 還包含多條金屬通道，它們會穿過該基板8〇4並且讓互連 ❹層812電氣連接該基板804之外部表面上的接點。此等金 屬通道是配合圖4E所述。用於製造該等金屬通道的製程是 配合圖5A至5H所述並且同樣可套用於圖8A的基板8〇4。 所以，本發明的實施例應該被視為解釋性而不具限制意 義’而且本發明並不受限於本文所提出的細節，相反地， 還可以在隨附申請專利範圍的範疇與等效範疇裡面進行修 正0 【圖式簡單說明】 配合隨附的圖式來參考上面的說明，可以對本發明及 37 201034154 其優點達到最佳的理解效果，其中： 圖1所示的是根據本發明一實施例’含有多個積體電 路和互連層的封裝的剖面圖。 圖2所示的是根據本發明一實施例，用於封裝積體 路的晶圓層級製程的製程流程圖。 圖3A至3L所示的是圖2之製程中選定步驟的剖面圖。 圖4A至4E所示的是根據本發明各種替代實 裝的刮面圖。 _In Fig. 9B, a plurality of cavities 904 will be formed in the substrate 902. Cavity 904 can be formed using wet or plasma etching, although other suitable techniques can be utilized. The chemical used in the etching process and the crystalline structure of the germanium in the substrate 902 can help control the angle of the sidewalls of the cavity 9〇4. For example, it has been discovered that a germanium crystal structure can help more straight sidewalls and/or help form a sidewall that is approximately perpendicular to the bottom surface of its corresponding cavity. A die attach adhesive 9〇3 is applied to the bottom of the cavity 9〇4 to help adhere the integrated circuit 906 to the bottom surface of the cavity 904' as shown in Figure 9C. In an alternate embodiment, the die attach adhesive 903 is first applied to the integrated body in an individual manner or in the wafer level prior to placing the integrated circuit 906 in the cavity 904. The back surface of circuit 906. Depending on the needs of the particular application, the die attach adhesive may be conductive or non-conductive. In some embodiments, the adhesives of the two types 30 201034154 are simultaneously used in the same package, such that one of the integrated circuits electrically connects a conductive substrate via its bottom surface, while the other integrated body The circuit is electrically isolated from the substrate (discussed below for various applications). In Fig. 9D, a planarized, photoimageable epoxy layer 9〇8 is deposited over the cavity R 904, the substrate 9〇2, and the integrated circuits _. The epoxy layer 908 is preferably su_8, but other suitable materials may also be used. The epoxy layer can extend over the active surface of the integrated circuit 906 and directly contact the active surface of the integrated circuit 9〇6 and can be filled into the cavity 9〇4 in the substrate 9〇2. As previously mentioned, one of the advantages of using a photoimageable epoxy resin (e.g., su_8) is that it has a better degree of control than its use of photolithography. In Fig. 9E, one or more openings 91A are formed in the epoxy layer 908. These openings 91 can be produced in a variety of ways known to those skilled in the art of semiconductor processing. For example, the epoxy layer 908 may be photolithographically patterned and a portion of the epoxy layer 908 may be dissolved using a developer solution. The openings 910 are capable of exposing I/O pads on the active surface of the integrated circuit 906 that are embedded within the epoxy layer 908. Shown in Figure 9F is the formation of interconnect layer 912, which can be implemented using various suitable techniques known in the art. One of the methods similar to the steps described in connection with FIGS. 3F to 3J includes: depositing a seed layer and a photoresist layer; patterning the photoresist layer; and plating a metal for the openings 9 j 〇 A conductor line 912a and a conductor path 912b are formed. In various embodiments, 31 201034154 the interconnect layer 912 electrically connects a plurality of integrated circuit dies 906 embedded in the substrate 9 〇 2 . Then, an additional epoxy layer 918, integrated circuit 922 and/or interconnect layer 916 can be formed over the substrate 〇2, the integrated circuit 〇6' epoxy layer 908, and the interconnect layer 912. . The layers and devices can be arranged in a wide variety of ways, and any of the permutations and features discussed in connection with Figures i through 7C can be utilized to modify any of the aspects of the embodiments shown. For example, the one or more interconnect layers 912 and/or 916 can be used to electrically connect the integrated circuits 9〇6 disposed in the substrate 9〇2 and be embedded in the epoxy resin. Any or all of the integrated circuits 922 within $918. Suitably or unsuitable for use (4) The electrical signal heat pipe is extended from the substrate-based integrated circuit die 906 to any external surface of the integrated circuit package 921. As described previously, various passive devices and active devices, heat pipes, heat sinks, sensors, etc. can be formed or placed in almost any position of the integrated circuit package 921 (for example, on the substrate 9) In the case of 〇2, on the substrate 902, embedded between the epoxy layer 918, etc., the substrate 902 may also be subjected to back grinding or any other operation suitable for reducing the thickness of the substrate 902. Figure 9G shows the additional epoxy tree layer, the interconnect layer, and the integrated circuit after being applied over the substrate 902, the integrated circuit 906, the epoxy layer 9〇8, and the interconnect layer 912. An example of an integrated circuit package of the drawing is shown in Figures 10A to 1D, each of which also includes a substrate having one or more buried integrated circuits. A shows an integrated circuit package ι〇〇〇 comprising: a conductive and conductive 32 201034154 thermal substrate 1002 having a buried integrated circuit 1〇〇4; a planarized photoimageable epoxy layer 1〇〇6; and an interconnect layer 1〇〇8. Integrated circuit seal 1000 may be formed using any of the techniques described in connection with Figures 9 through 9F. The integrated circuit 1004b is disposed on the bottom surface of the cavity 1〇〇5 in the substrate 1002 using the conductive adhesive 1〇12b. The circuit 1 is electrically coupled to the substrate 1002 and/or can dissipate heat to the outer surface of the package using the substrate 1 。 2. Some implementations also include an integrated circuit 1 〇〇 4a ' Electrically insulated from the conductor substrate 1002 by a non-conductor adhesive 10 12a. Although only two integrated circuits are shown in the embodiment shown in the figure; however, it may be disposed in the substrate 1 〇〇 2 There are fewer or more integrated circuits, each of which is electrically coupled to the substrate 1 2 or electrically insulated from the substrate 1002. In various embodiments, the substrate 1 〇 02 can serve as a Electrically grounded connection. The package 1000 includes a ground interconnection 1〇2〇 formed over the epoxy layer 1006 and extending through the epoxy layer ◎ 1006 and electrically coupled to the substrate A ground contact zone 1014 in 1〇〇2. The interconnect 1020 is made of a conductive material (e.g., copper) and may have been formed at least partially during formation of the interconnect layer 1008, as previously described in connection with Figure 9F. The ground contact region 1014 of the substrate 1002 And other portions of the substrate 1〇〇2 are made of tantalum and may be doped to improve their electrical conductivity. To facilitate electrical connection between the substrate 1002 and the ground interconnect 1020, the ground contact region 1014 The doping concentration is substantially higher than one or more other portions of the substrate 1 〇〇 2. In various implementations, the substrate 1 〇〇 2 is made of p 33 201034154 . Contact region 1014 is a p++ doped region; however, substrate 1002 and ground contact region 1014 can also be doped with any suitable material and/or concentration known to those skilled in the art. Thus, when the ground interconnect 1020 is electrically grounded, the integrated circuit 1004b, the substrate 1002, and the ground contact region ι 14 are electrically coupled to the ground interconnect 1020 and are also electrically grounded. Figure 10B provides an enlarged view of area 1010 of Figure 10A, in accordance with one embodiment of the present invention. The figure includes a substrate 1〇〇2 having a lower surface: a ground contact region 1014, an interlayer dielectric 1〇16, a passivation layer 1〇18, a conductive plug 1022, © electrical interconnection lines 1024 and 1020, and an epoxy layer 1 〇〇6 and ground interconnection 1020. Various techniques known to those skilled in the art of semiconductor fabrication can be used to deposit, pattern, and/or develop interlayer dielectric 10 and passivation layer 1018, and form plugs 1022 and electrical interconnects 1〇24. . Plug 1022 and electrical interconnect 1024 may be made of a variety of suitable conductive materials - which comprise tungsten and aluminum, respectively. The epoxy layer 1 〇〇 6 and the interconnect 1 〇 2 〇 can be formed using various techniques including the techniques described in conjunction with Figures 9D through 9F. The technique for forming the interlayer dielectric 1〇16 and the passivation layer 1〇18 of Fig. 10B can be integrated into the technique for forming the cavity 1〇〇5 of Fig. 1A. For example, during formation of cavity 1005, interlayer dielectric ι 16 will be deposited across top surface 1〇〇3 of substrate 1〇〇2. The interlayer dielectric is patterned and etched to not only create space for the plugs 1 and 22, but also to form a mask to form the cavity 〇〇5 in the substrate 1〇〇2. This approach can help reduce the number of processing steps used to fabricate integrated circuit packages. 34 201034154 Another embodiment of the invention is illustrated in Figure 1c. Fig. 10C includes an integrated circuit package 1〇3〇' which forms an integrated circuit, a planarized photoimageable epoxy layer, and an interconnect layer on both sides of a substrate. In the embodiment shown in the drawing, the integrated circuit 1〇36, the epoxy layer 1〇4〇, and the interconnect layer 1038 are formed over the top surface 1〇34 of the substrate 1〇32. The epoxy layer 1 〇 44 and the interconnect layer 1 〇 46 are formed over the reverse bottom surface ι 46 of the substrate 1032. One of the ways to form the integrated circuit package 1030 is to apply the techniques discussed in connection with Figures 9A through 9F over both the top and bottom surfaces of the substrate 1"32. One particular implementation of integrated circuit package 1030 includes arranging a plurality of integrated circuits 'to optically communicate with each other via a light transmissive substrate. In the embodiment shown in the figures, for example, the integrated circuits 310a and 1042a are vertically aligned with each other and include a plurality of optical devices, such as laser diodes, optical detectors, etc. (again In another embodiment, a plurality of optical devices (eg, optical sensors, optical detectors, laser diodes, etc.) may be used instead of the integrated circuits 103a and/or 1〇42a. ). Portions 1〇34 of the substrate at least between the integrated circuits 1〇36& and 1042a are transmissive and are arranged to allow optical communication between the integrated circuits 1〇36a and 1042a. The light transmissive substrate may be made of various materials including glass and quartz. Some modes of operation include a substrate 1 〇32 that is entirely made of a single light transmissive material and/or has a uniform composition. Another way includes a substrate 1032 made of tantalum. The enamel substrate 1032 can electrically insulate the integrated circuits i 〇 36a and 1 〇 42a; however, in the case of 35 201034154, it allows the & μ u ^ | to use ultraviolet light (which can travel through The optical communication is performed. Further, another embodiment of the present invention is illustrated in FIG. 10D. The integrated circuit package 〇5〇 of FIG. 1D has a structure for mitigating being embedded in the package substrate. Inside the 1052 - or a plurality of stress characteristic elements on the integrated circuit 1 〇 54. The integrated circuit package 1 〇 5 〇 includes a substrate 1 〇 52 · cavity 1060, integrated circuit 1054, photo-imageable The epoxy layer 1〇56 and the interconnect layer 1〇58. Each cavity 1〇6〇 includes an air gap 1062 between a sidewall 1064 of the cavity 1〇6〇 and the integrated circuit 1054. © During the test and operation, the integrated circuit 1054 and the package 1〇5〇 will perform a temperature cycling operation. The temperature increase may cause the integrated circuit 1054 and other devices in the package 1050 to expand. 〇54 is encapsulated in a flexible material, this swelling can be Additional stress is imposed on the integrated circuit 1054. The air gap 1 〇 62 can provide space for the integrated circuit 1 〇 54 to expand, and thereby help to reduce this stress. Accordingly, the epoxy layer 1056 The cavity 1060 is covered, but does not extend substantially into the cavity 1060. There are various ways in which the features of the integrated circuit package 1050 can be formed. For example, a cavity 1060 is formed in the substrate 1052 and The placement of the integrated circuit 1 〇 54 in the cavity 1060 can be carried out as previously described in connection with Figures 9A through 9C. Thereafter, a layer of previously fabricated photoimageable epoxy resin can be applied (e.g., SU-8). The enamel will cover the cavity 1060 and the substrate 1052. In various embodiments, the epoxy layer 1056 is not sprayed and spin coated over the cavities 1060, but is laminated Above the base 36 201034154, the plate 1 〇 52. This approach helps to retain the air gap between each of the integrated circuits 1054 and the sidewalls 1 〇 64 of the corresponding cavity VIII 1060. Next, in the epoxy layer 1056 and the mutual The layer 1〇58 can form an opening to be worn. Figure 9E The operation described in JL 9F is performed in the same manner. For example, photolithography can be used to pattern the epoxy layer 1〇56, which causes curing of a portion of the epoxy layer 1056 and The invention has been described in detail herein; however, it should be understood that the invention may be practiced in many forms without departing from the spirit or scope of the invention. Various embodiments may sometimes illustrate unique and distinct features; however, the invention encompasses a wide variety of integrated circuit packages, each of which may each contain virtually any combination of the features described herein and utilize the teachings herein. Almost any combination of the described processes is formed. As an example, the substrate 8〇4 of the integrated circuit package 80A of FIG. 8A including one or more embedded integrated circuits 8〇2 may further include a plurality of metal channels which pass through the substrate 8〇4. And interconnecting the germanium layer 812 electrically connects the contacts on the outer surface of the substrate 804. These metal channels are described in conjunction with Figure 4E. The process for fabricating the metal vias is as described with respect to Figures 5A through 5H and is equally applicable to the substrate 8A of Figure 8A. Therefore, the embodiments of the present invention should be construed as illustrative and not restrictive, and the invention is not limited to the details disclosed herein. Correction 0 [Simple Description of the Drawings] With reference to the above description in conjunction with the accompanying drawings, the advantages of the present invention and 37 201034154 can be best understood, wherein: Figure 1 shows an embodiment in accordance with the present invention. 'A cross-sectional view of a package containing multiple integrated circuits and interconnect layers. 2 is a process flow diagram of a wafer level process for packaging integrated circuits in accordance with an embodiment of the present invention. 3A to 3L are cross-sectional views showing selected steps in the process of Fig. 2. 4A through 4E are plan views of various alternatives in accordance with the present invention. _

圖5A至5H所示的是根據本發明另一實施例用於封穿 積體電路的晶圓層級製程中的選定步驟。 、 6 C所示的是根據本發明另一實施例用於封裝 積體電路的晶圓層級製程中的選定步驟。 圖7A至7C:所不的是根據本發明又一實施例用於封裳 積體電路的晶圓層級製程中的選定步驟。 圖 8A 5 8R — 所不的是根據本發明各種實施例的封裝的5A through 5H are selected steps in a wafer level process for encapsulating an integrated circuit in accordance with another embodiment of the present invention. Shown at 6 C is a selected step in a wafer level process for packaging integrated circuits in accordance with another embodiment of the present invention. Figures 7A through 7C are all selected steps in a wafer level process for sealing a body circuit in accordance with yet another embodiment of the present invention. Figure 8A 5 8R - what is not encapsulated in accordance with various embodiments of the present invention

J面圖# 封裝皆包含一具有埋置積體電路的基板。 圖 9Α至9G所一 71不的是根據本發明另一實施例用於形成 十裝的曰曰圓層級製裎中的選定步驟，#-個封裝皆包含一 具有埋置積體電路的基板。 圖10Α至10D 排列的剖面圖。 所示的是根據本發明各種實施例的封裝 在圖式中’有時候會使用相同的元件符號來表示相同 的、’、》構性兀件。還應該理解的是，圖中所描繪者僅為示意 圖而並未依比例繪製。 38 201034154 【主要元件符號說明】 無J-Picture # The package includes a substrate having a buried integrated circuit. 9 to 9G are not selected in accordance with another embodiment of the present invention for forming a ten-layered tantalum crucible, and each of the #-packages includes a substrate having a buried integrated circuit. Figure 10 is a cross-sectional view of the arrangement of 10D to 10D. The illustrations are shown in the drawings in accordance with various embodiments of the invention, and the same element symbols are sometimes used to refer to the same. It should also be understood that the figures are not intended to be 38 201034154 [Explanation of main component symbols]

❹ 39❹ 39

Claims (1)

201034154 七、申請專利範圍： i.-種積體電路封裝，其包括： 複數個堆疊的巳固化、平坦化介電層; 一電氣裝置，其 、里置在該等介電層中的至少其中一者 裡面； 的互連層’每—個互連層皆埋置在至少—相關聯 的介電層裡面；以及 導…e其疋由導熱材料製成並且埋置在至少一相 關聯的介電層裡面’該導熱管會彎折俾使該導熱管的一第 °p分在一第一方向延伸且該導熱管的-第二部分在一實 質上不同於該第—方 耳 熱耦接@ 1： Μ # h - 11 _ ’其中’該導熱管 μ電虱裝置及該積體電路封裝的至少— 該等複數個堆叠層包含一第一介電層和一第二·介 該導熱管的該第一部分埋置在該第—介電層之 管的該第-部分的長軸實質上平行於該第—介雷居 伸；以及 ’丨1：層 該導熱管的該第二部分埋置在該第二介 導熱管的該第二部分的長軸實質上垂直之中且 伸。 且於該第二介電層 3. 如申請專利範圍第1項之積體電路封裝， 乳裝置是—積體電路晶粒且該導熱管S由銅所製該 4. 如申請專利範圍第丨項之積體電路 眾，其包括： 2·如申請專利範圍第i項之積體電路封裝，‘中：。 該蓉选叙加H i & 層； 201034154 複數個積體電路，每-個積體電路皆埋置在 關聯的介電層裡面；以及 複數個導熱管，該等導熱管中的 笙接骑個導熱管熱裁接該 專積體電路中的多個積體電路和該封 φ ^ 衮中至少一外部表面 中的多個外部表面。 5. 如申請專利範圍第i項之積體電路封裝，其中： 該積體電路封裝包括一安置在該 加 ❿ ❿ 的散熱片;以& f裝的-外部表面上 該導熱管熱耦接該電氣裝置和該散熱片。 6. 如申請專利範圍第5項之積體雷牧& # 埶片县—推 < 檟體電路封裝，其中，該散 … 導體層，其涵蓋範圍實質 直中— I, 因上雷冋於該等介電層中 ^ Ύ 者的涵蓋範圍。 •如申睛專利範圍第1項之積體雷 熱管_傳自料，Μ，該導 得送來自該電氣裝置的電氣資料訊號。 .如申請專利範圍第丨項之積體電封 介電層中的备^ 0 纷封裝，其中，該# 的母一者皆疋由SU-8所製成。 9.如申請專利範圍第 埶管自項之積體電路封裝，其中，該導 …含至少-導熱線路和至少一導熱通道。 導熱管^^專㈣圍第1項之積體電路封裝，其中，該 表面及Γ 電氣裝置和該積體電路封I的-第一外部 面實質：第二外部表面’該第-外部表面及該第二外部表 # ^ ^ „ 其中，忒導熱管調適成用以藉 傳輸熱量以消散來自”： 第二外部表面來 肖政來自該電氣裝置的熱量。 201034154 π·—種積體電路封裝，其包括： 複數個緊密相鄰堆疊的已固化、平坦化、可光成像的 環氧樹脂層； 至少一互連層，每一個互連層皆埋置在一相關聯的環 氧樹脂層裡面並且包含複數條互連線路；201034154 VII. Patent application scope: i.--integrated circuit package, comprising: a plurality of stacked tantalum-cured, planarized dielectric layers; an electrical device, disposed at least in the dielectric layers One of the interconnect layers 'each interconnect layer is embedded in at least the associated dielectric layer; and the conductive layer is made of a thermally conductive material and embedded in at least one associated dielectric layer Inside the electrical layer, the heat pipe is bent such that a second phase of the heat pipe extends in a first direction and the second portion of the heat pipe is substantially different from the first ear. 1: Μ #h - 11 _ 'where 'the heat pipe μ electric device and at least the integrated circuit package - the plurality of stacked layers comprise a first dielectric layer and a second dielectric layer The long axis of the first portion of the tube in which the first portion is buried in the first dielectric layer is substantially parallel to the first portion; and the second portion of the heat conducting tube is embedded in the layer The long axis of the second portion of the second dielectric tube is substantially perpendicular and extendsAnd in the second dielectric layer 3. As described in the first aspect of the patent application, the milk device is an integrated circuit die and the heat pipe S is made of copper. The integrated circuit of the item includes: 2. The integrated circuit package of the item i of the patent application scope, '中:. The Rong Xuanjia Plus H i &layer; 201034154 a plurality of integrated circuits, each of which is embedded in the associated dielectric layer; and a plurality of heat pipes, the bridges in the heat pipes The heat pipe is hot cut to the plurality of integrated circuits in the integrated circuit and the plurality of outer surfaces of the at least one outer surface of the seal φ ^ 。. 5. The integrated circuit package of claim i, wherein: the integrated circuit package comprises a heat sink disposed on the twisted turn; the heat transfer tube is thermally coupled to the outer surface of the & f The electrical device and the heat sink. 6. For example, in the fifth paragraph of the patent application scope, the body of Leimu &#埶片县-推< 槚 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路The coverage of those dielectric layers. • For example, the integrated heat pipe of the first item of the scope of the patent application _ transmitted from the material, Μ, the guide will send the electrical information signal from the electrical device. For example, in the integrated electrical seal dielectric layer of the application scope of the patent application, the mother of the # is made of SU-8. 9. The integrated circuit package of claim 1, wherein the guide comprises at least a heat conducting line and at least one heat conducting channel. The heat conductor tube (4) is an integrated circuit package of the first item, wherein the surface and the electrical device and the first outer surface of the integrated circuit package are substantially: the second outer surface 'the first outer surface and The second external table # ^ ^ „ wherein the heat transfer tube is adapted to transfer heat to dissipate the heat from the second external surface to the heat from the electrical device. 201034154 π--integrated circuit package, comprising: a plurality of closely adjacent stacked cured, planarized, photoimageable epoxy layers; at least one interconnect layer, each interconnect layer being embedded An associated epoxy layer and comprising a plurality of interconnect lines; 複數個I/O觸墊，它們裸露在該封裝的一第一表面上. 一積體電路，其設置在該等環氧樹脂層中的至少其中 一者裡面並且具有一主動表面，其中，該等環氧樹脂層中 的至少其中一者在該積體電路的該主動表面的上方延伸且 該積體電路至少部分經由該至少一互連層被電氣耦接至至 少一相關聯的I/O觸塾；以及 至少一導熱管熱耦接該積體電路和該積體電路封裝的 外部。 12. 如申請專利範圍第u項之積體電路封裝，其包括一 被安置在該封裝的一外部表面上的散熱片，其中，該至少 一導熱管熱耦接該積體電路和該散熱片。a plurality of I/O pads that are exposed on a first surface of the package. An integrated circuit disposed in at least one of the epoxy layers and having an active surface, wherein At least one of the epoxy layers extends over the active surface of the integrated circuit and the integrated circuit is electrically coupled to at least one associated I/O at least in part via the at least one interconnect layer Touching; and at least one heat pipe is thermally coupled to the integrated circuit and the exterior of the integrated circuit package. 12. The integrated circuit package of claim U, comprising: a heat sink disposed on an outer surface of the package, wherein the at least one heat pipe is thermally coupled to the integrated circuit and the heat sink . 13. 如申請專利範圍第u項之積體電路封裝，其中，該 至少-導熱管無法傳送來自該積體電路的電氣資料訊號。 14. -種用於封裝積體電路的晶圓層級方法，該方 括： 在一基板的上方依序沉積多層環氧樹脂，以便在讀 板的上方形成多個平坦化的環氧樹脂層，纟中，該等瑪 樹脂層是藉由旋塗法來沉積，装右一 ^ 躓其有一最頂端的環氧樹脂^ 在至少某些該等環梟谢t 衣氧樹脂層被沉積之後且在下一個 42 201034154 氧樹脂層被沉積之前以光微影方式來圖樣化至少某些該等 環氧樹脂層； 在至少某些該等環氧樹脂層被圖樣化之後且在下—個 環氧樹脂層被沉積之前於至少某些該等已圖樣化的環氧樹 脂層之中形成多個開口； 將一積體電路擺放在該等開口中的一相關聯開口裡 面’其中’該積體電路具有複數個I/O焊接觸墊而且該等環 氧樹脂層中的至少其中一者在擺放該積體電路之後被沉 ® 積’從而覆蓋該積體電路； 形成至少一導電互連層，其中，每一個互連層皆會形 成在一相關聯的環氧樹脂層的上方； 形成至少一導熱管’其中，每一個導熱管皆形成在一 相關聯的環氧樹脂層的上方並且熱耦接該積體電路和一封 裝的至少一外部表面； 形成多個外部封裝接點，其中，該積體電路會至少部 〇 分經由該等導體互連層中的至少其中一者被電氣連接至複 數個該等外部封裝接點；以及 從忒等被依序沉積的環氧樹脂層中形成一積體電路封 裝其中’該至少一導熱管會熱輕接該積體電路和該積體 電路封裝的至少一外部表面。 15.如申凊專利範圍第14項之方法，其中，該至少一互 連層中其中一者的形成是在和該至少一導熱管中其中一者 的形成實質上相同的時間處被實施。 16·如申請專利範圍第14項之方法，其中： 43 201034154 該至少一外部表面包含複數個外部表面； 以及 每一個該等複數個外部表面實質上面向不同的方向； 該至少-導熱管熱輕接該積體電路和每一個該等複數 個外部表面。 17.如申請專利範圍第〗4項之方法，其_ : 該基板是一導體金屬層； ❹ 該^少一導熱管被形成，俾使該積體電路透過該至少 一導熱官來熱耦接該導體金屬層。 18.如申請專利範圍第14項之方法，其巾，該至少 .、、、管中的-第-導熱管彎折’俾使該第一導熱 A:與該第-導熱管中的-第二部分在實質上不同的方 管包Γ-如八申請專利範圍第18項之方法，其中，該第一導熱 管，該等Si:段’該第一導熱管在該處分叉成複數條子 伸。複數條子管中的每-者皆在實質上不同的方向延 〇 2ί)·如申請專利範圍第14項之方 贿層中的每—者皆是…所製成法、、中，該等環氧樹 八、圖式： (如次頁） 4413. The integrated circuit package of claim U, wherein the at least the heat pipe cannot transmit an electrical data signal from the integrated circuit. 14. A wafer level method for packaging an integrated circuit, the method comprising: depositing a plurality of layers of epoxy resin sequentially over a substrate to form a plurality of planarized epoxy layers over the read plate, The resin layer is deposited by spin coating, and has a topmost epoxy resin after the deposition of at least some of the loops of the epoxy resin layer and the next 42 201034154 Patterning at least some of the epoxy layers by photolithography prior to deposition of the oxy-resin layer; at least after some of the epoxy layers are patterned and before at least one epoxy layer is deposited Forming a plurality of openings in some of the patterned epoxy layers; placing an integrated circuit in an associated opening in the openings 'where' the integrated circuit has a plurality of I/O soldering a contact pad and at least one of the epoxy layers is deposited after the integrated circuit is disposed to cover the integrated circuit; forming at least one conductive interconnect layer, wherein each interconnect layer All will Formed on top of an associated epoxy layer; forming at least one heat pipe 'where each heat pipe is formed over an associated epoxy layer and thermally coupled to the integrated circuit and a package At least one external surface; forming a plurality of external package contacts, wherein the integrated circuit is electrically connected to at least the plurality of external package contacts via at least one of the conductor interconnection layers; And forming an integrated circuit package from the sequentially deposited epoxy resin layer, wherein the at least one heat pipe is thermally connected to the integrated circuit and at least one external surface of the integrated circuit package. The method of claim 14, wherein the forming of one of the at least one interconnect layer is performed at substantially the same time as the formation of one of the at least one heat pipe. The method of claim 14, wherein: at least one outer surface comprises a plurality of outer surfaces; and each of the plurality of outer surfaces substantially faces in a different direction; the at least - the heat pipe is hot The integrated circuit and each of the plurality of external surfaces are connected. 17. The method of claim 4, wherein: the substrate is a conductor metal layer; ❹ the heat pipe is formed, and the integrated circuit is thermally coupled through the at least one heat conductor The conductor metal layer. 18. The method of claim 14, wherein the at least one, the - heat pipe bends in the tube, the first heat conduction A: and the first heat pipe The method of claim 18, wherein the first heat pipe, the Si: the first heat pipe is bifurcated into a plurality of slivers Stretch. Each of the plurality of sub-pipes is extended in substantially different directions. · Each of the bribe layers in the 14th paragraph of the patent application is made, ..., the middle, the rings Oxygen tree eight, schema: (such as the next page) 44
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