TW201032484A - Diversity combining iterative decoder - Google Patents
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201032484 六、發明說明: 【發明所屬之技術領域】 本發明概略地相關於無線數位通訊系統,而尤其是有 關運用於此等系統中並且含有疊代解碼器的接收器。 【先前技術】 在無線數位通訊系統中,接收天線的指向對於接收器 效能而言可具有重大影響。有些天線指向可能會造成該信 號無法被接收器運用。一種為了克服此一問題的眾知方式 即為利用「天線分集」。這牵涉到藉兩個以上接收天線來 接收相同的傳送信號,並且在接收器中合併該等信號。在 此一類型接收器中的合併信號通常比起單獨該等組成信號 其一者可擁有較高獲得正確解碼的機率。 在一分集接收器中用以合併信號的最佳方式稱為「最 大比例結合」。此方式為業界所眾知者,並且可溯返至類 Φ 比通訊及真空管的時代。這牽涉到藉其個別的信號雜訊比 以加權各個信號,然後再將這些信號相加合一。其他的次 佳方式既已針對無線數位通訊進行研究,該等相較於該最 大比例結合器具有較低的效能水準然較少的實作複雜度。 一種稱為「區塊式選定」的方式,牵涉到若確實可自該等 信號路徑之任一者獲用,則僅選定一不具位元錯誤的資料 區塊。許多數位通訊系統含有區塊數碼,這些數碼讓接收 器能夠偵測及/或校正資料區塊内的位元錯誤。範例包含 Reed_ Solomon (Rs)數碼及循環冗餘檢查(CRC)數碼。可將 201032484 對於這些數碼之解碼結果運^ 作於來自多個天線 接收器藉以在多個運 選定。區塊式選定雖無法配“輸出間進行區塊式 ..θ ,, ^ ^ 法配比於該最大比例結合的效能, 、: '坦加成性白色高斯雜訊(AWGN)頻道的情 況,然此方式對於許多實際情境而 Ν)頻道的情 下提供顯著的增益。 境而。確施在單一天線情況 已知的刀集合併器通常是 天線的信號。然而,此… 式處理接收自多個 α> mz姐 限於無法利用一解碼器的輸 出來影響另一解碼器的操作。 在數位通訊系統中,常見為利用兩個層級的錯誤校正 編二:-内部數瑪及一外部數碼,而其間設有—交錯器。 般說來’該内部數碼可供校正較短的錯誤事件而該交 錯器及該外部數碼的組合可供校正較長的錯誤事件。例 t ’在根據「先進電視系統委員會(ATSC)」之標準A/5 3所 傳送的數位電視信號裡是利用一内部栅格數碼,且連同於 一交錯器及一外部Reed_solomon數碼。 在傳統的先前技藝接收器中,該等内部解碼器及外部 解碼器係獨立地運作,而其間設有一解交錯器。不過,這 些傳統接收器通常係遠於對它們的個別資料速率和信號帶 寬的Shannon限制而言為多個dB所運作。例如,最佳的傳 統ATSC接收器通常可按「可見度門檻值(τ〇ν)」處理約“ 9 犯的載波雜訊比(C/N),然其Shann〇n限制則約為丨〇 $犯。 部份的此一差異可為肇因於栅格及Reed_s〇1〇m〇n (rs)數碼 本身的限制。然而’此-差異的顯著部份確因傳統的解碼 201032484 m成’此架構並未完全運用於栅格及rs 力。此一先前系統的範例可如圖丨所示。 能 圖1顯示一先前技藝解應1fv _ 突” 碼1〇,其中含有-内部解碼 器12,此者自一信號處理電 鉍拉& . 电峪(禾予圖不)接收其輪入並經 耦接於一解交錯器14’而此解 ΙΑ 交錯器係經顯示為耦接於一 :解碼器16。該内部解碼器12通常❹栅格解碼技術, 收心演算法’藉以部份地解碼自該信號處理電路所 ::言號,而該外部解瑪器16則通常是利用RS解碼技 :二 ekamp-Massey演算法,藉以對出現在該所收 7内的剩餘編碼進行解碼。該外部解碼器16提供被 應予接收且解碼的信號。注旁釗 為 隨M w TSC A/53系統含有― 隨機產生器,因此該外部解碼器 生器(未予圖示)加以處理,如此產解隨機產 =匕們的編碼演算法可為如何優化,該等内部及外部解 仍無法完全地運用所匯集之編碼技術的能 作為該等内部及外部解碼器12及16是彼此獨立地運 編竭^ =強化像是在爪㈢53傳輸#使用之所匯集 的完全能力。在-些先前技藝系統裡,一昼代解 :牵涉到對-外部解碼器輸出進行再交錯、再編碼及再 參昭於藉Γ產生對於一後續内部解碼器的已知輸入,同時 限二騎星(DBS)」標準。前揭先前技藝系統的其-艮制為再編碼處理可能具備有限的記憶艘,因此該外部解 号器輸出内的-錯誤可能造成該經再編碼輸出自該點處起 201032484 向前即為錯誤。在一些傳輸系統中,可藉由該編碼器狀態 係依規則性區間所重置之事實以減緩此一課題。然在許多 傳輸系統裡並非如此,包含在ATSC A/53中所定義者。 其他的先前技藝技術是利用來自一外部解碼器的資訊 以改善一後續内部解碼器的效能,並且宣稱提供按146 dB C/N ’ 一 0.3 dB之増益的ATSC A/53信號之解碼處理。有 些來自該外部解碼器的資訊雖可用於改善内部解碼器效 能’然此一技術並無未完全地運用所有資訊。例如,此技 術並未利用在該Reed-Solomon解碼器之輸出處可獲用的經 可靠校正資料位元。 又在其他的先前技藝技術裡,一疊代解碼器牽涉到再 交錯來自一外部解碼器的一「經標註解碼輸出」,並且利 用以扣減後續内部解碼器中的狀態,同時宣稱對於「數位 視訊廣播(DVB)」標準中所使用之數碼在c/N效能方面具約 1·〇 dB的增益。與此增益相關聯之主要成本是在於為儲存 經延遲輸入並執行再交錯所必要的額外記憶體。在前揭技 術中’各個解碼器疊代要求大量的額外記憶體,同時並未 提供對於一給定疊代次數而用以在記憶體大小與效能進行 取捨的機制。 此外,所有上述先前技藝疊代解碼器皆為針對於單— 輪入情境。 ' — 有鑑於前揭說明,對於利用疊代解碼之分集合併器 需更完全地運用其所匯集之數碼的能力,並且減少記憶= 大小而同時保持或改善效能。而對於此—分集合併器進 201032484 步需要的能夠適用於根據ATSC A/53所傳送的信號 【發明内容】201032484 VI. Description of the Invention: Field of the Invention The present invention relates generally to wireless digital communication systems, and more particularly to receivers for use in such systems and including iterative decoders. [Prior Art] In a wireless digital communication system, the orientation of the receiving antenna can have a significant impact on receiver performance. Some antenna pointing may cause the signal to be unusable by the receiver. A well-known way to overcome this problem is to use "antenna diversity." This involves borrowing more than two receive antennas to receive the same transmitted signal and combining the signals in the receiver. The combined signal in this type of receiver typically has a higher probability of obtaining a correct decoding than one of the constituent signals alone. The best way to combine signals in a diversity receiver is called "maximum ratio combining." This method is well known to the industry and can be traced back to the era of Φ than communication and vacuum tubes. This involves weighting the individual signals by their individual signal-to-noise ratios and then adding the signals together. Other sub-optimal approaches have been studied for wireless digital communications, which have lower performance levels and less implementation complexity than the largest scale combiner. A method called "block selection" involves the selection of only a data block that does not have a bit error if it is indeed available from any of these signal paths. Many digital communication systems contain block numbers that allow the receiver to detect and/or correct bit errors within the data block. Examples include Reed_ Solomon (Rs) Digital and Cyclic Redundancy Check (CRC) numbers. The decoding results of these numbers for 201032484 can be selected from multiple antenna receivers to be selected in multiple operations. Although the block type selection cannot be matched with the "block between the output..θ, ^ ^ method is proportional to the performance of the maximum ratio,": the case of the 'Tenged white Gaussian noise (AWGN) channel, However, this method provides significant gain for many actual situations and channels. Context. It is true that the knife set known in the case of a single antenna is usually the signal of the antenna. However, this method is received from the antenna. Αα> mz sister is limited to the inability to use the output of one decoder to affect the operation of another decoder. In digital communication systems, it is common to use two levels of error correction 2: - internal digital and an external digital, and In the meantime, there is an interleaver. Generally speaking, the internal digital can be used to correct a short error event and the combination of the interleaver and the external digital can be used to correct a long error event. Example t' is based on the "Advanced Television System" The digital television signal transmitted by the standard (ATS) of the Commission (ATSC) utilizes an internal grid number and is coupled to an interleaver and an external Reed_solomon digital. In conventional prior art receivers, the internal decoders and external decoders operate independently with a deinterleaver therebetween. However, these conventional receivers typically operate at multiple dBs over the Shannon limits for their individual data rates and signal bandwidths. For example, the best traditional ATSC receiver can usually handle the carrier noise ratio (C/N) of about 9 according to the "visibility threshold (τ〇ν)", but the Shann〇n limit is about 丨〇$ Part of this difference can be due to the limitations of the grid and Reed_s〇1〇m〇n (rs) digital itself. However, the significant part of this difference is indeed due to the traditional decoding 201032484 m The architecture is not fully applicable to grid and rs forces. An example of this prior system can be shown in Figure 能. Figure 1 shows a prior art solution 1fv _ ” ” code 1〇 containing the internal decoder 12, The 自 交错 交错 amp amp 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收Decoder 16. The internal decoder 12 is typically a raster decoding technique in which the heart algorithm "is partially decoded from the signal processing circuit:: the word number, and the external hacker 16 typically utilizes the RS decoding technique: two ekamp - Massey algorithm to decode the remaining codes appearing within the received 7 . The external decoder 16 provides a signal that should be received and decoded. Note that the M w TSC A/53 system contains a random generator, so the external decoder generator (not shown) is processed, so that the yield is randomized = our coding algorithm can be optimized The internal and external solutions still cannot fully utilize the incorporated coding techniques as the internal and external decoders 12 and 16 are independently programmed to each other. ^=Enhanced image is used in the claw (3) 53 transmission # The full capacity of the collection. In some prior art systems, a one-of-a-kind solution involves interleaving, re-encoding, and re-encoding the output of the external decoder to generate a known input for a subsequent internal decoder, while limiting the ride. Star (DBS) standard. The pre-existing prior art system may have a limited memory bank for the re-encoding process, so the error in the output of the external decipherer may cause the re-encoded output to be an error from the point of 201032484. . In some transmission systems, this problem can be mitigated by the fact that the encoder state is reset by a regular interval. This is not the case in many transmission systems and is included in the ATSC A/53. Other prior art techniques utilize information from an external decoder to improve the performance of a subsequent internal decoder and claim to provide decoding processing of the ATSC A/53 signal at a benefit of 146 dB C/N '- 0.3 dB. Some of the information from this external decoder can be used to improve the internal decoder performance. However, this technology does not fully use all the information. For example, this technique does not utilize reliable corrected data bits available at the output of the Reed-Solomon decoder. In still other prior art techniques, an iterative decoder involves reinterleaving an "annotated decoded output" from an external decoder and utilizing to deduct the state in the subsequent internal decoder while asserting for "digital" The digital used in the Video Broadcasting (DVB) standard has a gain of about 〇 dB in terms of c/N performance. The primary cost associated with this gain is the additional memory necessary to store the delayed input and perform the re-interlacing. In the prior art, 'decoder aliasing requires a large amount of additional memory, and does not provide a mechanism for trade-off between memory size and performance for a given number of iterations. In addition, all of the above prior art iterative decoders are directed to a single-round scenario. In view of the foregoing, the ability to more fully utilize the digitals it collects for the use of iterative decoding and reduce the memory = size while maintaining or improving performance. For this, the components required for the step-by-step integration into the 201032484 can be applied to the signals transmitted according to the ATSC A/53.
簡言之,在本發明之一具體實施例裡,一種叠代解碼 器電路’纟包含N個子解碼器,該等子解碼器中個各 者回應於-來自Μ個信號處理電路之其一者的基帶信號。 該等N-i個子解碼以者包含:―内部延遲,此者回應於 一由一相重十應信號處理電路所提供的基帶信冑以產生一内 部延遲信號;-經修改解碼器’此者接收該内部延遲信號 並且產生-設定分割信號’該設定分割信號之—部份比起 先前的設定分割信號具有較少錯誤。一第N個内部延遲係 回應於該基帶信號並且提供一第N個内部延遲信號。一第N 個經修改解碼器回應於該_則固内部延遲信號及該設定分 割信號’並且提供一輸出信號’纟中可藉由校正在部份該 等設定分割信號内之錯誤以降低該輸出信號的錯誤機率。 自下列參照於多份圖式之較佳具體實施例詳細說明, 將即能顯知本發明的前揭及其他目的、特性與優點。 【實施方式】 為克服前揭先前技藝中的限制,並且克服其他自閱讀 及暸解本申請文件後所能顯知的限制,本發明揭示一種用 以對一利用疊代解碼技術自一天線或自多個天線所收到之 信號進行解碼的設備及方法,藉此在低信號雜訊比下能造 成降低的位元錯誤率,而同時減少記憶體要求。即如本揭 9 201032484 所使用者,雜訊是指所不欲之資料,或是不應為該經傳送 且欲予接收之信號的一部份之資料,此屬無意義者。 在後載申請專利範圍中’特徵描述本發明之該等和其 他新賴優點與特性係按特定方式所指明,並且構成本發明 的一部份。然為更佳地瞭解本發明、其優點與其經運用而 可獲致之目的’在此參照於構成本發明之進一步部份的圖 式’同時參照於隨附說明項目,其中說明且描述本發明具 體實施例的特定範例。 圖2顯示一信號處理電路22,此者接收根據「先進電 視系統委員會(ATSC)」之標準A/53所廣播的數位地面電視 信號。在圖2中,一信號處理電路22係經顯示為含有一調 諸器201、一類比至數位(A/D)轉換器203、一基帶混合器 2〇4、一載波復原電路206、一時序復原電路2〇5及一調適 性等化器207。該調諧器接收射頻(RF)輸入2〇〇,並且將一 中頻(IF)信號202提供至該者所耦接的a/D轉換器203。該 A/D轉換器203係耦接於該調諧器201及該基帶混合器2〇4 兩者β該A/D轉換器203在一並非與遠端傳送器同步的速 率下對該類比IF信號進行取樣,藉以產生一數位IF信號。 然後將該數位IF信號傳至該基帶混合器2〇4 ^該基帶混合 器204將該數位IF信號下行轉換至基帶,並將下行轉換之 基帶信號傳至該者所耦接的時序復原電路205。該基帶混合 器204係耦接於該a/D轉換器203、該時序復原電路205 及該載波復原電路206。該載波復原電路206係耦接於該基 帶混合器204及該時序復原電路2〇5。該載波復原電路可用 201032484 205 〜器同步於該1波頻率。該時序復原電路 ’、,’生接於該基帶混合器204及該調適性等化器2〇7, 並且用以在一同步於該遠端傳送器的速率下對該下行轉換 之基帶信號進行再取樣。該時序復原電路205自動地更新 其再取樣速率以維持與該遠端傳送器的同步性。該調適性 等化器=7係輛接於該時序復原電路2()5,並且為在該信號 離開該&號處理電路22而前往該叠代解碼器電路Μ之前 的最終處理步驟。該調適性等化ϋ斯自該信號移除掉多 重路徑扭曲以及其他形式的符號間干擾(isi卜在2⑼7年^ 月5曰所提申,標題為「dynamic DETECTION DEVICE AND METHOD」之美國專利申請案第 ll/620,226號案文中提供該信號處理電路22的進一步細 節,茲將該案揭示併入本案作為整體說明以當參考。Briefly, in one embodiment of the invention, an iterative decoder circuit '纟" includes N sub-decoders, each of which responds to - from one of the signal processing circuits Baseband signal. The Ni sub-decodings include: an "internal delay" in response to a baseband signal provided by a phase-receiving signal processing circuit to generate an internal delay signal; - a modified decoder that receives the The internal delay signal and the generation-set split signal 'the set split signal' are partially less erroneous than the previous set split signal. An Nth internal delay is responsive to the baseband signal and provides an Nth internal delay signal. An Nth modified decoder responds to the _th solid internal delay signal and the set split signal 'and provides an output signal 纟 to reduce the output by correcting errors in some of the set split signals The probability of a signal error. The foregoing and other objects, features and advantages of the present invention will become apparent from the Detailed Description of Description [Embodiment] To overcome the limitations of the prior art, and to overcome other limitations that can be apparent from the reading and understanding of the present application, the present invention discloses a method for utilizing an iterative decoding technique from an antenna or a self. Apparatus and method for decoding signals received by multiple antennas, thereby enabling a reduced bit error rate at low signal to noise ratios while reducing memory requirements. That is, if the user is a user who does not want the information, or should not be part of the signal transmitted and intended to be received, this is meaningless. The features and other features and characteristics of the present invention are set forth in a particular form and form part of the invention. For a better understanding of the invention, the advantages thereof, and the advantages thereof, which are utilized in the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; A specific example of an embodiment. Figure 2 shows a signal processing circuit 22 that receives digital terrestrial television signals broadcast according to Standard A/53 of the Advanced Television Systems Committee (ATSC). In FIG. 2, a signal processing circuit 22 is shown to include a modulator 201, an analog to digital (A/D) converter 203, a baseband mixer 2〇4, a carrier recovery circuit 206, and a timing sequence. The recovery circuit 2〇5 and an adaptive equalizer 207. The tuner receives a radio frequency (RF) input 2 〇〇 and provides an intermediate frequency (IF) signal 202 to the a/D converter 203 to which the person is coupled. The A/D converter 203 is coupled to the tuner 201 and the baseband mixer 2〇4. The A/D converter 203 compares the analog IF signal at a rate that is not synchronized with the remote transmitter. Sampling is performed to generate a digital IF signal. The digital IF signal is then passed to the baseband mixer 2〇4. The baseband mixer 204 downconverts the digital IF signal to baseband and transmits the downlink converted baseband signal to the timing recovery circuit 205 to which the partner is coupled. . The baseband mixer 204 is coupled to the a/D converter 203, the timing recovery circuit 205, and the carrier recovery circuit 206. The carrier recovery circuit 206 is coupled to the baseband mixer 204 and the timing recovery circuit 2〇5. The carrier recovery circuit can be synchronized to the 1 wave frequency with 201032484 205. The timing recovery circuit ',' is coupled to the baseband mixer 204 and the adaptive equalizer 2〇7, and configured to perform the downlink converted baseband signal at a rate synchronized with the remote transmitter. Resample. The timing recovery circuit 205 automatically updates its resampling rate to maintain synchronism with the remote transmitter. The adaptor equalizer = 7 is connected to the timing recovery circuit 2 () 5 and is the final processing step before the signal leaves the & processing circuit 22 and goes to the iterative decoder circuit. The adaptive equalization of the Muse removes the multipath distortion and other forms of intersymbol interference from the signal (Isis is filed in 2(9) 7 years ^ 5 曰, US Patent Application entitled "dynamic DETECTION DEVICE AND METHOD" Further details of the signal processing circuit 22 are provided in the text of the ll/ 620, 226, the disclosure of which is hereby incorporated by reference in its entirety.
在該信號處理電路22的一替代性具體實施例裡,該 A/D取樣速率係同步化於該遠端傳送器。此具體實施例可消 除對於該時序復原電路205的需要。進一步替代性具體實 施例含有一自動增益控制(AGC)、數位濾波器及各種同步化 電路。在替代性具體實施例中,可將不同的通訊系統及不 同的彳s號處理組態納入考量。在此雖既已揭示該信號處理 電路22的一具體實施例,然應瞭解熟諳本項技藝之人士考 量確能構思其他的具體實施例。 現參照圖3’根據本發明之一具體實施例,一接收器 20係經顯示為含有複數個信號處理電路22,各者自一個別 天線接收一輸入而柄接於一經修改疊代解瑪器電路24。該 201032484 疊代解碼器電路24係運作如一分集合併器。 該等複數個信號處理電路22係_;為含有N個信號 處理電路48_52’此NL。各個信號處理電路係經顯 示為自-相對應天線接收-輸入。例如該第一信號處理電 路48係經顯示為自—天線ANT #1接收其輸人該第二信 號處理電路50係經顯示為自-天線ANT #2接收其輸入, 而該第N信號處理電路52係經顯示為自一天線膽州接 收其輸入等等。即如圖^可利用任意數量的天線以自此 接收該㈣,並且制相對應數量的信號處理電路以自一 相對應天線接收該信號。亦考量到該等n㈣號處理電路 之一或更多者本身可具備多個天線輸人,並且利用最大比 例結合或其他技術以進行第_階的分集合併。《了本發明 之目的具備多重天線輸入之單-信號處理電路的輸出 被視為與一具備單—JC. 天線輸入之皁一信號處理電路者相 同。而為簡化本說明書之㈣’該信號處理電路係經描述 且說明為具有[天線輸人。㈣,即如熟諳本項技藝之 所眾去纟在本發明之替代性具體實施例裡,任何戍 所有的信號處理電路皆可具傷多重天線輸人。 ’ 該等k號處理電路22各者可用以將其自一射頻⑽)信 號所收到的信號轉換成一適於由該叠代解碼器電路進行解 碼的數位基帶信號。該等信號處理電路各者所收到的作號 通常因所運用的解碼技術本f之故而經交錯q而必^ 該接收器20予以躲吞^ ^ 乂錯。該等信號處理電路22各者產生 數位基帶#號以由該疊代解碼器電路24進行解碼。 12 201032484 在圖3中,該疊代解碼器電路24係經顯示為含有\個 子解碼器,該等子解碼器26、34及46各者係經耦接以自 一個別信號處理電路22接收輸入。例如,該子解碼器26 係經顯示為自該信號處理電路48接收輸入,該子解竭器34 係經顯示為自該信號處理電路5〇接收輸入,而該子解碼器 46係經顯示為自該信號處理電路52接收其輸入。 該等信號處理電路22各者產生一基帶信號,此信號係In an alternate embodiment of the signal processing circuit 22, the A/D sampling rate is synchronized to the remote transmitter. This particular embodiment eliminates the need for the timing recovery circuit 205. A further alternative embodiment includes an automatic gain control (AGC), a digital filter, and various synchronization circuits. In alternative embodiments, different communication systems and different 彳s number processing configurations can be considered. Although a specific embodiment of the signal processing circuit 22 has been disclosed herein, it will be appreciated that those skilled in the art will be able to contemplate other embodiments. Referring now to Figure 3, in accordance with an embodiment of the present invention, a receiver 20 is shown as comprising a plurality of signal processing circuits 22, each receiving an input from a different antenna and being coupled to a modified iterative gema Circuit 24. The 201032484 iterative decoder circuit 24 operates as a sub-collector. The plurality of signal processing circuits 22 are _; containing N signal processing circuits 48_52' NL. Each signal processing circuit is shown as a self-corresponding antenna receive-input. For example, the first signal processing circuit 48 is shown as receiving its input from the antenna ANT #1. The second signal processing circuit 50 is shown as receiving its input from the antenna ANT #2, and the Nth signal processing circuit is received. The 52 series is shown to receive its input from an antenna biliary state, and the like. That is, as shown in Fig. 2, any number of antennas can be utilized to receive the (4) therefrom, and a corresponding number of signal processing circuits are received from the corresponding antenna. It is also contemplated that one or more of the n(d) processing circuits may themselves have multiple antenna inputs and utilize a maximum ratio combining or other technique to perform the fractional ordering of the first order. The output of the single-signal processing circuit having multiple antenna inputs for the purpose of the present invention is considered to be the same as that of a soap-signal processing circuit having a single-JC. antenna input. To simplify the description of the present specification, the signal processing circuit has been described and illustrated as having [antenna input. (d), that is, in the alternative embodiment of the present invention, any of the signal processing circuits can be inflicted with multiple antenna inputs. Each of the k processing circuits 22 can be used to convert the signal it receives from a radio frequency (10) signal into a digital baseband signal suitable for decoding by the iterative decoder circuit. The numbers received by each of the signal processing circuits are usually interleaved by the decoding technique used, and the receiver 20 is obscured. Each of the signal processing circuits 22 generates a digital baseband # number for decoding by the iterative decoder circuit 24. 12 201032484 In FIG. 3, the iterative decoder circuit 24 is shown as containing \ sub-decoders, each of which is coupled to receive input from a separate signal processing circuit 22. . For example, the sub-decoder 26 is shown as receiving input from the signal processing circuit 48, the sub-destroyer 34 is shown receiving input from the signal processing circuit 5, and the sub-decoder 46 is shown as The input is received from the signal processing circuit 52. Each of the signal processing circuits 22 generates a baseband signal, and the signal system
❹ 提供至一相對應子解碼器的一相對應内部延遲。例如,該 信號處理電路48的輸出係一基帶信號23,此者係提供至該 子解碼器26的内部延遲28。同樣地,該信號處理電路二 的輸出係-基帶信號35,此者係經提供至該子解碼器^的 内部延遲36以作為輸入,同時該信號處理電路52的輸出 係一基帶信號41’此者係經提供至該子解碼器心内部延 遲42以作為輸入。 該等N個子解碼n的各個内部延遲產生—内部延遲信 號通並提供至-其㈣接的經修改解例如,該内部 延遲28係、_示為產生—内部延遲信號.並將此 至該經修轉M 3G。該㈣延遲%係 内' 部延遲信號”,並將此者提供至該經修改解碼器3產8: 該㈣延遲42係經顯示為產生該内部延遲信號器43 = 者提供至該經修改解碼器44, ’ ^ 輸出信號45,而此幹出…/解竭器係經顯示為提供該 延遲信號^ 定延遲。該内部延遲信號信號分別地具有固 固疋延遲可視需要而予設定 13 201032484 為零,藉以自該叠代解碼器電路2G移除該内部延遲a。 該=N個子解碼器中之個的經修改解碼器各者產 疋刀割信號,並且將此者提供至一其所耦接的外部 延遲/換言之,該等N個子解碼器之經修改解碼器各者: 除最後或第N個經修改解碼器外,皆產生一設定分割信號。 該等叹定分割信號31及33係經一可變延遲所延遲, 藉此產生經延遲的設定分割信號54及2卜這些是用以從一 後續子解碼器的考量中消除—些符號。若因該子解瑪器中 的失效而無法獲用可靠的設定分割資訊,則會在該設定分 割信號表述此一失效。 現參照於圖3具體實施例以特定說明,該經修改解碼 器30係經顯示為產生一設定分割信號3丨,並且將該者提供 至該外部延遲32。該經修改解碼器38係經顯示為產生—設 定分割信號33,並且將該者提供至該外部延遲4〇。該子2 碼器34的設定分割信號33比起該子解碼器26的設定分割 k號3 1具有較低的錯誤機率,原因是各個經修改解碼器皆 具備自受惠於一先前子解碼器結果之信號中移除額外錯誤 的能力。換句話說,在本發明的各式具艚實施例裡,像是 圖3、12、14及15者,在一些設定分割信號之内的錯誤會 被相對於前行設定分割信號所校正。從而能夠有利地降低 整體錯誤機率,或在圖3具體實施例裡為該信號45内的錯 誤機率,而這相比於先前技藝疊代解碼技術具有較低的每 —子解碼器製造成本。 即如本揭中所使用者,可靠性是描述一具有最少錯誤 201032484 的設定分割信號。在本發明之一具體實施例裡可靠性描 述含有極低的錯誤機率(le_10或以下的數階卜例如一 Reed-Solomon (RS) (207、187)數碼字組,像是該 atsc A,” 系統所使用者,若並未被一唯錯Rs解碼器(亦即一並無先 驗錯誤位置資訊的RS解碼器)積測到無法校正錯誤則屬可 靠者。 在本發明之-替代性具體實施例裡,其中是使用一錯 ❹ ❹ 誤及消除(em>r-and_erasures) RS解碼器(亦即一利用一先 驗錯誤位置資訊的RS解碼器),沒有偵測出無法校正錯誤 的數碼字組並*必然地確為可靠,原因在於有些錯誤及消 除計數的組合具有高度的假解碼機率。當在錯誤校正之後 決定該數碼?組究料可#或不可㈣,必須將此假解碼 機率納入考量。 該第-經修改解瑪器’或圖3的經修改解碼器3〇,產 生最低可靠的設^分割信號(具有最高的錯誤機率該第二 經修改解碼器’或該經修改解碼@ 38,產生—設定分割作 號,此者比起該解碼器3G具有較低的錯誤機率然比起後 續子解碼器的設定分割信號具有較高錯誤機率等等。 該等N個子解碼器之N]個各者的外部延遲回應於一 :對應設定分割信號,並且運作以對—後續子解碼器的經 解碼器產生―經延遲較分割信號。例如,在圖3中, =料器26料部延遲32係經㈣為接收該設定分割 化號3 1 ’同時產生— 至該子解Μ ^ 以遽54且將該者提供 解瑪器34的經修改解喝器38。該子解碼器34的外 15 201032484 部延遲40係經顯示為接收該設定分割信號”,同時產生一 經延遲設定分割信號21且將該者提供至該子解碼器46的 經修改解碼器44。該等經延遲設^分割信號^2】具有 ㈣於該等設定分割信號31及33的可變延遲。此可變延 遲是由在料料遲電路之㈣位址邏輯所㈣,即如後 文所述。 圖3具體實施例之M個内部延遲28、%及42各者係 一傳統延遲線$,即如業界所幕知纟。各個内部延遲可含 有一單-延遲線路或-多個較小延遲線路的組合。該等β 〇 部延遲各者可令其|帶信號輸入在提供至一$内部延遲所 耦接的經修改解碼器之前先延遲一預定(或固定)時段。 在本發明之一具體實施例裡,該固定延遲可經設計以 補償一子解碼器的最劣情況延遲。對於根據ATSC Α/53所 傳送的信號,一補償該最劣情況子解碼器延遲的固定延遲 為43884個符號。又在另一具體實施例裡,可選擇一較大 延遲以補償較長的處理延遲。在更進一步具體實施例裡, 可選擇一不會補償該最劣情況子解碼器延遲的較短延遲。 ❹ 然而’當利用此一延遲時’有時將無法及時地獲用該設定 分割信號以由後續子解碼器使用,且因此必須由後續子解 碼器視為不可靠所對待。 圖3具體實施例的Ν-1個外部延遲32及40各者比起 该等内部延遲較為複雜’原因在於該經修改解碼器内的解 交錯處理程序,即如後文中所進一步詳細討論者。一示範 性外部延遲的進一步細節可按如圖9及11所提供且討論。 16 201032484 ,在一示範性應用裡,該接收器20係運用於一無線通訊 系統中,並且輸入至該信號處理電路22的信號為數位地面 電視信號’像是由「先進電視系統委員會(ATS。)」採用之 已知,準A/53所定義者。後文中進-步討論此-應用。 操作上,該接收器2〇透過其N個天線接收一信號並 且該等N個天線各者將所收信號提供至該等信號處理電路 22之一相對應者,然後再由此者處理該所收信號,同時將 基帶信號提供至該等相對應子解碼$ 26、34、46的—内部 延遲28、36、42。該等内部延遲將該基帶信號延遲一量值, 該量值係決定於子解碼器之最劣處理延遲,以及於記憶體 大小與可靠設定分割信號之可獲用性之間的所欲取捨情 況。接著,經該内部延遲所延遲之後’將該基帶信號提供 至一相對應的經修改解碼器,此者足以產生像是該信號3 ^ 或33的設定分割信號,而該信號足以對後續子解碼器提供 足夠資訊,藉以按一給定符號區間之考量而消除部份的群 集點。在本發明之一具體實施例裡,該設定分割信號由兩 個子信號所組成。該第一子信號含有對於各個所收符號的 設定分割資訊,而其中該資訊可或無須為可靠者。該第二 子信號則含有一對於一所收符號區塊的可靠性指示器。就 以根據ATSC A/53所傳送的信號來說,會對各個具有828 個符號的區塊,即對應於一 207個位元組的Reed s〇i〇m〇n 數碼字組,產生一可靠性指示器。總結而言,各個子解碼 器的設定分割輸出比起先前的子解碼器會擁有較高或相等 的可靠性。 17 201032484 圖4顯不一時序圖,其中說明Reeds〇1〇in〇n解碼器輪 - 出如何地關聯於該等設定分割信號。圖4中顯示出六個信 號:RS_fail 301、RS一out[7:0] 302、syml 303、symO 304、 set一part 305、set_part_rel 30ό。RS_fail 301 係一 1 位元信 號。當该RD解瑪器偵測到無法校正錯誤時,該信號3 〇丨會 被設定為1。RS一Out[7:0] 302為該RS解碼器的一 8位元輪 出位元組。Syml 303為符號資料的最大有效位元(圖6之 ATSC A/53 Part 2圖6.8中的X2)。SymO 304為符號資料的 最低有效位元(圖6之ATSC A/53 Part 2圖6.8中的XI)。 ❾ Set_part 305為設定分割信號,即等於Sym〇 3〇4。❹ Provide a corresponding internal delay to a corresponding sub-decoder. For example, the output of the signal processing circuit 48 is a baseband signal 23 which is provided to the internal delay 28 of the sub-decoder 26. Similarly, the output of the signal processing circuit 2 is a baseband signal 35, which is provided as an input to the internal delay 36 of the sub-decoder, while the output of the signal processing circuit 52 is a baseband signal 41' The internal delay 42 is provided to the sub-decoder as an input. The respective internal delays of the N sub-decodes are generated - the internal delay signal is supplied and provided to - the modified solution of the (four) connection, for example, the internal delay 28 is, - is shown to generate - an internal delay signal. Repair M 3G. The (d) delay % is the 'partial delay signal' and provides this to the modified decoder 3 to produce 8: the (four) delay 42 is shown to produce the internal delay annunciator 43 = provided to the modified decoding 44, ' ^ output signal 45, and the dry out ... / decommissioner is shown to provide the delayed delay of the delayed signal. The internal delayed signal signal has a solid delay delay, respectively, which can be set as required 13 201032484 Zero, by which the internal delay a is removed from the iterative decoder circuit 2G. Each of the modified decoders of the =N sub-decoders produces a knife-cut signal and provides this to a coupled The external delay/in other words, the modified decoders of the N sub-decoders: each of the last or the Nth modified decoder, generates a set split signal. The singular split signals 31 and 33 are Delayed by a variable delay, thereby generating delayed set split signals 54 and 2 which are used to remove some symbols from a subsequent sub-decoder consideration. If due to a failure in the sub-solver Unable to use reliable settings The failure is expressed in the set split signal. Referring now to the specific embodiment of FIG. 3, the modified decoder 30 is shown to generate a set split signal 3 丨 and the person provides the External delay 32. The modified decoder 38 is shown as generating - setting the split signal 33 and providing the one to the external delay 4. The set split signal 33 of the sub-coder 33 is compared to the sub-decoder Setting 26 split k number 3 1 has a lower probability of error because each modified decoder has the ability to remove extra errors from signals that benefit from a previous sub-decoder result. In other words, in this In the various embodiments of the invention, as in Figures 3, 12, 14 and 15, errors in some of the set split signals are corrected relative to the forward set split signal, thereby advantageously reducing overall errors. The probability, or in the embodiment of Figure 3, is the probability of error within the signal 45, which has a lower per-sub-decoder manufacturing cost compared to prior art iterative decoding techniques. Reliability is a description of a set split signal with minimal error 201032484. In one embodiment of the invention the reliability description contains a very low probability of error (le_10 or less) such as a Reed-Solomon (RS) (207 187) a digital block, such as the atsc A," the system user, if not detected by a faulty Rs decoder (that is, an RS decoder without a priori error location information) The error is reliable. In an alternative embodiment of the invention, an error correction and elimination (em > r-and_erasures) RS decoder is used (i.e., using a priori error location information). The RS decoder) does not detect digital blocks that cannot be corrected for errors and is necessarily necessarily reliable because the combination of some errors and elimination counts has a high probability of false decoding. When the error is corrected, the number is determined? The group can be # or not (4), and this false decoding probability must be taken into account. The first modified numerator 'or the modified decoder 3 of FIG. 3 produces a least reliable set split signal (the second modified decoder with the highest probability of error ' or the modified decoding @ 38, Generate - set the split number, which has a lower error probability than the decoder 3G and has a higher error probability than the set split signal of the subsequent sub-decoder, etc. N] of the N sub-decoders The external delay of each responds to one: correspondingly sets the split signal, and operates to generate a delayed-rectified split signal for the decoder of the subsequent sub-decoder. For example, in Figure 3, the hopper 26 has a delay of 32. The modified decanter 38 of the sub-decoder 34 is provided by (4) for receiving the set partition number 3 1 'at the same time - to the sub-extraction ^ 遽 54 and providing the defragmenter 34. The 201032484 section delay 40 is shown as receiving the set split signal", while generating a delayed set split signal 21 and providing the one to the modified decoder 44 of the sub-decoder 46. The delay-set split signal ^ 2] has (d) in these settings The variable delay of signals 31 and 33. This variable delay is determined by the (four) address logic of the material delay circuit (4), as will be described later. Figure 3 shows the internal delays 28, % and 42 of the specific embodiment. Each is a conventional delay line $, as is known in the industry. Each internal delay can contain a single-delay line or a combination of multiple smaller delay lines. Each of these beta delays can be made to | The band signal input is delayed by a predetermined (or fixed) period before being provided to the modified decoder coupled to an internal delay. In one embodiment of the invention, the fixed delay can be designed to compensate for a sub-decode. The worst case delay of the device. For a signal transmitted according to ATSC Α/53, the fixed delay for compensating for the worst case sub-decoder delay is 43884 symbols. In another embodiment, a larger one can be selected. Delay to compensate for longer processing delays. In still further embodiments, a shorter delay that does not compensate for the worst case sub-decoder delay may be selected. ❹ However, 'when using this delay' sometimes cannot Get this setting in time The signal is split for use by subsequent sub-decoders and must therefore be treated as unreliable by subsequent sub-decoders. The Ν-1 external delays 32 and 40 of the Figure 3 embodiment are more complex than the internal delays. 'The reason is that the de-interlacing process within the modified decoder, as discussed in further detail below. Further details of an exemplary external delay can be provided and discussed in Figures 9 and 11. 16 201032484, in a In an exemplary application, the receiver 20 is used in a wireless communication system, and the signal input to the signal processing circuit 22 is a digital terrestrial television signal 'like the one used by the Advanced Television Systems Committee (ATS). Know, the person defined by A/53. In the following article, we will discuss this-application. Operationally, the receiver 2 receives a signal through its N antennas and each of the N antennas provides a received signal to a corresponding one of the signal processing circuits 22, and then processes the The signal is received while the baseband signal is provided to the internal delays 28, 36, 42 of the corresponding sub-decodes $26, 34, 46. The internal delay delays the baseband signal by a magnitude that is determined by the worst processing delay of the sub-decoder and the desired trade-off between the size of the memory and the availability of the reliably set split signal. . Then, after being delayed by the internal delay, the baseband signal is provided to a corresponding modified decoder, which is sufficient to generate a set split signal like the signal 3^ or 33, and the signal is sufficient to decode the subsequent sub-sequence The device provides enough information to eliminate some of the cluster points by considering a given symbol interval. In one embodiment of the invention, the set split signal is comprised of two sub-signals. The first sub-signal contains set split information for each received symbol, wherein the information may or may not be reliable. The second sub-signal then contains a reliability indicator for a received symbol block. In the case of signals transmitted according to ATSC A/53, a reliable block is generated for each block having 828 symbols, ie, a Reed s〇i〇m〇n digital block corresponding to a 207 byte. Sex indicator. In summary, the set split output of each sub-decoder will have higher or equal reliability than the previous sub-decoder. 17 201032484 Figure 4 shows a different timing diagram illustrating how the Reeds〇1〇in〇n decoder wheel is associated with the set split signal. Six signals are shown in Figure 4: RS_fail 301, RS-out[7:0] 302, syml 303, symO 304, set-part 305, set_part_rel 30ό. RS_fail 301 is a 1-bit signal. When the RD numerator detects an uncorrectable error, the signal 3 〇丨 is set to 1. RS-Out[7:0] 302 is an 8-bit round-out tuple of the RS decoder. Syml 303 is the most significant bit of the symbol data (X2 in Figure 6.8 of ATSC A/53 Part 2 of Figure 6). SymO 304 is the least significant bit of the symbol data (XI of Figure 6 in ATSC A/53 Part 2, Figure 6.8). ❾ Set_part 305 is the set split signal, which is equal to Sym〇 3〇4.
Set一part一rel 306為設定分割可靠性信號,即等於Rs_fau 30卜在本例中,二進位「丨」表示一不可靠設定分割信號。 該等信號set_part 305及set— part_rel 306會被儲存在外部 延遲記憶體内’這在圖14中將進一步詳細討論。 圖4顯示一樣本情境,其中標示為「〇χΑ6」的第—位 元組為一經可靠地解碼(亦即並未偵測到無法校正錯誤)之 第一 Reed-Solomon數碼字組的最後位元組’而標示為 ❹ 「OxB 1」的第二位元組為一無法被可靠地解碼(亦即偵測到 無法校正錯誤)之第二Reed-Solomon數碼字組的第一位元 組。syml及sym〇的層級可藉由將該等8位元位元組劃分 成多個2位元符號所導出,而以最大有效位元為開始。 圖5顯示,根據本發明之一具艎實施例’該等N個經 修改解碼器之各者的進一步細節。在圖5中,一經修改解 碼器60係經顯示為含有一經修改内部解碼器62,此者係經 18 201032484 顯示為柄接於—解交錯器64,此解 於一經修改外部解^ 15係經顯示為耦接 1聊崎1§ 66。該經修改解猓 解碼器38相同。為冑# # s _ '器60與該經修改 J為簡化起見,該經修改解^ @ 它就是該經修改解碼器38而加以解釋,而解:器6。將如同 子解碼器34内。 者位在該第二 該修改外部解碼器66對於一 定分割俨號兮< 6 '^解瑪器提供一設 疋刀害仏號。該狄定分割信號 從在一给宏χ便躓内部解碼器能夠 疋符號間距下之考量而消除至少一群隹& 4崎 定公名丨>ρ-站*於群集點。該設 刀割仏唬係基於可能群集點之決 器的經錯誤校正輸出、》果以自該外部解碼 4正輸出所導出,而此等群集點若經給定對該 2之内部編碼器的輸人等於該外部解碼器之經錯誤校 正輸出,則可在該傳送器處產生。 該經修改内料碼㈣係經顯Μ⑽於'經延遲的 割信號7卜注意到在本例中該信號71與該信號Μ 該經修改㈣解碼器62係經進—步顯示為回應於該 ❾ 。延遲信號73,此者在本例中是與該信號37相同。該經 :文内^解碼器62可運作以產生—經修改内部解碼器信號 並且將3玄者提供至該解交錯器64。該解交錯器Μ係經 顯示為回應於該經修改内部解碼器信號63,並且可運作以 產生-經解交錯信號65,同時將該者提供至該經修改外部 解碼器66。該經修改外部解瑪器㈣經顯示為回應於該經 :交錯信號65’並且可運作以產生一設定分割信號67,此 s號在本例中疋與該信號21相同。在該解碼器位於該 第—子解碼器26之内的情況下,不會有經延遲的設定分割 201032484 信號71’同時可利用一傳統内部解碼器 位於該最後子解碼器46之 碼器6〇 門的If況下,該信號67為 求信號45,並且可利用一傳統外部解碼器。 給定已知-些符號已由該設定分割信號基於考量而消 除,故可利用該經修改内部解碼器62在接收自天 線之前,解碼出已由該傳逆 應天 碼。在本發明之一利用噹 門#數 扪用該ATSC A/53標準的示範性具 施例裡,該内部數碼係一柵炊 貫 “丄^ 糸栅格數碼’並且該經修改内部解 ❹ 碼1§由12個平行栅格解碼器 號消除部分符號,各者執行v. 由於㈣定分割信 各者執订一 Vl_演算法以決定最佳 符號序列。該解交錯器64係-傳統解交錯器,並可用 以解交錯該所收信號或是移除在其傳輸之前已經引入至該 ^内的交錯效果。在本發明之—示範性具體實施例裡广 :解交錯器64由下列兩個部份組成:-迴旋解交錯器,此 者運作於8位元資料位❹上,以及—栅格數碼解交錯器, 此者運作於2位元資料符號上。Set a part-rel 306 is a set partition reliability signal, that is, equal to Rs_fau 30. In this example, the binary "丨" indicates an unreliable set split signal. The signals set_part 305 and set_part_rel 306 will be stored in external delay memory' which will be discussed in further detail in Figure 14. Figure 4 shows the same situation in which the first byte labeled "〇χΑ6" is the last bit of the first Reed-Solomon digital block that is reliably decoded (ie, no error can be detected). The second byte of the group 'marked as O "OxB 1" is the first byte of the second Reed-Solomon digital block that cannot be reliably decoded (ie, an uncorrectable error is detected). The levels of syml and sym〇 can be derived by dividing the octet of bytes into a plurality of 2-bit symbols starting with the most significant bit. Figure 5 shows further details of each of the N modified decoders in accordance with one embodiment of the present invention. In FIG. 5, a modified decoder 60 is shown as containing a modified internal decoder 62, which is shown as a handle-deinterleaver 64 via 18 201032484, which is modified by an external solution. Displayed as coupled to 1 Liaoqi 1 § 66. The modified decoding decoder 38 is identical. For the 胄## s _ '器 60 and the modified J, for the sake of simplicity, the modified solution is explained by the modified decoder 38, and the solution is 6. It will be like the sub-decoder 34. The second modified external decoder 66 provides a set 仏 对于 for a certain split 兮 兮 < 6 '^ 解 。. The Di Ding split signal eliminates at least one group of 隹 & 4 定 公 丨 ρ 于 于 于 于 于 于 于 于 于 。 。 。 。 。 。 。 。 。 。 。 。 。 消除 消除 消除 消除 消除 消除 消除 消除 消除 消除 消除 消除 消除The set of cuts is based on the error corrected output of the possible cluster point, and is derived from the external output 4 positive output, and if the cluster points are given to the internal encoder of the 2 The input is equal to the error corrected output of the external decoder and can be generated at the transmitter. The modified internal code (4) is displayed (10) in the 'delayed cut signal 7'. Note that in this example the signal 71 and the signal Μ the modified (four) decoder 62 is further displayed in response to the Oh. The delay signal 73, which in this example is the same as the signal 37. The via decoder 62 is operative to generate - the modified internal decoder signal and to provide the 3x to the deinterleaver 64. The deinterleaver is shown responsive to the modified internal decoder signal 63 and is operative to generate a deinterleaved signal 65 while the person is provided to the modified external decoder 66. The modified external damper (4) is shown responsive to the interlaced signal 65' and is operative to generate a set split signal 67, which in this example is the same as the signal 21. In the case where the decoder is located within the first sub-decoder 26, there will be no delayed set split 201032484 signal 71' while a legacy internal decoder is located at the last 6 of the final sub-decoder 46. In the case of the gate, the signal 67 is the seek signal 45 and a conventional external decoder can be utilized. Given that the known symbols have been removed based on the set split signal based on considerations, the modified internal decoder 62 can be utilized to decode the transmitted day code before being received from the antenna. In an exemplary embodiment of the present invention utilizing the ATSC A/53 standard, the internal digital system is smashed through the "丄 糸 糸 数码 ' ” and the modified internal unlock code 1 § Partial symbols are eliminated by 12 parallel grid decoder numbers, each performing v. Since (4) the splitting signal each performs a Vl_ algorithm to determine the optimal symbol sequence. The deinterleaver 64 is a conventional solution. An interleaver that can be used to deinterlace the received signal or to remove interleaving effects that have been introduced into the device prior to its transmission. In the exemplary embodiment of the present invention, the deinterleaver 64 is comprised of the following two The components are: a cyclotron deinterleaver, which operates on an 8-bit data bit, and a raster digital deinterleaver, which operates on a 2-bit data symbol.
該經修改外料^ 66可心解碼在傳輸之前經施用 於該信號的外部數碼’進一步產生一設定分割信號,以由 一後續經修改内部解碼器運^在本發明之-利用該ATSC 亡/53標準的不範性具體實施例裡,該經修改外部解碼器係 一 Reed-Solomon 解碼器,η 去·^ 者了運作以校正該所收資料位 疋組内的錯誤,並且輸出一自該等經錯誤校正之資料位元 :所導出的設定分割信號67。該設定分割信號Μ由兩個子 仏號組成·該第一子作辨冬古批#* 于亿號含有對於各個所收符號的設定分 20 201032484 割資訊’此者包含A/53中所定義的Χι及χ2位元,其中對 於各個錯誤校正資料位元組有4個X1位元及4個乂2位元。 該第一子信號内所包含的設定分割資訊可或無須為可靠。 該第二子信號含有可靠性資訊,其中包含一對於各個828 符號之區塊的1位元通過/失敗信號,表示一個2〇7位元組 Reed-Solomon數碼字組。若在該數碼字組中偵測到無法校 正錯誤,則該Reed-Solomon解碼器失敗。若該數碼字組内 的錯誤數量小於或等於其錯誤校正能力,則該Reed· Solomon解碼器通過。 相符於ATSC A/53標準的傳統内部解碼器一般是運用 Viterbi演算法以解碼該栅格數碼。在一傳統内部解碼器 中,一陪集切片器接收按一基帶信號之形式的輸入。此基 帶信號通常為一其中含有等化器之信號處理電路的輸出。 如 http://www.atsc.org/stanards/a_53-Part-2-2007.pdf 網站 上所發表之ATSC A/53標準定義8個用於傳輸作業的符號 層級。圖6顯示—運用該ATSC A/53標準的内部柵格編碼 器,藉以更佳瞭解本發明具艘實施例對此之應用方式。即 如圖6中所示,在該傳送器内的各個符號間距處,三個位 π(Ζ2、Z1及Z0)係用以選定該等8個符號的其一者而這 二個位元為該内部編碼器的輸出。 該經修改内部解碼器62的進一步細節可如圖7所示。 該經修改内部解碼器62係經顯示為含有一耦接於—分$選 擇電路214之陪集切片$ 212,以及一經轉接於該電路214 的路徑回溯電路216。該陪集切片器212係經顯示為接收該 21 201032484 内部延遲信號73,並可運作以產生具相關分支測度211的 陪集決策,這些測度會被提供作為對該電路214的輸入。 該電路214係經進一步顯示為接收來自一先前外部延遲的 經延遲設定分割輸入信號213。根據這些輸入,該分支選定 電路214可運作以選擇進入各個可能柵格狀態的最佳柵格 刀支,並且產生輸出信號217»該輸出信號217是由該路徑 回溯電路216所接收。在一較佳具體實施例裡,利用一四 狀態柵格解碼器以解碼在ATSC A/53中所定義的内部數 碼。該分支選定電路214維護一由該路徑回溯電路216所鲁 使用的狀態移轉歷史,而該電路216可運作以產生該經修 改内部解碼器信號63。 該陪集切片器212,即如熟諳本項技藝之人士所眾知 者,可用以摘測在該所傳群集之一或更多陪集中對於該所 收符號的最接近群集層,級。自該(等)所傳符號至該(等)最接 近群集層級的(多個)距離,可用以計算(多個)相關的分支測 度。該距離的絕對值或平方值通常是運用在測度產生作業。 該電路214可運作以利用該等分支測度來決定對於該 ◎ 柵格數碼之各個狀態而良好適用於解碼該所收信號的最佳 分支,並且儲存對於該等最佳分支的陪集決策,同時累加 對於各個狀態的路徑測度》 ' 該經修改内部解碼器62不同於傳統的内部解碼器之處 是在於將該經延遲的設定分割輸入213增置於該分支選定 電路214。該經延遲設定分割輸入213含有設定分割資訊以 及設定分割可靠性資訊。在該經修改内部解碼器62中該 22 201032484 等具相關分支測度2"之陪集決策以及該設定分割輸入2i3 兩者皆用於選定對各個狀態的最佳接收符號與相關栅格分 支,藉此有利地改善對於各個狀態之栅格分支的選定結 果。該經修改内部解碼器利其對於—些輸人符號之先前 知識以供比起傳統的内部解碼器更能經常地選擇到正確的 柵格分支。在傳統的内部解碼㈣,該選定電路僅利用該 等具相關分支測度之陪集決策來選定對於各個狀態的最佳 拇格分支。 ❹ ❹ 注意到在該等内部與外部解碼器62及66之間可有一 個以上的解交錯器。在本發明之各式具體實施例的解碼器 應用項目接收A/53信號之情況下,該解碼器具有兩個解交 器 匕紅位元組解交錯器及一柵格數碼解交錯器。 在本發明之一具體實施例裡,該經修改外部解碼器之 設定分割輸出是按該等所產生的次序儲存在記憶體内。此 為-異於對後續經修改内部解碼器之輸入所需者的不同次 序原因在於該(等)解交錯器的效應。即如參照後續圖式所 顯示及討論者位址邏輯可產生—序列的指帛因此該 等經修改内部解碼器輸入會按照正確次序。 表1說明於傳統内部解碼器與該經修改内部解碼器之 ::邏輯差異。在表”,「目前狀態」代表儲存在該柵 格解蜗器延遲構件内的位元’並且是按二進位註記所表 哭认=等认定刀割資訊位元」為一先前經修改外部解碼 、'出’並且含有對應於該目前符號的XI及χ2位元, 而按一進位註記表示為上女\ 衣丁為X2X1。該「設定分割可靠性位元」 23 201032484 亦為同一先前經修改外部解碼器的輸出,並且含有一通過/ 失敗位70 ’此位元是表示與該目前接收符號相關聯的Reed-Solomon數碼字組是否成功地解碼。該「設定分割可靠性位 元」係經顯示為被設定成α表示何靠肖時「〇」 是表示可靠。「可能符號(傳統)」列出在傳統内部解碼器中 可獲用以供選定的可能符號。「可能符號(經修改)」為一在 該經修改内部解碼器中可獲用以供選定的可能符號列表。 對於傳統及經修改内部料器兩者而言,I自該陪集切片 器而具最佳測度的可能符號係由該分支選定電路所選出。 在本發明之各式具體實施例裡,該經修改内部解碼器Μ可 有利地限制其可能符號的集合’減少不正確符號決策的機 會,因此讓該經修改内部解碼器62能夠比起傳統内部解碼 器作出更正確的決策。 目前狀態 設定分割資訊 位元ραχι) 設定分割 可靠性位元 可能符號 (傳統) 可能符號 (經修改)The modified external material 66 can decode the external digital signal applied to the signal prior to transmission to further generate a set split signal for use by a subsequent modified internal decoder in the present invention - utilizing the ATSC to die / In a specific embodiment of the 53 standard, the modified external decoder is a Reed-Solomon decoder, and the η to ^^ operate to correct errors in the received data bit group, and output one from the The error corrected data bit: the derived set split signal 67. The set split signal Μ is composed of two sub-numbers. The first sub-segment is used to identify the winter batch. #* The billion-number contains the set points for each received symbol. 20 201032484 Cut information 'This is defined in A/53. Χι and χ 2 bits, where there are 4 X1 bits and 4 乂 2 bits for each error correction data byte. The set split information contained in the first sub-signal may or may not be reliable. The second sub-signal contains reliability information including a 1-bit pass/fail signal for each block of 828 symbols, representing a 2-7-bit Reed-Solomon digital block. If an error cannot be detected in the digital block, the Reed-Solomon decoder fails. If the number of errors in the digital block is less than or equal to its error correction capability, the Reed Solomon decoder passes. Conventional internal decoders that conform to the ATSC A/53 standard typically use the Viterbi algorithm to decode the raster digital. In a conventional internal decoder, a coset slicer receives an input in the form of a baseband signal. This baseband signal is typically the output of a signal processing circuit that contains an equalizer. The ATSC A/53 standard, as published on the http://www.atsc.org/stanards/a_53-Part-2-2007.pdf website, defines eight symbol levels for transmission jobs. Figure 6 shows an internal grid encoder using the ATSC A/53 standard to better understand the application of the embodiment of the present invention. That is, as shown in FIG. 6, at each symbol pitch in the transmitter, three bits π (Ζ2, Z1, and Z0) are used to select one of the eight symbols and the two bits are The output of this internal encoder. Further details of the modified internal decoder 62 can be as shown in FIG. The modified internal decoder 62 is shown as including a coset slice $212 coupled to the $select circuit 214, and a path traceback circuit 216 coupled to the circuit 214. The coset slicer 212 is shown as receiving the 21 201032484 internal delay signal 73 and is operable to generate a coset decision with the associated branch measure 211 that is provided as an input to the circuit 214. The circuit 214 is further shown to receive the delayed set split input signal 213 from a previous external delay. Based on these inputs, the branch selection circuit 214 is operative to select the optimum grid tool for each possible grid state and to generate an output signal 217» which is received by the path traceback circuit 216. In a preferred embodiment, a four state raster decoder is utilized to decode the internal digital code defined in ATSC A/53. The branch selection circuit 214 maintains a state transition history that is used by the path traceback circuit 216, and the circuit 216 is operative to generate the modified internal decoder signal 63. The coset slicer 212, i.e., as known to those skilled in the art, can be used to extract the closest cluster level to the received symbol in one or more of the cohesive clusters. The distance(s) from which the (or) transmitted symbol is to the nearest cluster level can be used to calculate the associated branch measure(s). The absolute or square value of the distance is usually used in the measure generation work. The circuit 214 is operative to utilize the branching metrics to determine an optimum branch that is well suited for decoding the received signal for each state of the ◎ grid number, and to store coset decisions for the best branches, while Accumulating the path measure for each state" The modified internal decoder 62 differs from the conventional internal decoder in that the delayed set split input 213 is placed in the branch selection circuit 214. The delayed set split input 213 includes setting split information and setting split reliability information. In the modified internal decoder 62, the 22 201032484 and other associated branch measure 2" coset decisions and the set split input 2i3 are both used to select the best received symbols and associated raster branches for each state, This advantageously improves the selection of the raster branches for the various states. The modified internal decoder provides prior knowledge of some of the input symbols for more frequent selection of the correct raster branch than conventional internal decoders. In conventional internal decoding (4), the selected circuit uses only these co-set decisions with associated branch measures to select the best thumb branch for each state. ❹ 注意到 Note that there may be more than one deinterleaver between the internal and external decoders 62 and 66. In the case where the decoder application of the various embodiments of the present invention receives an A/53 signal, the decoder has two demultiplexer blush byte deinterleaver and a raster digital deinterleaver. In one embodiment of the invention, the set split output of the modified external decoder is stored in the memory in the order in which they are generated. This is different from the different order required for the subsequent modification of the internal decoder input due to the effect of the (equal) deinterleaver. That is, as shown in the subsequent figures and discussed by the discussr address logic, the index of the sequence can be generated so that the modified internal decoder inputs are in the correct order. Table 1 illustrates the ::logical differences between the legacy internal decoder and the modified internal decoder. In the table, "current state" represents the bit 'stored in the delay component of the raster de-worm" and is a binary-marked crying = equal-knowledge information bit" as a previously modified external decoding , 'out' and contain XI and χ2 bits corresponding to the current symbol, and a carry note is expressed as the upper female \ 衣丁 is X2X1. The "set split reliability bit" 23 201032484 is also the output of the same previously modified external decoder and contains a pass/fail bit 70 'This bit represents the Reed-Solomon digital word associated with the currently received symbol. Whether the group was successfully decoded. The "set split reliability bit" is displayed as being set to "a" indicating that "〇" is reliable. "Possible Symbols (Traditional)" lists the possible symbols available for selection in a conventional internal decoder. The "possible symbol (modified)" is a list of possible symbols available for selection in the modified internal decoder. For both conventional and modified internal stockers, the possible sign of the best measure from the coset slicer is selected by the branch selection circuit. In various embodiments of the present invention, the modified internal decoder may advantageously limit the set of possible symbols to reduce the chance of incorrect symbol decision making, thus allowing the modified internal decoder 62 to be compared to a conventional internal The decoder makes a more correct decision. Current status Set split information Bit ραχι) Set split reliability bit Possible symbol (traditional) Possible symbol (modified)
❹ 24 201032484❹ 24 201032484
表table
G ^ 。顯不,根據本發明之一具體實施例,該經修改外 66的進一步細節。該經修改外部解碼器66係經 顯不為含有該Reed-SGl()mGn解碼器218及該「位元組至符 號轉換電路」22G。收到該信號65的解碼器218係經顯示 Ο為執接於該電路220,並且提供一輸出219。該Reed s〇i〇m〇nG ^. Further details of this modified 66 are shown in accordance with an embodiment of the present invention. The modified external decoder 66 is shown not to include the Reed-SG1() mGn decoder 218 and the "byte-to-symbol conversion circuit" 22G. Decoder 218, which receives this signal 65, is shown to be connected to circuit 220 and provides an output 219. The Reed s〇i〇m〇n
器218運作於具一固定數量之位元組的數碼字組上, 而其中該固定數量在ATSC A/53標準裡是等於207。這些 位元組中的某一數量為資料位元組(在ATSC A/53標準裡是 187)而其餘則是由該Reed-Solomon解碼器根據一產生器 多項式增置於該等資料位元組的同位位元組(在ATSC A/53 標準裡疋20)。假設在該接收器中並未使用像是軟性測度或 肖示扣示器的外部資訊,則一 Reed_s〇]〇m〇n解碼器可校正 、數碼子組中達該同位位元組一半之數量的錯誤(在ATSC 25 201032484 A/53私準裡是1〇)。若還 [,,t 尺夕的錯誤,則該解碼處理蔣生 敗。此失敗通常是由一J π处理將失 在 ι Reed-So!om〇n 解碼器 可獲用的通過/失敗位开之輸出處 天敗位兀所表不。該位元組至符號 220自該經錯誤校正 轉換電路 八划㈣ 之輸出中擷取出對於各個符號的設定 : 而對於該經錯誤校正之輸出的每個位元組,該 設定分割資訊由4個XI〆古分; 個X1位70及4個χ2位元(選擇性地) 所組成。 、圖9顯不’根據本發明之—具體實施例,—外部延遲 的進步細。應瞭解圖3具體實施例的所有外部延遲皆❹ 含有經顯示為包含在該外部延遲69之内者,並按—類似方 式運作。 圖9的外部延遲69係、類似於圖3的n i個外部延遲之 任一者,像是該外料遲m料部延遲69係經顯 不為含有-延遲記憶體68’此者可回應於一位址邏輯7〇的 輸出°該延遲記憶體68係經進—步顯示為回應於—設定分 d信號78,即按χη所表示者。該延遲記憶體68係經顯示 為產生一經延遲設定分割信號80,即按Xam表示者。該信 G 號78與該等信號31或33之任一者相同,並且該信號8〇 與該等彳S號54或21之任_者相同。該外部延遲69係經進 —步顯示為含有一選配輪出多工器(mux) 236,此者回應於 該經延遲設定分割信號8〇且回應於一選配旗標72,此旗標 是由該位址邏輯70所產生。 該外部延遲69係經顯示為含有該延遲記憶體68,此者 係耦接以接收該設定分割信號78,即按χη*表示者,姐立 26 201032484 可運作以產生該經延遲設定分割信號8〇。該設定分割信號 78是由一經修改解碼器所產生,此解碼器係耦接於該外部 延遲69 ’即如前述者。該延遲記憶體68係經進一步顯示為 接枚一由一位址邏輯7〇所產生的位址邏輯信號75,此位址 邏輯係經顯示為經由該位址邏輯信號75而耦接於該延遲記 憶體68。該位址邏輯7〇係經進一步顯示為產生一選配旗標 72該旗標72有利地表示對應於由該經修改内部解碼器62 ❹ 所處理之目前接收符號的設定分割信號尚非可獲用。若該 内部解碼器記憶體大小少於一子解碼器的最劣情況延遲, 則該旗標72為必要。當該旗標72為設定時,該選配輸出 多工器(mux) 236產生一内定設定分割信號,此信號表示該 叹疋分割資訊並非可靠。而當該旗標72為未設定時,該輸 出多工器即輸出按照該位址邏輯而自記憶體中所擷取出的 設定分割信號。 該位址邏輯70通常會產生一序列的指標,並且補償該 ❹ 等内部及外部解碼器間包含解交錯器在内的操作效應,同 時導致對於後續經修改内部解碼器的設定分割輸入具有正 確次序,且對齊於該等經延遲符號輸入。 操作上’會將一序列的輸入(亦即設定分割信號78而按 所表不者)寫入至該延遲記憶體68。該設定分割信號78 係經延遲以一可變時間量,並且接著按一和被輸入至該延 遲δ己憶體68之次序的不同次序(即由該位址邏輯7〇所決定 者)自該延遲記憶體68所讀出。該位址邏輯7〇可運作以將 該經延遲設定分割信號80對齊於該等經延遲輸入信號以利 27 201032484 後續内部解碼器運用。例如,在該外部解碼器69為圖3具 體實施例之外部延遲32的情況下,該位址邏輯%可運作 以將該信號54對齊於該信號37。 該外部延遲69在圖9巾雖料示為具有__單—延遲線 路(或構件)’然此者可含有多個延遲構件,亦可含有一多個 較小延遲線路的組合。在該示範性ATSC則應用中對 於ysc a/53應用的典型外部延遲大小為4遞個符號, =是53個Reed_s〇1〇m〇n數碼字組。該atsc a/53符號速 率約為10.76 MHZ,使得總延遲時間約為4 〇75ms<)該延遲 ◎ 時間可逐符號而改變’其範圍係根據位址邏輯而定為〇_ 4.075 ms。該延遲構件68可由暫存器、具任何時間之記憶 體或者任何其的儲存邏輯所㉟成。根據本發明之-特點’該等内部及外部延遲的大小可經微調以在成本及效 能間加以取捨。例如,可令該外部延遲69的大小足夠微小, 使件該位址邏輯70有時會參照於一尚未被先前經修改外部 :碼器所寫入的記憶體位置。換言之,此者是參照於該先 月J外部解碼器的一未來輸出。在此一情況下,該位址邏輯❹ 7〇係經組態設定以令該旗標72於無法獲用該所欲輸出(亦 即該信號80)時有所表示。該旗標72係用於通知後續内部 解碼器以說明對於其目前輸入並無可獲用的設定分割資 訊0 當該旗標72是表示沒有對於其目前輸入所可獲用之設 定分割資訊的後續内部解碼器時,該後續内部解碼器運作 如一傳統内部解碼器。而當該設定分割資訊因該外部解碼 28 201032484 器失敗之故而並非可靠時,該 遲,因此該設定分割資訊有時為可'獲$ ^於該可變延 以實現效能改善,此者並無必要隨時皆可獲用。則否。然為 圖ίο顯示,根據本發明‘― 。 70的進-步細節。該位址邏輯7Q係經顯=含=位址邏輯 數器222、一輸出計數器23 ‘ ,含有一輸入計 …數器230、一位移計算電路咖 法電路224及一溢流比較器22^ / ❹ 該輸入汁數器222係經顯示為耦接於該電路以並且 對其產生-輸出,此輸出會自亦經顯示為轉接於該電路以 之位移計算電路226的輸出中所減除。該電路咖接收兮 輸出§十數器230的輸出以作為輸入。在操作上’該電路226 計算一在該外部延遲記憶體之定址過程中所使用的位移。 該電路224將其減法的結果提供至該比較器,同時該比 較器228的輸出表示減法溢流與否的結果亦即是於 或大於零》 、 即以對於該ATSC A/53具艘實施例由該電路226所執 仃的位移計算作業,這可概如下列副程式所描述,在此一 情況下會進行一假設’即該等設定分割資訊位元係經餘存 在 位元寬度的s己憶體中’並且相對於該RS解碼器輸出 位兀組而按自最大有效至最低有效X2X1位元所排置。該副 程式係按似C程式碼之註記所表示,即如業界所眾知者。 然該位移計算作業並不限於一軟體實作,並且可利用替代 f生邏輯所導出’只要能夠如由下列副程式所產生者般在相 同序列中產生該等位移即可。 29 201032484 off 1 = (out_cnt% 1 2)*4+(out_cnt/12)+(out_cnt/48)*44; off2 = (out_cnt%3 3 12)/828; if ((off2>0) && (((out_cnt%828)/12)<(4-off2))) { if((out_cnt% 12)<8) offl+=16; else offl- = 32; } off=43 264* (off 1/208)-82 8 *(offl/4)+(offl%4); 例如,假設該第一 RS輸出位元組係按二進位註記而表 示如R7R6R5R4R3R2R1R0。在位移0、1、2及3處之記憶 體位置的内容分別為R7R6、R5R4、R3R2及R1R0。對於該 等等式的輸入為該輸出計數(「〇ut_cnt」),其中對於一攔位 内的第一符號該〇ut_cnt為0。該等等式的輸出為一相對於 一攔位中之第一符號的位移(「off」)。根據該延遲記憶體的 組態而定,可能需要將該位移加上一開始位址,藉以獲得 該所欲設定分割信號的位址。同時,若是使用一環形延遲 緩衝器,則必須進行依該延遲緩衝器大小為模數的指標計 算。 該輸入計數器222持續追蹤經儲存在該延遲記憶體内 之輸入的數量。此者在接收過程十可被週期性地重置為一 201032484 固定數值。在本發明之一利用該ATSC A/53標準的示範性 具體實施例裡,該輸入計數器222在當由該子解碼器處理 一欄位之第一符號時會被設定為一固定數值。該固定數值 係基於該内部延遲大小所算得,使得該欄位的第一符號對 齊於適當的設定分割信號。該輸出計數器23〇維護由該外 部延遲69所產生之符號的數量。此者在接收過程中可被週 期性地重置為零。在本發明之一利用該ATSC A/53標準的 示範性具體實施例裡,該輸出計數器230在當由該解碼器 處理一欄位之第一符號時會被重置為零。該位移計算電路 226計算出為自該延遲記憶體中擷取對應於該目前接收符 號之適當設定分割信號所必要的位址位移。 該減法電路224自該位移減去該輸入計數。一正或〇 位移疋表不對應於目前接收符號的設定分割信號尚非可獲 用。若該減法電路224的輸出大於或等於〇,則該溢流比較 器228設定一旗標72。在本發明之一利用該atsc八/”標 ◎ 準的不範性具體實施例裡,當該旗標72為設定時,該輸出 多工器會將該設定分割可靠性子信號設定為「丨」,這表示 該設定分割資訊並非可靠。 圖11顯示該經修改解碼器60,此者耦接於該外部延遲 而其中3有本發明各式具體實施例之疊代解碼器的N 個階段之其一者。該延遲記憶體68係經顯示為接收該信號 78’並且該經修改内部解碼器62係經顯示為接收該信號 %。該延遲記憶體68係經顯示為將該信號8()提供至該經 修改内部解碼器62。該經修改外部解碼器66係經顯示為產 31 201032484 生設定分割信號67,而若圖1丨之具體實施例為一疊代解碼 器中除了該第N個子解碼器以外的任一子解碼器,則會將 此信號提供至後續的内部解碼器。圖丨丨的外部延遲69係 經顯不為並無該選配旗標信號及輸出多工器因此這是表 不其中該内部延遲大小為足夠大而能夠補償該最劣情況子 解碼器延遲的情形。 圖12顯示,根據本發明之另一具體實施例,。” L號處理電路92的接收器9〇,而此電路自一天線接收一秦The 218 operates on a digital block having a fixed number of bytes, wherein the fixed number is equal to 207 in the ATSC A/53 standard. One of these bytes is a data byte (187 in the ATSC A/53 standard) and the rest are added to the data bytes by the Reed-Solomon decoder according to a generator polynomial Colocated byte (疋20 in the ATSC A/53 standard). Assuming that no external information such as a softness measure or a schematic indicator is used in the receiver, a Reed_s〇]〇m〇n decoder can correct the number of half of the parity bits in the digital subgroup. The error (in the ATSC 25 201032484 A/53 private standard is 1〇). If [,, t is the fault of the rule, then the decoding process will be lost. This failure is usually handled by a J π and will be lost at the output of the pass/fail bit available at the ι Reed-So!om〇n decoder. The byte to symbol 220 extracts the settings for each symbol from the output of the error correction conversion circuit eight (4): and for each byte of the error corrected output, the set split information is composed of four XI〆古分; consists of X1 bit 70 and 4 χ 2 bits (optional). Figure 9 shows a detailed progress of the external delay in accordance with the present invention. It should be understood that all of the external delays of the particular embodiment of Figure 3 are shown to be included within the external delay 69 and operate in a similar manner. The external delay 69 of FIG. 9 is similar to any of the ni external delays of FIG. 3, such as the delay of 69 of the external material, which is shown to be delayed by the inclusion-delay memory 68'. The output of the address logic 7 ° the delay memory 68 is displayed in response to the set-point d signal 78, i.e., as indicated by χη. The delayed memory 68 is shown as generating a delayed set split signal 80, i.e., as indicated by Xam. The letter G 78 is identical to any of the signals 31 or 33, and the signal 8 is the same as any of the numbers S or 54 or 21. The external delay 69 is further shown as including an optional round-out multiplexer (mux) 236 that responds to the delayed set split signal 8 and responds to an optional flag 72, the flag It is generated by the address logic 70. The external delay 69 is shown to include the delayed memory 68, which is coupled to receive the set split signal 78, that is, by χη*, the sister 26 201032484 can operate to generate the delayed set split signal 8 Hey. The set split signal 78 is generated by a modified decoder coupled to the external delay 69' as previously described. The delay memory 68 is further shown as an address logic signal 75 generated by the address logic 7 ,, the address logic being shown coupled to the delay via the address logic signal 75 Memory 68. The address logic 7 is further shown to generate an optional flag 72. The flag 72 advantageously indicates that the set split signal corresponding to the currently received symbol processed by the modified internal decoder 62 尚 is not yet available. use. This flag 72 is necessary if the internal decoder memory size is less than the worst case delay of a sub-decoder. When the flag 72 is set, the optional output multiplexer (mux) 236 generates a default set split signal indicating that the sigh split information is not reliable. When the flag 72 is not set, the output multiplexer outputs a set split signal extracted from the memory according to the address logic. The address logic 70 typically produces a sequence of metrics and compensates for operational effects including deinterlacers between internal and external decoders such as ❹, while causing the correct ordering of the split input for subsequent modified internal decoders. And aligned to the delayed symbol inputs. The operation 'writes a sequence of inputs (i.e., sets the split signal 78 to the one shown) to the delay memory 68. The set split signal 78 is delayed by a variable amount of time and then followed by a different order of input to the delayed delta recall 68 (i.e., as determined by the address logic 7) The delay memory 68 is read out. The address logic 7 is operable to align the delayed set split signal 80 to the delayed input signals to facilitate subsequent internal decoder operation. For example, where the external decoder 69 is externally delayed 32 of the particular embodiment of FIG. 3, the address logic % is operative to align the signal 54 to the signal 37. The external delay 69 is shown in Fig. 9 as having a __single-delay line (or component). This may include a plurality of delay members, and may also include a combination of a plurality of smaller delay lines. The typical external delay size for the ysc a/53 application in this exemplary ATSC application is 4 hands-on symbols, = 53 is the Reed_s 〇 1 〇 m 〇 digital block. The atsc a/53 symbol rate is approximately 10.76 MHZ, such that the total delay time is approximately 4 〇 75 ms <) the delay ◎ time can be changed symbol by symbol' and its range is 〇 _ 4.075 ms depending on the address logic. The delay member 68 can be formed by a scratchpad, memory of any time, or any storage logic thereof. According to the features of the present invention, the magnitude of these internal and external delays can be fine tuned to trade off between cost and effectiveness. For example, the size of the external delay 69 can be made sufficiently small that the address logic 70 can sometimes refer to a memory location that has not been previously written by a previously modified external:coder. In other words, this is a future output with reference to the previous J external decoder. In this case, the address logic is configured to cause the flag 72 to be represented when the desired output (i.e., the signal 80) is not available. The flag 72 is used to notify the subsequent internal decoder to indicate that the split information 0 is not available for its current input. When the flag 72 is a follow-up indicating that there is no set split information available for its current input. In the case of an internal decoder, the subsequent internal decoder operates as a conventional internal decoder. When the setting split information is not reliable due to the failure of the external decoding 28 201032484, the setting of the split information may sometimes be 'obtained $ ^ in the variable delay to achieve performance improvement, and there is no such It must be available at all times. Then no. However, as shown in the figure, according to the present invention ‘―. 70 step-by-step details. The address logic 7Q is a ===address logic 222, an output counter 23', and includes an input meter 230, a displacement calculation circuit 224 and an overflow comparator 22^ / The input juice counter 222 is shown coupled to the circuit and produces an output thereof that is subtracted from the output of the displacement calculation circuit 226 that is also shown to be transferred to the circuit. The circuit receives the output of the § decimator 230 as an input. In operation, the circuit 226 calculates a displacement used in the addressing of the external delay memory. The circuit 224 provides the result of its subtraction to the comparator, while the output of the comparator 228 indicates that the result of the subtraction overflow is either at or greater than zero, ie, for the ATSC A/53 ship embodiment The displacement calculation operation performed by the circuit 226 can be described as follows in the following subroutine. In this case, a hypothesis is assumed, that is, the setting of the divided information bits is the width of the remaining bits. It is 'in the body' and is arranged from the maximum valid to the least significant X2X1 bit with respect to the RS decoder output bit group. The subroutine is represented by a note like C code, as is well known in the industry. However, the displacement calculation operation is not limited to a software implementation, and may be derived using alternative f-generated logic as long as the displacements can be generated in the same sequence as produced by the following sub-programs. 29 201032484 off 1 = (out_cnt% 1 2)*4+(out_cnt/12)+(out_cnt/48)*44; off2 = (out_cnt%3 3 12)/828; if ((off2>0) &&;(((out_cnt%828)/12)<(4-off2))) { if((out_cnt% 12)<8) offl+=16; else offl- = 32; } off=43 264* (off 1/208)-82 8 *(offl/4)+(offl%4); For example, assume that the first RS output byte is represented by a binary annotation as R7R6R5R4R3R2R1R0. The contents of the memory locations at shifts 0, 1, 2, and 3 are R7R6, R5R4, R3R2, and R1R0, respectively. The input to the equation counts the output ("〇ut_cnt"), where 〇ut_cnt is zero for the first symbol within a block. The output of the equation is a displacement ("off") relative to the first symbol in a block. Depending on the configuration of the delayed memory, it may be necessary to add the start address to the offset to obtain the address of the split signal to be set. At the same time, if a circular delay buffer is used, it is necessary to perform an index calculation based on the delay buffer size. The input counter 222 continues to track the amount of input stored in the delayed memory. This person can be periodically reset to a 201032484 fixed value during the receiving process. In an exemplary embodiment of the present invention utilizing the ATSC A/53 standard, the input counter 222 is set to a fixed value when the first symbol of a field is processed by the sub-decoder. The fixed value is calculated based on the internal delay magnitude such that the first symbol of the field is aligned to the appropriate set split signal. The output counter 23 maintains the number of symbols generated by the external delay 69. This person can be periodically reset to zero during reception. In an exemplary embodiment of the present invention utilizing the ATSC A/53 standard, the output counter 230 is reset to zero when the first symbol of a field is processed by the decoder. The displacement calculation circuit 226 calculates the address shift necessary to extract the appropriate set split signal corresponding to the current received symbol from the delayed memory. The subtraction circuit 224 subtracts the input count from the displacement. A positive or negative displacement table does not correspond to the currently set symbol. The split signal is not yet available. If the output of the subtraction circuit 224 is greater than or equal to 〇, the overflow comparator 228 sets a flag 72. In an embodiment of the present invention that utilizes the atsc octave standard, when the flag 72 is set, the output multiplexer sets the set partition reliability sub-signal to "丨". This means that the split information is not reliable. Figure 11 shows the modified decoder 60 coupled to the external delay and wherein 3 has one of the N stages of the iterative decoder of the various embodiments of the present invention. The delayed memory 68 is shown as receiving the signal 78' and the modified internal decoder 62 is shown as receiving the signal %. The delayed memory 68 is shown to provide the signal 8() to the modified internal decoder 62. The modified external decoder 66 is shown as producing 31 201032484 to generate the split signal 67, and the specific embodiment of FIG. 1 is any sub-decoder other than the Nth sub-decoder in the iterative decoder. , this signal is provided to the subsequent internal decoder. The external delay 69 of the figure is not shown to be without the optional flag signal and the output multiplexer. Therefore, this indicates that the internal delay size is large enough to compensate for the worst case sub-decoder delay. situation. Figure 12 shows another embodiment in accordance with the present invention. The receiver 9 of the L-processing circuit 92 is 〇, and the circuit receives a Qin from an antenna.
入147,並且耦接於一經修改疊代解碼器電路94 ^該疊子 解碼器電路94運作如—分集合併器。不以合併來自多個^ :的輸入(即如圖3者)該疊代解碼器電路Μ是合併來自_ 卓-天線且按多個延遲而具不同設定分割資訊的輸入。 s信號處理電路92係按與圖3之信號處理電路48、$ 及52相同的方式運作,祐.當& 器電路94產生一㈣μ 對該經修改叠代解勒 94係缍& 基帶信號93°該經修改疊代解碼器電與147, and coupled to a modified iterative decoder circuit 94. The stack decoder circuit 94 operates as a diversity combiner. The iterative decoder circuit 不 is an input that combines input from a plurality of ^s (i.e., as shown in FIG. 3) to merge information from the _--the antenna and has different settings for multiple delays. The s signal processing circuit 92 operates in the same manner as the signal processing circuits 48, $ and 52 of Fig. 3, and the && circuit 94 produces a (four) μ for the modified iterative solution 94 system & baseband signal 93° the modified iterative decoder
含有如該等子解二Γ6 34 : 5及401,該等分㈣ 方式運作。_ ” 46者的類似元件並以類似 所』圖12之具體實施例的子解瑪器是按不同方式 :子解碼ϋ 103係經顯示為含有_内部延遲 回應於該基帶信號93,並且可運作 此者 號113至-亦經顯示為納入在該 延遲信 二解碼器%。該經修改解碼器96係=^ 產生—設定分割信號1〇7,此延 外部延遲 此外部延遲亦經顯示為納入 32 201032484 在該子解碼器103之内。該外部延遲97係經 經延遲設定分割信號1 15。 ’生 =子解碼器1〇5係經顯示為含有一内部延遲%、 修改解碼器99及一外部延遲9 过 ^ 該内部延遲98係經顯示 為回應於該信號113,並且可運作以“ 係絰顯不 109至一回應於該信號u ° 顯示為產生一設定分割”二。該解碼器_ _ J仁號111至該外部延遲91,此者係 經顯不為產生^一經延遽%中八《ίΜ 1 ,、 ©部征遞07 信號117。應注意到該等外 。延遲97卩91各者具有相同結構,並且在與該外部延遲 相同的方式t運作。因此,由其個別經修改解碼器所產 生的設定分割信號不僅被延遲,同時亦對齊於一後續内部 延遲的序列或信號。例如,該外部延遲97㈣位址邏輯可 令該信號115對齊於該信號! 〇9。 該子解碼器4〇1係經顯示為含有一内部延遲彻,此者 係麵接於-經修改解碼器1〇1。該内部延遲係經顯示為 ◎ 回應於該内部延遲信號1G9,並且可運作以產生—内部延遲 信號119而予以輸入至該解碼器1〇1。該解碼器ι〇ι係進一 步回應於該錢117,並且可運作以產生—欲予接收的信 號,或是該輸出信號121。該等内部延遲信號113、1〇9及 119相對於該基帶信號93具有固定延遲。該信號的固 疋延遲可為零,藉以自該疊代解碼器電路之内有效地移除 該内部延遲95。 由於該疊代解碼處理程序之故,因此圖12的輸出信號 121比起傳統單通解碼器之輸出將能有利地擁有相同或較 33 201032484 少的位元錯誤。由於在本具體實施例中所運用的新式結構 之故’可藉相比於先前技藝疊代解碼器而為較少的記憶趙 大小以獲致一效能增益。減少記憶體大小通常可獲得較低 的接收器製造成本。底下將簡要說明在信號雜訊比和記憶 體容量方面之增益的其一範例。 在本發明之—利用ATSC A/53應㈣示範性具體實施 例裡’該接收器90的外部延遲可經組態設定以僅儲存幻 個位元來作為該設定分割信號。由於僅有一個天線、調諧 器及信號處理電路,因此各個子解碼器輸入擁有相同的雜 訊水準。在可被該疊代解碼器容忍的雜訊水準處能夠可靠 地解碼X2位元,只要在該柵格解碼器内的狀態移轉為正確Contains such sub-solutions as Γ6 34: 5 and 401, which operate in the same way as (4). The similar elements of the 46-bit and the sub-solver similar to the embodiment of Figure 12 are in different ways: the sub-decoding ϋ 103 is shown to contain the _internal delay in response to the baseband signal 93 and is operational This number 113 to - is also shown as being included in the delayed signal decoder %. The modified decoder 96 is = generating - setting the split signal 1 〇 7 , and this external delay is also shown as incorporating 32 201032484 is within the sub-decoder 103. The external delay 97 is delayed to set the split signal 1 15. The 'sheng=sub-decoder 1〇5 is shown to contain an internal delay %, modify the decoder 99 and an external Delay 9 </ RTI> The internal delay 98 is shown as responsive to the signal 113 and is operable to "reproduce the signal 109 to respond to the signal u ° as a set split". The decoder _ _ J Ren No. 111 to the external delay 91, this is not a result of the generation of a delay of the middle of the eight "ίΜ 1, , © Department of the Departmental 07 signal 117. Should be noted that the delay. 97卩91 each Have the same structure and are in phase with the external delay The same way t operates. Therefore, the set split signal generated by its individual modified decoder is not only delayed, but also aligned to a sequence or signal of a subsequent internal delay. For example, the external delay 97 (four) address logic can make The signal 115 is aligned with the signal! 〇 9. The sub-decoder 4〇1 is shown to contain an internal delay, which is connected to the modified decoder 〇1. The internal delay is shown as ◎ Responding to the internal delay signal 1G9, and operable to generate an internal delay signal 119 for input to the decoder 1〇1. The decoder ι〇ι further responds to the money 117 and is operable to generate The received signal, or the output signal 121. The internal delay signals 113, 1 〇 9 and 119 have a fixed delay with respect to the baseband signal 93. The solid delay of the signal can be zero, thereby decoding from the iteration The internal delay 95 is effectively removed within the circuit. Due to the iterative decoding process, the output signal 121 of Figure 12 can advantageously have the same or less than the output of a conventional single pass decoder. 3 201032484 A small bit error. Due to the new structure used in this embodiment, it can be used to achieve a performance gain compared to the prior art iterative decoder. The body size typically results in lower receiver manufacturing costs. An example of the gain in signal noise ratio and memory capacity will be briefly explained below. In the present invention - the use of ATSC A/53 should (4) an exemplary implementation In the example, the external delay of the receiver 90 can be configured to store only the magic bits as the set split signal. Since there is only one antenna, tuner and signal processing circuit, each sub-decoder input has the same The level of noise. The X2 bit can be reliably decoded at the level of noise that can be tolerated by the iterative decoder as long as the state within the raster decoder is shifted to the correct
即可。由於僅有該等幻位元影響到栅格解碼器狀態移轉 因此僅該等需予儲存以供後續子解碼器使用。相對地,1 該子解碼器輸人内的雜訊信號為彼此互無關聯時,即如= 使用多個天線時經常如&,即必須將該 外部延遲m彳,對WW之能Just fine. Since only these ghost bits affect the raster decoder state transition, only those bits need to be stored for use by subsequent sub-decoders. In contrast, when the noise signals in the input of the sub-decoder are not related to each other, that is, when using multiple antennas, such as &, the external delay must be m彳, the power of WW
根據該最終子解碼器輸入内的雜訊水準而定,然這可感4 地遠高於該等先前子解碼器者。 當相較於一傳統解碼器時, 叮項寺信號121及45在低 號雜訊比處可體驗到降低的位元辦鬼奢 疋錯誤率。尤其是在信號12 的情況下’比起傳統疊代解碼器所 1裔所使用者,可藉較少記销 體而獲致降低的位元錯誤率,你而、士, 從而減少該接收器的製造居 本。底下將簡要說明在信號雜邙t i ^ 雜訊比和記憶體容量方面之增 益的其一範例。 34 201032484 該接收器90係經顯示為僅具備一個來自一天線的輸 入’而非由該接收器20所接收的N個天線輸入。因此該接 收器90相對於該接收器2〇係經簡化。該接收器9〇通常相 比於該接收器20會具有較低成本,因為該接收器2〇要求 多個天線、調諧器和信號處理電路,然該接收器90僅需該 等各一者°同時,可降低外部延遲記憶體要求,即如前文 對於該示範性ATSC A/53應用所述者。不過,該接收器20 在位元錯誤率方面可獲致更佳的改善結果,特別是當位於 各天線輸入處的雜訊是與在其他天線輸入處的雜訊並無關 聯時尤甚。 在圖12的具體實施例裡是使用一單一信號處理電路 92,並且其輸出係藉由差異化對多個解碼器之輸入的量 值,即如由該等子解碼器103、1〇5及4〇1的内部延遲決定 所延遲。在圖12中,有N個子解碼器,並因而有N個 一部延遲。熟諳本項技藝之人士亦將能瞭解,在本發明之 〇 :具體實施例裡,該等内部延遲95、98及伽可為藉由一 固延遲構件的組合,或是藉由一且 單 ’飞疋糟自具備多個、經延遲輸出的 延遲構件,所實作。各個延遲構件 線路布县女 從僻什有一單一延遲 俗次疋一多個較小延遲線電路的組合。 且討論m π _ 便躓圓式係呈現 Λ供顯示此等變化項目的範例。 可瞭解該等接收器20及90各者雖經顯 15,然確可運用任意數量的子解碼。不遇久彻^ 瑪器舍#不過各個子解 %會對該接枚器增入更多成本,同時解 例如増置一笛J吁會出現遞減結果, 第二子解碼器的增益是小於增置—第二子解碼 35 201032484 器的增益。 圖13顯示’根據本發明之一具體實施例’一三階段接 收器208 ’其中含有階段N-l、N及N+1。注意到在圖13Depending on the level of noise in the final sub-decoder input, this can be felt much higher than the previous sub-decoders. When compared to a conventional decoder, the 寺 temple signals 121 and 45 can experience a reduced bit error rate at the low noise ratio. Especially in the case of signal 12, compared to the users of the traditional iterative decoder, the lower bit error rate can be obtained by using less memorization, and you can reduce the receiver. Manufacturing costs. An example of the gain in signal noise t i ^ noise ratio and memory capacity will be briefly explained below. 34 201032484 The receiver 90 is shown as having only one input from one antenna instead of the N antenna inputs received by the receiver 20. Therefore, the receiver 90 is simplified relative to the receiver 2. The receiver 9A typically has a lower cost than the receiver 20 because the receiver 2 requires multiple antennas, tuners, and signal processing circuits, but the receiver 90 only needs one of them. At the same time, the external delay memory requirement can be reduced, i.e., as previously described for the exemplary ATSC A/53 application. However, the receiver 20 achieves better results in terms of bit error rate, especially when the noise at the input of each antenna is unrelated to noise at other antenna inputs. In the embodiment of Figure 12, a single signal processing circuit 92 is used, and its output is differentiated by the magnitude of the input to the plurality of decoders, i.e., by the sub-decoders 103, 1 and 5, and The internal delay decision of 4〇1 is delayed. In Figure 12, there are N sub-decoders and thus there are N one-part delays. Those skilled in the art will also appreciate that, in the present invention, the internal delays 95, 98, and gamma may be by a combination of a solid delay member, or by a single The fly stalk is self-contained with multiple delay components with delayed output. Each delay component is a combination of a number of smaller delay line circuits. And discuss the m π _ note round system to present an example for showing these changes. It can be appreciated that although each of the receivers 20 and 90 can be used, it is possible to use any number of sub-decodings. If you don't encounter a long time, you can add more cost to the receiver. At the same time, for example, if you set a flute, you will have a decrement result. The gain of the second sub-decoder is less than the add-on. - Second sub-decode 35 201032484 gain. Figure 13 shows a 'three-stage receiver 208' having phases N-1, N and N+1 in accordance with an embodiment of the present invention. Noted in Figure 13
中該第一外部延遲含有位址邏輯116及延遲記憶體118,且 經顯不為該子解碼器102的一部份,同時該第二外部延遲 含有位址邏輯152及延遲記憶體128’且經顯示為該子解碼 器104的—部份。此為一對比於該接收器90的替代性具體 實施例’其中該等外部延遲32及40係經分別地描繪為該 等子解碼器26及34的一部份。可考量到替代性具體實施 例’其中該等位址邏輯丨丨6及延遲記憶體丨丨8為該子解碼 器1〇〇的一部份,並且該等位址邏輯152及延遲記憶體128 為該子解碼器102的一部份。該接收器208係類似於該接 收器90 ’並顯示出該等經修改解碼器及外部延遲的進一步 細節。該接收器208係經顯示為在其三個階段中含有一子 解碼器N·〗100、一子解碼器N 1〇2及一子解碼器N+丨1〇4。 s玄子解碼器N-1係經顯示為含有一經修改内部解碼器 110、一解交錯器112及一經修改外部解碼器114,該等共 集地組成一經修改解碼器Ν_1β該經修改内部解碼器1丨〇可 運作以產生内部解碼器信號3G7,此信號是由該解交錯器The first external delay includes address logic 116 and delay memory 118, and is not shown as part of the sub-decoder 102, while the second external delay includes address logic 152 and delay memory 128' and Shown as part of the sub-decoder 104. This is an alternative embodiment of the receiver 90 wherein the external delays 32 and 40 are depicted as part of the sub-decoders 26 and 34, respectively. Alternative embodiments may be considered in which the address logic 丨丨6 and the delay memory 丨丨8 are part of the sub-decoder 1 并且, and the address logic 152 and the delay memory 128 Is part of the sub-decoder 102. The receiver 208 is similar to the receiver 90' and displays further details of the modified decoder and external delays. The receiver 208 is shown to include a sub-decoder N·100, a sub-decoder N 1〇2, and a sub-decoder N+丨1〇4 in its three stages. The scorpion decoder N-1 is shown to include a modified internal decoder 110, a deinterleaver 112, and a modified external decoder 114, which collectively comprise a modified decoder Ν_1β. The modified internal decoder 1丨〇 operable to generate an internal decoder signal 3G7 by which the deinterleaver
Π2所接收。該解交錯器112可運作以產生一經解交錯作 3〇9’此信號是該經修改外部解碼器114由所接收。該子 碼器N 102係經顯不為含有一内部延遲、位址邏〗 116、-延遲記憶體118、一經修改内部解蜗器 交錯器122及-經修改外部解碼器124。該位址邏輯"卜 36 201032484 運作以產生位址邏輯信號308,此信號是由該延遲記憶體 118所接收。該延遲記憶體118可運作以產生經延遲設定分 割信號312,此信號是由該經修改内部解碼器151所接收。 該經修改内部解碼器15卜該解交錯器122及該經修改外部 解碼器124共集地組成一經修改解碼器N,並且該位址邏輯 116及該延遲記憶體118共集地組成該外部延遲N。該經修 改内郤解碼器15 1可運作以產生一經修改内部解碼器信號 314,此托號是由該解交錯器丨22所接收◊該解交錯器}22 了運作以產生一解交錯器信號316,此信號是由該經修改外 部解碼器124所接收。該子解碼器1〇4係經顯示為含有一 内部延遲108、位址邏輯152、一延遲記憶體128、一經修 改内部解碼器153、一解交錯器132及一經修改外部解碼器 134。該位址邏輯152可運作以產生位址邏輯信號32〇,此 仏號是由該延遲記憶體128所接收《該經修改内部解碼器 153、該解交錯器132及該經修改外部解碼器丨34共集地組 成一經修改解碼器N+1,並且該位址邏輯152及該延遲記憶 體128共集地組成該外部延遲N+1。該經修改内部解碼器 153可運作以產生一經修改内部解碼器信號324,此信號是 由該解交錯器132所接收。該解交錯器132可運作以產生 一解交錯器信號326,此信號是由該經修改外部解碼器134 所接收。該經修改解碼器係類似於該經修改解碼器6〇, 且可按相同方式運作。同樣地,該等經修改解碼器N & n+i 各者係類似於該經修改解碼器6〇β該等外部延遲N+i 各者為類似於該外部延遲69β該等内部延遲1〇6及ι〇8各 37 201032484 者為類似於該内部延遲28或36或42或95或98或400Π2 received. The deinterleaver 112 is operative to generate a deinterleaved 3'9' which is received by the modified external decoder 114. The subcoder N 102 is shown to include an internal delay, address logic 116, delay memory 118, a modified internal descrambler interleaver 122, and a modified external decoder 124. The address logic "b 36 201032484 operates to generate an address logic signal 308 that is received by the delayed memory 118. The delay memory 118 is operative to generate a delayed set split signal 312 that is received by the modified internal decoder 151. The modified internal decoder 15 and the modified external decoder 124 collectively form a modified decoder N, and the address logic 116 and the delay memory 118 collectively comprise the external delay N. The modified inner decoder 15 1 is operative to generate a modified internal decoder signal 314 that is received by the deinterleaver 22 and operates on the deinterleaver 22 to generate a deinterleaver signal 316, this signal is received by the modified external decoder 124. The sub-decoder 1 〇 4 is shown to include an internal delay 108, address logic 152, a delay memory 128, a modified internal decoder 153, a deinterleaver 132, and a modified external decoder 134. The address logic 152 is operative to generate an address logic signal 32, which is received by the delay memory 128, "The Modified Internal Decoder 153, the Deinterleaver 132, and the Modified External Decoder" 34 is collectively configured to modify decoder N+1, and the address logic 152 and the delay memory 128 collectively comprise the external delay N+1. The modified internal decoder 153 is operative to generate a modified internal decoder signal 324 that is received by the deinterleaver 132. The deinterleaver 132 is operative to generate a deinterleaver signal 326 that is received by the modified external decoder 134. The modified decoder is similar to the modified decoder 6 and can operate in the same manner. Similarly, the modified decoders N & n+i are similar to the modified decoder 6 〇 β. The external delays N+i are similar to the internal delay of the external delay 69β. 6 and ι〇8 each 37 201032484 is similar to the internal delay of 28 or 36 or 42 or 95 or 98 or 400
圖13具體實施例不同之處在於該信號3〇〇,此信號來 自於一單一信號處理電路,而該電路則為耦接於該子解碼 器N 102的内部延遲106以及該子解碼器N1的經修改内 部解碼器110。注意到可藉由從圖12中移除該内部延遲% 以獲致一類似組態《該内部延遲1〇6產生一内部延遲信號 310,此信號係耦接於該子解碼器N+1的内部延遲1〇8,並 且耦接於該子解碼器N 102的經修改内部解碼器151。該子 解碼器N-1的經修改外部解碼器114為該設定分割信號 21〇,此者係耦接於該子解碼器N 1〇2的延遲記憶體118。The specific embodiment of FIG. 13 differs in that the signal is from a single signal processing circuit, and the circuit is coupled to the internal delay 106 of the sub-decoder N 102 and the sub-decoder N1. The internal decoder 110 is modified. It is noted that the internal delay % can be removed from FIG. 12 to obtain a similar configuration. The internal delay 1 〇 6 generates an internal delay signal 310 coupled to the interior of the sub-decoder N+1. The delay is 1〇8 and is coupled to the modified internal decoder 151 of the sub-decoder N 102. The modified external decoder 114 of the sub-decoder N-1 is the set split signal 21〇, which is coupled to the delay memory 118 of the sub-decoder N 1〇2.
該經修改外部解碼器124產生一設定分割信號318,此者係 耦接於該子解碼器N+1 104的延遲記憶體128。該子解碼器 N+1 104的經修改外部解碼器134產生該輸出信號328,此 者即為所尋求以予解碼的信號.藉該接收器2〇8的各個階 段,由各個階段所產生的設定分割信號比起先前階段會含 有較少錯誤。因此’所要求以利達到一所欲位元錯誤率的 信號雜訊比對於各個額外階段來說會為較低。 該等子解碼器N 1〇2及N+1 104係經顯示為含有與該 經修改解碼器60相同的結構,然該子解碼器N1並不含有 内部及外部延遲。 圖14顯示根據本發明之另一具體實施例的接收器 120。該接收器12〇含有一信號處理電路154,此者回應於 來自一天線的信號,並且進-步含有一幾乎與該接收器9〇 相同方式的疊代解碼器155,除該接收器12()的疊代解瑪器 38 201032484 i 5 5含有一個内部延遲i 2 6以外,此延遲分別地對該等經修 改解碼器157、158及159產生内部延遲信號181、183及 185。注意到該内部延遲信號181可相對於該信號處理奮路 的基帶信號輸出而具有零延遲。該等經修改解碼器157、158 及159係分別地類似於該等解碼器%、99及ι〇ι,並且該 等外部延遲130及156為分別地類似於該等外部延遲叼及 91。在該疊代解碼器155裡該等經修改解碼器與外部延遲 之間的連接性係類似於該疊代解碼器94的相對應連接性。 該解碼H 159可運作以產生該輸出㈣138,此者即為所尋 求以供解碼的信號。 圖15顯示一根據本發明之又另一具體實施例的接收器 140。該接收器140含有一信號處理電路142,此者回應於 一來自-天線的信號’並且進—步含有—幾乎與該接收器 120相同方式的疊代解碼器143’除該接收器14〇的疊代解 碼器143含有一個外部延遲146以外。例如,該疊代解碼 器155的所有外部延遲13〇及156係經合併成一個外部延 遲146該内延遲!44係經顯示為耦接於解碼器1、1 % 及159。若該等延遲大小係經設計為小於該最劣情況子解瑪 :延遲:造成有時無法獲用來自該緊鄰先前子解碼器的設 定分割資訊’則即如圖15㈣—單—外部延遲可為有利 的。如此’―子解碼11可利用來自於該等先前子解碼器之 任一者(而非僅來自彡緊鄰先前子解碼器)的設定分割資 訊該單一外部延遲架構的另一優點為,對於由先前 碼器所產生的可靠設定分割資訊,後續子解碼器無須再度 39 201032484 地產生該設定分割資訊。後續子解碼器僅在當該先前子解 碼器設定分割輸出為不可靠時方才需要產生設定分割資 訊。這可減少所必要的RS解碼器操作量,故降低整體實作 複雜度。注意到可藉由將各個外部延遲搞接至所有的後續 子解碼器’而非僅有該緊鄰後續子解碼器,以在該接收器 90中獲致相同優點。一般說來,接收器90、120及140擁 有等同的功能性並達到相同的效能增益。選擇運用何種記 憶體架構通常是基於設計考量而超越本發明的範圍之外。 圖16顯示,對於該示範性ATSc A/53應用,本發明單 一天線具體實施例之經修改解碼器的外部延遲之一具體實 施例。更詳細地說’ MEM 1 160係經組態設定以儲存N個The modified external decoder 124 generates a set split signal 318 coupled to the delay memory 128 of the sub-decoder N+1 104. The modified external decoder 134 of the sub-decoder N+1 104 generates the output signal 328, which is the signal sought to be decoded. By the various stages of the receiver 2〇8, generated by the various stages Setting the split signal will contain fewer errors than the previous stage. Therefore, the signal noise ratio required to achieve a desired bit error rate will be lower for each additional stage. The sub-decoders N 1 〇 2 and N +1 104 are shown to contain the same structure as the modified decoder 60, although the sub-decoder N1 does not contain internal and external delays. Figure 14 shows a receiver 120 in accordance with another embodiment of the present invention. The receiver 12A includes a signal processing circuit 154 responsive to the signal from an antenna and further comprising an iterative decoder 155 in the same manner as the receiver 9〇, except for the receiver 12 ( The iterative numerator 38 201032484 i 5 5 contains an internal delay i 2 6 which generates internal delay signals 181, 183 and 185 for the modified decoders 157, 158 and 159, respectively. It is noted that the internal delay signal 181 can have a zero delay relative to the baseband signal output of the signal processing. The modified decoders 157, 158, and 159 are similar to the decoders %, 99, and ι, respectively, and the external delays 130 and 156 are similar to the external delays 91 91, respectively. The connectivity between the modified decoder and the external delay in the iterative decoder 155 is similar to the corresponding connectivity of the iterative decoder 94. The decode H 159 is operative to generate the output (four) 138, which is the signal sought for decoding. Figure 15 shows a receiver 140 in accordance with yet another embodiment of the present invention. The receiver 140 includes a signal processing circuit 142 that responds to a signal from the antenna and further includes an iterative decoder 143' in the same manner as the receiver 120 except the receiver 14 The iterative decoder 143 contains an external delay 146. For example, all of the external delays 13 〇 and 156 of the iterative decoder 155 are combined into an external delay 146 for the internal delay! The 44 series is shown coupled to the decoders 1, 1% and 159. If the delay size is designed to be smaller than the worst case scenario: delay: causing sometimes unavailable segmentation information from the immediately adjacent sub-decoder is obtained, ie, as shown in FIG. 15(4) - the single-external delay may be advantageous. Another advantage of the single external delay architecture is that the sub-decoding 11 can utilize any of the previous sub-decoders (rather than only from the immediately preceding sub-decoder) to split the information. The segmentation information generated by the encoder is reliably set, and the subsequent sub-decoder does not need to generate the segmentation information again. The subsequent sub-decoder only needs to generate the set splitting information when the previous sub-decoder sets the split output to be unreliable. This reduces the amount of RS decoder operation necessary, thus reducing overall implementation complexity. It is noted that the same advantages can be achieved in the receiver 90 by fusing each external delay to all subsequent sub-decoders rather than just the immediately subsequent sub-decoder. In general, receivers 90, 120, and 140 have equivalent functionality and achieve the same performance gains. The choice of which memory architecture to use is often based on design considerations beyond the scope of the present invention. Figure 16 shows a specific embodiment of the external delay of the modified decoder of the single antenna embodiment of the present invention for the exemplary ATSc A/53 application. In more detail, the MEM 1 160 system is configured to store N
Reed-Solomon解碼操作的Xl個位元,並且MEM2 162係經 組態設定以儲存N個Reed-Solomon解碼操作(由該經修改 外部解碼器所執行)的通過/失敗表示。即如圖示,該MEM1 160的大小為828*N個位元,該MEM2 162的大小為N個 位元。可在一單一記憶體構件内的不同位址位移處實作該 等MEM1 160及MEM2 162。圖16的記憶體結構僅為說明 之目的’同時熟諳本項技藝之人士將能瞭解替代性記憶體 組態確實存在,且歸屬於本發明範圍之内。在一替代性組 態中,可對該MEM1之内的各個X1位元複製該MEM2之 内的通過/失敗位元’如此可增加該MEM 1的位元寬度,同 時將總記憶體大小提高至828*N*2個位元。 圖17顯示一流程圖,其中說明一由該位址邏輯^^所 執行’而用以讀取該設定分割信號以供該經修改内部解嗎 201032484 器使用之步驟的具體實施例。這些步驟執行一經修改柵格 解碼器的功能。&意到# ® 17所示之程序可用以計算前文 參照於圖ίο位移計算電路226所述的位移。同時,在此係 假設為圖16所示之記㈣結構,而該設定分割信號係經儲 存在ΜΕΜ1中,且該設定分割可靠性信號儲存在μεμ2中。 圖17流程圖所示之程序係針對每一至該柵格解碼器(内部 解碼器)的輸入執行一次,並且產生相對應之設定分割信號 在該延遲記憶體(ΜΕΜ_的位址。該程序說明傳統位元組 父錯器及該栅格數碼交錯器兩者在Α/53中所標定的效果。 在此程序裡,該第一步驟172為檢查目前栅格解碼器輸入 是否為一欄位的第一者,即如在ATSC Α/53標準中所定義 般。若是’則在步驟174處將該等内部計數器m〇D52、 MOD12和MOD4,以及該栅格索引位移TRE,全部初始化 為〇。同時,該指標數值PTR1被設定為一初始數值p,此 值係經選定使得在該位址p處的設定分割信號能夠對齊於 @ 該攔位的第一栅格解碼器輸入。在步驟174後或若在步 驟172處的決定結果為否,則步驟188檢查該目前柵格解 碼器輸入是否為一節段的第一者,即如ATSC A/53標準所 定義般。若是,則在步驟190將m〇D4比較於〇。若m〇D4 不等於〇,則在步驟192將TRE設定為4。在步驟192後, 或若在步驟190中M0D4不等於〇,或若如步驟188所決定 該目刖符號並非一節段中的第一者,則在步驟丨76中按照 如MOD52、MOD12、TRE、PTR1以及整鱧記憶體大小 (MEM_SIZE)的函數來計算該指標數值pTR。注意到該模數 201032484 運算子「%」係用以表示在兩個運算元之除法後的餘數,即 如業界所常用者《其次,在步驟178處,將該數值M〇D12 更新以在次一柵格解碼器輸入間距中使用。在步驟18〇中, 將MOD12比較於〇。若M0D12等於〇,則在步驟ι82更新 MOD4的數值^在步驟182後,若其確經採行,則在步驟 184中將MOD4比較於〇。若M0D4等於〇,則在步驟186 中更新MOD52、PTR1及TRE的數值。而在步驟186後, 或若在步驟180中MOD12並非〇,或若在步驟184中m〇D4 並非〇,則達到對於一個栅格解碼器輸入之程序的結束步驟❿ 194 ° 位在MEM1中之位址PTR處的設定分割信號會被輸入 至該經修改柵格解碼器以運用於群集設定分割。此外,相 對應設定分割可靠性信號在MEM2中的位址可為按照如 flooMPTR/QOTM))所算出,其中fl〇〇r()函數送返小於或等 於其運算元的最接近整數。同時,若該記憶體大小係經設 冲為小於該完全交錯器深度,則必須驗核該pTR藉以確保 此者不會指向一尚未由該先前經修改外部解碼器(即基本上❿ 為一經修改Reed-Solomon解碼器)所產生的未來設定分割 信號。若PTR確指向一未來設定分割信號,則一内定設定 分割信號會被輸出至該柵格解碼器,並且設定該設定分割 可靠性信號以表示該設定分割信號為不可靠。 表2顯示本發明之各種具體實施例的模擬效能結果, 其中該延遲記憶體68具有足夠大小以處置最劣情況子解碼 器延遲,使得該位址邏輯70絕不會參照於未來外部解碼器 42 201032484 輸出。為本範例之目的而設用一簡易「加成性白色高斯雜 訊(AWGN)」頻道模型。對於各個接收天線是採用無關聯的 雜訊來源。資料係根據ATSC A/53所編碼,並且輸出係按 2500個攔位(在實際時間上約等於1分鐘)所監視。表2所 列報的SNR是代表為以在該等2500個欄位裡並無位元錯誤 的最高雜訊水準’可至最接近〇·1 dB〇第一橫列為參考數 值,這代表一先前技藝接收器的效能。表2的增益縱行即 參照於此一數值。 〇 接收天線數量 解瑪器路徑數量 SNR(dB) 増益(dB) 1 1 14.7 0.0 1 2 14.2 0.5 1 3 13.9 0.8 1 4 13.7 1.0 2 2 14.0 0.7 3 3 13.7 1.0 4 4 13.5 1.2 5 5 13.4 1.3 表2 〇 在先前技藝之區塊選定分集合併的情況下,利用2個 天線及2個解碼器路徑’該Snr的結果約為14 3 dB而增 益為0.4 dB。而這相較於表2中的2個天線、2個解碼器路 徑,結果為14.0 dB而增益為〇.7dB。本發明之分集合併疊 代解碼器的效能優於先前技藝之區塊選定分集合併。 為說明延遲大小與效能間的取捨,茲考量1個接收天 線及2個解碼器路徑’而在該等解碼器之間具有各種延遲 大小的情況’其結果係如底下表3所示。此情況係按atsc 43 201032484 A/53信號及一飭且 在,m ^ f 道模型。在表3中,延遲大小 係經標準化,因故 Λ也主 此1.0代表最大可用延遲,其中來自該第一 外部解碼器的所t ^ 所有权疋刀割輸出皆可為及時獲用而供以該 第二内部解碼器運用。延遲大小〇〇代表僅具丨個解碼器路 徑的先前技藝情況。 延遲大小 SNRidKl 增益_ 0.00 -----^ 7 —_14.7 0.0 0.07 _14.7 0.0 0.15 —_14.7 0.0 0.17 一_14.7 0.0 0.18 ___14.7 0.0 0.20 14.6 0.1 0.22 _ 14.6 0.1 0.26 14.5 0.2 0.28 14.5 0.2 0.30 14.4 0.3 0.38 14.4 0.3 0.39 14.4 03 0.41 14.4 0.3 0.43 14.3 0.4 0.45 14.3 0.4 0.53 14.3 0.4 0.61 14.3 0.4 0.62 14.3 0.4 0.64 14.3 0.4 0.66 14.2 0.5 0.70 14.2 0.5 0.78 14.2 0.5 0.85 14.2 0.5 0.93 14.2 0.5 1.0 14.2 0.5 表3The Reed-Solomon decodes the X1 bits of the operation, and MEM2 162 is configured to store the pass/fail representation of the N Reed-Solomon decoding operations (performed by the modified external decoder). That is, as shown, the size of the MEM1 160 is 828*N bits, and the size of the MEM2 162 is N bits. The MEM1 160 and MEM2 162 can be implemented at different address displacements within a single memory component. The memory structure of Figure 16 is for illustrative purposes only. Those skilled in the art will recognize that alternative memory configurations do exist and are within the scope of the present invention. In an alternative configuration, the pass/fail bit within the MEM2 can be copied for each X1 bit within the MEM1. This increases the bit width of the MEM 1 while increasing the total memory size to 828*N*2 bits. Figure 17 shows a flow diagram illustrating a specific embodiment of the steps performed by the address logic to read the set split signal for use by the modified internal solution. These steps perform the function of modifying the raster decoder. The program indicated by &## 17 can be used to calculate the displacement described above with reference to the displacement calculation circuit 226. Meanwhile, it is assumed here that the structure is shown in Fig. 16, and the set division signal is stored in ΜΕΜ1, and the set division reliability signal is stored in μεμ2. The program shown in the flow chart of Fig. 17 is executed once for each input to the raster decoder (internal decoder), and generates a corresponding set split signal in the delayed memory (ΜΕΜ_ address. The program description The effect of the traditional byte decoder and the raster digital interleaver in Α/53. In this procedure, the first step 172 is to check whether the current raster decoder input is a field. The first one, as defined in the ATSC Α/53 standard, is then initialized to 〇 at step 174 with the internal counters m〇D52, MOD12 and MOD4, and the raster index offset TRE. At the same time, the index value PTR1 is set to an initial value p, which is selected such that the set split signal at the address p can be aligned to the first raster decoder input of the @bit. After step 174 Or if the decision at step 172 is negative, then step 188 checks if the current raster decoder input is the first of the segments, as defined by the ATSC A/53 standard. If so, then at step 190 m〇D4 is better than 〇. If m If D4 is not equal to 〇, then TRE is set to 4 in step 192. After step 192, or if M0D4 is not equal to 〇 in step 190, or if the target symbol is not the first one of the segments as determined in step 188 Then, in step 丨76, the index value pTR is calculated according to functions such as MOD52, MOD12, TRE, PTR1, and integer memory size (MEM_SIZE). Note that the modulus 201032484 operator "%" is used to indicate The remainder after division of the two operands, as commonly used in the industry, "Secondly, at step 178, the value M 〇 D12 is updated for use in the next raster decoder input spacing. In step 18, If MOD12 is equal to 〇, if M0D12 is equal to 〇, then the value of MOD4 is updated in step ι82. After step 182, if it is indeed taken, MOD4 is compared to 〇 in step 184. If M0D4 is equal to 〇, then The values of MOD 52, PTR 1 and TRE are updated in step 186. After step 186, or if MOD 12 is not 〇 in step 180, or if m 〇 D4 is not 〇 in step 184, the input to a raster decoder is reached. The end step of the program ❿ 194 ° in MEM1 The set split signal at the address PTR is input to the modified raster decoder for cluster setting splitting. In addition, the address of the split reliability signal in MEM2 can be set as follows (flooMPTR/QOTM)) It is calculated that the fl〇〇r() function returns the nearest integer that is less than or equal to its operand. Meanwhile, if the memory size is set to be smaller than the full interleaver depth, the pTR must be verified to ensure that the person does not point to an external decoder that has not been modified by the previous modification (ie, substantially modified) The Reed-Solomon decoder) generates a future set split signal. If the PTR does point to a future set split signal, a default set split signal is output to the raster decoder, and the set split reliability signal is set to indicate that the set split signal is unreliable. Table 2 shows the simulated performance results for various embodiments of the present invention, wherein the delay memory 68 is of sufficient size to handle the worst case sub-decoder delay such that the address logic 70 never refers to the future external decoder 42. 201032484 output. For the purposes of this example, a simple "additive white Gaussian noise (AWGN)" channel model is used. Uncorrelated sources of noise are used for each receive antenna. The data is encoded according to ATSC A/53 and the output is monitored by 2,500 stops (approximately equal to 1 minute in actual time). The SNR reported in Table 2 is represented by the highest level of noise with no bit errors in the 2500 fields, and can be up to 〇·1 dB. The first course is the reference value, which represents a The performance of previous technology receivers. The gain wales of Table 2 refer to this value. 〇Receiving antenna number Sigma path number SNR(dB) Benefit (dB) 1 1 14.7 0.0 1 2 14.2 0.5 1 3 13.9 0.8 1 4 13.7 1.0 2 2 14.0 0.7 3 3 13.7 1.0 4 4 13.5 1.2 5 5 13.4 1.3 2 〇 In the case where the prior art blocks are selected for diversity, using 2 antennas and 2 decoder paths, the result of the Snr is approximately 14 3 dB with a gain of 0.4 dB. This is 14.0 dB and the gain is 〇.7 dB compared to the 2 antennas and 2 decoder paths in Table 2. The diversity and sub-decoding decoder of the present invention is superior to the prior art block-selected diversity set. To illustrate the trade-off between delay size and performance, consider the case of one receive antenna and two decoder paths 'with various delay sizes between the decoders'. The results are shown in Table 3 below. This situation is based on the atsc 43 201032484 A/53 signal and a model of the m ^ f channel. In Table 3, the delay size is normalized, so that this 1.0 represents the maximum available delay, where the t ^ ownership cutoff output from the first external decoder can be used for timely use. The second internal decoder is used. The delay size 〇〇 represents a prior art case with only one decoder path. Delay size SNRidKl gain _ 0.00 -----^ 7 —_14.7 0.0 0.07 _14.7 0.0 0.15 —_14.7 0.0 0.17 _14.7 0.0 0.18 ___14.7 0.0 0.20 14.6 0.1 0.22 _ 14.6 0.1 0.26 14.5 0.2 0.28 14.5 0.2 0.30 14.4 0.3 0.38 14.4 0.3 0.39 14.4 03 0.41 14.4 0.3 0.43 14.3 0.4 0.45 14.3 0.4 0.53 14.3 0.4 0.61 14.3 0.4 0.62 14.3 0.4 0.64 14.3 0.4 0.66 14.2 0.5 0.70 14.2 0.5 0.78 14.2 0.5 0.85 14.2 0.5 0.93 14.2 0.5 1.0 14.2 0.5 table 3
即如可自表3得知,僅利用66%的最大可用記憶趙大 44 201032484 小(亦即為確保設定分割資訊總是可獲用所必要的大小)即 可能獲致藉由2個解碼器而達〇.5 dB的增益。因此,比起 無法對疊代間之延遲進行微調的先前技藝疊代解瑪器本 發明的分集合併疊代解碼器可按一較低成本所實作。 本發明雖既已按照特定具體實施例所描述,然可預期 對於熟諳本項技藝之人士而言其替換與修改將無疑地顯而 易見。故所欲者係應將後載申請專利範圍解譯為涵蓋所有 此等替換與修改而歸屬本發明的真實精神與範疇之内。 【圖式簡單說明】 圖1顯示一先前技藝接收器1〇。 圖2顯示一信號處理電路22。 圖3顯示一根據本發明之一具體實施例的接收器2〇。 圖4顯示一時序圖’其中說明Reed_s〇i〇m〇n解竭器輸 出是如何地關聯於該設定分割信號。 圖5顯示,根據本發明之一具體實施例,該等N個經 修改解碼器之各者的進一步細節。 圖6顯示ATSC A/53標準的圖6.8,藉以據此更佳地瞭 解本發明之具體實施例的應用方式。 圖7顯示經修改内部解碼器62的進一步細節。 圖8顯示,根據本發明之一具體實施例,該經修改外 部解碼器66的進一步細節。 圖9顯示,根據本發明之一具體實施例,一外部延遲 的進一步細節。 45 201032484 圖丨〇顯示,根據本發明之一具體實施例,該位址邏輯 70的進一步細節。 圖11顯示柄接於該外部延遲69的經修改解碼器60, 其中含有一本發明各式具體實施例之疊代解碼器的N個階 段之其中一者。 圖12顯示一含有一信號處理電路92的接收器90,而 根據本發明之另一具體實施例,此者自一天線接收一輸入 147並耦接於一經修改疊代解碼器94。 圖13顯示,根據本發明之一具鱧實施例,一含有階段 ❹ N·1、N及N+1的三階段接收器208。 圖丨4顯示一根據本發明之另一具體實施例的接收器 120。 圖15顯示一根據本發明之又另一具體實施例的接收 140。 。圖16顯示,對於該示範性aTSc A/53應用,一本發明 之單—信號處理電路具體實施例的經修改解碼器 遲具體實施例。 〇 —圖17顯示一流程圖,其中說明由該位址邏輯7()所執 行而為以讀φ v 項入丨位元而交由該經修改内部解碼 62軍 的步驟。 < 用 【主要元件符號說明】 10解碼器 12内部解碼器 46 201032484 14 解交錯器 16 外部解碼器 20 接收器 21 經延遲的設定分割信號 22 信號處理電路 23 基帶信號 24 疊代解碼器電路 26 子解碼器 28 内部延遲 29 内部延遲信號 30 解碼器 31 設定分割信號 32 外部延遲 33 設定分割信號 34 子解碼器 35 基帶信號 36 内部延遲 37 内部延遲信號 38 解碼器 40 外部延遲 41 基帶信號 42 内部延遲 43 内部延遲信號 44 解碼器 47 201032484 45 輸出信號 46 子解碼器 48 第一信號處理電路 50 第二信號處理電路 52 第N信號處理電路 54 經延遲的設定分割信號 60 經修改解碼器 62 經修改内部解碼器 63 經修改内部解碼器信號 ® 64 解交錯器 65 經解交錯信號 66 經修改外部解碼器 67 設定分割信號 68 延遲記憶體 69 外部延遲 70 位址邏輯 71 經延遲的設定分割信號 ® 72 旗標 73 内部延遲信號 75 位址邏輯信號 76、78、80 信號 90 接收器 91 外部延遲 92 信號處理電路 48 201032484 93 基帶信號 94 經修改疊代解碼器電路 95 内部延遲 96 經修改解碼器 97 外部延遲 98 内部延遲 99 經修改解碼器 100子解碼器 101解碼器 102、103、104、105 子解碼器 106内部延遲 107設定分割信號 10 8内部延遲 109内部延遲信號 1 10經修改内部解碼器 111設定分割信號 112解交錯器 113内部延遲信號 114經修改外部解碼器 I 15設定分割信號 116位址邏輯 11 7經延遲的設定分割信號 II 8延遲記憶體 119内部延遲信號 49 201032484 120接收器 121輸出信號 122解交錯器 124經修改外部解碼器 126内部延遲 128延遲記憶體 130外部延遲 132解交錯器 134經修改外部解碼器 Θ 138輸出信號 140接收器 142信號處理電路 143疊代解碼器 144内部延遲 146外部延遲 147輸入 148、150解碼器 ® 1 5 1經修改内部解碼器 152位址邏輯 153經修改内部解碼器 154信號處理電路 155疊代解碼器 1 5 6外部延遲 157 ' 158 ' 159 經修改解碼器 50 201032484 κ 160記憶體(MEM 1) 162記憶體(MEM2) 172-194 圖17中流程圖的每一個步驟 181、183、185 内部延遲信號 200射頻(RF)輸入 201調諧器 202中頻(IF)信號 203類比至數位(A/D)轉換器 © 204基帶混合器 205時序復原電路 206載波復原電路 207調適性等化器 208接收器 210設定分割信號 2 11相關分支測度 2 1 2陪集切片器 ® 213經延遲的設定分割輸入信號 214分支選定電路 216路徑回溯電路 217輸出信號 218 Reed-Solomon 解碼器 219輸出 220位元組至符號轉換電路 222輸入計數器 51 201032484 224減法電路 226位移計算電路 228比較器 230輸出計數器 236輸出多工器(mux) 300信號 301 信號 RS_fail 302 信號 RS_out[7:0] 303 信號 symlThat is, as can be seen from Table 3, only 66% of the maximum available memory Zhaoda 44 201032484 is small (that is, the size necessary to ensure that the split information is always available), that is, it can be obtained by two decoders. Up to .5 dB gain. Thus, the prior art sub-set solver of the present invention can be implemented at a lower cost than prior art techniques that cannot fine-tune the delay between iterations. The present invention has been described in terms of a particular embodiment, and it is to be understood that modifications and modifications will be apparent to those skilled in the art. Therefore, it is intended that the scope of the patent application should be interpreted as covering all such alternatives and modifications within the true spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a prior art receiver 1A. FIG. 2 shows a signal processing circuit 22. Figure 3 shows a receiver 2 in accordance with an embodiment of the present invention. Figure 4 shows a timing diagram 'which illustrates how the Reed_s〇i〇m〇n depleted output is associated with the set split signal. Figure 5 shows further details of each of the N modified decoders in accordance with an embodiment of the present invention. Figure 6 shows Figure 6.8 of the ATSC A/53 standard, whereby the application of the specific embodiment of the present invention is better understood. FIG. 7 shows further details of the modified internal decoder 62. Figure 8 shows further details of the modified external decoder 66 in accordance with an embodiment of the present invention. Figure 9 shows further details of an external delay in accordance with an embodiment of the present invention. 45 201032484 FIG. 4 shows further details of the address logic 70 in accordance with an embodiment of the present invention. Figure 11 shows a modified decoder 60 spliced to the external delay 69, which contains one of the N stages of an iterative decoder of various embodiments of the invention. 12 shows a receiver 90 including a signal processing circuit 92 which, in accordance with another embodiment of the present invention, receives an input 147 from an antenna and is coupled to a modified iterative decoder 94. Figure 13 shows a three-phase receiver 208 containing stages ❹ N·1, N and N+1 in accordance with one embodiment of the present invention. Figure 4 shows a receiver 120 in accordance with another embodiment of the present invention. Figure 15 shows a reception 140 in accordance with yet another embodiment of the present invention. . Figure 16 shows a modified embodiment of a modified decoder of a single-signal processing circuit embodiment of the present invention for the exemplary aTSc A/53 application. 〇 - Figure 17 shows a flow chart illustrating the steps performed by the address logic 7() to pass the modified internal decoding to the read φ v entry. < Description of [Main Element Symbol] 10 Decoder 12 Internal Decoder 46 201032484 14 Deinterleaver 16 External Decoder 20 Receiver 21 Delayed Set Split Signal 22 Signal Processing Circuit 23 Baseband Signal 24 Iterative Decoder Circuit 26 Subdecoder 28 Internal Delay 29 Internal Delay Signal 30 Decoder 31 Set Split Signal 32 External Delay 33 Set Split Signal 34 Sub Decoder 35 Baseband Signal 36 Internal Delay 37 Internal Delay Signal 38 Decoder 40 External Delay 41 Baseband Signal 42 Internal Delay 43 Internal Delay Signal 44 Decoder 47 201032484 45 Output Signal 46 Sub Decoder 48 First Signal Processing Circuit 50 Second Signal Processing Circuit 52 Nth Signal Processing Circuit 54 Delayed Set Split Signal 60 Modified Decoder 62 Modified Internal Decoder 63 Modified Internal Decoder Signal ® 64 Deinterleaver 65 Deinterleaved Signal 66 Modified External Decoder 67 Set Split Signal 68 Delay Memory 69 External Delay 70 Address Logic 71 Delayed Set Split Signal ® 72 Flag Standard 73 Internal Delay Signal 75 Address Logic Signal 7 6, 78, 80 Signal 90 Receiver 91 External Delay 92 Signal Processing Circuit 48 201032484 93 Baseband Signal 94 Modified Iterative Decoder Circuit 95 Internal Delay 96 Modified Decoder 97 External Delay 98 Internal Delay 99 Modified Decoder 100 Decoder 101 Decoder 102, 103, 104, 105 Subdecoder 106 Internal Delay 107 Set Split Signal 108 Internal Delay 109 Internal Delay Signal 1 10 Modified Internal Decoder 111 Set Split Signal 112 Deinterleaver 113 Internal Delay Signal 114 Modified External Decoder I 15 Set Split Signal 116 Address Logic 11 7 Delayed Set Split Signal II 8 Delay Memory 119 Internal Delay Signal 49 201032484 120 Receiver 121 Output Signal 122 Deinterleaver 124 Modified External Decoder 126 Internal Delay 128 Delay Memory 130 External Delay 132 Deinterleaver 134 Modified External Decoder 138 Output Signal 140 Receiver 142 Signal Processing Circuit 143 Iteration Decoder 144 Internal Delay 146 External Delay 147 Input 148, 150 Decoder® 1 5 1 modified internal decoder 152 address logic 153 modified internal decoder 154 signal Processing Circuit 155 Iterative Decoder 1 5 6 External Delay 157 ' 158 ' 159 Modified Decoder 50 201032484 κ 160 Memory (MEM 1) 162 Memory (MEM2) 172-194 Each step 181 of the flowchart in FIG. 183, 185 internal delay signal 200 radio frequency (RF) input 201 tuner 202 intermediate frequency (IF) signal 203 analog to digital (A / D) converter © 204 baseband mixer 205 timing recovery circuit 206 carrier recovery circuit 207 adaptability Equalizer 208 Receiver 210 Set Split Signal 2 11 Associate Branch Measure 2 1 2 Coset Slicer 213 Delayed Set Split Input Signal 214 Branch Select Circuit 216 Path Back Circuit 217 Output Signal 218 Reed-Solomon Decoder 219 Output 220-bit to symbol conversion circuit 222 input counter 51 201032484 224 subtraction circuit 226 displacement calculation circuit 228 comparator 230 output counter 236 output multiplexer (mux) 300 signal 301 signal RS_fail 302 signal RS_out[7:0] 303 signal syml
304 信號 symO 305 信號 set_part 306 信號 set_part_rel 307内部解碼器信號 308位址邏輯信號 309經解交錯信號 3 10内部延遲信號 3 12經延遲的設定分割信號 3 14經修改内部解碼器信號 3 16解交錯器信號 3 1 8設定分割信號 320位址邏輯信號 3 24經修改内部解碼器信號 326解交錯器信號 328輸出信號 201032484 400内部延遲 401子解碼器304 signal symO 305 signal set_part 306 signal set_part_rel 307 internal decoder signal 308 address logic signal 309 deinterleaved signal 3 10 internal delay signal 3 12 delayed set split signal 3 14 modified internal decoder signal 3 16 deinterleaver Signal 3 1 8 Set Split Signal 320 Address Logic Signal 3 24 Modified Internal Decoder Signal 326 Deinterleaver Signal 328 Output Signal 201032484 400 Internal Delay 401 Sub Decoder
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