TW201032321A

TW201032321A - Design improvement of butting and inserted pickup in electrostatic discharge (ESD) NMOS's

Info

Publication number: TW201032321A
Application number: TW98105904A
Authority: TW
Inventors: Chih-Yao Huang
Original assignee: Univ Ching Yun
Priority date: 2009-02-25
Filing date: 2009-02-25
Publication date: 2010-09-01
Also published as: TWI449157B

Abstract

In 0.18 μ m CMOS process butting or inserted layout of substrate/well pickups of MOSFETs strictly degrades ESD robustness owing to the effective substrate resistance shorting effect. Therefore, this work studies this layout restriction issue and develops new pickup design style to improve this ESD degradation. Splitting butting / inserted well / substrate pickups along the channel width direction in multi-finger NMOS layout structures can improve the ESD performance. The measured data of the new splitting pickup improvement confirmed that the ESD threshold level increases by 2 times for butting-pickup 1.8V devices and increases by 18% for butting-pickup 3.3V devices; the ESD threshold level increases by 5 times for the inserted-pickup 3.3V devices.

Description

201032321 六、發明說明：【發明所屬之技術領域】本發日w露-種靜電_N型錢半場效雜體之短路/置入型接 * 觸點的改良設計，可以有效改善其靜電防護能力，屬於改良型αΐδμίΒ 互補金氧半製程的技術範疇。 • 【先前技術】靜電放電(ESD)近年已經成為IC製程中一個重要的可靠性議題，般的N型金氧半電晶體更是常見的靜電放電保護元件。然而，這種 =件卻也遭遇到-些缺點的影響亟待更進—步的改良。舉例來說，多 • &狀型態的N型金氧半電晶體在靜電放電期間，經常發生不均勻啟動201032321 VI. Description of the invention: [Technical field of invention] The improved design of the short-circuit/insertion type contact of the static-type _N-type half-field hybrid body can effectively improve the electrostatic protection capability. It belongs to the technical category of the modified αΐδμίΒ complementary gold-oxygen half-process. • [Prior Art] Electrostatic discharge (ESD) has become an important reliability issue in IC processes in recent years. N-type MOS transistors are common ESD protection components. However, this kind of piece has also encountered the effect of some shortcomings to be improved. For example, multi- &-type N-type oxy-halide transistors often occur unevenly during electrostatic discharge.

的狀況(參考文獻[1] : D_ Scott，J. Hall and G. Giles, ,，A lumped element model for simulation of ESD failures in silicided devices, " EOS/ESDStatus (Ref. [1] : D_ Scott, J. Hall and G. Giles, ,, A lumped element model for simulation of ESD failures in silicided devices, " EOS/ESD

Symp_PiOC”pp.41 -47, 1986·)。靜電放電n型金氧半電晶體保護元件，經书遭丈到不均勻電流分佈問題的影響，而其相關的靜電放電保護設片也已見先蝻技術中（參考文獻[2] : t. p〇igreen a. Chatterjee, "Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow," IEEE TED. Vol. 39, no. 2, pp. 379 - 388, 1992.)。同時，有更多的佈局設計改良方法被提出（參考文獻⑺： Ming-Dou Ker, Che-Hao Chuang, and Wen-Yu Lo, "Layout Design On φ Multi- Finger MOSFET for On-Chip ESD Protection Circuit in a 0.18-umSymp_PiOC"pp.41-47, 1986·). Electrostatic discharge n-type MOS semi-transitor protection components, the book is affected by the uneven current distribution problem, and its related electrostatic discharge protection device has also seen蝻Technology (Reference [2] : t. p〇igreen a. Chatterjee, "Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow," IEEE TED. Vol. 39, no. 2, pp. 379 - 388, 1992.) At the same time, more layout design improvements have been proposed (Reference (7): Ming-Dou Ker, Che-Hao Chuang, and Wen-Yu Lo, "Layout Design On φ Multi- Finger MOSFET for On-Chip ESD Protection Circuit in a 0.18-um

Salicide CMOS Process," IEEE IEDM, 2001.) ' ([4] Ming-Dou Ker, Tung-Yang Chen, and Chung-Yu Wu,"ESD Protection Design In a 0.18um Salicide CMOS Technology By Using Substrate-Triggered Technique" IEEE IEDM., 2001.) ' [5] Ming-Dou Ker and Che-Hao Chung,"ESD - Implantations In 0.18um Salicide CMOS Technology for On-Chip ESDSalicide CMOS Process," IEEE IEDM, 2001.) ' ([4] Ming-Dou Ker, Tung-Yang Chen, and Chung-Yu Wu,"ESD Protection Design In a 0.18um Salicide CMOS Technology By Using Substrate-Triggered Technique" IEEE IEDM., 2001.) ' [5] Ming-Dou Ker and Che-Hao Chung,"ESD - Implantations In 0.18um Salicide CMOS Technology for On-Chip ESD

Protection Witii Layout Consideration" IEEE IEDM·, 2001.)，對此相關的研究也已經藉由模擬獲得驗證(參考文獻[6] : A. Burenkov，K. Tietzel,J. Lorenz, 'Optimization of 0.18um CMOS Device by Coupled Process and Device Simulation,” Solid-State Electronics, p.764-p.774, 2000.)。多指狀金氧半電晶體基底接點，採用短路型(短路源極擴散區）或 3 201032321 置入型(鄰近源極擴散區）基底或井區接觸點的方法，經常使用在現有的次微米製程技術中’用來節省佈局面積(參考文獻[7] : Toy〇kazu柯诉,Protection Witii Layout Consideration" IEEE IEDM·, 2001.), related research has also been verified by simulation (Reference [6]: A. Burenkov, K. Tietzel, J. Lorenz, 'Optimization of 0.18um CMOS Device by Coupled Process and Device Simulation," Solid-State Electronics, p.764-p.774, 2000.) Multi-finger MOS semi-transistor substrate contacts, short-circuit type (short-source source diffusion region) or 3 201032321 Placement (near source diffusion region) substrate or well contact points, often used in existing sub-micron process technology to save layout area (Reference [7] : Toy〇kazu Ke v.,

Shin Hashimoto, Yasushi Naito and Yuichi HirofUji，“Dual (n+/p+) polycide interconnect technology using poly-Si/ Wsi2/ Poly-Si structure and post B+ implantation，’’ IEDM92, pp.845-848, 1992.)或加強元件本身 ❿ 的能力。另外，在CMOS積體電路製程中，電晶體的源極端採用短路接觸基底接點也可以降低閂鎖效應(latch-Up)的敏感性(參考文獻间R· s. Payne, W. R. Grant, and W. J. Bertram, "Elimination of latchup in bulk CMOS," in IEDM Tech. Dig., pp. 248-251, 1980.) ^ ([9] C. Duvvuiy, R. N. Rountree, and O. Adams, "Internal chip ESD phenomena beyond the protection circuit, IEEE Trans, on Electron Devices, vol. 35a n〇. 12 pp 2133-2139, 1988.)。 ’ ’ . 然而，在0.18//m CMOS製程技術中，源極端短路/置入 (butting/inserted)基底接觸點佈局會導致ESD防護能力嚴重下降，一般的0.18//m製程規則中，這種金氧半電晶體中的短路/置入基底局樣態是被嚴格禁止的，但是在〇·18微米以上製程中並未發生問題，因此造成ESD防護能力下降的行為已_由電滅擬紐(參考文獻 [10] Chih-Yao Huang and Tzn-Lin Yuan, "Influence of substrate Pickup on ESD NMOS Robustness", 2005 Taiwan ESD Conference, pp.125-130, Nov. 2〇〇5_)。這是因為有效的基底電阻值被大幅縮小，使得在NM〇S’底下寄生的ΝΡΝΒΓΓ辭無法啟動。因此，這織題在目前製造技術上造成的影響仍然需要提出解決的辦法。一以下再舉目前常見糊實例，如後附第五圖，表示—閘極接地金寄t的橫向結構截面，這是在實際應用中很常見的曰、:凌置如弟八圖所不’通常會在元件的周圍有環繞的接觸點，目的是為了穩定基底偏壓，接地保護環用來收集雜訊區域發生問鎖效應等等。 ^ 1/〇月}圖ϋ不夕才曰狀则os元件源極端短路型基底接觸點的佈 1視圖，、7〇件的的剖面示意圖。第八圖表示多指狀刪⑺元件源極 U入型基底接觸點的佈局上視_元件_示賴。除了前面 4 201032321 =及外圍的保護環之外，上述第七圖和第八用於維持佈局結構狀自,& 局方式，是 =“邊緣的部分較少，因為從中=二:= 大，隨著總電流的增加這不均勾分佈電流使得==比較昇電流高密度區域的溫度鼓最後會5 元件。因此短跋/罟入仏/. j j刀配電饥的狀悲更快燒毁防止這種 ❹ =路:基底接觸或置入型基底接觸點的方法將嚴重的示的，都減無法解決上述不均勻分佈的情況。似顯魏貫驗所顯【發明内容】有繁於此’本發明乃提供一種靜電防護N型金氧半場祕職_，織嶋冑瞻力的問 ==;:=r於多指狀—佈力的提升:基底電阻調正刀配的不同佈局結構，以獲得ESD防護能為實現上述目的，本發明是採用下列技術手段。本發明的靜電_N型錄半場效電晶體之置良設計，主要特徵是，經由把整體的短路型接觸或置入型=】 =點區塊’分散成許多獨立的島狀方塊，以解決短路/置人接觸點的問滅0 上述分散式接觸點設計，包括如後附第一圖至第四圖中所揭示者’把P+塊狀接觸點短路或置入到N+源、極端的擴散區；據此能分配更多的塊狀接觸點在中央部分基底電阻較大的地方，更多的塊狀接觸點能夠降低其等效基底電阻’反之’配置較少的塊狀接觸點在邊緣的部分，可以增加其相對應的基底電阻值，如此在每個·底下對應的個 201032321 別等效基底電阻可以分配的更均勻，進而提高ESD防護能力。、以短路難觸代表性的例子而言，本發明是把紐的短路型接觸刀散成泎多獨立的塊狀接觸方塊並且使P+塊狀接觸點短路接觸極擴散區。 ΜShin Hashimoto, Yasushi Naito and Yuichi HirofUji, "Dual (n+/p+) polycide interconnect technology using poly-Si/Wsi2/ Poly-Si structure and post B+ implantation, '' IEDM92, pp.845-848, 1992.) or strengthening The ability of the component itself. In addition, in the CMOS integrated circuit process, the source terminal of the transistor uses a short-circuit contact with the substrate contact to reduce the latch-up sensitivity (References between R· s. Payne) , WR Grant, and WJ Bertram, "Elimination of latchup in bulk CMOS," in IEDM Tech. Dig., pp. 248-251, 1980.) ^ ([9] C. Duvvuiy, RN Rountree, and O. Adams, "Internal chip ESD phenomena beyond the protection circuit, IEEE Trans, on Electron Devices, vol. 35a n〇. 12 pp 2133-2139, 1988.). ' ' . However, in 0.18//m CMOS process technology The source short-circuit/buterted (butting/inserted) substrate contact point layout will cause a serious drop in ESD protection. In the general 0.18//m process rule, the short-circuit/insert substrate in the MOS transistor State is strictly prohibited, but in · There is no problem in the process of 18 micron or more, so the behavior of reducing the ESD protection ability has been eliminated. (Ref. [10] Chih-Yao Huang and Tzn-Lin Yuan, "Influence of substrate Pickup on ESD NMOS Robustness", 2005 Taiwan ESD Conference, pp. 125-130, Nov. 2〇〇5_). This is because the effective substrate resistance value is greatly reduced, so that the parasitic rumors under NM〇S' cannot be activated. The effect of this weaving problem on the current manufacturing technology still needs to be solved. One of the following examples of common pastes, as shown in the attached fifth figure, shows the transverse structural section of the gate grounded gold. It is very common in practical applications: 凌如如八八图 ' ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” Lock effect and more. ^ 1 / 〇 } } } } } os os os os os os os source source of the short-circuit type base contact point of the cloth 1 view, 7-section schematic view. The eighth figure shows the layout of the multi-finger-shaped (7) component source U-type substrate contact point. In addition to the previous 4 201032321 = and the outer guard ring, the above seventh and eighth are used to maintain the layout structure, and the & bureau mode is = "the part of the edge is less, because from the middle = two: = large, As the total current increases, this uneven distribution of the current makes the == comparison of the current in the high-density area of the temperature drum will eventually be 5 components. Therefore short 跋 / 罟仏 /. jj knife distribution hunger sorrow faster burnout prevention This kind of ❹ = way: the method of contacting or placing the contact point of the substrate into the substrate will be severely shown, and the above uneven distribution can not be solved. It seems obvious that Wei Weizheng [exposing content] The invention provides an electrostatic protection N-type gold oxygen half-field secret _, woven 嶋胄的 = ========================================================================== In order to achieve the above object, the present invention adopts the following technical means. The electrostatic_N type recording half field effect transistor of the present invention is well-designed, and the main feature is that the entire short-circuit type is contacted or placed. =] = point block 'divided into many independent islands Block to solve the short circuit / contact point of the problem 0 The above decentralized contact point design, including as disclosed in the attached first to fourth figures, 'short or P + block contact point to the N + source , the extreme diffusion zone; according to this, more block contact points can be allocated in the central part where the base resistance is larger, more block contact points can reduce the equivalent base resistance, and vice versa. The part of the contact point at the edge can increase its corresponding base resistance value, so that the corresponding base resistance of each of the 201032321 can be more evenly distributed, thereby improving the ESD protection capability. As an example, the present invention disperses a short-circuit contact knife of a New Zealand into a plurality of independent block contact blocks and shorts the P+ bulk contact point to the pole diffusion region.

短路接觸方塊的面積，尺相及周長比傳統更小。每—個ρ+塊狀接觸點有1至2個金屬接點連接金屬第i層的導線。代表性的ρ+塊狀接觸點配置如後附第-鼠第二晒示，有2個p+塊狀基底接觸點位於最，邊卿分的N+祕概區’# 8個p+塊狀赫點位於最遠邊緣算起紅漏N+_擴舰，収有丨6個p+塊狀基底接觸點位於中央部分的N+祕織區。P+塊狀短路型接點在最外圍部分靠近保護環的邊緣可魏置於N+祕紐㈣如第―圖；或者錄n+源極擴散區的最外圍如第二圖。置入型接_代表性例子而言，本發明是把紐的置人型接觸分散成許«立的输_找，並骑P+塊綠獅置入N+祕擴散置入接觸方塊的面積，尺寸以及周長比傳統更小。其中置入的p+ 接點與N+擴散區之關間隙約略碰大於最小設計規則容許距母一個P+塊狀的接觸點有1〜2個金屬接點連接金屬第1層的導線。性的塊狀置人型接觸點配置圖例如後附第三目及第四®所示，圖有2個P+塊狀基底接觸點位於最遠邊緣部分的N+源極紐區，有8 塊狀基絲繼倾最遠雜算起f二排的N+祕舰區，以及有16個P+塊狀基底接觸點位於中央部分的讲源極擴散區，盆狀基底f觸轉是正方形的外觀。錢狀置人藤时最外圍近保魏的邊緣可以配置於N+源極擴散區内如第三圖，或者位於N+源極擴散區的最外圍如第四圖。 ^述本發日㈣靜電防型錢辆效電晶體之祕/置入型接觸的言傳輸線脈波產生印Lp)制-姆型接觸點元件 2>^電_線、33V短路型接觸點元件的電流_電壓鱗、以及量測紐自人錢觸點凡件的電流-電壓曲線，其結果顯示本發明分散式基底接觸點設計的ESD防護臨界等級日_加強，τ〇)電流量測值亦明顯 6 201032321 板同與改善，能有效達到本發明前揭預定目的。【實施方式】 μ本發明的靜餘護Ν型金氧半場效電晶體之贿，置人健觸點改良設計’主要是把整體的短路型接觸或置人型接_基底接點區塊，分散成許多獨立的島狀方塊。後附第-圖，為本發明分散式基底接觸點設計結構與ρ+塊狀基底接觸點10短路接觸Ν+源極擴散區η的佈局上視圖。第-圖’為本發明分散式基底接觸點設計結構與p+塊狀基底接觸點10短路接觸Ν+源極擴散區U第二實施例的佈局上視圖。 e ❹ 第-圖及第二圖中’顯示本發明分散式接觸點設計佈局，把p+塊狀基底接觸點10短路到N+源極端的擴散區U。第二圖，為本發明分散式基底接觸點設計結構與p+塊狀基底接觸點20置入N+源極擴散區21的佈局上視圖。第四圖，為本發明分散式基底接觸點設計結構與p+塊狀基底接觸點20置入N+源極擴散區21第二實施例的佈局上視圖。第三圖及第四圖中，顯示本發明分散式接觸點設計的佈局，把p+ 塊狀基底接觸點20置入到N+源極端的擴散區21。以短路型接觸代表性的例子而言，本發明的方法是，把整段的短路型接觸，分散成許錢立的塊狀觀方塊並且使p+塊狀基底接觸點 10短路接觸N+源極擴散區η,如第—圖及第二圖。短路接觸的面積，尺寸以及周長比傳統更小，其中，每一個塊狀的接觸點有1至2個金屬接點連接金屬第！層的導線。代表性的短路型塊狀接觸點配置如第一圖及第二圖所示，圖中有2 個P+塊狀基底接觸點1〇，位於最遠邊緣部分的N+源極擴散區n，有 8個P+塊狀基底接觸點1〇位於最遠邊緣算起第二排的N+源極擴散區 11，以及有16個p+塊狀基底接觸點10位於中央部分12的N+源極擴月文區11。其中每一個P+塊狀基底接觸點10都是正方形的外觀，其大小在等於或稍大於最小設計容許規範下大約最小是12//m x 12em 尺寸。而塊狀短路型接觸點在最外圍部分靠近保護環13的邊緣，可以 7 201032321 配置於N+源極擴散區11内如第一圖，最外圍如第二圖。或者位於N+源極擴散區 11的以置人雜_條_子而言’本翻的方法是婦段 =接觸分散餅«立的職_方錢錢p+塊狀基底接觸點置入N+源極擴散區21如第三圖及第四圖。 —’、、置入接觸方塊的面積，尺寸以及周長比傳統更小，其中置 2()與N+_擴散區21之間的嶋約略稍微大於最小觸點2G有1至2個金屬接點連接The area of the short-circuit contact block, the phase and the circumference are smaller than conventional. Each of the ρ+ block contacts has 1 to 2 metal contacts connecting the wires of the metal i-th layer. The representative ρ+ block contact point configuration is as follows: the second mouse shows the second sun, there are 2 p+ block base contact points at the most, and the N+ secret area of the edge group is #8 p+ block-shaped points. At the farthest edge, the red leak N+_ expands the ship, and the N+ secret weaving area with the p6 p+ block-shaped base contact points is located in the central part. The P+ block short-circuit type contact can be placed at the outermost portion near the edge of the guard ring to be placed on the N+ key (4) as shown in Fig. 1; or the outermost periphery of the n+ source diffusion region is as shown in the second figure. In the case of the placement type _ representative example, the present invention is to divide the contact type of the New Zealand into the area of the contact block, and to ride the P+ block green lion to place the N+ secret diffusion into the area of the contact block, the size And the perimeter is smaller than the tradition. The gap between the p+ contact and the N+ diffusion region is slightly larger than the minimum design rule. The P+ block contact point has 1~2 metal contacts to connect the metal layer 1 conductor. The block diagram of the block-shaped contact type is shown in the third and fourth ®, for example, the P+ block-shaped base contact point is located at the N+ source of the farthest edge, and has 8 blocks. The base wire is the farthest mixed with the N+ secret ship area of the second row, and the 16 P+ block-shaped base contact points are located in the central source part of the source diffusion region, and the basin-shaped base f-tact is a square appearance. The outermost edge of the money-like vine can be placed in the N+ source diffusion region as shown in the third figure, or at the outermost periphery of the N+ source diffusion region as shown in the fourth figure. ^ 述本日日(4) Static anti-type money effect of the effect of the crystal system / insert type contact transmission line pulse wave production printing Lp) system - m type contact point component 2 > ^ electric _ line, 33V short-circuit contact point components The current-voltage scale, and the current-voltage curve of the measurement of the contact point of the person, the result shows that the ESD protection critical level of the distributed base contact point design of the present invention is _enhanced, τ〇) current measurement value It is also obvious that the 2010 201032321 board is improved and can effectively achieve the intended purpose of the present invention. [Embodiment] μ The brim of the static sputum-type gold-oxygen half-field effect transistor of the present invention is improved in the design of the contact point of the person's health contact, which is mainly to connect the whole short-circuit type or the connection type _ base contact block. Dispersed into a number of independent island-shaped squares. The attached figure is a top view of the layout of the distributed substrate contact point design structure of the present invention and the short-circuit contact Ν + source diffusion region η of the ρ + bulk substrate contact point 10. Fig. 1 is a top view of the layout of the second embodiment of the distributed substrate contact point design structure of the present invention and the p+ bulk substrate contact point 10 short circuit contact Ν + source diffusion region U. e ❹ In the first and second figures, the decentralized contact point design layout of the present invention is shown, shorting the p+ bulk substrate contact point 10 to the diffusion region U of the N+ source terminal. The second figure is a top view of the layout of the dispersed substrate contact point design structure of the present invention and the p+ bulk substrate contact point 20 placed in the N+ source diffusion region 21. The fourth figure is a top view of the layout of the second embodiment of the N+ source diffusion region 21 in which the distributed substrate contact point design structure of the present invention and the p+ bulk substrate contact point 20 are placed. In the third and fourth figures, the layout of the decentralized contact point design of the present invention is shown, with the p+ bulk substrate contact 20 placed into the diffusion region 21 of the N+ source terminal. In a representative example of a short-circuit type contact, the method of the present invention is to disperse the entire short-circuit type contact into a block-like block of a sturdy stand and short-circuit the p+ block-like base contact point 10 to the N+ source diffusion. Area η, such as the first map and the second map. The area, size and circumference of the short-circuit contact are smaller than conventional ones, where each block-shaped contact point has 1 to 2 metal contacts to connect the metal! Layer of wire. Representative short-circuit type block contact points are arranged as shown in the first figure and the second figure. There are 2 P+ block-shaped substrate contact points 1〇, and the N+ source diffusion area n at the farthest edge part has 8 The P+ bulk substrate contact point 1〇 is located at the farthest edge and counts the N+ source diffusion region 11 of the second row, and the 16+ p+ bulk substrate contact points 10 are located at the N+ source diffuser region 11 of the central portion 12. . Each of the P+ bulk substrate contact points 10 has a square appearance with a size that is approximately equal to or slightly greater than the minimum design tolerance specification and is approximately 12//m x 12em. The block short-circuit type contact point is adjacent to the edge of the guard ring 13 at the outermost portion, and can be disposed in the N+ source diffusion region 11 as shown in the first figure, and the outermost periphery is as shown in the second figure. Or in the N+ source diffusion region 11 for the sake of the person's _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The diffusion region 21 is as shown in the third and fourth figures. —', the area of the contact block, the size and the circumference are smaller than the conventional one, wherein the 之间 between the 2() and N+_diffusion regions 21 is slightly larger than the minimum contact 2G has 1 to 2 metal connections Point connection

代表性的置人型塊狀接觸點配置如第三圖及第四圖所示，圖中有2 個P+塊狀基底接觸點2〇位於最遠邊緣部分的N+源極擴舰21，有8 個P+塊狀基底接觸點2〇位於最遠邊緣算起第二排的N+源極擴散區 2卜以及有i6個塊狀基底接觸點2〇位於中央部分22㈣十源極擴散區21。其中每-個p+塊狀基底接觸點2()都是正方形的外觀，其大小在等於或稍大於最小設計容許規範下A約最小是χ Μ難尺寸。而塊狀置入型接繼在最外圍部分靠近保護環Μ的邊緣，可以配置於Ν+源極擴散區21内如第三圖，或者位於Ν+源極擴散區21的最外圍如第四圖。如前述，本發明把短路難觸或置人·_基錢點區塊，分散成許多獨立的島狀方塊，其目的是為了分配更多的塊狀接觸點在中央部分基底雜較大的齡，更多的魏接繼能嶋低其等效基底電阻。而相反的，配置較少的塊狀接觸點在邊緣的部分，可以增加其相對應的基底電阻值。如此在每侧極底下對應的彳_等效基底電阻可以分配的更均勻進而提高ESD防護能力。經由貫際量測，結果顯示本發明分散式基底接觸點設計的ESD防護臨界等級明顯加強，TLP H責電流量測值㈣顯提高與改善；如下表所示。 8 201032321 表一：TLP(傳輸線脈波產生器)量測1.8V驅動電壓元件在短路型基底接觸點狀態的TLP電流-電壓曲線。 —1.8V—comparison—butting —1.8V_buttingThe representative human-shaped block contact point configuration is shown in the third figure and the fourth figure. In the figure, there are 2 P+ block-shaped base contact points 2〇 N+ source extension ship 21 located at the farthest edge part, there are 8 The P+ bulk substrate contact point 2〇 is located at the farthest edge and counts the second row of N+ source diffusion regions 2 and has i6 bulk substrate contact points 2〇 located at the central portion 22 (four) ten source diffusion regions 21. Each of the p+ block-like substrate contact points 2() is a square appearance whose size is equal to or slightly greater than the minimum design tolerance specification. A is a minimum of about χ. The block-shaped type is connected to the edge of the protection ring 最 at the outermost portion, and may be disposed in the Ν+source diffusion region 21 as shown in the third figure, or at the outermost periphery of the Ν+source diffusion region 21 as the fourth Figure. As described above, the present invention disperses a short circuit into a plurality of independent island-shaped blocks, and the purpose thereof is to allocate more block-shaped contact points at a central portion of the base. More Wei can continue to lower its equivalent base resistance. Conversely, a smaller number of block contact points at the edge portion can increase their corresponding substrate resistance values. Thus, the corresponding 彳_equivalent base resistance at each pole bottom can be more evenly distributed to improve ESD protection. Through the continuous measurement, the results show that the ESD protection critical level of the decentralized substrate contact point design of the present invention is significantly enhanced, and the TLP H charge current measurement value (IV) is significantly improved and improved; as shown in the following table. 8 201032321 Table 1: TLP (Transmission Line Pulse Generator) measures the TLP current-voltage curve of the 1.8V drive voltage component in the short-circuit type base contact state. —1.8V—comparison—butting —1.8V_butting

1.201.20

表二：TLP量測3.3V短路型接觸點元件的電流-電壓曲線。Table 2: TLP measures the current-voltage curve of a 3.3V short-circuit contact element.

—3.3 V_comparison__buttng 3 3 V—butting—3.3 V_comparison__buttng 3 3 V—butting

V—TLP (V) 9 201032321 表三：TLP量測3.3V置入型接觸點元件的電流-電壓曲線。 3·3V_comparison—inserted 3.3V一insertedV-TLP (V) 9 201032321 Table 3: TLP measurement of the current-voltage curve of a 3.3V placed contact element. 3·3V_comparison—inserted 3.3V an inserted

表四.列出本發明分散式基底接觸點方法與傳統對照組結構比較，平均TLP電流ESD/ΗΒΜ的耐受等級與改善的比率。 \ Splitting pickup Ave. ESD (v) Splitting pickup TLP current (A) Comparison ave. ESD (V) Ave. ESD ratio of Splitting pickup to comparison Comparison TLP current (A) Current ratio of splitting pickup to comparison 1.8V butting 5750 1.00 2600 2.21 0.886 1.13 3.3V inserted 4600 1.40 800 5.75 0.334 4.19 3.3V butting 1300 1.35 1100 --- U8 0.0668 20.21 如上揭表一至表四Table 4. Lists the ratio of tolerance to improvement of the average TLP current ESD/ΗΒΜ compared to the conventional control structure for the method of the dispersed substrate contact of the present invention. ESD (V) Ave. ESD (of) ESD ratio of Splitting pickup to comparison TLP current (A) Current ratio of splitting pickup to comparison 1.8V butting 5750 1.00 2600 2.21 0.886 1.13 3.3V inserted 4600 1.40 800 5.75 0.334 4.19 3.3V butting 1300 1.35 1100 --- U8 0.0668 20.21 As shown in Table 1 to Table 4 above

里数媒呈現出1.8V系豆路型接觸點元件的 ESD防護臨界等級加強了 2倍，並且3.3v短路型接觸點元件加強了 201032321 180/〇。 3.3V置入型接觸點元件的ESD防護臨界等級加強了 5倍。短路型接觸點元件的TLP二次崩潰電流量測值顯示提高了 13% 〇 3.3V短路型接觸點元件的TLp電流值有2〇倍的改善；而3·3ν置入型接觸點元件的TLP電流值加強了 4倍。本發明的靜獅護方法關能提高保魏力，因為分散式的基底 f觸塊狀結構，使得沿通«度分佈的題電敲為-致。本發明分In the case of the digital media, the ESD protection critical level of the 1.8V system-type contact point component is doubled, and the 3.3V short-circuit contact element is strengthened by 201032321 180/〇. The ESD protection threshold of the 3.3V placed contact element is enhanced by a factor of five. The TLP secondary breakdown current measurement of the short-circuit contact element shows an increase of 13%. The TLp current value of the V3.3V short-circuit contact element is improved by 2 times; and the TLP of the 3·3ν-mounted contact element The current value is increased by 4 times. The static lion protection method of the invention can improve the preservative force, because the decentralized base f touches the block structure, so that the problem along the general distribution is electrically-induced. The invention

政式的塊狀接觸點結構幫助均分等效的基底電阻值，進而使電流分佈更一致。祕數鋪擬證明了短路/置人型的樣式與—般正常的基底接觸 ρ:+ 會大幅的吸收基底電流，換言之，小尺寸的短路/置入型可以維持足夠的有效基底電阻值，小尺寸的短路/置氧半常結構°«一樣少的基底電流。因此，在金乳牛電崎底下寄生的BJr，仍財以正常的工作。者得===翻功能及目的，且本發明已料說明使f於此藝構改尚及二二、'、、而以上所舉之實施例僅用以說明，舉凡所有等效έ 士【圖:‘ΐ:Γ神的類似修改’均應爾觸輸卿__點短路接觸^ρ+義娜短路接輸與《的ρ+難祕觸點置入 w㈣-細觸點置入面:意Ξ為傳摘轉地金氧半電晶體元件内部橫向寄生BJT結構剖 201032321 視圖。θ為傳顧極接地金氧钱晶體元件實際細在佈局的結構上第七圖為傳統多指狀結構NM〇S 極端的佈局上視圖與元件剖面圖。元件及其基底接觸點短路接觸在源 ^八圖為傳統多指狀結構NM〇s元件及其基底接娜置人接觸在源極端的佈局上視圖與元件剖面圖。【主要元件符號說明】The political block contact structure helps to equalize the equivalent substrate resistance, which in turn makes the current distribution more consistent. The secret number paving proves that the short-circuit/place-type pattern and the normal substrate contact ρ:+ will greatly absorb the substrate current. In other words, the small-sized short-circuit/insert type can maintain sufficient effective substrate resistance value. The short-circuit/oxygen semi-constant structure of the size «the same as the base current. Therefore, the BJr parasitic under the golden cow Ozaki still has a normal job. The function and purpose of the present invention have been explained, and the present invention has been described with reference to the embodiment of the present invention, and the above embodiments are for illustrative purposes only, and all equivalents are shown. : 'ΐ: Similar modifications of Γ神' are all touching qing __ point short-circuit contact ^ ρ + yina short-circuit transmission and " ρ + difficult contact placement w (four) - fine contact placement surface: meaning Ξ is a cross-sectional view of the internal lateral parasitic BJT structure of the gold-oxygen semi-transistor element. θ is the structure of the layout of the gold-oxygen crystal element actually finely laid out. The seventh figure is the layout top view and component cross-section of the traditional multi-finger structure NM〇S extreme. The element and its substrate contact point are short-circuited at the source. The figure is a conventional multi-finger structure NM〇s element and its substrate is placed in contact with the source terminal at the top view and the component profile. [Main component symbol description]

lG Ρ+塊狀基底接觸點 U N+源極擴散區 12中央部分 13保護壤 20 P+塊狀基底接觸點 21 N+源極擴散區 22中央部分 23保護壞lG Ρ + block substrate contact point U N+ source diffusion region 12 central portion 13 protected soil 20 P + bulk substrate contact point 21 N+ source diffusion region 22 central portion 23 protection bad

Claims

201032321 七、申請專利範圍： 1.種靜電防護N型金氧半場效電晶體之短路/置入型接觸點改良設計，其特徵為，短路型接觸點是把整段的短路型接觸，分散成許多獨立的塊狀接觸方塊，並使p+塊狀基底接觸點短路接觸於N+源極擴散區，短路接觸的面積、尺寸以及周長比傳統更小；其中： ' 每一個P+塊狀基底接觸點有1至2個金屬接點連接金屬第i層的導線；有2個P+塊狀基底接觸點，位於最遠邊緣部分的N+源極擴散區；有8個P+塊狀基底接觸點位於最遠邊緣算起第二排的N+源極擴散區; 有16個P+塊狀基底接觸點位於中央部分的^^十源極擴散區。 Φ 2·依據申請專利範圍第1項中所述的靜電防護N型金氧半場效電晶體之短路/置入型接觸點改良設計，其中：每一個P+塊狀基底接觸點，都是正方形的外觀，其大小在等於或稍大於隶小設計容許規範下大約最小是1.2#πι X 1.2μιη尺寸。 3. 依據申請專利範圍第1項中所述的靜電防護Ν型金氧半場效電晶體之短路/置入型接觸點改良設計，其中包括：ρ+塊狀基底接觸點在最外圍部分靠近保護環的邊緣，可以配置於Ν+源極擴散區内。 4. 依據申請專利範圍第1項中所述的靜電防護Ν型金氧半場效電晶體之短路/置人型接難改良設計，其愧括：ρ+塊狀基底接觸點在最外 • 圍部分靠近保護環的邊緣，可以配置於Ν+源極擴散區的最外圍。 5·種靜电防s蒦Ν型金氧半％效電晶體之短路/置入型接觸點改良設 4 ’其特徵為’置人型接觸點是把紐的置人型接觸，分散成許多獨立的塊狀接觸方塊，並使Ρ+塊狀基底接觸點置入Ν+源極擴散區，置入接觸方塊的面積、尺寸以及周長比傳統更小，置入的ρ+塊狀基底接觸點與 - N+源極擴散區之間的間隙，稍大於最小設計容許距離；其中：每一個Ρ+塊狀基底接觸點有丨至2個金屬接點連接金屬第丨層的導線；有2個Ρ+塊狀基底接觸點，位於最遠邊緣部分的Ν+源極擴散區；有8個Ρ+塊狀基底接觸點，位於最遠邊緣算起第二排的胸原極擴散區； ’、有16個Ρ+塊狀基底接觸點，位於中央部分的Ν+源極擴散區。 13 201032321 6.依據申請專利範Μ 5項中所述的靜電防護N型體之短路/置入型接觸點改良設計，其中：穷效電晶每-個P+塊狀基底接觸點’都是正方形的外觀，其大小在等於最小設計容許規範下大約最小是x i.2#m尺寸。…明人 7·依據申請專利範圍第5項中所述的靜電防護N型金氧半場效體之短路/置入型接觸點改良設計，其中包括：曰曰緣，可以配置於N+源 P+塊狀基底接觸點在最外圍部分靠近保護環的邊極擴散區内。201032321 VII. Patent application scope: 1. Improved design of short-circuit/insertion type contact point for electrostatic protection N-type gold-oxygen half-field effect transistor, characterized in that the short-circuit type contact point is to disperse the entire short-circuit type contact. A plurality of individual block contact blocks, and the p+ bulk substrate contact point is short-circuited to the N+ source diffusion region, the area, size and perimeter of the short-circuit contact are smaller than conventional; wherein: 'Each P+ bulk substrate contact point There are 1 to 2 metal contacts connecting the metal ith layer of wires; there are 2 P+ block substrate contact points, the N+ source diffusion region at the farthest edge portion; there are 8 P+ block substrate contact points at the farthest The edge counts the N+ source diffusion region of the second row; there are 16 P+ bulk substrate contact points located at the central source portion of the source diffusion region. Φ 2· According to the improved design of the short-circuit/insertion contact point of the electrostatic protection N-type gold-oxygen half-field effect transistor described in the first paragraph of the patent application, wherein: each P+ block-shaped substrate contact point is square Appearance, the size of which is equal to or slightly larger than the minimum design tolerance specification is about 1.2#πι X 1.2μιη size. 3. According to the improved design of the short circuit/insertion type contact point of the electrostatic protection type galvanic half field effect transistor described in the first paragraph of the patent application, including: ρ + block substrate contact point in the outermost part close to protection The edge of the ring can be placed in the Ν+source diffusion region. 4. According to the application scope of the patent scope, the electrostatic protection type MOS type half-effect transistor is short-circuited/applied and difficult to be improved, including: ρ+ block-shaped base contact point at the outermost circumference Partially close to the edge of the guard ring, it can be placed at the outermost periphery of the Ν+source diffusion region. 5. Electrostatic anti-s蒦Ν type gold oxide half-effect transistor short circuit / placed contact point improved design 4 'characterized by 'the human contact point is the contact of the new type of contact, scattered into many independent The block contact block and the Ρ+ bulk substrate contact point are placed in the Ν+source diffusion region, the area, size and circumference of the contact block are smaller than conventional, and the ρ+ bulk substrate contact point is placed The gap between the and -N+ source diffusion regions is slightly larger than the minimum design tolerance; where: each Ρ+block substrate contact has two metal contacts connecting the metal 丨 layer; there are 2 Ρ + bulk substrate contact point, located at the farthest edge portion of the Ν + source diffusion region; there are 8 Ρ + block substrate contact points, located at the farthest edge to count the second row of the chest-polar diffusion region; 16 Ρ + block substrate contact points, located in the central part of the Ν + source diffusion region. 13 201032321 6. Improved design of short-circuit/insertion-type contact points for electrostatic protection N-type bodies as described in the application for patents, in which: “Efficient electro-crystals per P+ block-like substrate contact points” are square The appearance, the size of which is equal to the minimum design tolerance specification, is approximately x i.2#m size. ...明人7·Improved design of short-circuit/insertion type contact points for electrostatic protection N-type MOS half-field effect according to item 5 of the patent application scope, including: 曰曰 edge, can be configured in N+ source P+ block The contact point of the base is near the peripheral diffusion portion of the guard ring.

8.依據申請專繼®第5項巾所_靜餘独型金氧半場效電晶體之短路/置入型接觸點改良設計，其中包括： P+塊狀基底接觸點在最外圍部分靠近保護環的邊緣，可以配置於N+源極擴散區的最外圍。8. According to the application of the special ® 5th towel _ quiet single-type gold oxygen half-field effect transistor short circuit / placed contact point improved design, including: P + block substrate contact point in the outermost part close to the guard ring The edge can be placed at the outermost periphery of the N+ source diffusion region.

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