TW201032307A - Window type semiconductor package - Google Patents

Window type semiconductor package Download PDF

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Publication number
TW201032307A
TW201032307A TW098106548A TW98106548A TW201032307A TW 201032307 A TW201032307 A TW 201032307A TW 098106548 A TW098106548 A TW 098106548A TW 98106548 A TW98106548 A TW 98106548A TW 201032307 A TW201032307 A TW 201032307A
Authority
TW
Taiwan
Prior art keywords
substrate
semiconductor package
type semiconductor
package structure
window type
Prior art date
Application number
TW098106548A
Other languages
English (en)
Other versions
TWI380424B (en
Inventor
Kuo-Yuan Lee
Yung-Hsiang Chen
Wen-Chun Chiu
Original Assignee
Walton Advanced Eng Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Walton Advanced Eng Inc filed Critical Walton Advanced Eng Inc
Priority to TW098106548A priority Critical patent/TWI380424B/zh
Priority to US12/437,837 priority patent/US20100219521A1/en
Publication of TW201032307A publication Critical patent/TW201032307A/zh
Application granted granted Critical
Publication of TWI380424B publication Critical patent/TWI380424B/zh

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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  • Engineering & Computer Science (AREA)
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  • Computer Hardware Design (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

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201032307 . 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有關於/種窗口 型半導體封裝構造。 【先前技術】 在半導體封裝領域中，冑口型Μ體封裝構造能將内 部電性傳輸路徑集中於基板之接線通道（依細部架構或 ❹形狀不同’接線通道或可稱為通孔、槽孔或窗口），以能 有效縮小封裝產品之尺寸，因而得以符合電子產品輕薄 短小的發展趨勢。接線通道可允許金屬線或是其它已知 的線狀導電元件穿過基板，卩電性連接基板與晶片，故 可有效隱藏金屬線而減少封裝厚度。另以利用一模封膠 體將金屬線與晶片適當密封’以達到保護效果。然而在 接線通道之邊緣為模封膠體與黏晶膠之接合處，導致晶 片之主動面同時被模封膠體與黏晶膠所覆蓋。又，晶片 ❿主動面為積體電路形成表面，比晶片背面更為敏感容 易受到封膠影響而產生損傷。 如第1圖所示，一種習知窗口型半導體封裝構造i 〇〇 主要包3基板110、一晶片120、一黏晶膠130、複數 個金屬線140以及一模封膠體15〇。該基板11〇係具有 一上表面U1、—下表面112以及一接線通道113。通常 該基板.110係具有線路圖案與防銲層結構，例如印刷電 路板。該上表面lu與該下表面112係各形成有一内防 銲層.4與外防銲層115。設在該基板11〇之該下表 3 201032307 面112之複數個球墊117伤孙 你外露於該外防鋅層11 5。該 基板110之上表面111係用以承載該晶片12〇,其係： 用該黏晶冑130黏著該晶丨120之—主動面121。該黏 晶膠130係塗佈於該基板之該上表面m且不覆蓋 該接線通it U3,用以黏接該晶月12()之該主動面ΐ2ι 至該基板110之該上表面ill拍 11並利用该些金屬線140
通過該接線通道113，以電性連接該晶片12〇之複數個 銲塾122至該基板11G。藉由該模封膠體15〇包覆該晶 片120與該些銲墊122。此外，複數個鲜球係設置 於該些球墊117，以供對外表面接合。 如第1圖所示，當進行模封程序時該模封膠體15〇 係填充入該接線通道113以及形成在該接線通道113周 邊與在該晶片120與該基板11〇之間之縫隙，以包覆該 黏晶膠130。由於該縫隙比該接線通道113更為狹小， 僅約有該黏晶膠130之厚度，該模封膠體15〇不容易填 入該縫隙，在晶片120之主動面121會形成氣洞（v〇id)， 並且形成該模封膠體150之模流衝擊與模封後之應力會 損傷該晶片120之該主動面121，影響整體封裝構造1〇〇 之品質。 如第2圖所示’為另—種習知窗口型半導體封裝構 造’該窗口型半導體封裝構造200係與前例大致相同， 但省略了内防銲層之設置’可節省了内防銲層之設置成 本並有利於該基板110與該模封膠體15〇之結合。然而， 於此構造中，即使該基板110之該上表面U1不具有内 201032307 防銲層’形成在該接線通道113周邊與在該晶片12〇與 該基板110之間之縫隙仍是狹小並且容易受到黏晶壓力 與黏晶膠130之黏度特性而產生變化，對於該晶片12〇 之該主動面121受到損傷之問題仍無法改善。此外，該 基板11〇之該下表面U1具有該外防銲層115，在升溫 條件下’該基板110容易因上下表面之熱應力（ther ami stress)不同’而產生紐曲（warpage)現象，翹曲引起之應 力會使内部之晶片破裂（crack)或電子元件損壞。 ®【發明内容】 為了解決上述之問題，本發明之主要目的係在於提供 一種窗口型半導體封裝構造，能防止在接線通道之侧邊 處造成晶片主動面之受損’俾確保製成品之結構完整性 及良率。 本發明之次一目的係在於提供一種窗口型半導體封 装構造’基板在局部挖空（routing)以形成接線通道之過 φ 程中’防止在基板之上表面之防銲層產生斷裂或剝離分 層。 本發明之再一目的係在於提供一種窗口型半導體封 裝構造’有效控制黏晶膠之溢流，以避免溢膠至晶片銲 塾，以確保黏晶作業之品質。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種窗口型半導體封裝構造， 主要包含一基板、一晶片、一黏晶膠、複數個金屬線以 及一模封膠體。該基板.係具有一上表面、一下表面以及 5 201032307
❹ 至少一接線通道，其中該上表面係形成有一第一防銲 層。該晶片係具有一主動面以及複數個設於該主動面之 銲墊。該黏晶膠係黏接該晶片之該主動面至該基板之該 第一防銲層，並使該些銲墊對準於該接線通道内。該些 金屬線係經過該接線通道而電性連接該晶片之該些銲墊 至該基板。該模封膠體係至少形成於該接線通道内，以 密封該些金屬線。其中，該第一防銲層係具有一第一開 孔，其係顯露該接線通道但不與該接線通道切齊，以使 該第一防銲層至該接線通道之側邊之間構成一可供該模 封膠體填入之缺口，並且該模封膠體填入於該缺口之厚 度係大於該黏晶膠之厚度。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的窗口型半導體封裝構造中，該缺口係可為環 形，並圍繞該接線通道。 、在前述的窗口型半導體封裝構造中，該缺口係可包含 複數個條形’其係排列於該接線通道之兩側。 在前述的窗口型半導體封“造中，該缺口心 複數個區塊狀，其係位於該接線通道之兩側中央。 在前述的窗口型半導體封裝構造中，該缺口係 槽道，其係連通該基板之該上表面之兩相對側。 在前述的窗口型丰壤 呈午導體封裝構造中，該模封膠 更形成於該基板之該上表面。 在前述的窗口型丰缘躲& 牛導體封裝構造中，該模封膠體係可 201032307 完全密封該晶片與該黏晶膠。 在前述的窗口型半導體封裝構造中，該些銲墊係可勺 含複數個中央銲墊。 i 在前述的窗口型半導體封裝構造中，該基板係可為線 路基板。 在前述的窗口型半導體封裝構造中，該下表面係可形 成有-第二防銲層，其係具有一顯露區，以顯露但不與 該接線通道切齊。 ❹ 在前述的窗口型半導體封裝構造中，該第二防銲層係 可具有複數個第二開孔，並另包含複數個銲球，其係通 過該些第二開孔接合至該基板之複數個球墊。 在前述的窗口型半導體封裝構造中，該基板係可另具 有複數個接球孔，以顯露位於該上表面之複數個球墊， 並且該窗口型半導體封裝構造可另包含複數個銲球其 _係通過該些接球孔接合至該些球墊。 參 在前述的窗口型半導體封裝構造中，該基板係可為一 種僅有單面線路層之基板。 在前述的窗口型半導體封裝構造中，該基板之該第一 防銲層係可具有複數個周邊開孔，該些周邊開孔係鄰近 於該晶片之側緣。 在前遂的窗口型半導體封裝構造中，該些周邊開孔與 該第一開孔係可連接而呈環形。 由以上技術方案可以看出，本發明之窗口型半導體封 裝構造，具有以下優點與功效： 201032307 防焊層在基板之上表面的 之一技術手段，以使該第 側邊之間構成一可供該模 該模封膠體填入於該缺口 厚度，能防止在接線通道 之受損’俾確保製成品之 ，能有助於模封膠體填滿 〇
利用可黏接黏晶膠之第一 非完整覆蓋方式作為其中 一防銲層至該接線通道之 封膠體填入之缺口，並且 之厚度係大於該黏晶膠之 之侧邊處造成晶片主動面 結構完整性及良率。此外 該缺口’以防止氣洞產生 二、利用W防焊層在基板之上下表面的非完整覆蓋方 式作為其中之一技術手段，使上下防銲層皆不覆蓋 到基板之接線通道之切割線，基板在局部挖空 (routing)以形成接線通道之過程中，能防止或減輕 在基板之上表面之防銲層產生斷裂或剝離分層。 一利用可黏接黏晶膠之第一防焊層在基板之上表面的 非元整覆蓋方式作為其中之一技術手段，第一防銲 層至接線通道之側邊之間構成一可供該模封膠體填 入之缺口，能提供黏晶膠之溢流空間，有效控制黏 晶膠之溢流，更有利於溢膠至晶片銲墊之控制，以 確保黏晶作業之品質。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是’該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案 有關之元件與組合關係，圖中所顯示之元件並非以實際 8 201032307 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計’詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種窗口型半導體封 裝構造說明於第3圖之截面示意圖。該窗口型半導體封 裝構造300主要包含一基板31〇、一晶片32〇、一黏晶膠 330、複數個金屬線340以及一模封膠體350。 該基板310係可為一具有單層線路或多層線路之線 路基板，例如印刷電路板、陶瓷基板、玻璃基板、薄膜 基板或是預模導線架。較佳地，該基板310係可選用一 種可降低成本製作之僅有單面線路層之基板，可省去電 性佈局之複雜度與製程困擾，提高訊號處理高速化，並 降低基板之製作成本並提供適當之載體剛性。如為多層 線路，則該基板3 1 0内另應設有電性導通孔（圖中未繪 ❹ 出）’以連接不同層之線路層。 該基板310係具有一上表面311、一下表面312以及 至少一接線通道313，其中該上表面311係形成有一第 一防銲層314。在本實施例中，如第3圖所示，該下表 面312係可形成有一第二防銲層315。該第一防銲層314 與該第一防鋒層315即是俗稱之「綠漆」（soldermaskor solder resist)，主要是以液態方式塗佈於基板之表面，以 形成一遮覆導電跡線免於受外界水氣、污染物侵害之保 護層’通常該第一防銲層314與該第二防銲層315係可 201032307 為液態感光性防銲層（liquid photoimagable solder maSk ’ LPI)、感光性覆蓋層（ph〇t〇imagable cover layer， PIC)、或可為一般非感光性介電材質之非導電油墨或覆 蓋層（cover layer)。在本實施例中，如第3與4A圖所示， 該接線通道313係可為狹長形之中央槽孔，並貫穿該上 表面311與該下表面312。在本實施例中，一線路層可 形成於該基板310之該下表面312，以構成複數個球墊 317與複數個内接墊，並可達到電性連接。 如第3圖所示，該晶片32〇係面朝下而貼設於該基板 310之該上表面311，該晶片32〇係具有一主動面321以 及複數個設於該主動面321之銲墊3 22。該晶片320係 為微處理晶片、圖形顯示晶片或各種記憶體晶片。在本 實施例中’該些銲墊322係分佈排列於該晶片320之主 動面321之中央，即中央銲墊（central pad)。 該黏晶膠330係黏接該晶片32〇之該主動面321至該 ❿ 基板310之該第一防銲層314，並使該些銲墊322對準 於該接線通道313内。詳細而言，該黏晶層33〇係局部 覆蓋於該第一防銲層314上，該黏晶層33〇之材質可以 選自B階膠體、黏性膠片（film)、環氧黏膠（ep〇xy)、非 導電膠或液態膠體或是其它可多階固化之黏晶材料。 該些金屬線340係經過該接線通道313而電性連接該 晶片320之該些銲墊322至該基板31〇，例如接合至該 基板3 10位於該下表面3 12之接指。在本實施例中該 些金屬線340係打線形成之銲線（b〇nding wires)。該棋 10 201032307 封膠體350係至少形成於該接線通道313内，以密封該 些金屬線340。該模封膠體35〇係可為具有填充物之樹 脂化合物，例如環氧模封化合物（EMC)。詳細而言，該 模封膠體3 50係可更形成於該基板31〇之該上表面3ιι， 更可元全密封該晶片320與該黏晶膠330，俾令該晶片 320及該些金屬線34〇與外界氣密隔離，而不致受外界 衝擊（impact)或污染物侵害。 參 詳細而言，如第3圖及其放大圖所示，該第一防銲層 314係具有一第一開孔3UA，其係顯露該接線通道 但不與該接線通道3 1 3切齊，以使該第一防銲層3丨4至 該接線通道313之侧邊之間構成一缺口 316。該缺口 31 6 係可供該模封膠體350之填入。並且，該模封膠體35〇 填入於該缺口 316之厚度係大於該黏晶膠33〇之厚度。 因此利用該缺口 3 1 6能擴大形成在該接線通道3 1 3侧 邊與在該晶片220與該基板210之間之縫隙，故該模封 • 膠體350填入在該缺口 316之厚度係可等於該黏晶膠 33〇之厚度加上該第一防銲層314之厚度，相較於習知 之封裝構造，厚度與空間明顯增多，特別是在黏晶製程 中，無法準確控制該黏晶膠330之厚度時，該缺口 316 提供了該模封膠體350填入黏晶缝隙之最低下限值，有 利於該模封膠體350在模封時填充至該缺口 316，並能 防止在該接線通道313處造成該晶片32〇之該主動面 3 2 1之受損’俾確保製成品之結構完整性及良率。 具體而言’如第4A至4C圖所示，該第一防銲層314 201032307 之該缺口 316之形狀係可選自環形、矩形或其他形狀。 如第4A圖所示’該缺口 316係為環形並圍繞該接線 通道313,以使該第一防鲜層314完全不與該接線通道 313切齊。或者，如第4B圖所示該缺口 gw係可包含 複數個條形，其係排列於該接線通道3 13之兩侧，以使 該第一防銲層314不與該接線通道313之兩平行側邊切 齊。或者，在一變化例中，如第化圖所示，該缺口 316 φ 係可包含複數個區塊狀，其係位於該接線通道313之兩 側中央，以使該第一防銲層3 14不與該接線通道3 η之 兩平行側邊之某一容易形成氣洞之區段相切齊。或者， 在另一變化例中，如第4D圖所示，該缺口 316係可為 一槽道，其係連通該基板31〇之該上表面3ιι之兩相對 侧，可幫助該模封膠體350之模流可由該接線通道313 之一端導入以及由另一端排出，達到方便在該接線通道 313進行灌注膠體之功效。該缺口 3 16之形狀係可由製 ❿ 作該第一防銲層314時使用之曝光顯影技術加以控制。 或者，該缺口 316能在該第一防銲層314之塗佈製程中 同步形成’兼具有製造容易而不會額外增加基板製造成 本及製造步驟之功效。 此外，該缺口 316能提供該黏晶膠330之溢流空間、 有效控制該黏晶膠3 3 0之溢膠狀況，當有溢膠時，將被 導流至該第一防銲層314之該缺口 316(如第3圖之放大 圖所不）’但以不填滿該缺口 316為較佳，俾使該黏晶膠 330不致溢勝至該些録墊322而產生不當之溢谬問題， 12 201032307 以確保黏晶作業之品質。 如第3圖所示，該第二防銲層315係可具有複數侗第 一開孔3 1 5A，並另包含複數個銲球36〇 ,其係通過鸪此 第一開孔315A接合至該基板31〇之該些球墊317，使診 封裝構造300具有球格陣列封裝型態，以對外表面接 合。具體而言，該第二防銲層315另包含有一顯露區 31 5B’以顯露該接線通道3 13與該些内接墊，以供後續 φ 打線。因此’該基板310之兩面防焊層314與315皆非 完整覆蓋在該基板310之上下表面，不與該接線通遒3i3 相切齊，具有改善在基板製程中局部挖空（r〇uting)以形 成該接線通道313之製程良率。 請參閱第5A與5B圖之截面示意圖，本發明進一步 說明該基板310在局部挖空（routing)以形成該接線通道 313之過程，以彰顯本案之功效。 如第5A圖所示’該第一防銲層314與該第二防銲層 φ 315係分別形成在該基板310之該上表面311與該下表 面312。該第一防銲層314與該第二防銲層315的塗佈 方式大致可分為：網印（screen printing)、簾幕塗佈 (curtain coating)、喷霧塗佈（spray coating)、滚輪塗佈 (roller coating)等。該第一防銲層314與該第二防銲層 315之厚度通常係為相同’但在不同實施例中，亦可適 當加厚該第一防銲層314之厚度以達到蓄膠與容易封膠 填滿之功效。 如第5A與5B圖所示’該第一防銲層314之該第一 13 201032307 開孔314A係顯露該基板31〇之該接線通道313之切割 線L，即不覆蓋到該切割線£並不與該接線通道3 13切 齊。該第二防銲層315之該顯露區315B係顯露該接線 通道313與該些内接墊，不覆蓋到該切割線L，故不與 切割後形成之該接線通道3丨3切齊。 如第5B圖所示’在局部挖空（r〇uting)以形成該接線 通道313之過程中’切割刀（圖未繪出）係不會磨切到或 _ 減少磨切該第一防銲層314與該第二防銲層315。 因此’在上述之窗口型半導體封裝構造3〇〇中，利用 該第一防銲層314形成該缺口 316，有利於該模封膠體 350在模封時填充至該缺口 316，擴充該缺口 316之空 間，能防止在該接線通道3 13處造成該晶片320之該主 動面3 2 1之受損，俾確保製成品之結構完整性及良率。 此外，該基板3 1 0在局部挖空（routing)以形成該接線通 道313之過程中，防止在該基板310之該第一防銲層 % 314與該第二防銲層315產生斷裂或剝離分層。 依據本發明之第二具體實施例，另一種窗口型半導體 封裝構造說明於第6圖之截面示意圖。該窗口型半導體 封裝構造400主要包含一基板310、一晶片320、一黏 晶膠330、複數個金屬線340以及一模封膠體350。其 中與第一實施例相同的主要元件將以相同符號標示，故 可理解亦具有上述之相同作用，在此不再予以贅述。 較佳地，該基板310之該第一防銲層314係具有複數 個周邊開孔4 14B ’該些周邊開孔4 1 4B係鄰近於該晶片 14 201032307 320之側緣。尤佳地，該些周邊開孔4ΐ4β與該第一開 孔314A係可連接而呈環形，以環繞在該晶片32〇之侧 緣到靠近該些銲墊322 層314在該晶片32〇 之一中心部位’以使該第一防銲 之下方係呈現至少兩個島狀支撐 墊，以作為該黏晶膠330之設置區域並提供黏晶後之基 e
本灌膠缝隙，該第一防銲層314之厚度加上該黏晶膠 330之厚度可作為在該晶片32〇與該基板31〇之間的灌 膠縫隙。因此，該缺口 316與該些周邊開孔414B能提 供該黏晶膠330之溢流空間，有效控制該黏晶膠33〇之 溢膠狀況’當有溢膠時，將被導流至該第一防銲層314 之該缺口 316與該些周邊開孔414B，俾使該黏晶膠330 不致溢膠至該些銲墊3 22與流出該基板310之該上表面 3 11而產生不當之溢膠問題，以確保黏晶作業之品質。 依據本發明之第三具體實施例，另一種窗口型半導體 封裝構造說明於第7圖之截面示意圖。其中與第一實施 例相同的主要元件將以相同符號標示，不再細加贅述。 該窗口型半導體封裝構造5 00主要包含一基板310、一 晶片320、一黏晶膠330、複數個金屬線34〇以及一模 封膠體350。 在本實施例中，該基板3 1 0係可為一種隹有單面線路 層之基板，可降低成本製作以及可省去電性佈局之複雜 度與製程困擾。如第7圖所示，該些金屬線340係可為 該基板310之内部元件，例如懸空内引線。ί位於該基板 | 310上表面311之該線路層係可構成該些4墊317與該 15 201032307 些金屬線340 ’並可利用内引腳壓合治具（ILB bondiilg he ad)將該些金屬線340壓合接觸至該些銲墊322，而與 該bb片320電性連接。該基板31〇係可另具有複數個接 球孔518’以顯露位於該上表面311之該些球墊317。 該些銲球360係通過該些接球孔518並接合至該些球墊 317，以作為與外部連接之電性端子。該第一防焊層314 係非完整形成於該基板31〇之該上表面311。更具體 地，除了具有第一開孔314A，該第一防焊層314之周 邊可不對齊該基板31〇之該上表面311，以構成在該基 板310上的一體貼附的、獨立的且電絕緣的支撐墊，並 提供該接線通道313之側邊上可供該模封膠體35〇填入 之缺口 3 16。 在黏晶步驟時，該缺口 316能提供該黏晶膠33〇之溢 崴工間有效控制該黏晶膠3 3 0之溢膠狀況，並有利於 該模封膠體350在模封時填充至該缺口 316。 、
以上所述，僅是本發明的較佳實施例而已，並非對本 發明作任何形式上的限制，雖然本發明已以較佳實施例 :露如上’然而並非用以限定本發明，任何熟悉本項技 备者’在不脫離本發明之技術範圍内，所作的任何簡單 1改、等效性變化與修飾’均仍屬於本發明的技術範圍 【圖式簡單說明】 第1圖··為一種習知窗口型半導體封裝構造之截面示意 圖。 、 201032307 第2圖•為另一種習知兹口剂士 徑$知由口型+導體封裝構造之 意圖》 埤如不 第3圖 '為依據本發明之第一具體實施例的一種窗口型 半導體封裝構造之截面示意圖以及防銲層 之缺口之局部放大圖。 第4A至4D圖：為依據本發明之第一具體實施例的窗口
型半導體封裝構造之第一防銲層之缺口不同變 化例的俯視圖。 第5A至5B圖.為依據本發明之第一具體實施例的窗口 型半導體封裝構造之基板在局部挖空（r〇uting) 以形成接線通道之過程中之截面示意圖。 第6圖：為依據本發明之第二具體實施例的另一種窗口 型半導體封裝構造之截面示意圖。 第7圖：為依據本發明之第三具體實施例的另一種窗口
型半導體封裝構造之截面示意圖。 【主要元件符號說明】 100 窗 口型半導 體封莱 :構造 110 基 板 111 上表 113 接 線通道 114 内防 115 外 防銲層 117 球墊 120 晶 片 121 主動 130 黏 晶膠 140 金屬 160 銲 球 L 切割線 面 112下表面 銲層 面 122銲墊 線 1 5 0模封膠體 17 201032307 312下表面 3 14A第一開孔 3 15B顯露區 200窗口型半導體封裝構造 3 00窗口型半導體封裝構造 310基板 311 上表面 313接線通道 314第一防銲層 3 15第二防銲層 315A第二開孔 316缺口 317 球墊 322銲墊 3 5 0模封膠體 320 晶片 321主動面 330黏晶膠 340金屬線 ® 360銲球 400窗口型半導體封裝構造 414B周邊開孔 500窗口型半導體封裝構造 5 1 8接球孔
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Claims (1)

  1. 201032307
    申請專利範圍： -種窗口型半導體封裝構造，包含 一基板，係具有一上表面 線通道，其中該上表面 一晶片，係具有一主動面 之銲墊； 、—下表面以及至少一接 係形成有—第一防銲層； 以及複數個設於該主動面 一黏晶膠，係黏接該晶片之該主動面至該基板之該
    ，第-防銲層’並使該些銲墊對準於該接線通道内; 複數個金屬線，係經過贫aA ,¾ H過这接線通道而電性連接該晶 片之該些銲墊至該基板；以及 模封膠體’係至少形成於該接線通道内，以密封 該些金屬線； 其中’該第-防銲層係具有一第一開孔，其係顯露 該接線通道但不與該接線通道切齊，以使該第一 防銲層至該接線通道之侧邊之間構成一可供該模 封膠體填入之缺口，並且該模封膠體填入於該缺 口之厚度係大於該黏晶膠之厚度。 2、 根據申凊專利範圍第1項之窗口型半導體封裝構 造，其中該缺口係為環形，並圍繞該接線通道。 3、 根據申請專利範圍第1項之窗口型半導體封裝構 造’其中該缺口係包含複數個條形，其係排列於該 接.線通道之兩側。 4、 根據申請專利範圍第1項之窗口型半導體封裝構 造，，其中該缺口係包含複數個區塊狀，其係位於該 19 201032307 接線通道之兩側中央。 5、根據申請專利範圍第1項之窗口型半導體封裝構 造，其中該缺口係為一槽道，其係連通該基板之該 上表面之兩相對側。 6、 根據申請專利範圍第1項之窗口型半導體封裝構 造’其中該模封膠體係更形成於該基板之該上表面。
    7、 根據申請專利範圍第6項之窗口型半導體封裝構 造，其中該模封膠體係完全密封該晶片與該黏晶膠。 8、 根據申請專利範圍第1項之窗口型半導體封裝構 造’其中該些銲墊係包含複數個中央銲墊。 9、 根據申请專利範圍第1項之窗口型半導體封裝構 造’其中該基板係為線路基板。 10、 根據申請專利範圍第！項之窗口型半導體封裝構 造，其中該下表面係形成有一第二防銲層，係具有 —顯露區，以顯露但不與該接線通道切齊。 "、根據申請專利範圍第10項之窗口型半導體封裝構 造’其中該第二防銲層係具有複數個第二開孔，並 另包含複數個銲球，其係通過該些第二開孔接合至 該基板之複數個球墊。 12、根據申請專利範圍第1項之窗口型半導體封裝 造，其中該基板係另具有複數個接球孔，以顯露 於該上表面之複數個球墊，並且該窗口型半導體 裝構造另包含複數個銲球，其係通㈣些接球孔 合至該些球塾。 20 201032307 13、 根據申請專利範圍第1、11或 體封裝構造’其中該基板係為一 之基板。 14、 根據申請專利範圍第1項之窗 造，其中該基板之該第一防銲層 開孔，該些周邊開孔係鄰近於該 直5、根據申請專利範圍第14項之窗 、土，其中該些周邊開孔與該第一 12項之窗口型半導 種僅有單面線路層 口型半導體封t構 係具有複數個周邊 晶片之侧緣。 口型半導體封裝構 開孔係連接而呈環
    21
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TWI455261B (zh) * 2011-03-16 2014-10-01 Walton Advanced Eng Inc 包覆基板側邊之模封陣列處理方法
TWI792791B (zh) * 2020-12-25 2023-02-11 上海易卜半導體有限公司 半導體封裝方法、半導體元件以及包含其的電子設備

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CN102709198A (zh) * 2011-03-28 2012-10-03 华东科技股份有限公司 防止基板周边外露的模封阵列处理方法
US9758372B1 (en) * 2013-02-13 2017-09-12 Amkor Technology, Inc. MEMS package with MEMS die, magnet, and window substrate fabrication method and structure
US20180315682A1 (en) * 2015-10-21 2018-11-01 GM Global Technolgy Operations LLC Systems and methods for reinforced adhesive bonding using textured solder elements
US10818602B2 (en) 2018-04-02 2020-10-27 Amkor Technology, Inc. Embedded ball land substrate, semiconductor package, and manufacturing methods
KR20220009622A (ko) 2020-07-16 2022-01-25 삼성전자주식회사 반도체 패키지

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TWI455261B (zh) * 2011-03-16 2014-10-01 Walton Advanced Eng Inc 包覆基板側邊之模封陣列處理方法
TWI792791B (zh) * 2020-12-25 2023-02-11 上海易卜半導體有限公司 半導體封裝方法、半導體元件以及包含其的電子設備

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