201027928 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種包含連續逼近暫存器（Successive Approximation Register; SAR)的類比轉數位轉換器(Analog to201027928 VI. Description of the Invention: [Technical Field] The present invention relates to an analog-to-digital converter including a Continuous Approximation Register (SAR) (Analog to
Digital Converter; ADC) ’特別是關於一種可切換位元解析度的 類比轉數位轉換器及其控制方法。 【先前技術】 圖1係習知SAR ADC的方塊圖’包括取樣電路(Sample and Hold Circuit; S/H)12、比較器14、數位轉類比轉換器 (Digital-to-Analog Converter; DAC)18 以及連續逼近控制邏輯 16，以二元搜尋(Binary Search)的方式對所取樣的類比輸入作 連續逼近。 ADC 10的動作始於取樣階段(Sampling Phase)，在取樣階段期 間’取樣電路12將類比輸入完整地取樣存取，接著，aqc 10進入位元循環階段(Bit-cyclingPhase)，決定數位碼輸出的轉 換。圖2以一 3位元(bit)之SAR ADC為例，配合圖1說明二 元搜尋如何完成連續逼近。在位元循環階段開始時，連續逼近 控制邏輯16先將輸入DAC 18之最高（第一）位元 (Most-significant Bit; MSB)B2 設定為 1 (邏輯高準位），第二及 第二位元Βι、B〇為〇 (邏輯低準位）’使DAC 18之類比輸出 VDAC為Vref2 ’此時將類比輸出Vdac與類比輸入％作比較， 類比輸出VDAC小於類比輸入Vin，比較器輸出為〇，連續逼近 控制邏輯16決疋第一位元的值為1 ;接著，連續逼近控制 3 201027928 邏輯16維持第一位元&為1，將第二位元Βι由〇設為丄，第 二位元B〇仍設為〇 ’此時類比輸出VDAc^(Vref/2)+(Vref/4)， 大於類比輸入Vin，比較器14輪出結果為丨，第二位元Βι被決 定為0 ;最後’連續逼近控制邏輯16將第三位元Bg設為i， 此時類比輸出VDAC為(Vref/2)+(Vre沒8)，小於類比輸入Vin，比 較器14輸出結果為〇，決定第三位元％為i，轉換類比輸入 之電位值Vin產生之對應數位碼輸出^為101，結束位元循 環階段。 ❹ 圖3為習知12-bit的ADC示意圖，通常内建在微控制器中， 取樣及DAC電路22係以電容陣列組成之電容式數位轉類比轉 換器(CDAC)實現，提供取樣以及數位轉類比的功能，連續逼 近控制邏輯20以訊號DA[ll:〇]控制取樣及DAC電路22中的 開關SW11〜SWO。圖3之每一開關SW11〜SWO實際上是以兩 個開關實現的’參照圖4 ’例如開關SW11係由開關SW11A 和開關SW11B組成，皆由訊號DA[11]控制，當DA[n卜〇時， ❹ 開關SW11A關上而開關SW11B開路，反之當DA[11]=1時， 開關SW11A開路而開關swilB關上，換言之，取樣及DAC 電路22中的各個電容不是連接至Vref+就是連接至Vm，％ 在取樣階段時連接至類比輸入vin，在位元循環階段時則連接 至Vref•。在這種架構下，當要以12-bit的ADC做較低解析度 轉換時’雖然將電路内節點電位充放到位之準確度要求降為 8-bit解析度可減少些許時間，但12_bit的電容陣列總電容值仍 是固定的(CT0TAL=2NC，N=12)，轉換時之充放電時間仍受此一 大電容限制，例如電動自行車對解析度之需求僅為 201027928 8需 =，但要求高轉換速度’目前_建ADc便難以滿足此類 美國專利第72657G8號提出-種纽排列 之電容’以獲得期望之電容值來達成所需之解析度的方:陣二] 這種方法的電路控制甚為複雜，需付出較大的晶片^二 也相應提高。 <本 【發明内容】 〇 ❹ 種可切換位元解析度的類比轉 本發明的目的之一，在於提出一 數位轉換器。 本發明的目的之-’在於糾-種可域位元解析度的類比轉 數位轉換器的控制方法。 根據本發明，一種可切換位元解析度的類比轉數位轉換器包括 取樣及數位轉類比電路’提供取樣及數位轉類比的功能，包括 由複數個並聯的電容以及複數個串聯每一該電容的開關組成 的電谷陣列，取樣類比輸入而產生第一電位，比較器將該取樣 及數位轉類比電路上的第二電位與該第一電位相比較，產生比 較結果，以及連續逼近控制邏輯，控制該電容陣列中該些開關 的切換，並根據該比較結果獲得該類比輸入的對應數位碼，其 中，該連續逼近控制邏輯-根據·一位元解析度選擇訊號調整其取 樣和位元循環階段的時間，並控制該些開關的切換，使該些電 容處於第一連接狀態、第二連接狀態或無效狀態。 根據本發明’ 一種可切換位元解析度的類比轉數位轉換器的控 制方法’該類比轉數位轉換器包括取樣及數位轉類比電路，該 201027928 取樣及數位轉類比電路包括由複數個並聯的電容以及複數個 串聯每一該電容的開關組成的電容陣列，該控制方法包括根據 一位元解析度選擇訊號調整取樣階段時間和位元循環階段時 間’切換該些開關’使部份的該些電容處於無效狀態，取樣類 比輸入而產生第一電位，切換該些開關，使其他的該些電容處 於第一連接狀態或第二連接狀態，以在該取樣及數位轉類比電 路上產生第二電位，比較該第一電位及該第二電位’產生比較 結果，以及根據該比較結果，決定該類比輸入對應的數位碼。 其中，該些電容在該無效狀態時被浮接、短路或連接到任意其 他電壓。變化地，更包括以電阻串以及解碼器組成之電阻式數 位轉類比電路，連接該連續逼近控制邏輯以及該電容陣列。 【實施方式】 本發明長:出一種可切換位元解析度的類比轉數位轉換器及其 控制方法，圖5係根據本發明第一實施例的示意圖，為方便說 Ο 明’本說明書中皆以12-bit SAR ADC切換為10-bit舉例說明。 在圖5之實施例中’以電容陣列組成之電容式數位轉類比轉換 器(CDAC)實現的取樣及DAC電路％連接連續逼近控制邏輯 30和比較器34，位元解析度選擇訊號由腳位BITSEL輸入， 當腳位BITSEL被設定為〇時，adc以最大位元數工作，連 續逼近控制邏輯以訊號DA[11:〇]控制取樣及DAC電路幻中 開關SW11〜SW0的切換’換言之，各電容僅有兩種狀離，不 是連接至爾+就是連接至Vm。在取樣階段期間，開關〜觀 及SWB導通，開關Swc開路，Vm連接至類比輸入％，所 201027928 有電容的另一端則與比較器34的正輸入端共同連接節點p， 類比接地電位AGND經由開關SWB提供給節點p，節點p處 的電位以VP表示，取樣階段結束時，取樣及DAC電路32兩 端的電壓差為(Vin-AGND) ; ADC進入位元循環階段時，開關 SWA及SWB開路，開關SWC導通，並經由連續逼近控制邏 輯30送出訊號DA[11:0] ’切換開關SW11〜SW0，依照電荷守 恆原理’正輸入端P處的電位VP為AGND+AV ’其中Δν因 @ 開關SW11〜SW0使各電容連接之電位不同而改變，比較器34 比較輸出之結果決定開關SW11〜SW0之連接電位，在位元循 環階段結束時使Δν最接近〇，換言之，此時的VP最接近 AGND ’因而決定類比輸入％相對之數位碼Dout，並由連續 逼近控制邏輯30輸出。藉由電荷守恆原理獲得類比輸入之相 對數位碼為習知技術，熟習本發明技術領域者當知。 而當腳位BITSEL被設定為1時，如圖6所示，ADC由12-bit 切換為1 Ο-bit，連續逼近控制邏輯30以訊號DAS [ 11 ]和DAS [ 10] G 將最高位元電容2048C及次高位元電容i〇24C浮接(floating) 而無效，並調整取樣階段時間及位元循環階段時間。參照圖4， 在本實施例中’訊號DAS[11]將構成開關11的開關SW11A及 SW11B都開路，訊號DAS[10]亦然，電容2048C及1024C在 整個ADC的轉換過程中維持浮接，因此在連續逼近的過程 中’節點P處的電位VP與電容2048C及電容1024C無關， 此時取樣及DAC電路32等效於10-bit的CDAC，整個ADC 的解析度下降為10-bit。 本發明提出之類比轉數位轉換器藉由增加一訊號控制連接至 201027928 電容陣列之開關，使電容陣列中的電容除了原先的第一連接狀 態(Vref+)和第二連接狀態(Vm)外，增加了無效狀態，因此可 使電容陣列等效之CDAC的位元數數目降低，因而實現另一 解析度位元數之類比轉數位轉換器。 . ADC完成-筆類比輸人轉換所需的時，取樣階段時間加上 位元循環階段時間。位元循環階段時，對N_bitADC的電容陣 列兩端電位充放電時間的計算式如下 T=0.69x(N+l)xReqxCeq 式工 ❹ 其中’分別表示電容陣列在充放電路徑上的等效電阻 及電容。 在圖6之實施例中，ADC解析度的降低係藉由降低内部 DAC的解析度達$，因此在解析度由⑽红降低為ι嫩時， 除了其位元郷之逼近次數由12降為1()以外，電位充放到位 =要求之解析度降低且最纽元所需充放電之電容數目減 少，使得位元猶環之時間亦賴縮短。取樣階段所需時間的公 0 式如下： 取樣時間(Sampling)= (n+Ux㈣χ r，τ =RxC 式 2 由式2可知取樣時間與電容值成正比，因此，與12脱運算相 本實施例在lG-bit運算時不但減少了位元循環時的逼近次 數々、減少每次逼近時所需的充放電時間(TAD10<TAD]2)，取樣時 ^效電谷匸叫亦降低為為原本的四分之一，更縮短了取樣階 &所需的時間。圖7為本發明第—實施例的時序圖，可以 整體轉換時間明顯減少。 圓8係本發明之第二實施例的示意圖 ，係以電阻串48組成之 201027928 電阻式數位轉類比轉換器(RDAC)，以及包含電容陣列的取樣 及DAC電路46混合實現12-bit SAR ADC。在本實施例中， 以電阻串48構成之RDAC為最高位元成份(Most-significant Bits; MSBs)，取樣及DAC電路46構成之CDAC為最低位元 成份(Least-significant Bits; LSBs)。使用者藉由控制腳位 BITSEL選擇ADC的解析度’當腳位BITSEL為〇時，adc 以最大解析度工作，在取樣階段期間，開關SWA及SWB導 通’開關SWC及SWD開路，此時所有電容之一端Vrn連接 ® 至類比輸入Vin ’電位AGND連接至比較器42的正輸入端， 並透過節點P連接所有電容的另一端，取樣及Dac電路46 將類比輸入Vin完整地取樣存取’在取樣階段結束時，取樣及 DAC電路46兩端的電位為(Vin-AGND)。接著，ADC進入位 元循環階段，此時開關SWA及SWB開路而開關SWC及SWD 導通連接至電阻串48，連續逼近控制邏輯4〇送出訊號da[1 1:6] 控制解碼器44選擇電阻串48上之電位連接至取樣及DAC電 ❹ 路46中電容的一端’待電阻串48解出MSBs之後，連續逼近 控制邏輯40再切換取樣及DAC電路46中開關SW5〜SW0之 連接’並經比較器42比較輸出之結果，決定開關SW5〜SW0 之連接電位使節點p的電壓vp最接近電壓AGND，此時連接 電阻串48之解碼器44與取樣及DAC電路46的輸入碼(input code)DA[l 1 :〇]即為類比輸入Vin相對之數位碼，並由連續逼近 邏輯40輸出。 當BITSEL=1時，如圖9所示，連續逼近控制邏輯4〇以訊號 DAS[5]和DAS[4]將取樣及DAC電路46中之開關§"^5及SW4 201027928 開路，使電容32C和電容16C浮接而處於無效狀態，因此在 ADC連續逼近的過程中，電壓VP與電容32C及電容16C無 關，此時之取樣及DAC電路46等效為4-bit的DAC，因此整 體而言，ADC的解析度切換成i〇-bit。 圖10係根據本發明之第三實施例的示意圖，改以包含電容陣 列的取樣及DAC電路56作為MSBs，電阻串52作為LSBs， 利用控制腳位BITSEL選擇ADC之解析度。在BITSEL=〇時， ADC以最大位元數工作’在取樣階段期間，開關SWA、SWB ❺ 及SWDA導通，開關SIWC及SWD開路，此時所有電容之一 端Vm連接至類比輸入vin，另一端經由節點p連接至比較器 58輸入正端之電位AGND，取樣及DAC電路56取樣存取類 比輸入Vin，取樣階段結束時，取樣及DAC電路56兩端電位 為(Vin-AGND)，接著ADC進入位元循環階段，此時開關SWA 及SWB開路’開關SWC及SWD分別導通並連接至Vref+及 Vref-，此外’最末端的電容1C於we轉換MSBs時透過開 © 關SWDA連接至Vref-，連績逼近控制邏輯5〇送出訊號 DA[11:6]切換電容陣列56中開關SW11〜SW6，並經比較器58 比較輸出之結果決定SW11〜SW6之連接電位，取樣及DAc 電路56完成MSBs之轉換後，電阻串52構成之繼績 完成位元循環袼鹿，此時取樣及DAC電路％最末端的電容 ic的一端連接節點p，另一端經由開關SWDA以及訊號 DA[5:0]對解碼器54的控制，連接至電阻串52上的電位。由 於位域環過程巾連接之電位不同，依電荷守㈣理，節點p 處的電壓VP會改變為AGND+ΔΥ，位元循環階段結束時，會 201027928 使Δν最接近0而VP最接近AGND，此時連接電阻串52之 解碼器54與取樣及DAC電路56的輸入碼DA[11:0]即為類比 輸入Vin相對之數位碼，並由連續逼近控制邏輯5〇輪出。 在BITSEL=1時，如圖u所示，訊號DAS[11]和訊號DAS[10] 將開關SW11和SW10開路，使電容32C及電容16C浮接而 無效’因此在ADC連續逼近的過程中’節點P處的電位vp 與電容64C及電容32C無關，此時之取樣及DAC電路56等 效於4-bit的CDAC，因此對整體ADC而言其解析度也已改 ® 變為 ΙΟ-bit。 參照圖5，除了將電容浮接以外，還有許多方法可以將電容切 換成無效狀態，圖12至14繪示將取樣及DAC電路32切換成 ΙΟ-bit之CDAC的各實施例。 如圖12所示，開關SW11...SW0的切換和習知技術相同，受 訊號DA[11]."DA[0]控制，僅有切換連接到電壓Vref+和Vm 兩種狀態’但在每一電容連接到節點P的路徑上增設開關 ❹ SW11C、SW10C...SW1C 和 SWOC，受訊號 DAS[11]和訊號 DAS[l〇]控制而開路，使電容2048C和1024C無效。 圖13繪示取樣及DAC電路32的另一實施例，當解析度由 12-bit切換成i〇_bit時，開關SW11C和SW10C受控切換石連 接任意其他電位AGND2，使電容2048C和1024C在取樣及 DAC電路32中無效。 圖14繪示取樣及DAC電路32的又一實施例，當解析度由 12-bit切換成 10_bit 時，開關 swilC、SWU、SW10C 以及 SW10 受控切換使電容2048C和1024C短路，對於整體CDAC而言， 11 201027928 電容2048C和1024C不存在，此時取樣及DAC電路32所構 成之CDAC的解析度為l〇-bit。 在其他實施例中，參照圖6，亦可以將開關SW11〜SW10由浮 接改為切換連接至任意其他電壓，或者，參照圖，切換開Digital Converter; ADC) ' Especially for analog-to-digital converters with a switchable bit resolution and its control method. [Prior Art] FIG. 1 is a block diagram of a conventional SAR ADC 'Sample and Hold Circuit (S/H) 12, a comparator 14, and a digital-to-analog converter (DAC) 18 And continuous approximation control logic 16 for continuous approximation of the sampled analog input in a Binary Search manner. The action of ADC 10 begins in the sampling phase, during which the sampling circuit 12 takes a complete sample access to the analog input, and then aqc 10 enters the bit-cycling phase to determine the digital code output. Conversion. Figure 2 takes a 3-bit SAR ADC as an example. Figure 1 illustrates how binary search performs continuous approximation. At the beginning of the bit cycle phase, the continuous approximation control logic 16 first sets the highest (first) bit (MSB) B2 of the input DAC 18 to 1 (logic high level), second and second. Bits Βι, B〇 are 〇 (logic low level) 'Let DAC 18 analog output VDAC is Vref2 ' At this time, the analog output Vdac is compared with the analog input %, the analog output VDAC is smaller than the analog input Vin, and the comparator output is 〇, the continuous approximation control logic 16 determines that the value of the first bit is 1; then, the continuous approximation control 3 201027928 The logic 16 maintains the first bit & 1 and sets the second bit 〇 from 〇 to 丄, the first The two-bit B〇 is still set to 〇' at this time, the analog output VDAc^(Vref/2)+(Vref/4) is greater than the analog input Vin, the comparator 14 turns the result to 丨, and the second bit Βι is determined as 0; Finally, the continuous approximation control logic 16 sets the third bit Bg to i. At this time, the analog output VDAC is (Vref/2)+ (Vre is 8), which is smaller than the analog input Vin, and the output of the comparator 14 is 〇. Decide that the third bit % is i, and the corresponding digital code output generated by the conversion analog input potential value Vin is 101, Beam bit cycle stage. ❹ Figure 3 is a schematic diagram of a conventional 12-bit ADC, usually built into a microcontroller. The sampling and DAC circuit 22 is implemented by a capacitive digital-to-digital converter (CDAC) consisting of a capacitor array, providing sampling and digital conversion. Analogous to the function, the continuous approximation control logic 20 controls the sampling and the switches SW11 to SWO in the DAC circuit 22 with a signal DA[11:〇]. Each of the switches SW11 to SWO of FIG. 3 is actually implemented by two switches 'refer to FIG. 4'. For example, the switch SW11 is composed of the switch SW11A and the switch SW11B, and is controlled by the signal DA[11], when DA[n] When , switch SW11A is closed and switch SW11B is open, when DA[11]=1, switch SW11A is open and switch swilB is closed, in other words, each capacitor in sampling and DAC circuit 22 is not connected to Vref+ or is connected to Vm, % Connected to the analog input vin during the sampling phase and to Vref• during the bit cycle phase. Under this architecture, when a 12-bit ADC is used for lower resolution conversion, the accuracy of charging and sinking the node potential in the circuit is reduced to 8-bit resolution, which can reduce the time, but 12_bit. The total capacitance of the capacitor array is still fixed (CT0TAL=2NC, N=12), and the charge and discharge time during conversion is still limited by this large capacitance. For example, the demand for resolution of electric bicycle is only 201027928 8 required, but the requirement High conversion speed 'currently _ ADc is difficult to meet the requirements of such US Patent No. 72657G8 - the capacitance of the array arrangement to obtain the desired capacitance value to achieve the required resolution: Array 2] Circuit of this method The control is very complicated, and it takes a lot of wafers to be added. <Abstract> This is an analogy of the resolution of the switchable bit element. One of the objects of the present invention is to propose a digital converter. The object of the present invention is to control the analog-to-digital converter of the domain-resolvable bit-domain resolution. According to the present invention, an analog-to-digital converter of switchable bit resolution includes a sampling and digital to analog circuit that provides a sampling and digital to analog function, including a plurality of capacitors in parallel and a plurality of capacitors in series. An array of electric valleys composed of switches, sampling analog input to generate a first potential, the comparator comparing the second potential on the sampling and digital analog circuit with the first potential, generating a comparison result, and continuously approximating control logic, controlling Switching between the switches in the capacitor array, and obtaining a corresponding digital code of the analog input according to the comparison result, wherein the continuous approximation control logic adjusts the sampling and bit cycle stages according to the one-bit resolution selection signal Time, and controlling the switching of the switches, so that the capacitors are in the first connected state, the second connected state, or the inactive state. According to the present invention, a control method for an analog-to-digital converter of switchable bit resolution, the analog-to-digital converter includes a sampling and digital to analog circuit, and the 201027928 sampling and digital to analog circuit includes a plurality of capacitors connected in parallel And a plurality of capacitor arrays each of which is connected in series with each of the capacitors, the control method includes: adjusting a sampling phase time according to a bit resolution selection signal and a bit cycle phase time to "switch the switches" to make the capacitors In an inactive state, the sampling analog input generates a first potential, and the switches are switched such that the other capacitors are in a first connected state or a second connected state to generate a second potential on the sampling and digital analog circuit. Comparing the first potential and the second potential to generate a comparison result, and determining a digital code corresponding to the analog input based on the comparison result. Wherein, the capacitors are floated, shorted or connected to any other voltage in the inactive state. Optionally, a resistive digital to analog circuit comprising a resistor string and a decoder is coupled to the continuous approximation control logic and the capacitor array. [Embodiment] The present invention is directed to an analog-to-digital converter and a control method thereof, and FIG. 5 is a schematic diagram of a first embodiment of the present invention. An example of switching a 12-bit SAR ADC to 10-bit is illustrated. In the embodiment of FIG. 5, the sampling and DAC circuit % implemented by a capacitive digital-to-digital converter (CDAC) composed of a capacitor array is connected to the continuous approximation control logic 30 and the comparator 34, and the bit resolution selection signal is from the pin position. BITSEL input, when the pin BITSEL is set to 〇, adc works with the maximum number of bits, the continuous approximation control logic controls the sampling with the signal DA[11:〇] and the switching of the DAC circuit phantom switches SW11~SW0. In other words, each The capacitor has only two kinds of separation, not connected to er + or connected to Vm. During the sampling phase, the switch ~ view and SWB are turned on, the switch Swc is open, Vm is connected to the analog input %, and the other end of the capacitor of 201027928 is connected to the positive input of the comparator 34 to the node p, the analog ground potential AGND is via the switch SWB is supplied to node p, and the potential at node p is represented by VP. At the end of the sampling phase, the voltage difference between the sampling and DAC circuit 32 is (Vin-AGND); when the ADC enters the bit cycle, the switches SWA and SWB are open. The switch SWC is turned on, and the signal DA[11:0] 'switches SW11~SW0 are sent via the continuous approximation control logic 30. According to the principle of conservation of charge, the potential VP at the positive input terminal P is AGND+AV 'where Δν is @@SW11 ~SW0 changes the potential of each capacitor connection, and the result of comparator 34 comparison output determines the connection potential of switches SW11~SW0. At the end of the bit cycle phase, Δν is closest to 〇, in other words, VP is closest to AGND at this time. Thus, the digital code Dout is compared to the analog input % and is output by the continuous approximation control logic 30. The acquisition of analog-to-digital codes by analogy of charge conservation is a well-known technique and is well known to those skilled in the art. When the pin BITSEL is set to 1, as shown in Figure 6, the ADC is switched from 12-bit to 1 Ο-bit, and the continuous approximation control logic 30 uses the signals DAS [11] and DAS [10] G to the highest bit. The capacitor 2048C and the next highest bit capacitor i〇24C are floated and invalidated, and the sampling phase time and the bit cycle phase time are adjusted. Referring to FIG. 4, in the present embodiment, the signal DAS[11] opens the switches SW11A and SW11B constituting the switch 11, and the signals DAS[10] are also the same, and the capacitors 2048C and 1024C maintain the floating connection during the conversion process of the entire ADC. Therefore, during the continuous approximation, the potential VP at the node P is independent of the capacitor 2048C and the capacitor 1024C. At this time, the sampling and DAC circuit 32 is equivalent to the 10-bit CDAC, and the resolution of the entire ADC is reduced to 10-bit. The analog-to-digital converter proposed by the present invention increases the connection of the capacitor to the 201027928 capacitor array by adding a signal to increase the capacitance in the capacitor array in addition to the original first connection state (Vref+) and the second connection state (Vm). The invalid state, so that the number of bits of the CDAC equivalent of the capacitor array can be reduced, thus implementing an analog-to-digital converter of another resolution number of bits. When the ADC completes - pen analog input conversion is required, the sampling phase time plus the bit cycle phase time. In the bit cycle phase, the calculation of the potential charge and discharge time of the capacitor array of the N_bitADC is as follows: T=0.69x(N+l)xReqxCeq] where 'represents the equivalent resistance of the capacitor array on the charge and discharge path and capacitance. In the embodiment of FIG. 6, the resolution of the ADC is reduced by reducing the resolution of the internal DAC by $, so when the resolution is reduced from (10) red to ι, the number of approximations of the bit 郷 is reduced from 12 to 1 In addition to (), the potential is charged and discharged in place = the required resolution is reduced and the number of capacitors required for charging and discharging of the most new element is reduced, so that the time of the bit is also shortened. The time required for the sampling phase is as follows: Sampling = (n + Ux (four) χ r, τ = RxC Equation 2 From Equation 2, the sampling time is proportional to the capacitance value. Therefore, the 12-off operation phase is lG-bit operation not only reduces the number of approximations in the bit cycle, but also reduces the charge and discharge time required for each approximation (TAD10<TAD]2). When sampling, the effect is also reduced to the original One quarter, the time required for the sampling stage & is further shortened. Figure 7 is a timing diagram of the first embodiment of the present invention, which can significantly reduce the overall conversion time. Circle 8 is a schematic diagram of a second embodiment of the present invention, A 12-bit SAR ADC is realized by a 201027928 resistive digital-to-digital converter (RDAC) composed of a resistor string 48 and a sampling and DAC circuit 46 including a capacitor array. In this embodiment, the RDAC is formed by a resistor string 48. For the Most-significant Bits (MSBs), the CDAC formed by the sampling and DAC circuit 46 is the Least-significant Bits (LSBs). The user selects the resolution of the ADC by controlling the pin BITSEL. When the pin position BITSEL is 〇, a Dc operates at maximum resolution. During the sampling phase, switches SWA and SWB turn on 'switch SWC and SWD open, at which point one of the capacitors Vrn is connected to the analog input Vin' potential AGND is connected to the positive input of comparator 42. The other end of all capacitors is connected through node P, and the sampling and Dac circuit 46 completely samples the analog input Vin. At the end of the sampling phase, the potential across the sampling and DAC circuit 46 is (Vin-AGND). Next, the ADC In the bit cycle phase, the switches SWA and SWB are open and the switches SWC and SWD are connected to the resistor string 48. The continuous approximation control logic 4 sends the signal da[1 1:6] to control the decoder 44 to select the resistor string 48. The potential is connected to the sampling and DAC circuit. One end of the capacitor in the path 46. After the resistor string 48 resolves the MSBs, the continuous approximation control logic 40 switches the sampling and the connection of the switches SW5 to SW0 in the DAC circuit 46' and compares by the comparator 42. As a result of the output, the connection potential of the switches SW5 to SW0 is determined such that the voltage vp of the node p is closest to the voltage AGND, and at this time, the decoder 44 of the resistor string 48 and the input code DA of the sampling and DAC circuit 46 are connected [ l 1 :〇] is the digital code of analog input Vin, and is output by continuous approximation logic 40. When BITSEL=1, as shown in Figure 9, continuous approximation control logic 4 signals DAS [5] and DAS [ 4] Open the switch §"^5 and SW4 201027928 in the sampling and DAC circuit 46, so that the capacitor 32C and the capacitor 16C are floating and in an inactive state, so during the continuous approximation of the ADC, the voltage VP and the capacitor 32C and the capacitor Regardless of 16C, the sampling and DAC circuit 46 at this time is equivalent to a 4-bit DAC, so overall, the resolution of the ADC is switched to i〇-bit. Figure 10 is a schematic illustration of a third embodiment of the present invention, with sampling and DAC circuit 56 comprising a capacitor array as MSBs and resistor string 52 as LSBs. The resolution of the ADC is selected using control pin BITSEL. When BITSEL=〇, the ADC operates with the maximum number of bits. During the sampling phase, the switches SWA, SWB ❺ and SWDA are turned on, and the switches SIWC and SWD are open. At this time, one of the capacitors Vm is connected to the analog input vin, and the other end is connected via the analog input vin. The node p is connected to the potential AGND of the positive terminal of the comparator 58 input, and the sample and DAC circuit 56 samples the access analog input Vin. At the end of the sampling phase, the potential of the sample and DAC circuit 56 is (Vin-AGND), and then the ADC enters the bit. In the meta-cycle phase, at this time, the switches SWA and SWB are open, 'the switches SWC and SWD are respectively turned on and connected to Vref+ and Vref-, and the 'endmost capacitor 1C' is connected to Vref- through the open/close SWDA when the MSBs are converted. The proximity control logic 5 sends the signal DA[11:6] to switch the switches SW11~SW6 in the capacitor array 56, and the result of the comparison output of the comparator 58 determines the connection potential of the SW11~SW6, and the sampling and DAc circuit 56 completes the conversion of the MSBs. The resistor string 52 constitutes a successor to complete the loop of the elk. At this time, one end of the sampling and DAC circuit % terminal ic is connected to the node p, and the other end is connected to the decoder 54 via the switch SWDA and the signal DA[5:0]. control Connected to the potential on the resistor string 52. Since the potential of the bit field loop process towel is different, according to the charge (4), the voltage VP at the node p will change to AGND+ΔΥ. At the end of the bit cycle phase, 201027928 will make Δν closest to 0 and VP closest to AGND. At this time, the decoder 54 connecting the resistor string 52 and the input code DA[11:0] of the sampling and DAC circuit 56 are the digital code of the analog input Vin, and are rotated by the continuous approximation control logic. When BITSEL=1, as shown in Figure u, signal DAS[11] and signal DAS[10] open switches SW11 and SW10, causing capacitor 32C and capacitor 16C to float and fail 'so in the process of ADC continuous approximation' The potential vp at the node P is independent of the capacitor 64C and the capacitor 32C. At this time, the sampling and DAC circuit 56 is equivalent to the 4-bit CDAC, so the resolution of the overall ADC has also been changed to ΙΟ-bit. Referring to Figure 5, in addition to floating the capacitance, there are a number of ways to switch the capacitance to an inactive state. Figures 12 through 14 illustrate various embodiments of a CDAC that switches the sampling and DAC circuit 32 to a ΙΟ-bit. As shown in FIG. 12, the switching of the switches SW11...SW0 is the same as the prior art, and is controlled by the signal DA[11]."DA[0], and only switches to the voltages Vref+ and Vm. The switches ❹ SW11C, SW10C...SW1C and SWOC are added to the path of each capacitor connected to the node P, and are opened by the signal DAS[11] and the signal DAS[l〇] to make the capacitors 2048C and 1024C invalid. 13 illustrates another embodiment of the sampling and DAC circuit 32. When the resolution is switched from 12-bit to i〇_bit, the switches SW11C and SW10C are controlled to switch to any other potential AGND2, so that the capacitors 2048C and 1024C are The sampling and DAC circuit 32 is invalid. 14 illustrates yet another embodiment of the sampling and DAC circuit 32. When the resolution is switched from 12-bit to 10_bit, the controlled switching of the switches swilC, SWU, SW10C, and SW10 shorts the capacitors 2048C and 1024C, for the overall CDAC. , 11 201027928 Capacitors 2048C and 1024C do not exist. At this time, the resolution of the CDAC composed of the sampling and DAC circuit 32 is l〇-bit. In other embodiments, referring to FIG. 6, the switches SW11 SWSW10 may be switched from floating to switched to any other voltage, or, with reference to the figure, switched on.
關 SW11C、SW11、SW10C 以及 SW10 使電容 2048C 和 1024C 短路並連接到任意其他電壓。 本發明藉由將電容陣列中之電容以控制邏輯切換成無效’達到 ❾ 改變電容陣列所構成之CDAC的解析度，因而調整整體adc 的解析度。 以上對於本發明之較佳實施例所作的敘述係為闡明之目的，而 無意限定本發明精確地為所揭露的形式，基於以上的教導或從 本發明的實施例學習而作修改或變化是可能的，實施例係為解 說本發明的原理以及讓熟習該項技術者以各種實施例利用本 發明在實際應用上而選擇及敘述，本發明的技術思想企圖由以 下的申請專利範圍及其均等來決定。 【圖式簡單說明】 圖1係習知SARADC的方塊圖； 圖2繪示3-bit之SARADC如何以二元搜尋完成連續逼近； 圖3係習知12-bit SAR ADC的示意圖； 圖4係圖3中開關swil的實際組成示意圖； 圖5係本發明第一實施例以最大位元(12-bit)工作時的示意圖； 圖6係圖5之實施例切換成10-bit時的示意圖； 圖7為本發明第一實施例的時序圖； 12 201027928 圖係本發明之第二實施例以最大位元工作時的示意圖； 圖9係圖8之實施例切換成i〇-bit時的示意圖； 圖10係本發明第三實施例以最大位元工作時的示意圖； 圖11係圖10之實施例切換成i〇_bit時的示意圖； 圖12係根據本發明之取樣及DAC電路一實施例的示意囷； 圖13係根據本發明之取樣及DAC電路另一實施例的示意圖； 以及 圖14係根據本發明之取樣及DAC電路又一實施例的示意圖。 【主要元件符號說明】 10 ADC 12 取樣電路 14 比較器 16 連續逼近控制邏輯 18 DAC 20 連續逼近控制邏輯 22 取樣及DAC電路 24 比較器 30 連續逼近控制邏輯 32 取樣及DAC電路 34 比較器 40 連續逼近控制邏輯 42 比較器 44 解碼器 13 201027928 46 取樣及DAC電路 48 電阻串 50 連續逼近控制邏輯 52 電阻串 54 解碼器 56 取樣及DAC電路 58 比較器 14Off SW11C, SW11, SW10C, and SW10 short-circuit capacitors 2048C and 1024C and connect to any other voltage. The present invention adjusts the resolution of the overall adc by changing the capacitance of the capacitor array to control by the control logic to achieve the resolution of the CDAC formed by the capacitor array. The above description of the preferred embodiments of the present invention is intended to be illustrative, and is not intended to limit the scope of the invention to the disclosed embodiments. It is possible to make modifications or variations based on the above teachings or learning from the embodiments of the present invention. The embodiments are described and illustrated in the practical application of the present invention in various embodiments, and the technical idea of the present invention is intended to be equivalent to the scope of the following claims. Decide. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a conventional SARADC; FIG. 2 is a schematic diagram showing how a 3-bit SARADC performs continuous approximation by binary search; FIG. 3 is a schematic diagram of a conventional 12-bit SAR ADC; 3 is a schematic diagram of the actual composition of the switch swil; FIG. 5 is a schematic diagram of the first embodiment of the present invention operating with the largest bit (12-bit); FIG. 6 is a schematic diagram of the embodiment of FIG. 5 when switched to 10-bit; FIG. 7 is a timing chart of the first embodiment of the present invention; 12 201027928 is a schematic diagram of the second embodiment of the present invention operating with the largest bit; FIG. 9 is a schematic diagram of the embodiment of FIG. 8 when switching to i〇-bit Figure 10 is a schematic diagram of the third embodiment of the present invention operating with the largest bit; Figure 11 is a schematic diagram of the embodiment of Figure 10 when switched to i〇_bit; Figure 12 is a sampling and DAC circuit implementation in accordance with the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 13 is a schematic illustration of another embodiment of a sampling and DAC circuit in accordance with the present invention; and Figure 14 is a schematic illustration of yet another embodiment of a sampling and DAC circuit in accordance with the present invention. [Main component symbol description] 10 ADC 12 Sampling circuit 14 Comparator 16 Continuous approximation control logic 18 DAC 20 Continuous approximation control logic 22 Sampling and DAC circuit 24 Comparator 30 Continuous approximation control logic 32 Sampling and DAC circuit 34 Comparator 40 Continuous approximation Control Logic 42 Comparator 44 Decoder 13 201027928 46 Sampling and DAC Circuit 48 Resistor String 50 Continuous Approximation Control Logic 52 Resistor String 54 Decoder 56 Sampling and DAC Circuit 58 Comparator 14