TW201027699A - Wiring member for semiconductor device, composite wiring member for semiconductor device, and resin-sealed semiconductor device - Google Patents

Wiring member for semiconductor device, composite wiring member for semiconductor device, and resin-sealed semiconductor device Download PDF

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Publication number
TW201027699A
TW201027699A TW098123933A TW98123933A TW201027699A TW 201027699 A TW201027699 A TW 201027699A TW 098123933 A TW098123933 A TW 098123933A TW 98123933 A TW98123933 A TW 98123933A TW 201027699 A TW201027699 A TW 201027699A
Authority
TW
Taiwan
Prior art keywords
semiconductor device
semiconductor wafer
wiring member
wiring
terminal portion
Prior art date
Application number
TW098123933A
Other languages
Chinese (zh)
Other versions
TWI416688B (en
Inventor
Susumu Baba
Masachika Masuda
Hiromichi Suzuki
Original Assignee
Dainippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2009004827A external-priority patent/JP5110441B2/en
Application filed by Dainippon Printing Co Ltd filed Critical Dainippon Printing Co Ltd
Publication of TW201027699A publication Critical patent/TW201027699A/en
Application granted granted Critical
Publication of TWI416688B publication Critical patent/TWI416688B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

To provide a wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device, each of which is capable of surely mounting thereon a (fined) semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device for a semiconductor device 10 electrically connects an electrode 15A provided on a semiconductor chip 15 with an external wiring device 21. The wiring device for a semiconductor device 10 has an insulating layer 11, a metal substrate 12 and a copper wiring layer 13. The metal substrate 12 is provided on one side of the insulating layer 11. The copper wiring layer 13 is provided on another side of the insulating layer 11. The wiring device has a semiconductor chip support portion 11A provided on the side of the copper wiring layer 13 with respect to the insulating layer 11. The copper wiring layer 13 includes a first terminal 13D, a second terminal 13E and a wiring portion 13C. The first terminal 13D is connected with the electrode 15A provided on the semiconductor chip 15. The second terminal 13E is connected with the external wiring device 21. The wiring portion 13C connects the first terminal 13D with the second terminal 13E.

Description

201027699 六、發明說明 【發明所屬之技術領域】 本發明關於半導體裝置用配線構件、半導體裝置用複 合配線構件、及樹脂密封型半導體裝置，亦即關於可以確 實安裝較習知更小型化之半導體晶片之同時，可以降低製 造成本的半導體裝置用配線構件、半導體裝置用複合配線 構件、及樹脂密封型半導體裝置。 【先前技術】 . 近年來，半導體裝置由高積體化或小型化技術之進 步、電子機器之高性能化與輕薄短小化之傾向，進展爲更 加高積體化、高功能化。於此種高積體化、高功能化之半 導體裝置中，被要求外部端子（pin)之總和之增加或更 爲多端子化。 作爲此種半導體裝置之半導體封裝，有在引線框架搭 φ 載1C晶片、LSI晶片等之半導體晶片，以絕緣性樹脂予 以密封之構造者。於此種半導體裝置，伴隨高集積化及小 型化之進展，封裝之構造亦從 SOJ ( Small Outline J-Leaded Package)或 QFP( Quad Flat Package)等外部引 線由樹脂封裝之側壁朝外側突出之形態，進展成爲外部引 線不朝外側突出，而是外部引線以露出樹脂封裝之背面的 方式被埋設的 QFN ( Quad Flat Non-leaded Package)或 SON ( Small Outline Nonleaded Package )等薄型、安裝 面積較小的形態。 -5- 201027699 另外，爲迴避QFP封裝具有之安裝效率、安裝性問 題，以錫球作爲封裝之外部端子而具備的被稱爲表面安裝 型封裝之BG A ( Ball Grid Array )之樹脂密封型半導體裝 置被量產。另外，取代BG A之錫球，改設置矩陣狀平面 電極構成之外部端子而構成之表面安裝型封裝，有稱爲 LGA ( Land Grid Array)之半導體裝置。 專利文獻1 :特許第2688099號公報 專利文獻2:特開平10-41434號公報 φ 【發明內容】 · (發明所欲解決之課題） · 但是，半導體晶片益加進展爲小型化（fine )，引線 框架之內部引線之間距（間隔）之狹窄化有其限制，因 此，可以預見將此種小型化半導體晶片搭載於引線框架漸 次變爲困難。 又，進行此種半導體裝置之檢測時，需要安裝半導體 G 晶片，作爲包含半導體晶片之半導體裝置完成後進行之檢 測。因此，在半導體晶片非良品時需要廢棄半導體裝置全 體。因此，半導體晶片之良品率惡化時，成本面之損失變 大之可能性存在。 本發明有鑑於此問題，目的在提供可以確實安裝小型 化之半導體晶片之同時，在作爲半導體裝置被進行密封 前’可以進行半導體晶片之檢測，而且可降低製造成本的 半導體裝置用配線構件、半導體裝置用複合配線構件、及 -6- 201027699 樹脂密封型半導體裝置。 (用以解決課題的手段） 本發明之半導體裝置用配線構件，係用於電連接半導 體晶片上之電極與外部配線構件者；其特徵爲具備：絕緣 層；配置於絕緣層之一側的金屬基板；及配置於絕緣層之 另一側的銅配線層；在絕緣層之於銅配線層側或銅配線層 φ 上形成半導體晶片載置部；銅配線層，係包含：第1端子 部，被連接於半導體晶片上之電極；第2端子部，被連接 於外部配線構件；及配線部，用於連接第1端子部與第2 ' 端子部。 本發明之半導體裝置用配線構件之中，金屬基板，係 由不鏽鋼構成。 本發明之半導體裝置用配線構件之中，銅配線層，係 具有：電連接於半導體晶片上之複數電極的端子區塊部。 Ο 本發明之半導體裝置用複合配線構件，係用於電連接 半導體晶片上之電極與配線基板者；其特徵爲具備：配線 構件；及電連接於該配線構件的引線框架；配線構件係具 有：絕緣層；配置於絕緣層之一側的金屬基板；及配置於 絕緣層之另一側的銅配線層；在絕緣層之於銅配線層側或 銅配線層上形成半導體晶片載置部；銅配線層，係包含： 第1端子部，被連接於半導體晶片上之電極；第2端子 部，被連接於引線框架；及配線部，用於連接第1端子部 與第2端子部；銅配線層之第2端子部與引線框架係藉由 201027699 第2連接部被連接。 本發明之半導體裝置用複合配線構件之中，金屬基 板，係由不鏽鋼構成。 本發明之半導體裝置用複合配線構件之中，第2連接 部，係由焊錫構成。 本發明之半導體裝置用複合配線構件之中，第2連接 部，係由接合導線構成。 本發明之樹脂密封型半導體裝置，其特徵爲具備：配 Q 線構件，其具有：絕緣層；配置於絕緣層之一側的金屬基 板；及配置於絕緣層之另一側的銅配線層；在絕緣層之於 銅配線層側或銅配線層上形成半導體晶片載置部；銅配線 層係包含：第1端子部，被連接於半導體晶片上之電極； 第2端子部，被連接於外部配線構件；及配線部，用於連 接第1端子部與第2端子部；引線框架，電連接於該配線 構件；及半導體晶片，被載置於配線構件之半導體晶片載 置部，其具有電極；半導體晶片上之電極與第1端子部係 © 藉由第1連接部被電連接；第2端子部與引線框架係藉由 第2連接部被電連接；在露出引線框架之一部分之狀態 下，使半導體晶片、銅配線層、引線框架、第1連接部及 第2連接部藉由樹脂密封部施予樹脂密封。 本發明之樹脂密封型半導體裝置，其特徵爲具備：配 線構件，具有：絕緣層；配置於絕緣層之一側的金屬基 板；及配置於絕緣層之另一側的銅配線層；在絕緣層之於 銅配線層側或銅配線層上形成半導體晶片載置部；銅配線 -8- 201027699 層係包含：第1端子部，被連接於半 第2端子部，被連接於外部配線構件 接第1端子部與第2端子部；及半導 被載置於該配線構件之半導體晶片載 導體晶片上之電極與第1端子部係藉 接；在銅配線層之第2端子部上設有 接部；使銅配線層、半導體晶片及第 φ 脂部施予密封，第2連接部由密封樹 本發明之樹脂密封型半導體裝置 係由焊錫構成。 本發明之樹脂密封型半導體裝置 由不鏽鋼構成。 本發明之半導體裝置用複合配線 半導體晶片上之電極與配線基板者； 構件；及電連接於該配線構件之同時 〇 的引線框架；配線構件係具有：絕緣 一側的金屬基板；及配置於絕緣層之 在銅配線層上形成半導體晶片載置ΐ 含：第1端子部，被連接於半導體晶 子部，被連接於引線框架；及配線部 部與第2端子部；銅配線層之第2端 由第2連接部被連接；引線框架，係 的晶粒焊墊（die pad );及設於晶粒 晶粒焊墊之中至少載置半導體晶片的 導體晶片上之電極； :及配線部，用於連 體晶片，介由黏接層 置部，具有電極；半 由第1連接部被電連 外部連接用之第2連 1連接部藉由密封樹 脂部露出外方。 之中，第2連接部， 之中，金屬基板，係 構件，係用於電連接 其特徵爲具備：配線 ，用於載置配線構件 層；配置於絕緣層之 另一側的銅配線層； 那；銅配線層，係包 片上之電極；第2端 ，用於連接第1端子 子部與引線框架係藉 具有：載置配線構件 焊墊外方的引線部； 中央區域之厚度，係 201027699 較引線部之厚度爲薄。 本發明之半導體裝置用複合配線構件之中，金屬基 板，係由不鏽鋼構成。 本發明之半導體裝置用複合配線構件之中，第2連接 部，係由接合導線構成。 本發明之半導體裝置用複合配線構件之中，晶粒焊 墊，係具有：中央區域，用於載置半導體晶片；及周緣區 域，位於中央區域外周，和引線部大略爲同一厚度；在中 @ 央區域與周緣區域之間設有縫隙孔。 本發明之樹脂密封型半導體裝置，其特徵爲具備：配 線構件，其具有：絕緣層；配置於絕緣層之一側的金屬基 板；及配置於絕緣層之另一側的銅配線層；在銅配線層上 形成半導體晶片載置部；銅配線層係包含：第1端子部， 被連接於半導體晶片上之電極；第2端子部，被連接於外 部配線構件；及配線部，用於連接第1端子部與第2端子 部；引線框架，電連接於該配線構件之同時，用於載置配 © 線構件：及半導體晶片，被載置於配線構件之半導體晶片 載置部，具有電極；半導體晶片上之電極與第1端子部係 藉由第1連接部被電連接；第2端子部與引線框架係藉由 第2連接部被電連接；在露出引線框架之一部分之狀態 下，使半導體晶片、銅配線層、引線框架、第1連接部及 第2連接部藉由密封樹脂部施予樹脂密封；引線框架，係 具有：載置配線構件的晶粒焊墊；及設於晶粒焊墊外方的 引線部；晶粒焊墊之中至少載置半導體晶片的中央區域之 -10- 201027699 厚度，係較引線部之厚度爲薄。 本發明之樹脂密封型半導體裝置之中，晶粒焊墊，係 具有：中央區域，用於載置半導體晶片；及周緣區域，位 於中央區域外周’和引線部大略爲同一厚度；在中央區域 與周緣區域之間設有縫隙孔。 本發明之樹脂密封型半導體裝置之中，晶粒焊墊底面 至密封樹脂部下面爲止之長度，和配線構件至密封樹脂部 φ 上面爲止之長度，係大略爲相同。 本發明之樹脂密封型半導體裝置，其特徵爲具備··配 線構件’其具有：絕緣層；配置於絕緣層之一側的金屬基 板；及配置於絕緣層之另一側的銅配線層；在銅配線層上 形成半導體晶片載置部；銅配線層係包含：第1端子部， 被連接於半導體晶片上之電極；第2端子部，被連接於外 部配線構件；及配線部，用於連接第1端子部與第2端子 部；及半導體晶片，介由黏接層被載置於該配線構件之半 φ 導體晶片載置部，具有電極；半導體晶片上之電極與第1 端子部係藉由第1連接部被電連接；在銅配線層之第2端 子部上設有外部連接用之第2連接部；使銅配線層、半導 體晶片及第1連接部藉由密封樹脂部施予密封，第2連接 '部由密封樹脂部露出外方；第2連接部係由焊錫形成；第 1連接部與第2連接部之連接用配線部，係以包圍第2端 子部的方式被迂迴佈局。 本發明之樹脂密封型半導體裝置之中，金屬基板，係 由不鏽鋼構成。 -11 - 201027699 本發明之半導體裝置用複合配線構件，係用於電連接 半導體晶片上之電極與配線基板者；其特徵爲具備：配線 構件；及電連接於該配線構件之同時，用於載置配線構件 的引線框架；配線構件係具有：絕緣層；配置於絕緣層之 一側的金屬基板；及配置於絕緣層之另一側的銅配線層； 在銅配線層上形成半導體晶片載置部；銅配線層，係包 含：第1端子部，被連接於半導體晶片上之電極；第2端 子部，被連接於引線框架；及配線部，用於連接第1端子 Q 部與第2端子部；銅配線層之第2端子部與引線框架係藉 由第2連接部被連接；引線框架，係具有：載置配線構件 的晶粒焊墊；及設於晶粒焊墊外方的引線部；晶粒焊墊， 係具有：中央區域，對應於半導體晶片；及周緣區域，位 於中央區域外周之同時被連結於中央區域，在其和中央區 域之間形成密封樹脂流入空間；配線構件，係配置於晶粒 焊墊之中央區域至周緣區域爲止之區域：配線構件，係至 少在晶粒焊墊之中央區域及周緣區域使用樹脂糊被黏接。 © 本發明之半導體裝置用複合配線構件之中，金屬基 板，係由不鏽鋼構成。 本發明之半導體裝置用複合配線構件之中，樹脂糊， 係以多點狀或直線狀被塗敷。 本發明之半導體裝置用複合配線構件之中，晶粒焊墊 之中，至少在中央區域及周緣區域被施予鍍層處理。 本發明之樹脂密封型半導體裝置，其特徵爲具備：配 線構件，具有：絕緣層；配置於絕緣層之一側的金屬基 -12- 201027699 板；及配置於絕緣層之另一側的銅配線層；在銅配線層上 形成半導體晶片載置部；銅配線層係包含：第1端子部， 被連接於半導體晶片上之電極；第2端子部，被連接於外 部配線構件；及配線部，用於連接第1端子部與第2端子 部；引線框架，電連接於該配線構件之同時，用於載置配 線構件；及半導體晶片，被載置於配線構件之半導體晶片 載置部，具有電極；半導體晶片上之電極與第1端子部係 φ 藉由第1連接部被電連接；第2端子部與引線框架係藉由 第2連接部被電連接；在露出引線框架之一部分之狀態 下，使半導體晶片、銅配線層、引線框架、第1連接部及 第2連接部藉由密封樹脂部施予樹脂密封；引線框架，係 具有：載置配線構件的晶粒焊墊；及設於晶粒焊墊外方的 引線部；晶粒焊墊，係具有：中央區域，對應於半導體晶 片；及周緣區域，位於中央區域外周之同時被連結於中央 區域，在其和中央區域之間形成密封樹脂流入空間；配線 • 構件，係配置於晶粒焊墊之中央區域至周緣區域爲止之區 域；配線構件，係至少在晶粒焊墊之中央區域及周緣區域 使用樹脂糊被黏接。 本發明之樹脂密封型半導體裝置之中，金屬基板，係 由不鏽鋼構成。 本發明之樹脂密封型半導體裝置之中，樹脂糊，係以 多點狀或直線狀被塗敷。 本發明之樹脂密封型半導體裝置之中，晶粒焊墊之 中，至少在中央區域及周緣區域被施予鍍層處理。 -13- 201027699 【實施方式】 以下依據圖面說明本發明之實施形態。 (第1實施形態） 圖1-圖11爲本發明第1實施形態之圖。圖1爲本發 明第1實施形態之槪略斷面圖。圖2爲本發明第1實施形 態之槪略平面圖。圖3爲本發明第1實施形態之變形例1 之槪略斷面圖。圖4爲包含圖1之半導體裝置用配線構件 @ 的半導體裝置之槪略斷面圖。圖5爲包含圖3之半導體裝 置用配線構件的半導體裝置之槪略斷面圖。圖6(a) -(d)爲半導體裝置用配線構件之製造方法之圖。圖7 (a) - (f)爲圖4所示半導體裝置之製造方法之圖。圖8 (a) - (f)爲圖5所示半導體裝置之製造方法之圖爲。 圖9爲本發明第1實施形態之半導體裝置用配線構件之變 形例2之槪略平面圖。圖10爲本發明第1實施形態之半 導體裝置用配線構件之變形例3之槪略平面圖。圖11 Q (a)爲本發明第1實施形態之半導體裝置用配線構件之 變形例4之槪略平面圖，圖11(b)爲圖ll(a)之a-a 線斷面圖。圖14(a) - (f)爲圖4所示半導體裝置之製 造方法之變形例之圖。圖15(a) - (f)爲圖5所示半導 體裝置之製造方法之變形例之圖。 首先，依據圖1-3說明本發明之半導體裝置用配線構 件之槪略。 如圖1所示，本實施形態之導線連接型半導體裝置用 -14 - 201027699 配線構件10，係將半導體晶片15之電極15A (如後述說 明）與例如引線框架20之內引線部21 (如後述說明）等 外部配線構件予以電連接者。 此種半導體裝置用配線構件10，係具備：例如聚醯 亞胺形成之絕緣層11;配置於絕緣層11之一側的金屬基 板12;及配置於絕緣層11之另一側的銅配線層13。其 中，銅配線層13，係包含：複數個第1端子部13D，分 φ 別被連接於半導體晶片15之電極15A;複數個第2端子 部13E，分別被電連接於內引線部21 (外部配線構件）； 及複數個配線部13C，分別用於電連接第1端子部13D與 第2端子部13E。 又，於銅配線層13之各第2端子部13E上各設有引 線框架20用之第2連接部19。亦即，第2連接部19之 一端被連接於分別對應之第2端子部13E之同時，另一端 連接於引線框架20之內引線部21 (如後述說明）。又， φ 於圖1、2，各第2連接部19，係由金製之接合導線構 成。 另外，銅配線層13之配線部13C，分別如圖2所 示，係由半導體晶片15以放射狀被延伸。另外，銅配線 層13之斷面，如圖1所示，係由中心之銅層13A與覆蓋 銅層13A的鑛層13B構成。其中，鍍層13B，係由例如 鎳鎪層，與設於鎳（Ni)鍍層上之金（Au)鍍層構成。 金屬基板12可使用各種金屬，但金屬基板12最好由 不鏽鋼（stainless)構成。藉由金屬基板12由不鏽鋼構 -15- 201027699 成，可提升金屬基板12之剛性，薄化金屬基板12之厚 度。另外，半導體晶片15之熱可由金屬基板12背面散 熱。 在絕緣層11之於銅配線層13側形成半導體晶片載置 部11A。半導體晶片15,係如圖2所示，具有沿周圍設 置之複數個電極15A。半導體晶片15，係藉由黏接層14 被載置、固定於半導體晶片載置部11A上。半導體晶片 15之各電極15A與銅配線層13之各第1端子部13D之 @ 間，係分別藉由金（Au )接合導線形成之第1連接部1 6 被連接。 以下依據圖3說明半導體裝置用配線構件10之另一 構成（變形例1)。於圖3,和圖1、2之半導體裝置用配 線構件10同一部分附加同一符號，並省略詳細說明。 如圖3所示，焊錫連接型半導體裝置用配線構件 10，係具備：絕緣層11;配置於絕緣層11之一側的金屬 基板12;及配置於絕緣層11之另一側的銅配線層13。 〇 在絕緣層11之於銅配線層13側形成半導體晶片載置 部11A，半導體晶片15係藉由黏接層14被載置於半導體 晶片載置部11A。半導體晶片15與銅配線層13之第1端 子部13D之間 '係藉由金（Αυ)接合導線形成之第1連 接部16被電連接。 於圖3，於銅配線層13之各第2端子部13Ε上分別 設有引線框架20用之第2連接部18。亦即，第2連接部 18，其之下端被連接於分別對應之第2端子部13Ε之同 -16- 201027699 時，上端連接於引線框架20之內引線部21(如後述說 明）。又，於圖3，各第2連接部18，係由焊錫 (solder)連接部（錫球）構成。 於圖1，係由半導體裝置用配線構件1〇;電連接於該 半導體裝置用配線構件10的引線框架20;電連接銅配線 層13之第2端子部13E與引線框架20的第2連接部 18、19，來構成半導體裝置用複合配線構件10A。藉由該 φ 半導體裝置用複合配線構件10A，可以進行半導體晶片 15之電極15A與外部配線基板（未圖示）間之電連接。 其中，作爲如圖1或3所示半導體裝置用配線構件 10之使用形態，在半導體晶片15之各電極15A與銅配線 層13之第1端子部13D之間之電連接，係使用接合導線 (第1連接部16)，但作爲其他連接方法，亦可使用金 凸塊連接或錫球連接。使用金凸塊或錫球之連接方法時， 半導體晶片15,係以其之電極15A和配線構件10之第1 φ 端子部13D呈對向的方式予以配置、載置（未圖示）。 另外，第1連接部16之連接方法，使用金凸塊或錫球之 方法，於BGA封裝對應之第2實施形態（如後述說明） 亦可被使用。 以下依據圖4、5說明具有上述半導體裝置用配線構 件的半導體裝置之槪略。 圖4之半導體裝置30,係包含圖1之半導體裝置用 配線構件1 〇。亦即，半導體裝置30，係具有：引線框架 20，其具有晶粒焊墊22 ;半導體裝置用配線構件10，被 17- 201027699 載置於引線框架20之晶粒焊墊22上，電連接於引線框架 20;及半導體晶片15，被載置於半導體裝置用配線構件 10之半導體晶片載置部11A，具有電極15A。 其中，於引線框架20之上面被形成複數個導電性內 引線部21，接合導線所構成之各第2連接部19,係用於 電連接銅配線層13之各第2端子部13E與對應之內引線 部21。另外，半導體晶片15之電極i5A與第1端子部 13D之間，係藉由第1連接部16被電連接。另外，於露 @ 出引線框架20之一部分之狀態下，使半導體晶片15、銅 配線層13、引線框架20、第1連接部16及第2連接部 19藉由樹脂密封部23施予樹脂密封。 另外，圖5之半導體裝置30,係包含圖3之半導體 裝置用配線構件10。亦即，半導體裝置30，係具有：引 線框架20;半導體裝置用配線構件1〇，被載置於引線框 架20之中心，電連接於引線框架20 ;及半導體晶片15， 被載置於半導體裝置用配線構件10之半導體晶片載置部 @ 11A，具有電極15A。 其中，於引線框架20之下面被形成複數個導電性內 引線部21’焊錫連接部所構成之各第2連接部18,係用 於電連接銅配線層13之各第2端子部13E與對應之內引 線部21。另外，半導體晶片15上之電極15A與第丨端子 部13D之間’係藉由第i連接部16被電連接。另外，於 露出引線框架20之一部分（稱爲外引線部）之狀態下， 使半導體晶片15、銅配線層13、引線框架20、第1連接 -18- 201027699 部16及第2連接部18藉由樹脂密封部23施予樹脂密 封。 於圖4、5說明將圖1、3所示半導體裝置用配線構件 1〇搭載於引線框架20之例，但不限定於此，例如可使配 線構件10或圖12所示半導體裝置（如後述說明），內藏 於增層基板（build-up board)來製造薄型半導體裝置。 以下說明上述構成所形成之本實施形態之作用。 0 首先，依據圖6(a)-(d)說明製造上述半導體裝置 用配線構件10之方法。 首先，準備由不鏽鋼構成之金屬基板12(圖 6 (a))。之後，於金屬基板12上積層由聚醯亞胺構成之 絕緣層11(圖6(b))。 之後，於絕緣層11上藉由加成法或蝕刻法形成銅層 13A (圖6(c))。之後，藉由電解鍍層或無電解鍍層， 於銅層13A上形成例如由鎳（Ni )鍍層及金（Au)鍍層 φ 構成之鍍層13B，如此而形成由銅層13A及鍍層13B構 成之銅配線層13(圖6(d))。此時，亦同時形成銅配 線層13之第1端子部13D、第2端子部13E及配線部 1 3 C。如此則，可以製作具有絕緣層1 1、金屬基板1 2及 銅配線層13的半導體裝置用配線構件10。 接著，依據圖7(a) - (f)說明製造包含導線連接型 半導體裝置用配線構件的半導體裝置（圖4)之方法。 首先，藉由上述圖6(a) - (d)所示工程製造半導體 裝置用配線構件1〇(圖7(a))。之後，使半導體晶片 19- 201027699 15介由黏接層14被載置、固定於半導體裝置用配線構件 10之半導體晶片載置部11A上（圖7(b))之同時，藉 由接合導線所構成之第1連接部16，進行半導體晶片15 之各電極15A與銅配線層13之各第1端子部13D之間之 連接（圖7 ( c))。 之後，準備具有內引線部21與晶粒焊墊22的引線框 架20,於該引線框架20之晶粒焊墊22上載置半導體裝 置用配線構件1〇(圖7(d))。 @ 之後，分別藉由接合導線所構成之第2連接部19， 進行銅配線層13之各第2端子部13E與對應之引線框架 20之內引線部21之間之連接（圖7(e))。之後，於露 出引線框架20之一部分（外引線部）之狀態下，使半導 體裝置用配線構件10、半導體晶片15、第1連接部16、 晶粒焊墊22、第2連接部19及內引線部21藉由樹脂密 封部23施予樹脂密封，製成圖4所示半導體裝置30 (圖 7 ( f) )。 ◎ 接著，依據圖14(a) - (f)說明製造包含導線連接 型半導體裝置用配線構件的半導體裝置（圖4)之方法之 變形例。 首先，藉由上述圖6(a) - (d)所示工程製造半導體 裝置用配線構件1〇(圖14(a))。之後，準備具有內引 線部21與晶粒焊墊22之引線框架20,將半導體裝置用 配線構件10載置於該引線框架20之晶粒焊墊22上（圖 14(b))。 -20- 201027699 之後，使半導體晶片15介由黏接層14被載置、固定 於半導體裝置用配線構件10之半導體晶片載置部11A上 (圖14(c))之同時，藉由接合導線所構成之第1連接 部16，進行半導體晶片15之各電極15A與銅配線層13 之各第1端子部13D之間之連接（圖14(d))。 之後，分別藉由接合導線所構成之第2連接部19, 進行銅配線層13之各第2端子部13E與對應之引線框架 φ 20之內引線部21之間之連接（圖7(e))。之後，於露 出引線框架20之一部分（外引線部）之狀態下，使半導 體裝置用配線構件10、半導體晶片15、第1連接部16、 晶粒焊墊22、第2連接部19及內引線部21藉由密封樹 脂部23施予密封，而獲得圖4所示半導體裝置30(圖14 (f) ) ° 接著，依據圖8(a) - (f)說明製造包含焊錫連接型 半導體裝置用配線構件的半導體裝置（圖5)之方法。 φ 首先，藉由上述圖6(a)-(d)所示工程製造半導體 裝置用配線構件1〇(圖8(a))。之後，使半導體晶片 15介由黏接層14被載置、固定於半導體裝置用配線構件 10之半導體晶片載置部11A上（圖8(b))之同時，藉 由接合導線所構成之第1連接部16，進行半導體晶片15 之各電極15A與銅配線層13之各第1端子部13D之間之 連接（圖8 ( c ))。 之後’於銅配線層13之各第2端子部13E上，分別 設置由焊錫連接部（錫球）形成之引線框架20用之第2 -21 - 201027699 連接部18(圖8(d))。 之後’準備引線框架20，分別進行各第2連接部18 與對應之引線框架20之內引線部21之間之連接（圖8 (e))。之後，於露出引線框架20之一部分（外引線 部）之狀態下，使半導體裝置用配線構件10、半導體晶 片15、第1連接部16、第2連接部18、及內引線部21 藉由密封樹脂部23施予密封，製成圖5所示半導體裝置 30 (圖 8 ( f))。 魏 接著，依據圖15(a) - (f)說明製造包含焊錫連接 型半導體裝置用配線構件的半導體裝置（圖5)之方法之 變形例。 首先’藉由上述圖6(a) - (d)所示工程製造半導體 裝置用配線構件10(圖15(a))。之後，於半導體裝置 用配線構件10之銅配線層13之各第2端子部13E上，分 別設置由焊錫連接部（錫球）構成之引線框架20用之第 2連接部18(圖15(b))。之後，準備引線框架20，分 ❹ 別進行各第2連接部18與對應之引線框架20之內引線部 21之間之連接（圖1 5 ( c ))。 之後，使半導體晶片15介由黏接層14被載置、固定 於半導體裝置用配線構件10之半導體晶片載置部11A上 (圖15(d))之同時，藉由接合導線所構成之第i連接 部16，進行半導體晶片15之各電極15A與銅配線層13 之各第1端子部13D之間之連接（圖15(e))。 之後，於露出引線框架20之一部分（外引線部）之 -22- 201027699 狀態下’使半導體裝置用配線構件10、半導體晶片15、 第1連接部10、第2連接部18及內引線部21藉由密封 樹脂部23施予密封，而獲得圖5所示半導體裝置3〇 (圖 15(f))。 如上述說明，依據本實施形態，可將較習知更微細化 (fine )的小型半導體晶片15搭載於引線框架2〇。亦 即，引線框架20之內引線部21間之間距較寬（例如 φ 13(^m) ’半導體晶片15之電極15A間之間距較窄（例 如40μιη)。即使此情況下，依據本實施形態，半導體晶 片15之各電極15Α與銅配線層13之各第丨端子部13D 之間’可藉由第1連接部16予以連接，銅配線層13之第 2端子部13E與引線框架20之內引線部21之間，可藉由 第2連接部18、19予以連接，因此可將半導體晶片15確 實電連接於引線框架20。 相對於此，作爲比較例，亦可考慮直接藉由金接合導 φ 線來連接半導體晶片15之電極15A與引線框架20之內 引線部21。但是，此情況下，金接合導線之長度相對變 長，製造成本上升。相對地，依據本實施形態，第1連接 部16與第2連接部18、19之間存在銅配線層13，因 此，和直接藉由金接合導線來連接半導體晶片15之電極 15A與引線框架20之內引線部21之情況（上述比較例） 比較，可降低半導體裝置30之製造成本。 另外，依據本實施形態，作爲半導體裝置30進行封 裝之前，可以搭載於半導體裝置用配線構件10或之狀態 -23- 201027699 下進行半導體晶片1 5之檢測。 另外’依據本實施形態，金屬基板12由不鏽鋼形 成，和習知由聚醯亞胺形成之基板比較更具有剛性，容易 處理，而且厚度可以較薄。另外，來自半導體晶片15之 熱可由金屬基板12之背面予以散熱。 以下依據圖9-11說明半導體裝置用配線構件1〇之其 他構成（變形例2-4)。於圖9-11，和圖1-3所示半導體 裝置用配線構件10同一之部分附加同一符號並省略詳細 @ 說明。 於圖9(變形例2)，銅配線層13具有：電源端子區 塊部13F，介由第1連接部16電連接於半導體晶片15上 之複數個電源端子用電極15A; GND (接地）端子區塊部 13G，介由第1連接部16電連接於半導體晶片15上之複 數個接地端子用電極15A;其他之第1連接部16分別被 連接的第1端子部13D;及第2連接部19被連接的平行 四邊形之第2端子部13E。另外，於第1端子部13D與第 〇 2端子部13E之間，於電源端子區塊部13F與第2端子部 13E之間，以及GND (接地）端子區塊部13G與第2端 子部13E之間，分別存在配線部13C。 於圖1〇(變形例3)，銅配線層13具有：電源端子 區塊部13F，介由第1連接部16電連接於半導體晶片15 上之複數個電源端子用電極15A;GND (接地）端子區塊 部13G，介由第1連接部16電連接於半導體晶片15上之 複數個接地端子用電極15A;其他之第1連接部16分別 -24- 201027699 被連接的第1端子部13D;及第2連接部18被連接的圓 形狀之第2端子部13E。另外’於第1端子部13D與第2 端子部13E之間，於電源端子區塊部13F與第2端子部 13E之間，以及GND (接地）端子區塊部13G與第2端 子部13E之間，分別存在配線部13C。另外，於圖10 (變形例3)，連接於第2端子部13E的配線（配線部 13C )、引出線，爲防止錫球安裝時之焊錫流動，而分別 φ 構成爲曲柄形狀之配線、引出線。 如圖9、10所示，設置電源端子區塊部13F與GND (接地）端子區塊部13G，將電極15A之中之電源端子與 接地端子分別統合予以電連接，如此則，可以減少第2連 接部1 8、1 9之數目。 於圖11(變形例4)，半導體裝置用配線構件10， 係載置於較半導體裝置用配線構件10稍大的分割晶粒焊 墊2 0A上。另外，銅配線層13具有：及電源端子區塊部 φ 13F，介由第1連接部16電連接於半導體晶片15上之複 數個電源端子用電極15A ; GND (接地）端子區塊部 13G。分割晶粒焊墊20A係作爲GND區塊而構成。分割 晶粒焊墊20A與GND (接地）端子區塊部13G係藉由第 2連接部1 9連接。 於圖11，設置電源端子區塊部13F與GND (接地） 端子區塊部13G，將電極15A之中之電源端子與接地端子 分別統合予以電連接，而且，藉由第2連接部19將分割 晶粒焊墊20A與GND (接地）端子區塊部13G予以連 •25- 201027699 接，如此則，可以減少半導體裝置全體中之第2連接部 1 9之數目。 於圖9-11 (變形例2-4)，設置由較半導體晶片15 之尺寸大的銅配線層構成之晶粒焊墊，於該晶粒焊墊上介 由絕緣薄膜（或糊）搭載半導體晶片15亦可。此情況 下，以銅配線層構成之晶粒焊墊作爲GND (接地）層予 以構成，藉由導線來連接半導體晶片15之電極15A與晶 粒焊墊，如此則，可以減少半導體裝置全體中之總端子 數。 (第2實施形態） 以下，依據圖12及圖13(a) - (e)說明本發明第2 實施形態。 圖12爲本發明第2實施形態之槪略斷面圖。圖13 (a) - (e)爲封裝型之半導體裝置之製造方法之圖。圖 12及圖13(a) - (e)所示第2實施形態之不同點在於， φ 第2連接部由密封樹脂部露出於外方，其他構成大略和上 述第1實施形態同一。於圖12及圖13(a) - (e)，和圖 1-11所示第1實施形態同一部分被附加同一符號，並省 略詳細說明。 如圖12所示，本實施形態之封裝型半導體裝置40， 係具備：上述半導體裝置用配線構件1〇;及於半導體裝 置用配線構件10之半導體晶片載置部11Α上介由黏接層 I4被載置，具有複數個電極15Α的半導體晶片15。 -26- 201027699 半導體晶片15之電極15A與銅配線層13之第1端 子部13D之間，係分別藉由金接合導線形成之第1連接 部1 6予以連接。 另外，於銅配線層13之各第2端子部13E上各設 有，由焊錫連接部構成之外部連接用之第2連接部24。 如圖12所示，第2連接部24,係由錫球積層2段予以構 成，但只要第2連接部24之高度能設爲一定以上，則不 φ 限定於該構造。 銅配線層13、半導體晶片15及第1連接部16係藉 由密封樹脂部23予以密封。另外，第2連接部24係由密 封樹脂部23露出外方。第2連接部24之中露出於密封樹 脂部23之外方之部分，係設爲例如和外部機器之導電性 構件連接用，如此則，可以確實電連接半導體晶片1 5與 外部機器。 金屬基板12可使用各種金屬，但金屬基板12最好由 φ 不鏽鋼構成。藉由金屬基板12由不鏽鋼構成，可提升金 屬基板12之剛性，薄化金屬基板12之厚度。另外，半導 體晶片15之熱可由金屬基板12背面散熱。 接著，依據圖13(a) - (e)說明製造圖12所示封裝 型半導體裝置40之方法。 首先，藉由圖6(a) - (d)所示工程製造半導體裝置 用配線構件10(圖13(a))。之後，使半導體晶片15 介由黏接層14被載置、固定於半導體裝置用配線構件1〇 之半導體晶片載置部11A上（圖13(b))。之後’藉由 -27- 201027699 接合導線所構成之第1連接部16，進行半導體晶片15之 各電極15A與銅配線層13之各第1端子部13D之間之連 接（圖 13 ( c))。 之後’於銅配線層13之各第2端子部13E上，分別 設置外部連接用之第2連接部24 (錫球）（圖13 (d))。之後’使銅配線層13、半導體晶片15及第1 連接部16藉由密封樹脂部23施予密封，製成圖12所示 半導體裝置40 (圖13(e))。 如上述說明，依據本實施形態，可將較習知更小型半 導體晶片15連接於外部機器。亦即，依據本實施形態， 藉由第1連接部16進行半導體晶片15之各電極15A與 銅配線層13之第1端子部13D之間之連接，於銅配線層 13之各第2端子部13E上，設置由焊錫連接部構成之外 部連接用之第2連接部24。如此則，即使外部機器之各 導電性構件間之間距相對較寬，半導體晶片15之各電極 1 5 A間之間距相對較窄（例如4 0 μ m )之情況下，亦可確 實進行半導體晶片15與外部機器間之連接。 另外，依據本實施形態，第1連接部16與第2連接 部24之間存在銅配線層13，因此，和直接藉由金接合導 線來連接半導體晶片15之電極15A與第2連接部24之 情況比較，可降低半導體裝置40之製造成本。 另外，依據本實施形態，金屬基板12由不鏽鋼形 成’和習知由聚醯亞胺形成之基板比較更具有剛性，容易 處理’而且厚度可以較薄。另外，來自半導體晶片15之 -28- 201027699 熱可由金屬基板12之背面予以散熱。 圖6、圖9、圖20 (後述說明）所示半導體裝置用配 線構件10，或圖12所示半導體裝置40,係於多面附著狀 態（未圖示）下藉由切割器予以個別切離。但是，因金屬 基板12由不鏽鋼形成，切割半導體裝置時較爲困難，此 時可藉由半蝕刻或全鈾刻，事先於金屬基板12形成較切 割刀刃（blade)寬幅的切割線部，來提升切割效率。 φ 於上述各實施形態中，非於絕緣層11之銅配線層13 側，而在銅配線層13上形成半導體晶片載置部11A亦 可。此情況下，半導體晶片15係介由絕緣薄膜（或糊） 被載置於半導體晶片載置部11A。 (第3實施形態） 以下依據圖1 6-2 1說明本發明第3實施形態。 圖16爲本發明第3實施形態之半導體裝置用配線構 φ 件之槪略斷面圖。圖17爲本發明第3實施形態之半導體 裝置用複合配線構件之槪略斷面圖。圖18爲本發明第3 實施形態之半導體裝置用配線構件之變形例之槪略斷面 圖。圖19爲本發明第3實施形態之半導體裝置之槪略斷 面圖。圖20(a) - (d)爲本發明第3實施形態之半導體 裝置用配線構件之製造方法之圖。圖21 (a) - (f)爲本 發明第3實施形態之半導體裝置之製造方法之圖。於圖 16-21，和圖1-1 1所示第1實施形態同一之部分附加同一 符號。 -29- 201027699 首先，依據圖16說明本實施形態之半導體裝置用配 線構件之槪略。又’於圖16，爲求方便而將構成半導體 裝置用配線構件之部分以外以假想線（2點虛線）表示。 如圖16所示，本實施形態之導線連接型半導體裝置 用配線構件1 〇，係具備：例如聚醯亞胺形成之絕緣層 11;配置於絕緣層11之一側的金屬基板12;及配置於絕 緣層11之另一側的銅配線層13。其中，銅配線層13，係 包含：複數個第1端子部13D，分別被電連接於半導體晶 @ 片15之電極15A:複數個第2端子部13E，分別被電連 接於內引線部21 (外部配線構件）：及複數個配線部 13C，分別用於電連接第1端子部13D與第2端子部 13E。 金屬基板12可使用各種金屬，但金屬基板12最好由 不鏽鋼構成。藉由金屬基板12由不鏽鋼構成，可提升金 屬基板12之剛性，薄化金屬基板12之厚度。 在銅配線層13上形成半導體晶片載置部31。於該半 © 導體晶片載置部31上，可以載置沿其周圍設置之具有複 數個電極15A的半導體晶片15。此情況下，半導體晶片 15,係藉由黏接層14被載置、固定於半導體晶片載置部 31上。半導體晶片15之各電極15A與銅配線層13之各 第1端子部13D之間，可分別藉由金（Au)接合導線形 成之第1連接部16予以連接。 另外，銅配線層13之各第2端子部13E與引線框架 20之各內引線部21之間，係介由第2連接部19被電連 -30- 201027699 接。 以下依據圖17說明本實施形態之半導體裝 配線構件。又，於圖17，爲求方便而將構成半 用複合配線構件之部分以外以假想線（2點虛線 如圖17所示，半導體裝置用複合配線構件 由以下構成：上述半導體裝置用配線構件10; 該半導體裝置用配線構件10的引線框架20;銅 φ 之第2端子部13E與引線框架20之電連接用的 部19。該半導體裝置用複合配線構件10A，係 接半導體晶片15之電極15A與外部配線基板（ 者。 其中，引線框架20具有：載置半導體裝置 件1 〇的晶粒焊墊22 ;及位於晶粒焊墊22外方 25。又，於引線部25上設有銀鍍層或鈀（Pd) 之內引線部21 (外部配線構件）。 # 又，晶粒焊墊22，係具有：中央區域22a， 半導體晶片15;及周緣區域22b，位於中央區域 周，具有和引線部25大略同一厚度。在該晶粒却 中央區域22a與周緣區域22b之間設有縫隙孔 隙孔26，如後述說明，係將半導體裝置用配線構 引線框架20之黏接用的黏接劑所產生之氣體排 者。 又，晶粒焊墊22之中至少中央區域22a係 刻等方法形成爲較薄。亦即，中央區域22a之厚 置用複合 導體裝置 )表示。 10A，係 電連接於 配線層13 第2連接 用於電連 未圖示） 用配線構 的引線部 鍍層構成 用於載置 22a之外 P墊22之 26。該縫 Η牛1 〇與 出至外方 藉由半鈾 度被形成 -31 - 201027699 較引線部25及周緣區域2 2b之厚度爲薄。如此則，搭載 半導體晶片15的半導體裝置30可以構成薄型化。 另外，第2連接部19係由金接合導線構成，其之一 端被連接於對應之第2端子部13E之同時，另一端被連接 於引線框架20之內引線部21。 但是，如圖1 8之變形例所示，使半導體晶片1 5之各 電極15A朝向銅配線層13側之同時，使半導體晶片15 之各電極15A與銅配線層13之各第1端子部13D之間’ 藉由凸塊或錫球形成之第1連接部16A予以連接（覆晶 接合）亦可。 以下說明具有上述半導體裝置用配線構件及半導體裝 置用複合配線構件的半導體裝置之槪略。 圖19之半導體裝置30，係包含圖1之半導體裝置用 配線構件10及圖17之半導體裝置用複合配線構件10A。 亦即，半導體裝置30，係具有：引線框架20，其具有晶 粒焊墊22;半導體裝置用配線構件10，被載置於引線框 架20之晶粒焊墊22上，電連接於引線框架20;及半導 體晶片15’被載置於半導體裝置用配線構件1〇之半導體 晶片載置部31，具有電極15A。 其中’於引線框架20之上面被形成複數個導電性內 引線部21。接合導線所構成之各第2連接部19，係用於 電連接銅配線層13之各第2端子部13E與對應之內引線 部21。另外，半導體晶片15上之電極15A與第1端子部 13D之間’係藉由接合導線所構成之第〗連接部16被電 201027699 連接。另外，於露出引線框架20之引線部25之一部分之 狀態下，使半導體晶片15、銅配線層13、引線框架20、 第1連接部16及第2連接部19藉由樹脂密封部23施予 樹脂密封。 另外，晶粒焊墊22之構成係和圖1 7說明者同樣，因 此省略說明。 又，於圖19，晶粒焊墊22底面至密封樹脂部23下 φ 面爲止之長度，和半導體裝置用配線構件10至密封樹 脂部23上面爲止之長度H2，係大略爲同一長度。如此 則，吸濕試驗（迴焊（reflow )試驗）時可防止半導體裝 置30之產生彎曲或裂痕（詳如後述）。 以下說明由上述構成所形成之本實施形態之作用。 首先，依據圖20 ( a ) - ( d )說明製造本實施形態之 半導體裝置用配線構件1〇(圖16)之方法。 首先，準備由不鏽鋼構成之金屬基板 12(圖20 • (a))。之後，於金屬基板12上積層由聚醯亞胺構成之 絕緣層11(圖20(b))。 之後，於絕緣層11上藉由加成法或鈾刻法形成銅層 13A (圖20(c))。之後，藉由電解鍍層或無電解鍍 層，於銅層13A上形成例如由鎳（Ni)鍍層及金（Au) 鍍層構成之鍍層13B，如此而形成由銅層13A及鍍層13B 構成之銅配線層13(圖20 (d))。此時，亦同時形成銅 配線層13之第1端子部13D、第2端子部13E及配線部 13C»如此則，可以製作具有絕緣層11、金屬基板12及 -33- 201027699 銅配線層13的半導體裝置用配線構件10。另外，於銅配 線層13上被形成半導體晶片載置部31。 接著，依據圖21(a)-(f)說明製造本實施形態之 半導體裝置（圖19)之方法。 首先，藉由上述圖20 (a) - (d)所示工程製造半導 體裝置用配線構件1〇(圖21(a))。之後，準備具有內 引線部21與晶粒焊墊22的引線框架20，於該引線框架 20之晶粒焊墊22上載置半導體裝置用配線構件10(圖 21(b))。此時，半導體裝置用配線構件10，係使用黏 接劑被黏接於晶粒焊墊22。此情況下，半導體裝置用配 線構件10之表面被形成爲平坦，因此，半導體裝置用配 線構件10對晶粒焊墊22可於面內均勻加壓。如此則，黏 接後，於半導體裝置用配線構件10與晶粒焊墊22之間不 會產生間隙。 之後，使半導體晶片15介由黏接層14被載置、固定 於半導體裝置用配線構件10之半導體晶片載置部31上 (圖21(c))之同時，藉由接合導線所構成之第i連接 部16，進行半導體晶片15之各電極15A與銅配線層13 之各第1端子部13D之間之連接（圖21 (d))。 之後，分別藉由接合導線所構成之第2連接部19, 進行銅配線層13之各第2端子部13E與對應之引線框架 20之內引線部21之間之連接（圖21 ( e ))。之後，於 露出引線框架20之一部分（外引線部）之狀態下，使半 導體裝置用配線構件10、半導體晶片15、第1連接部 -34- 201027699 16、晶粒焊墊22、第2連接部19及內引線部21藉由樹 脂密封部23施予樹脂密封，製成圖19所示半導體裝置 30 (圖 21 ( f))。 但是，進行密封樹脂部23之樹脂密封時，半導體裝 置用配線構件1〇及晶粒焊墊22約以180°C被加熱。此 時，黏接半導體裝置用配線構件1〇及晶粒焊墊22的黏接 劑亦被加熱，因此有可能由黏接劑產生有機氣體。另外’ Φ 黏接劑吸濕之水亦被加熱而有可能產生水蒸汽。因此’本 實施形態中，於晶粒焊墊22之中央區域22a與周緣區域 22b之間設置縫隙孔26，在半導體裝置用配線構件10或 半導體晶片15之搭載固定後或密封樹脂部23固化爲止之 間，黏接劑產生之氣體（有機氣體及/或水蒸汽）會經由 縫隙孔26排出至外方，不會殘留於密封樹脂部23內。 另外，未設置縫隙孔26時，氣體（有機氣體及/或 水蒸汽）會殘留於晶粒焊墊22與半導體裝置用配線構件 ® 1 〇之間附近，於此狀態下密封樹脂部23被固化。如此 則，針對完成後之半導體裝置30進行吸濕試驗（迴焊試 驗）結果，發現氣體殘留部分會有膨潤，有可能由此而產 生裂痕。相對於此，依據本實施形態，藉由在晶粒焊墊 22設置縫隙孔26，可使來自黏接劑之氣體排出至外方， 吸濕試驗（迴焊試驗）時，半導體裝置30不會產生裂 痕。 如上述說明，依據本實施形態，可將較習知更微細化 (fine )的小型半導體晶片15搭載於引線框架20。亦 -35- 201027699 即’即使在引線框架2〇之內引線部2 i間之間距較寬（例 如130μιη) ’半導體晶片15之電極15A間之間距較窄 (例如40μιη )的情況下，亦可將半導體晶片1 5確實電連 接於引線框架20之內引線部21。 又’依據本實施形態，晶粒焊墊22之中至少載置半 導體晶片15的中央區域22 a之厚度被形成較引線部25之 厚度爲薄。因此，半導體裝置30可以構成薄型化。 又’依據本實施形態，在晶粒焊墊22之中央區域 Q 22a與周緣區域22b之間設有縫隙孔26，半導體裝置用配 線構件10與引線框架20之黏接用的黏接劑所產生之氣 體’可由縫隙孔26排出至外方，因此，可防止吸濕試驗 (迴焊試驗）時半導體裝置30之產生裂痕。 又，依據本實施形態，晶粒焊墊22底面至密封樹脂 部23下面爲止之長度，和半導體裝置用配線構件1〇之銅 配線層13起至密封樹脂部23上面爲止之長度，係設爲大 略同一長度。亦即，密封樹脂部23之體積，於半導體裝 © 置30之表面側與背面側成爲大略相同。結果，吸濕試驗 (迴焊（reflow)試驗）時，密封樹脂部23於表面側與 背面側產生均勻之膨脹，可防止半導體裝置30之產生彎 曲或裂痕。 又，依據本實施形態，第1連接部16與第2連接部 18之間存在銅配線層13，因此，和直接藉由金接合導線 來連接半導體晶片15之電極15A與引線框架20之內引 線部21之情況比較，可降低半導體裝置30之製造成本。 -36- 201027699 另外，依據本實施形態，金屬基板12由不鏽鋼形 成，和習知由聚醯亞胺形成之基板比較更具有剛性’容易 處理，而且厚度可以較薄。 (第4實施形態） 以下，依據圖22-25說明本發明第4實施形態。 圖22爲本發明第4實施形態之半導體裝置之槪略斷 φ 面圖。圖23爲本發明第4實施形態之半導體裝置使用之 半導體裝置用配線構件之平面圖。圖24(a) -(e)爲本 發明第4實施形態之半導體裝置之製造方法之圖。圖25 爲本發明第4實施形態之半導體裝置之變形例之槪略斷面 圖。圖22-2 5之第4實施形態之構成差異在於第2連接部 2 7A、27B、銅配線層13及半導體晶片載置部31之構 成，其他構成則和上述第2實施形態大略相同。於圖22_ 25，和圖12及圖13(a) - (e)所示第2實施形態同 • 部分附加同一符號並省略詳細說明。 如圖22所示，本實施形態之封裝型半導體裝置4〇, 係具備··上述半導體裝置用配線構件10;及半導體晶片 15，其介由黏接層14被載置於半導體裝置用配線構件1〇 之銅配線層13上所形成之半導體晶片載置部31上， 複數個電極15A。 半導體裝置用配線構件10，係具備：絕緣層U.加 如由不鏽鋼構成之金屬基板12;及銅配線層13。其中， 銅配線層13，係包含：複數個第1端子部UD，分別被 -37- 201027699 電連接於半導體晶片15之電極15A;外部連接用之複數 個第2端子部13E;及配線部13C，分別電連接第1端子 部13D與第2端子部13E。 另外，半導體晶片15之各電極15A與銅配線層13 之各第1端子部13D之間，係分別藉由金接合導線形成 之第1連接部16予以連接。 另外，於銅配線層13之各第2端子部13E上各設 有，由焊錫連接部構成之外部連接用之第2連接部27A、 Q 27B。各第2連接部27A、27B係由錫球構成。如圖22所 示，彼等第2連接部2 7A、27B之中，接近半導體晶片15 (第1端子部13D)的第2連接部以符號27A表示，遠離 半導體晶片15(第1端子部13D)的第2連接部以符號 27B表示。 銅配線層13、半導體晶片15及第1連接部16係藉 由密封樹脂部23予以密封。此情況下，上述第2連接部 27A、27B，其頂部由密封樹脂部23露出外方。彼等第2 ❹ 連接部27A、27B之中露出密封樹脂部23之外方之部 分，係設爲和例如外部機器之導電性構件電連接用，如此 則，可以電連接半導體晶片15與外部機器。 金屬基板12可使用各種金屬，但金屬基板12最好由 不鏽鋼構成。藉由金屬基板12由不鏽鋼構成’可提升金 屬基板12之剛性，薄化金屬基板12之厚度。另外’半導 體晶片15之熱可由金屬基板12背面散熱。 圖23爲本實施形態之半導體裝置40使用之半導體裝 -38- 201027699 置用配線構件10之平面圖。如圖23所示，銅配線層13 之複數個第2端子部13E分別具有平面圓形形狀。於圖 23’複數個第2端子部13E之中，接近第1端子部13D 的位置上設置之第2端子部以符號13Ei表示，遠離第1 端子部13D的位置上設置之第2端子部以符號13 £2表 不 ° 如圖23所示，銅配線層13之各配線部13C，係分別 0 於中途具有曲柄部13H。另外，第1端子部13D與（接近 第1端子部13D)的第2端子部El之連接用配線部 13C’係以包圍第2端子部El的方式被迂迴佈局（周圍部 131)。 如上述說明，藉由設置曲柄部13H及周圍部131可獲 得以下效果。亦即，於第2端子部Ε,、E2上藉由焊錫形 成第2連接部27A、27B時，溶融之焊錫會沿著配線部 13C流動。此情況下，藉由曲柄部13H及周圍部131可使 φ 流動之焊錫遠離第1端子部13D，如此則，焊錫不會到達 第1端子部13D。相對於此，假設未設置曲柄部13H及周 圍部131時，流動之焊錫有可能到達第1端子部13D。如 此則，於導線接合工程，第1連接部16(接合導線）無 法連接於第1端子部13D之情況有可能發生。 又，如圖25之變形例所示，於銅配線層1 3之背面， 介由散熱板黏接層28安裝散熱板29亦可。此情況下，散 熱板黏接層 28由例如小片黏接薄膜（die attachment film)構成，貫穿孔B39由例如銅構成。藉由此種構成， •39- 201027699 半導體晶片15之熱可介由散熱板29散熱至外方，更能提 升半導體裝置40之散熱特性。 接著，依據圖24 (a) - (e)說明製造圖22所示封裝 型半導體裝置40之方法。 首先，藉由圖20(a) -(d)所示工程製造半導體裝 置用配線構件1〇(圖24(a))。之後，於銅配線層13 之各第2端子部13E (第2端子部13Ei、第2端子部 E2)上’分別設置外部連接用之第2連接部27A、27B φ (錫球）（圖24(b))。此時，如上述說明，使配線部 13C包圍第2端子部13Ε,被迂迴佈局（圖23)。如此 則’形成第2連接部27A、27Β時，即使焊錫沿著配線部 13C流動時，該焊錫亦不會到達第1端子部13D。 之後，使半導體晶片15介由黏接層14被載置、固定 於半導體裝置用配線構件10之半導體晶片載置部31上 (圖24(c))。之後，藉由接合導線所構成之第1連接 部16’進行半導體晶片15之各電極15A與銅配線層13 〇 之各第1端子部13D之間之連接（圖24 (d))。 之後，使銅配線層13、半導體晶片15及第1連接部 16藉由密封樹脂部23施予密封，製成圖22所示半導體 裝置 40 (圖 24 ( e))。 如上述說明，依據本實施形態，可將較習知更小型的 半導體晶片15連接於外部機器。亦即，依據本實施形 態，藉由第1連接部16進行半導體晶片15之各電極15A 與銅配線層13之第1端子部13D之間之連接，於銅配線 -40- 201027699 層13之各第2端子部13E上，設置由錫球構成之外部連 接用之第2連接部27A、27B。如此則，即使外部機器之 各導電性構件間之間距相對較寬，半導體晶片1 5之各電 極1 5 A間之間距相對較窄（例如4 0 μιη )之情況下，亦可 確實進行半導體晶片15與外部機器間之連接。 另外，依據本實施形態，第1連接部16與第2連接 部27A、27Β之間存在銅配線層13，因此，和直接藉由金 0 接合導線來連接半導體晶片15之電極15Α與第2連接部 2 7Α、27Β之情況比較，可降低半導體裝置40之製造成 本。 另外，依據本實施形態，金屬基板12由不鏽鋼形 成，和習知由聚醯亞胺形成之基板比較更具有剛性，容易 處理，而且厚度可以較薄。另外，來自半導體晶片15之 熱可由金屬基板12之背面予以散熱。 φ (第5實施形態） 以下依據圖26-30說明本發明第5實施形態。 圖26爲半導體裝置用配線構件之槪略斷面圖。圖27 爲本實施形態之半導體裝置用複合配線構件之槪略斷面 圖。圖28爲本實施形態之半導體裝置用複合配線構件及 半導體裝置之平面圖。圖29爲本實施形態之半導體裝置 之槪略斷面圖。圖30(a) - (f)爲本實施形態之半導體 裝置之製造方法之圖。於圖26-30之第5實施形態，和圖 1-1 1所示第1實施形態及圖16-21所示第3實施形態同— -41 - 201027699 之部分附加同一符號並省略詳細說明。 首先’依據圖26說明本實施形態之半導體裝置用配 線構件之槪略。又’於圖26，爲求方便而將構成半導體 裝置用配線構件之部分以外以假想線（2點虛線）表示。 如圖26所示，本實施形態之導線連接型半導體裝置 用配線構件1〇’係具備：例如聚醯亞胺形成之絕緣層 11;配置於絕緣層11之一側的金屬基板12;及配置於絕 緣層11之另一側的銅配線層13。其中，銅配線層13，係 Q 包含：複數個第1端子部13D，分別被電連接於半導體晶 片15之電極15A;複數個第2端子部13E，分別被電連 · 接於內引線部21 (外部配線構件）；及複數個配線部 13C，分別用於電連接第1端子部13D與第2端子部 1 3E。 金屬基板12可使用各種金屬，但金屬基板12最好由 不鏽鋼構成。藉由金屬基板12由不鏽鋼構成，可提升金 屬基板12之剛性，薄化金屬基板12之厚度。 〇 在銅配線層13上形成半導體晶片載置部31。於該半 導體晶片載置部31上，可以載置沿其周圍設置之具有複 數個電極15A的半導體晶片15。 以下依據圖27、28說明本實施形態之半導體裝置用 複合配線構件。又，於圖27，爲求方便而將構成半導體 裝置用複合配線構件之部分以外以假想線（2點虛線）表 示。 如圖27所示，半導體裝置用複合配線構件1 0A，係 -42- 201027699 由以下構成：上述半導體裝置用配線構件10;電連接於 該半導體裝置用配線構件10的引線框架20;第2連接部 19’用於電連接銅配線層13之第2端子部13E與引線框 架20。該半導體裝置用複合配線構件i〇A，係用於電連 接半導體晶片15之電極15A與外部配線基板（未圖示） 者。 引線框架20具有：載置半導體裝置用配線構件1〇的 φ 晶粒焊墊22;及位於晶粒焊墊22外方的引線部25。又， 於引線部25上設有銀鍍層或鈀（Pd)鏟層構成之內引線 部21 (外部配線構件）。 又，晶粒焊墊22，係具有：中央區域22c，對應於半 導體晶片15 ;及周緣區域22d，位於中央區域22c之外 周，在和中央區域22c之間形成密封樹脂流入空間32。 其中，中央區域22c係介由配置於四角的吊掛引線 34連結於周緣區域22d(參照圖28)。另外，周緣區域 φ 22d係介由配置於四角的吊掛引線35被保持於引線框架 2〇內（參照圖28)。又，形成於中央區域22c與周緣區 域22d之間的密封樹脂流入空間32，係如後述說明，其 內部被流入密封樹脂部23，硬化後提升密封樹脂部23與 引線框架20間之密接性者。 本實施形態中，半導體裝置用配線構件10，係配置 於晶粒焊墊22之中央區域22 c至周緣區域22d爲止之區 域，亦即，如圖28所示，半導體裝置用配線構件1〇，係 覆蓋中央區域22c之全區域及密封樹脂流入空間32之全 -43- 201027699 區域，而且覆蓋周緣區域22d之一部分，而被配置。 半導體裝置用配線構件1〇,係於晶粒焊墊22之中央 區域22c及周緣區域22d，使用樹脂糊33被黏接，如圖 28所示，樹脂糊33，係於晶粒焊墊22之中央區域22c及 周緣區域22d，分別以多點狀被塗敷。但是不限定於此， 樹脂糊33亦可於晶粒焊墊22之中央區域22c及周緣區域 22d以直線狀被塗敷。此種樹脂糊33可使用例如環氧樹 脂、丙烯酸樹脂、聚醯亞胺系列樹脂等之樹脂糊（附加糊 @ 的材料）。 又，晶粒焊墊22之中至少於中央區域22c及周緣區 域22d事先施予鍍層處理較好。如此則，藉由對晶粒焊墊 22施予鍍層處理，可於晶粒焊墊22之表面形成微細凹 凸。如此則，塗敷樹脂糊3 3時可抑制樹脂糊3 3之流出。 另外，於晶粒焊墊22使用之壓延銅’於一定方向被形成 溝，樹脂糊3 3有可能沿著該溝流出。針對此’藉由對晶 粒焊墊22之表面施予鍍層處理，可塡埋該溝，可抑制樹 〇 脂糊3 3之流出。此種鍍層可爲例如銀鍍層、鈀鍍層、金 鍍層等，雖不限定種類，但就成本面而言最好是使用銀鍍 層。 又，如圖27所示，晶粒焊墊22之厚度被形成爲較引 線部25之厚度爲薄。如此則，搭載有半導體晶片15的半 導體裝置30可以構成薄型化。 另外，第2連接部19係由金接合導線構成’其之個 別之一端被連接於對應之第2端子部13E之同時，另一端 -44 - 201027699 被連接於引線框架20之內引線部21。 以下依據圖28、29說明具有上述半導體裝置用配 構件及半導體裝置用複合配線構件的半導體裝置之槪略 又’於圖28’爲求方便而圖示省略密封樹脂部之狀態。 圖28、29之半導體裝置30，係包含圖26之半導 裝置用配線構件10。亦即，半導體裝置30，係具有： 線框架20’其具有晶粒焊墊22;半導體裝置用配線構 φ 10’被載置於引線框架20之晶粒焊墊22上，電連接於 線框架20。另外，於半導體裝置用配線構件1〇之半導 晶片載置部31，被載置具有電極15A的半導體晶片15 該半導體晶片15，係介由黏接層14被載置、固定於半 體晶片載置部3 1上。 於引線框架20之上面被形成複數個導電性內引線 21。金接合導線所構成之各第2連接部19，係用於電 接銅配線層13之各第2端子部13E與對應之內引線 φ 21。另外，半導體晶片15上之電極15A與第1端子 1 3D之間，係藉由金接合導線所構成之第1連接部16 電連接。另外，於露出引線框架20之引線部25之一部 之狀態下，使半導體晶片15、銅配線層13、引線框 20、第1連接部16及第2連接部19藉由樹脂密封部 施予樹脂密封。 晶粒焊墊22，係具有：中央區域22c ’其對應於半 體晶片15 ;及周緣區域22d，位於中央區域22c之外周 同時，被連結於中央區域22c’在其和中央區域22〇之 線 體 引 件 引 體 TUz. 〇 導 部 連 部 部 被 分 架 23 導 之 間 -45- 201027699 被形成密封樹脂流入空間3 2。 另外，晶粒焊墊22之構成已使用圖27、28加以說 明，因此省略其詳細說明。 又，如圖29所示，半導體裝置用配線構件10’係配 置於晶粒焊墊22之中央區域22c至周緣區域22d爲止之 區域。該半導體裝置用配線構件10,係於晶粒焊墊22之 中央區域22c及周緣區域22d，使用樹脂糊33被黏接。 關於此點亦已使用圖27、28加以說明，因此省略其詳細 0 說明。 以下依據圖20 (a) - (d)及圖30(a) - (f)說明由 上述構成所形成之本實施形態之作用。 首先’製造圖26所示半導體裝置用配線構件1〇(圖 30(a))，該製造方法，係如使用圖20(a) - (d)加以 說明者。 之後’準備具有引線部25與晶粒焊墊22的引線框架 20，於該引線框架20之晶粒焊墊22上載置半導體裝置用 〇 配線構件10(圖30(b))。又，晶粒焊墊22之中至少 於中央區域22c及周緣區域22d事先施予鍍層處理較好。 此情況下’半導體裝置用配線構件10，係使用樹脂糊33 被黏接於晶粒焊墊22之中央區域22c及周緣區域22d。 具體Η之爲’首先，於晶粒焊墊22之中央區域22c 及周緣區域22d ’使樹脂糊33以例如多點狀被塗敷。此 情況下’可使用注射器（未圖示）將樹脂糊3 3 一點一點 滴下’或一次滴下複數點。另外，樹脂糊33亦可以直線 -46 - 201027699 狀被塗敷。以直線狀塗敷時，只需使注射器以直線狀移動 而將樹脂糊塗敷即可。 之後，將半導體裝置用配線構件1〇載置於晶粒焊墊 22之中央區域22c及周緣區域22d上。之後，對載置有 半導體裝置用配線構件1〇之引線框架20全體進行加熱以 硬化樹脂糊33，使半導體裝置用配線構件10固接於晶粒 焊墊22上。 φ 之後，使半導體晶片15介由黏接層14被載置、固定 於半導體裝置用配線構件10之半導體晶片載置部31上 (圖30 (c))之同時，藉由接合導線所構成之第1連接 部16,進行半導體晶片15之各電極15A與銅配線層13 之各第1端子部13D之間之連接（圖30(d))。 之後，分別藉由接合導線所構成之第2連接部19, 進行銅配線層13之各第2端子部13E與對應之引線框架 20之內引線部21之間之連接（圖30(e))。 φ 之後，於露出引線框架20之一部分（外引線部）之 狀態下，使半導體裝置用配線構件10、半導體晶片15、 第1連接部16、晶粒焊墊22、第2連接部19及內引線部 21藉由樹脂密封部23施予樹脂密封，製成圖29所示半 導體裝置30(圖30(f))。此時，在中央區域22c與周 緣區域22d之間被形成的密封樹脂流入空間32內，會流 入硬化前之密封樹脂部23。如此則，於密封樹脂部23硬 化後，密封樹脂部23與引線框架20間之密接性可以提 升。 -47- 201027699 如上述說明，於晶粒焊墊22搭載半導體裝置用配線 構件10時，在半導體晶片15之搭載後之硬化或烘烤時， 以及藉由密封樹脂部23之樹脂密封時，半導體裝置用配 線構件1 〇及晶粒焊墊22約以180°C之溫度被加熱。此 時，黏接半導體裝置用配線構件10與晶粒焊墊22的黏接 劑亦被加熱，因此，假設該黏接劑中含有水分時，吸濕之 水會被加熱而產生水蒸汽。相對於此，本實施形態中，半 導體裝置用配線構件10與晶粒焊墊22係使用樹脂糊33 φ 予以黏接。此種樹脂糊33，通常不容易產生有機氣體， 而且吸濕性低。因此，來自樹脂糊33之氣體（有機氣體 及水蒸汽）不容易殘留於密封樹脂部23內。 另外，假設在氣體殘留於晶粒焊墊22與半導體裝置 用配線構件1 〇之間附近之狀態下使密封樹脂部23固化， 針對完成後之半導體裝置30進行吸濕試驗（迴焊試驗） 時，氣體殘留部分會有膨潤，有可能由此而產生裂痕。相 對於此，依據本實施形態，如上述說明，藉由使用樹脂糊 © 33可減少密封樹脂部23內殘留之氣體，吸濕試驗（迴焊 試驗）時，半導體裝置30不會產生裂痕。 另外，依據本實施形態，在晶粒焊墊22之中央區域 22c與周緣區域22d之間形成密封樹脂流入空間32，可提 升密封樹脂部23與引線框架20之密接性。如此則，吸濕 試驗（迴焊試驗）時，可防止由晶粒焊墊22下面與密封 樹脂部2 3之間之間隙之產生裂痕。 如上述說明，依據本實施形態，可將較習知更微細化 -48 - 201027699 (fine )的小型半導體晶片1 5搭載於引線框架20。亦 即，即使在引線框架20之內引線部21間之間距較寬（例 如130μιη)，半導體晶片15之電極15A間之間距較窄 (例如40μιη)的情況下，亦可將半導體晶片15確實連接 於引線框架20之內引線部21。 又，依據本實施形態，晶粒焊墊22之中央區域22c 及周緣區域22d之厚度被形成較引線部25之厚度爲薄。 φ 因此，半導體裝置30可以構成薄型化。 又，依據本實施形態，半導體裝置用配線構件10, 係使用樹脂糊33被黏接於晶粒焊墊22之中央區域22c及 周緣區域22d。另外，在中央區域22c與周緣區域22d之 間形成密封樹脂流入空間3 2。如此則，吸濕試驗（迴焊 試驗）時，可防止半導體裝置30之產生裂痕。 又’依據本實施形態，樹脂糊33，係以多點狀或直 線狀被塗敷，因此，樹脂糊33可均勻塗敷於中央區域 φ 22c及周緣區域22d。 又’依據本實施形態，第1連接部16與第2連接部 18之間存在銅配線層13’因此’和直接藉由金接合導線 來連接半導體晶片1 5之電極15A與引線框架20之內引 線部2 1之情況比較，可降低半導體裝置3 〇之製造成本。 另外，依據本實施形態，金屬基板12由不鏽鋼形 成’和習知由聚酿亞胺形成之基板比較更具有剛性，容易 處理，而且厚度可以較薄。 -49- 201027699 (發明效果） 依據本發明，半導體晶片與銅配線層之間係藉由第1 連接部被連接，銅配線層與引線框架之間係藉由第2連接 部被連接，因此，針對較寬間距之引線框架之內引線部’ 與較窄間距之半導體晶片之電極之間，可以確實進行連 接。如此則，可以將較習知爲小的半導體晶片搭載於半導 體裝置之引線框架。 另外，依據本發明，作爲半導體裝置進行封裝之前， ❹ 可以搭載於半導體裝置用配線構件或半導體裝置用複合配 線構件之狀態下進行半導體晶片之檢測。 另外，依據本發明，以第1連接部與第2連接部之間 設有銅配線層，和直接藉由接合導線連接半導體晶片與引 線框架之情況比較，可降低製造成本。 另外，依據本發明，金屬基板由不鏽鋼形成，和習知 由聚醯亞胺形成之基板比較更具有剛性，容易處理，而且 厚度可以較薄。另外，來自半導體晶片之熱可由金屬基板 © 背面予以散熱。 另外，依據本發明，半導體晶片具有電連接於半導體 晶片上之複數個電極的端子區塊部，可將半導體晶片之電 極之中例如電源端子統合連接於該端子區塊部。如此則， 可減少第2連接部，可減少半導體裝置中之總端子數。另 外’可縮小封裝後之半導體裝置之外形，可增加引線框架 內之封裝之數目，可降低半導體裝置之製造成本。另外， 將半導體裝置用複合配線構件載置於較半導體裝置用複合 -50- 201027699 配線構件稍大的分割晶粒焊墊上之同時，將半導體裝置用 複合配線構件與晶粒焊墊予以結線，如此則可使該分割晶 粒焊墊構成爲GND區塊。另外，於半導體晶片之下介由 絕緣薄膜（或糊）配置銅配線層，使晶粒焊墊較半導體晶 片之尺寸爲大，以該晶粒焊墊作爲GND層可介由導線接 合予以連接，此情況下，可減少半導體裝置中之總端子 數。 Φ 【圖式簡單說明】 圖1爲本發明半導體裝置用配線構件（導線連接型） 之第1實施形態之槪略斷面圖。 圖2爲本發明第1實施形態之槪略平面圖。 圖3爲本發明第1實施形態之半導體裝置用配線構件 之變形例1 (焊錫連接型）之槪略斷面圖。 圖4爲包含圖1之半導體裝置用配線構件的半導體裝 φ 置之槪略斷面圖。 圖5爲包含圖3之半導體裝置用配線構件的半導體裝 置之槪略斷面圖。 圖6(a) - (d)爲半導體裝置用配線構件之製造方法 之圖。 圖7(a) - (f)爲圖4所示半導體裝置之製造方法之 圖。 圖8(a) - (f)爲圖5所示半導體裝置之製造方法之 圖爲。 -51 - 201027699 圖9爲本發明第1實施形態之半導體裝置用配線構件 之變形例2之槪略平面圖。 圖10爲本發明第1實施形態之半導體裝置用配線橇 件之變形例3之槪略平面圖。 圖11(a)爲本發明第1實施形態之半導體裝置用配 線構件之變形例4之槪略平面圖，圖11(b)爲圖 u (a)之A-A線斷面圖。 圖12爲本發明半導體裝置之第2實施形態之槪略斷 面圖。 圖13(a) - (e)爲封裝型之半導體裝置之製造方法 之圖。 圖14(a) - (f)爲圖4所示半導體裝置之製造方法 之變形例之圖。 圖15(a) - (f)爲圖5所示半導體裝置之製造方法 之變形例之圖。 圖16爲本發明第3實施形態之半導體裝置用配線構 件之槪略斷面圖。 圖17爲本發明第3實施形態之半導體裝置用複合配 線構件之槪略斷面圖。 圖18爲本發明第3實施形態之半導體裝置用配線構 件之變形例之槪略斷面圖。 圖19爲本發明第3實施形態之半導體裝置之槪略斷 面圖。 圖20(a) - (d)爲本發明第3實施形態之半導體裝 -52- 201027699 置用配線構件之製造方法之圖。 圖21(a) - (f)爲本發明第3實施形態之半導體裝 置之製造方法之圖。 圖22爲本發明第4實施形態之半導體裝置之槪略斷 面圖。 圖23爲本發明第4實施形態之半導體裝置使用之半 導體裝置用配線構件之平面圖。 圖24(a) _(e)爲本發明第4實施形態之半導體裝 置之製造方法之圖。 圖25爲本發明第4實施形態之半導體裝置之變形例 之槪略斷面圖。 圖26爲本發明第5實施形態使用之半導體裝置用配 線構件之槪略斷面圖。 圖27爲本發明第5實施形態之半導體裝置用複合配 線構件之槪略斷面圖。 © 圖28爲本發明第5實施形態之半導體裝置用複合配 線構件及半導體裝置之槪略平面圖。 圖29爲本發明第5實施形態之半導體裝置之槪略斷 面圖（圖28之B-B線斷面圖）。 圖3〇 ( a) - ( f)爲本發明第5實施形態之半導體裝 置之製造方法之圖。 【主要元件符號說明】 10:半導體裝置用配線構件 -53- 201027699 10A:半導體裝置用複合配線構件 1 1 :絕緣層 11A、31:半導體晶片載置部 12 :金屬基板 1 3 :銅配線層 1 3 A :銅層 1 3B :鍍層 13C :配線部 _ 13D :第1端子部 1 3 E :第2端子部 14 :黏接層 1 5 :半導體晶片 1 5 A :電極 16 :第1連接部 18、19、24、27A、27B ：第 2 連接部[Technical Field] The present invention relates to a wiring member for a semiconductor device, a composite wiring member for a semiconductor device, and a resin-sealed semiconductor device, that is, a semiconductor wafer which can be surely mounted more compactly At the same time, the wiring member for a semiconductor device, the composite wiring member for a semiconductor device, and the resin-sealed semiconductor device can be reduced in manufacturing cost. [Prior Art].  In recent years, The advancement of semiconductor devices by high integration or miniaturization techniques, The high performance of electronic equipment and the tendency to be thin and light, Progress is more integrated, Highly functional. In this high integration, In a highly functional semiconductor device, The sum of the external terminals (pins) is required to be increased or more multi-terminalized.  As a semiconductor package of such a semiconductor device, There is a 1C wafer on the lead frame a semiconductor wafer such as an LSI wafer, A structure that is sealed with an insulating resin. In such a semiconductor device, With the progress of high integration and miniaturization, The package structure is also formed by an external lead such as a SOJ (Small Outline J-Leaded Package) or a QFP (Qua Flat Package) protruding outward from the side wall of the resin package. Progression becomes the external lead that does not protrude to the outside, A thin type such as a QFN (Qua Flat Non-leaded Package) or a SON (Small Outline Nonleaded Package) in which the external lead is buried to expose the back surface of the resin package. The installation area is smaller.  -5- 201027699 In addition, To avoid the installation efficiency of the QFP package, Installation problems, A resin sealed semiconductor device called a surface mount package BG A (Ball Grid Array), which is provided with a solder ball as an external terminal of the package, is mass-produced. In addition, Replace the ball of BG A, a surface mount package formed by arranging external terminals formed by matrix planar electrodes, There is a semiconductor device called LGA (Land Grid Array).  Patent Document 1: Patent No. 2688099 Patent Document 2: JP-A-H04-41434 φ [Summary of the Invention] (Problems to be solved by the invention) · However, Semiconductor wafers are making progress toward miniaturization (fine), There is a limit to the narrowing of the distance (interval) between the inner leads of the lead frame. Therefore, It is expected that it will become difficult to mount such a miniaturized semiconductor wafer on a lead frame.  also, When performing such a detection of a semiconductor device, Need to install a semiconductor G chip, The detection is performed after the completion of the semiconductor device including the semiconductor wafer. therefore, When the semiconductor wafer is not good, it is necessary to discard the entire semiconductor device. therefore, When the yield of semiconductor wafers deteriorates, There is a possibility that the loss of the cost side becomes large.  The present invention is directed to this problem, The purpose is to provide a semiconductor wafer that can be mounted with miniaturization The semiconductor wafer can be inspected before being sealed as a semiconductor device, Moreover, the wiring member for a semiconductor device which can reduce the manufacturing cost, Composite wiring member for semiconductor device, And -6- 201027699 Resin-sealed semiconductor device.  (Means for Solving the Problem) The wiring member for a semiconductor device of the present invention, Used for electrically connecting electrodes and external wiring members on a semiconductor wafer; It is characterized by: Insulation; a metal substrate disposed on one side of the insulating layer; And a copper wiring layer disposed on the other side of the insulating layer; Forming a semiconductor wafer mounting portion on the copper wiring layer side or the copper wiring layer φ of the insulating layer; Copper wiring layer, The system contains: The first terminal, An electrode connected to the semiconductor wafer; Second terminal portion, Connected to an external wiring member; And wiring department, It is used to connect the first terminal part and the second 'terminal part.  Among the wiring members for a semiconductor device of the present invention, Metal substrate, It is made of stainless steel.  Among the wiring members for a semiconductor device of the present invention, Copper wiring layer, Department has: Electrically connected to the terminal block portion of the plurality of electrodes on the semiconductor wafer.  复合 The composite wiring member for a semiconductor device of the present invention, Used for electrically connecting electrodes and wiring substrates on a semiconductor wafer; It is characterized by: Wiring member And a lead frame electrically connected to the wiring member; Wiring member harnesses are: Insulation; a metal substrate disposed on one side of the insulating layer; And a copper wiring layer disposed on the other side of the insulating layer; Forming a semiconductor wafer mounting portion on the copper wiring layer side or the copper wiring layer of the insulating layer; Copper wiring layer, The system contains:  The first terminal portion, An electrode connected to the semiconductor wafer; The second terminal, Connected to the lead frame; And wiring department, For connecting the first terminal portion and the second terminal portion; The second terminal portion of the copper wiring layer and the lead frame are connected by the 201027699 second connection portion.  In the composite wiring member for a semiconductor device of the present invention, Metal substrate, It is made of stainless steel.  In the composite wiring member for a semiconductor device of the present invention, The second connection, It consists of solder.  In the composite wiring member for a semiconductor device of the present invention, The second connection, It consists of a bonding wire.  The resin-sealed type semiconductor device of the present invention, It is characterized by: With Q wire components, It has: Insulation; a metal substrate disposed on one side of the insulating layer; And a copper wiring layer disposed on the other side of the insulating layer; Forming a semiconductor wafer mounting portion on the copper wiring layer side or the copper wiring layer of the insulating layer; Copper wiring layer contains: The first terminal portion, An electrode connected to the semiconductor wafer;  Second terminal portion, Connected to an external wiring member; And wiring department, For connecting the first terminal portion and the second terminal portion; Lead frame, Electrically connected to the wiring member; And semiconductor wafers, Mounted on the semiconductor wafer mounting portion of the wiring member, It has an electrode; The electrode on the semiconductor wafer and the first terminal portion © are electrically connected by the first connection portion; The second terminal portion and the lead frame are electrically connected by the second connection portion; In a state where one of the lead frames is exposed, Making semiconductor wafers, Copper wiring layer, Lead frame, The first connecting portion and the second connecting portion are resin-sealed by a resin sealing portion.  The resin-sealed type semiconductor device of the present invention, It is characterized by: Wiring assembly, have: Insulation; a metal substrate disposed on one side of the insulating layer; And a copper wiring layer disposed on the other side of the insulating layer; Forming a semiconductor wafer mounting portion on the copper wiring layer side or the copper wiring layer of the insulating layer; Copper Wiring -8- 201027699 The layer system contains: The first terminal portion, Connected to the second terminal part, Connected to the external wiring member to connect the first terminal portion and the second terminal portion; And a semiconductor conductor that is placed on the semiconductor wafer carrier wafer of the wiring member is borrowed from the first terminal portion; Providing a joint portion on the second terminal portion of the copper wiring layer; Make the copper wiring layer, The semiconductor wafer and the φ grease portion are sealed, The second connecting portion is made of a sealing tree. The resin-sealed type semiconductor device of the present invention is made of solder.  The resin-sealed type semiconductor device of the present invention is composed of stainless steel.  The composite wiring for a semiconductor device of the present invention is an electrode and a wiring substrate on a semiconductor wafer;  member; And a lead frame electrically connected to the wiring member; The wiring member has: a metal substrate on one side of the insulation; And being disposed on the insulating layer to form a semiconductor wafer on the copper wiring layer. The first terminal portion, Connected to the semiconductor crystal part, Connected to the lead frame; And a wiring portion and a second terminal portion; The second end of the copper wiring layer is connected by the second connecting portion; Lead frame, a die pad of the system; And an electrode disposed on the conductor wafer on which at least the semiconductor wafer is placed in the die pad;  : And wiring department, Used in conjunction with wafers, Through the adhesive layer, With an electrode; The second connecting portion is electrically connected to the second connecting portion for external connection. The connecting portion is exposed to the outside by the sealing resin portion.  Among them, The second connection,  Among them, Metal substrate, Department component, Used for electrical connection. It is characterized by: Wiring, Used to mount a wiring member layer; a copper wiring layer disposed on the other side of the insulating layer;  that; Copper wiring layer, Attaching the electrodes on the sheet; Second end, Used to connect the first terminal and the lead frame. Mounting a wiring member; a lead portion outside the bonding pad;  The thickness of the central area, The thickness of the lead portion is thinner than 201027699.  In the composite wiring member for a semiconductor device of the present invention, Metal substrate, It is made of stainless steel.  In the composite wiring member for a semiconductor device of the present invention, The second connection, It consists of a bonding wire.  In the composite wiring member for a semiconductor device of the present invention, Die pad, Has: Central area, For mounting a semiconductor wafer; And the peripheral area, Located in the outer perimeter of the central area. And the lead portion is roughly the same thickness; There is a slit hole between the central area and the peripheral area.  The resin-sealed type semiconductor device of the present invention, It is characterized by: Wiring assembly, It has: Insulation; a metal substrate disposed on one side of the insulating layer; And a copper wiring layer disposed on the other side of the insulating layer; Forming a semiconductor wafer mounting portion on the copper wiring layer; The copper wiring layer contains: The first terminal portion,  An electrode connected to the semiconductor wafer; Second terminal portion, Connected to an external wiring member; And wiring department, For connecting the first terminal portion and the second terminal portion; Lead frame, Electrically connected to the wiring member, For mounting and dispensing components: And semiconductor wafers, Being placed on the semiconductor wafer mounting portion of the wiring member, With an electrode; The electrode on the semiconductor wafer and the first terminal portion are electrically connected by the first connection portion; The second terminal portion and the lead frame are electrically connected by the second connection portion; In a state where one of the lead frames is exposed, Making semiconductor wafers, Copper wiring layer, Lead frame, The first connecting portion and the second connecting portion are resin-sealed by the sealing resin portion; Lead frame, Department has: a die pad on which the wiring member is placed; And a lead portion disposed outside the die pad; Between the die pads, at least the thickness of the central region of the semiconductor wafer is -10- 201027699, It is thinner than the thickness of the lead portion.  In the resin-sealed type semiconductor device of the present invention, Die pad, Department has: Central area, For mounting a semiconductor wafer; And the peripheral area, Located at the outer periphery of the central region and the lead portion is substantially the same thickness; A slit hole is provided between the central area and the peripheral area.  In the resin-sealed type semiconductor device of the present invention, The length of the bottom surface of the die pad to the bottom of the sealing resin portion, And the length of the wiring member to the upper side of the sealing resin portion φ, The system is roughly the same.  The resin-sealed type semiconductor device of the present invention, It is characterized by having a wiring member 'which has: Insulation; a metal substrate disposed on one side of the insulating layer; And a copper wiring layer disposed on the other side of the insulating layer; Forming a semiconductor wafer mounting portion on the copper wiring layer; The copper wiring layer contains: The first terminal portion,  An electrode connected to the semiconductor wafer; Second terminal portion, Connected to an external wiring member; And wiring department, For connecting the first terminal portion and the second terminal portion; And semiconductor wafers, The adhesive layer is placed on the half φ conductor wafer mounting portion of the wiring member, With an electrode; The electrode on the semiconductor wafer and the first terminal portion are electrically connected by the first connection portion; a second connection portion for external connection is provided on the second terminal portion of the copper wiring layer; Make the copper wiring layer, The semiconductor wafer and the first connection portion are sealed by a sealing resin portion. The second connection 'portion is exposed to the outside by the sealing resin portion; The second connecting portion is formed of solder; a wiring portion for connection between the first connection portion and the second connection portion, The layout is bypassed in such a way as to surround the second terminal.  In the resin-sealed type semiconductor device of the present invention, Metal substrate, It is made of stainless steel.  -11 - 201027699 The composite wiring member for a semiconductor device of the present invention, Used for electrically connecting electrodes and wiring substrates on a semiconductor wafer; It is characterized by: Wiring member And electrically connected to the wiring member, a lead frame for mounting a wiring member; The wiring member has: Insulation; a metal substrate disposed on one side of the insulating layer; And a copper wiring layer disposed on the other side of the insulating layer;  Forming a semiconductor wafer mounting portion on the copper wiring layer; Copper wiring layer, The system contains: The first terminal portion, An electrode connected to the semiconductor wafer; The second end of the subsection, Connected to the lead frame; And wiring department, For connecting the first terminal Q portion and the second terminal portion; The second terminal portion of the copper wiring layer and the lead frame are connected by the second connection portion; Lead frame, Has: a die pad on which the wiring member is placed; And a lead portion disposed outside the die pad; Die pad,  Has: Central area, Corresponding to a semiconductor wafer; And the peripheral area, It is connected to the central area at the same time as the outer periphery of the central area. Forming a sealing resin inflow space between it and the central area; Wiring member, It is placed in the area from the central area of the die pad to the peripheral area: Wiring member, The resin paste is bonded to at least the central region and the peripheral region of the die pad.  © the composite wiring member for a semiconductor device of the present invention, Metal substrate, It is made of stainless steel.  In the composite wiring member for a semiconductor device of the present invention, Resin paste,  It is applied in a multi-point or linear shape.  In the composite wiring member for a semiconductor device of the present invention, Among the die pads, The plating treatment is applied at least in the central region and the peripheral region.  The resin-sealed type semiconductor device of the present invention, It is characterized by: Wiring assembly, have: Insulation; a metal base -12- 201027699 plate disposed on one side of the insulating layer; And a copper wiring layer disposed on the other side of the insulating layer; Forming a semiconductor wafer mounting portion on the copper wiring layer; The copper wiring layer contains: The first terminal portion,  An electrode connected to the semiconductor wafer; Second terminal portion, Connected to an external wiring member; And wiring department, For connecting the first terminal portion and the second terminal portion; Lead frame, Electrically connected to the wiring member, For mounting wire components; And semiconductor wafers, Being placed on the semiconductor wafer mounting portion of the wiring member, With an electrode; The electrode on the semiconductor wafer and the first terminal portion φ are electrically connected by the first connection portion; The second terminal portion and the lead frame are electrically connected by the second connection portion; In a state where one of the lead frames is exposed, Making semiconductor wafers, Copper wiring layer, Lead frame, The first connecting portion and the second connecting portion are resin-sealed by the sealing resin portion; Lead frame, Department has: a die pad on which the wiring member is placed; And a lead portion disposed outside the die pad; Die pad, Has: Central area, Corresponding to a semiconductor wafer; And the peripheral area, Located in the central area while being located outside the central area, Forming a sealing resin inflow space between it and the central region; Wiring • components, Arranging in a region from a central region of the die pad to a peripheral region; Wiring member, The resin paste is bonded at least in the central region and the peripheral region of the die pad.  In the resin-sealed type semiconductor device of the present invention, Metal substrate, It is made of stainless steel.  In the resin-sealed type semiconductor device of the present invention, Resin paste, It is applied in a multi-point or linear shape.  In the resin-sealed type semiconductor device of the present invention, Among the die pads, The plating treatment is applied at least in the central region and the peripheral region.  -13 - 201027699 [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings.  (First Embodiment) Figs. 1 to 11 are views showing a first embodiment of the present invention. Fig. 1 is a schematic cross-sectional view showing a first embodiment of the present invention. Fig. 2 is a schematic plan view showing the first embodiment of the present invention. Fig. 3 is a schematic cross-sectional view showing a first modification of the first embodiment of the present invention. 4 is a schematic cross-sectional view showing a semiconductor device including the wiring member for semiconductor device of FIG. 1. Fig. 5 is a schematic cross-sectional view showing a semiconductor device including the wiring member for a semiconductor device of Fig. 3; 6(a) to 6(d) are diagrams showing a method of manufacturing a wiring member for a semiconductor device. 7(a)-(f) are views showing a method of manufacturing the semiconductor device shown in Fig. 4. 8(a)-(f) are diagrams showing a method of manufacturing the semiconductor device shown in Fig. 5.  Fig. 9 is a schematic plan view showing a modification 2 of the wiring member for a semiconductor device according to the first embodiment of the present invention. Fig. 10 is a schematic plan view showing a modification 3 of the wiring member for a semiconductor device according to the first embodiment of the present invention. Fig. 11 (a) is a schematic plan view showing a fourth modification of the wiring member for a semiconductor device according to the first embodiment of the present invention. Figure 11 (b) is a cross-sectional view taken along line a-a of Figure 11 (a). Fig. 14 (a) - (f) are views showing a modification of the method of manufacturing the semiconductor device shown in Fig. 4. Fig. 15 (a) - (f) are views showing a modification of the method of manufacturing the semiconductor device shown in Fig. 5.  First of all, The outline of the wiring member for a semiconductor device of the present invention will be described with reference to Figs.  As shown in Figure 1, In the wire-bonding type semiconductor device of the present embodiment, the wiring member 10 is used for -14 - 201027699 The external wiring member such as the electrode 15A of the semiconductor wafer 15 (described later) and the lead portion 21 (described later) of the lead frame 20 are electrically connected.  Such a wiring member 10 for a semiconductor device, The system has: For example, an insulating layer 11 formed of polyimide; a metal substrate 12 disposed on one side of the insulating layer 11; And a copper wiring layer 13 disposed on the other side of the insulating layer 11. among them, Copper wiring layer 13, The system contains: a plurality of first terminal portions 13D, The φ is not connected to the electrode 15A of the semiconductor wafer 15; a plurality of second terminal portions 13E, Electrically connected to the inner lead portion 21 (external wiring member);  And a plurality of wiring portions 13C, The first terminal portion 13D and the second terminal portion 13E are electrically connected, respectively.  also, The second connection portion 19 for the lead frame 20 is provided on each of the second terminal portions 13E of the copper wiring layer 13. that is, One end of the second connecting portion 19 is connected to the corresponding second terminal portion 13E, The other end is connected to the inner lead portion 21 of the lead frame 20 (described later). also,  φ is shown in Figure 1. 2, Each of the second connecting portions 19, It is made of gold bonding wires.  In addition, Wiring portion 13C of copper wiring layer 13, As shown in Figure 2, It is radially extended by the semiconductor wafer 15. In addition, Copper wiring layer 13 section, As shown in Figure 1, It consists of a central copper layer 13A and a mineral layer 13B covering the copper layer 13A. among them, Plating 13B, For example, a layer of nickel ruthenium, It is composed of a gold (Au) plating layer provided on a nickel (Ni) plating layer.  The metal substrate 12 can use various metals. However, the metal substrate 12 is preferably made of stainless steel. By the metal substrate 12 being made of stainless steel -15-201027699, The rigidity of the metal substrate 12 can be improved, The thickness of the metal substrate 12 is thinned. In addition, The heat of the semiconductor wafer 15 can be dissipated by the back surface of the metal substrate 12.  The semiconductor wafer mounting portion 11A is formed on the side of the copper wiring layer 13 of the insulating layer 11. Semiconductor wafer 15, As shown in Figure 2, There are a plurality of electrodes 15A disposed along the circumference. Semiconductor wafer 15, Is placed by the adhesive layer 14, It is fixed to the semiconductor wafer mounting portion 11A. Between each electrode 15A of the semiconductor wafer 15 and each of the first terminal portions 13D of the copper wiring layer 13, The first connecting portions 16 formed by bonding wires of gold (Au) are respectively connected.  Another configuration (variation 1) of the wiring member 10 for a semiconductor device will be described below with reference to Fig. 3 . In Figure 3, And Figure 1, The same component is attached to the same portion of the wiring member 10 for a semiconductor device of 2, Detailed explanations are omitted.  As shown in Figure 3, Wiring member for solder connection type semiconductor device 10, The system has: Insulation layer 11; a metal substrate 12 disposed on one side of the insulating layer 11; And a copper wiring layer 13 disposed on the other side of the insulating layer 11.  形成 The semiconductor wafer mounting portion 11A is formed on the side of the copper wiring layer 13 of the insulating layer 11, The semiconductor wafer 15 is placed on the semiconductor wafer mounting portion 11A by the adhesive layer 14. The first connection portion 16 formed by the gold bonding wires between the semiconductor wafer 15 and the first terminal portion 13D of the copper wiring layer 13 is electrically connected.  In Figure 3, The second connection portion 18 for the lead frame 20 is provided on each of the second terminal portions 13 of the copper wiring layer 13. that is, The second connecting portion 18, When the lower end is connected to the corresponding second terminal portion 13 -16 - 201027699, The upper end is connected to the inner lead portion 21 of the lead frame 20 (as will be described later). also, In Figure 3, Each of the second connecting portions 18, It consists of a solder joint (tin ball).  In Figure 1, a wiring member 1 for a semiconductor device; Electrically connected to the lead frame 20 of the wiring member 10 for a semiconductor device; Electrically connecting the second terminal portion 13E of the copper wiring layer 13 and the second connection portion 18 of the lead frame 20, 19, The composite wiring member 10A for a semiconductor device is configured. With the φ semiconductor wiring device 10A for semiconductor devices, Electrical connection between the electrode 15A of the semiconductor wafer 15 and an external wiring substrate (not shown) can be performed.  among them, As a form of use of the wiring member 10 for a semiconductor device as shown in FIG. 1 or 3, Electrical connection between each electrode 15A of the semiconductor wafer 15 and the first terminal portion 13D of the copper wiring layer 13, Use a bonding wire (first connecting portion 16), But as other connection methods, Gold bump connections or solder balls can also be used. When using a gold bump or solder ball connection method,  Semiconductor wafer 15, The electrode 15A and the first φ terminal portion 13D of the wiring member 10 are arranged to face each other. Placed (not shown).  In addition, a method of connecting the first connecting portion 16, Using gold bumps or solder balls, The second embodiment (described later) corresponding to the BGA package can also be used.  According to Figure 4 below, 5 shows a schematic diagram of a semiconductor device having the wiring member for a semiconductor device described above.  The semiconductor device 30 of FIG. 4, The wiring member 1 for semiconductor devices of Fig. 1 is included. that is, Semiconductor device 30, Has: Lead frame 20, It has a die pad 22; Wiring member 10 for semiconductor device, Placed on the die pad 22 of the lead frame 20 by 17-201027699, Electrically connected to the lead frame 20; And the semiconductor wafer 15, The semiconductor wafer mounting portion 11A is placed on the wiring member 10 for a semiconductor device, There is an electrode 15A.  among them, A plurality of conductive inner lead portions 21 are formed on the upper surface of the lead frame 20, Bonding the second connecting portions 19 formed by the wires, It is used to electrically connect each of the second terminal portions 13E of the copper wiring layer 13 and the corresponding inner lead portion 21. In addition, Between the electrode i5A of the semiconductor wafer 15 and the first terminal portion 13D, The first connecting portion 16 is electrically connected. In addition, Yu Lu @ out of one part of the lead frame 20, Making the semiconductor wafer 15, Copper wiring layer 13, Lead frame 20, The first connecting portion 16 and the second connecting portion 19 are resin-sealed by the resin sealing portion 23.  In addition, The semiconductor device 30 of FIG. 5, The wiring member 10 for a semiconductor device of Fig. 3 is included. that is, Semiconductor device 30, Has: Lead frame 20; Wiring member for semiconductor device 1〇, Being placed in the center of the lead frame 20, Electrically connected to the lead frame 20; And the semiconductor wafer 15,  The semiconductor wafer mounting portion @ 11A is placed on the wiring member 10 for a semiconductor device, There is an electrode 15A.  among them, Each of the second connecting portions 18 formed by the plurality of conductive inner lead portions 21' solder connection portions is formed on the lower surface of the lead frame 20. It is used to electrically connect each of the second terminal portions 13E of the copper wiring layer 13 and the corresponding inner lead portion 21. In addition, The electrode 15A on the semiconductor wafer 15 and the second terminal portion 13D are electrically connected by the i-th connection portion 16. In addition, In a state where one part of the lead frame 20 is exposed (referred to as an outer lead portion),  Making the semiconductor wafer 15, Copper wiring layer 13, Lead frame 20, First connection -18- 201027699 The portion 16 and the second connecting portion 18 are resin-sealed by the resin sealing portion 23.  In Figure 4, 5 instructions will be shown in Figure 1. The example in which the wiring member for semiconductor device 1 is mounted on the lead frame 20 is shown in FIG. But not limited to this, For example, the wiring member 10 or the semiconductor device shown in Fig. 12 (described later), A thin-type semiconductor device is built in a build-up board.  The action of the embodiment formed by the above configuration will be described below.  0 First, A method of manufacturing the wiring member 10 for a semiconductor device described above will be described with reference to Figs. 6(a) through 6(d).  First of all, A metal substrate 12 made of stainless steel is prepared (Fig. 6 (a)). after that, An insulating layer 11 made of polyimide is laminated on the metal substrate 12 (Fig. 6(b)).  after that, A copper layer 13A is formed on the insulating layer 11 by an addition method or an etching method (Fig. 6(c)). after that, By electrolytic plating or electroless plating,  A plating layer 13B composed of, for example, a nickel (Ni) plating layer and a gold (Au) plating layer φ is formed on the copper layer 13A. Thus, the copper wiring layer 13 composed of the copper layer 13A and the plating layer 13B is formed (Fig. 6 (d)). at this time, At the same time, the first terminal portion 13D of the copper wiring layer 13 is formed, The second terminal portion 13E and the wiring portion 1 3 C. So, Can be made with an insulating layer 1 1 The wiring member 10 for a semiconductor device of the metal substrate 1 2 and the copper wiring layer 13 is used.  then, A method of manufacturing a semiconductor device (Fig. 4) including a wiring member for a wire-connecting type semiconductor device will be described with reference to Figs. 7(a) to (f).  First of all, The wiring member for semiconductor device 1A is manufactured by the above-described process shown in Figs. 6(a) to 6(d) (Fig. 7(a)). after that, The semiconductor wafer 19-201027699 15 is placed via the adhesive layer 14, While being fixed to the semiconductor wafer mounting portion 11A of the wiring member 10 for a semiconductor device (Fig. 7(b)), By the first connecting portion 16 formed by the bonding wires, The connection between each electrode 15A of the semiconductor wafer 15 and each of the first terminal portions 13D of the copper wiring layer 13 is performed (Fig. 7(c)).  after that, A lead frame 20 having an inner lead portion 21 and a die pad 22 is prepared, The wiring harness 22 for a semiconductor device is placed on the die pad 22 of the lead frame 20 (Fig. 7(d)).  @ after that, a second connecting portion 19 formed by joining wires,  The connection between each of the second terminal portions 13E of the copper wiring layer 13 and the inner lead portions 21 of the corresponding lead frames 20 is performed (Fig. 7(e)). after that, In a state where one part of the lead frame 20 (outer lead portion) is exposed, The wiring member 10 for the semiconductor device is used, Semiconductor wafer 15, The first connecting portion 16,  Die pad 22, The second connecting portion 19 and the inner lead portion 21 are resin-sealed by the resin sealing portion 23, The semiconductor device 30 shown in Fig. 4 is formed (Fig. 7(f)).  ◎ Next, A modification of the method of manufacturing a semiconductor device (Fig. 4) including a wiring member for a wire-bonding type semiconductor device will be described with reference to Figs. 14(a) through 14(f).  First of all, The wiring member 1a for a semiconductor device is manufactured by the above-described process shown in Figs. 6(a) to 6(d) (Fig. 14(a)). after that, A lead frame 20 having an inner lead portion 21 and a die pad 22 is prepared, The wiring member 10 for a semiconductor device is placed on the die pad 22 of the lead frame 20 (Fig. 14 (b)).  After -20- 201027699, The semiconductor wafer 15 is placed via the adhesive layer 14, While being fixed to the semiconductor wafer mounting portion 11A of the semiconductor device wiring member 10 (Fig. 14 (c)), By bonding the first connecting portion 16 formed by the wire, The connection between each electrode 15A of the semiconductor wafer 15 and each of the first terminal portions 13D of the copper wiring layer 13 is performed (Fig. 14 (d)).  after that, a second connecting portion 19 formed by joining wires,  The connection between each of the second terminal portions 13E of the copper wiring layer 13 and the inner lead portions 21 of the corresponding lead frames φ 20 is performed (Fig. 7(e)). after that, In a state where one part of the lead frame 20 (outer lead portion) is exposed, The wiring member 10 for the semiconductor device is used, Semiconductor wafer 15, The first connecting portion 16,  Die pad 22, The second connecting portion 19 and the inner lead portion 21 are sealed by the sealing resin portion 23, The semiconductor device 30 shown in FIG. 4 is obtained (FIG. 14(f)). A method of manufacturing a semiconductor device (Fig. 5) including a wiring member for a solder-connected semiconductor device will be described with reference to Figs. 8(a) through 8(f).  φ First, The wiring member for semiconductor device 1A is manufactured by the above-described process shown in Figs. 6(a) to 6(d) (Fig. 8(a)). after that, The semiconductor wafer 15 is placed via the adhesive layer 14, While being fixed to the semiconductor wafer mounting portion 11A of the wiring member 10 for a semiconductor device (Fig. 8(b)), By the first connecting portion 16 formed by the bonding wires, The connection between each electrode 15A of the semiconductor wafer 15 and each of the first terminal portions 13D of the copper wiring layer 13 is performed (Fig. 8(c)).  Thereafter, on each of the second terminal portions 13E of the copper wiring layer 13, The second portion - 21 - 201027699 connecting portion 18 (Fig. 8 (d)) for the lead frame 20 formed of the solder joint portion (tin ball) is separately provided.  After 'preparing the lead frame 20, The connection between each of the second connecting portions 18 and the inner lead portion 21 of the corresponding lead frame 20 is performed (Fig. 8(e)). after that, In a state where one part of the lead frame 20 (outer lead portion) is exposed, The wiring member 10 for a semiconductor device is used, Semiconductor wafer 15, The first connecting portion 16, The second connecting portion 18, And the inner lead portion 21 is sealed by the sealing resin portion 23, The semiconductor device 30 shown in Fig. 5 is formed (Fig. 8(f)).  Wei, then A modification of the method of manufacturing a semiconductor device (Fig. 5) including a wiring member for a solder-connected semiconductor device will be described with reference to Figs. 15(a) through 15(f).  First, the wiring member 10 for a semiconductor device is manufactured by the above-described process shown in Figs. 6(a) to 6(d) (Fig. 15(a)). after that, On each of the second terminal portions 13E of the copper wiring layer 13 of the wiring member 10 for a semiconductor device, The second connecting portion 18 for the lead frame 20 composed of the solder joint portion (tin ball) is separately provided (Fig. 15 (b)). after that, Preparing the lead frame 20, The connection between each of the second connecting portions 18 and the inner lead portion 21 of the corresponding lead frame 20 is performed (Fig. 15 (c)).  after that, The semiconductor wafer 15 is placed via the adhesive layer 14, While being fixed to the semiconductor wafer mounting portion 11A of the semiconductor device wiring member 10 (Fig. 15 (d)), By bonding the ith connection 16 formed by the wires, The connection between each electrode 15A of the semiconductor wafer 15 and each of the first terminal portions 13D of the copper wiring layer 13 is performed (Fig. 15(e)).  after that, In a state in which a portion (outer lead portion) of the lead frame 20 is exposed, in the state of -22-201027699, the wiring member 10 for a semiconductor device is used. Semiconductor wafer 15,  The first connecting portion 10, The second connecting portion 18 and the inner lead portion 21 are sealed by the sealing resin portion 23, The semiconductor device 3A shown in Fig. 5 is obtained (Fig. 15(f)).  As explained above, According to this embodiment, A small semiconductor wafer 15 which is finer than the conventional one can be mounted on the lead frame 2A. That is, The distance between the lead portions 21 in the lead frame 20 is wide (e.g., φ 13 (^m) '. The distance between the electrodes 15A of the semiconductor wafer 15 is narrow (e.g., 40 μm). Even in this case, According to this embodiment, The respective electrodes 15A of the semiconductor wafer 15 and the respective terminal portions 13D of the copper wiring layer 13 can be connected by the first connecting portion 16, Between the second terminal portion 13E of the copper wiring layer 13 and the inner lead portion 21 of the lead frame 20, By means of the second connecting portion 18, 19 to connect, Therefore, the semiconductor wafer 15 can be surely electrically connected to the lead frame 20.  In contrast, As a comparative example, It is also conceivable to connect the electrode 15A of the semiconductor wafer 15 and the inner lead portion 21 of the lead frame 20 directly by the gold bonding φ line. but, In this case, The length of the gold bond wire is relatively long, Manufacturing costs have risen. relatively, According to this embodiment, The first connecting portion 16 and the second connecting portion 18, There is a copper wiring layer 13 between 19, Therefore, And comparing the case where the electrode 15A of the semiconductor wafer 15 and the inner lead portion 21 of the lead frame 20 are directly joined by a gold bonding wire (the above comparative example), The manufacturing cost of the semiconductor device 30 can be reduced.  In addition, According to this embodiment, Before the semiconductor device 30 is packaged, The semiconductor wafer 15 can be mounted under the state of the semiconductor device wiring member 10 or the state -23-201027699.  In addition, according to the embodiment, The metal substrate 12 is formed of stainless steel. It is more rigid than the substrate formed by polyimine. Easy to handle, And the thickness can be thinner. In addition, Heat from the semiconductor wafer 15 can be dissipated by the back side of the metal substrate 12.  Other configurations of the wiring member 1 for semiconductor devices will be described below with reference to Figs. 9-11 (Modification 2-4). In Figure 9-11, The same portions as those of the wiring member 10 for a semiconductor device shown in Figs. 1-3 are denoted by the same reference numerals, and the detailed description is omitted.  In Fig. 9 (Modification 2), The copper wiring layer 13 has: Power terminal block block 13F, The plurality of power terminal electrodes 15A electrically connected to the semiconductor wafer 15 via the first connecting portion 16;  GND (ground) terminal block section 13G, a plurality of ground terminal electrodes 15A electrically connected to the semiconductor wafer 15 via the first connecting portion 16; a first terminal portion 13D to which the other first connecting portions 16 are connected; The second terminal portion 13E of the parallelogram that is connected to the second connecting portion 19 is provided. In addition, Between the first terminal portion 13D and the second terminal portion 13E, Between the power terminal block portion 13F and the second terminal portion 13E, And between the GND (ground) terminal block portion 13G and the second terminal portion 13E, The wiring portion 13C is present separately.  In Figure 1 (Modification 3), The copper wiring layer 13 has: Power terminal block portion 13F, a plurality of power terminal electrodes 15A electrically connected to the semiconductor wafer 15 via the first connecting portion 16; GND (ground) terminal block 13G, a plurality of ground terminal electrodes 15A electrically connected to the semiconductor wafer 15 via the first connecting portion 16; The other first connecting portion 16 is respectively -24-201027699 connected first terminal portion 13D; The second terminal portion 13E having a circular shape in which the second connecting portion 18 is connected. Further, between the first terminal portion 13D and the second terminal portion 13E, Between the power terminal block portion 13F and the second terminal portion 13E, And between the GND (ground) terminal block portion 13G and the second terminal portion 13E, The wiring portion 13C is present separately. In addition, In Figure 10 (Modification 3), The wiring (wiring portion 13C) connected to the second terminal portion 13E, Lead line, To prevent solder flow during solder ball installation, And φ is formed as a wiring of a crank shape, Lead line.  As shown in Figure 9, 10, The power terminal block portion 13F and the GND (ground) terminal block portion 13G are provided, The power terminal and the ground terminal of the electrode 15A are respectively integrated and electrically connected. So, The second connection portion 18 can be reduced. The number of 1 9 .  In Fig. 11 (Modification 4), Wiring member 10 for semiconductor device,  It is placed on the divided die pad 20A which is slightly larger than the wiring member 10 for semiconductor devices. In addition, The copper wiring layer 13 has: And the power terminal block section φ 13F, a plurality of power terminal electrodes 15A electrically connected to the semiconductor wafer 15 via the first connecting portion 16;  GND (ground) terminal block section 13G. The divided die pad 20A is configured as a GND block. The die pad 20A and the GND (ground) terminal block portion 13G are connected by the second connection portion 19 .  In Figure 11, The power terminal block portion 13F and the GND (ground) terminal block portion 13G are set, The power terminal and the ground terminal of the electrode 15A are respectively integrated and electrically connected. and, The divided die pad 20A is connected to the GND (ground) terminal block portion 13G by the second connecting portion 19, 25-201027699, So, It is possible to reduce the number of second connection portions 169 in the entire semiconductor device.  In Figure 9-11 (Modification 2-4), Providing a die pad composed of a copper wiring layer larger than the size of the semiconductor wafer 15, The semiconductor wafer 15 may be mounted on the die pad via an insulating film (or paste). In this case, A die pad composed of a copper wiring layer is formed as a GND (ground) layer, The electrode 15A of the semiconductor wafer 15 and the crystal pad are connected by wires, So, It is possible to reduce the total number of terminals in the entire semiconductor device.  (Second embodiment) Hereinafter, A second embodiment of the present invention will be described with reference to Figs. 12 and 13(a) through (e).  Figure 12 is a schematic cross-sectional view showing a second embodiment of the present invention. Fig. 13 (a) - (e) are diagrams showing a method of manufacturing a package type semiconductor device. The difference between the second embodiment shown in Fig. 12 and Fig. 13 (a) - (e) is that  φ The second connecting portion is exposed to the outside by the sealing resin portion. The other configurations are roughly the same as those of the first embodiment described above. In Figure 12 and Figure 13(a) - (e), The same reference numerals are attached to the same portions as those in the first embodiment shown in Figs. 1-11. And a little detailed explanation.  As shown in Figure 12, The package type semiconductor device 40 of the present embodiment,  The system has: The wiring member for semiconductor device 1〇; The semiconductor wafer mounting portion 11 of the semiconductor device wiring member 10 is placed on the adhesive layer I4. A semiconductor wafer 15 having a plurality of electrodes 15 turns.  -26- 201027699 between the electrode 15A of the semiconductor wafer 15 and the first terminal portion 13D of the copper wiring layer 13, The first connecting portions 16 formed by gold bonding wires are connected.  In addition, Each of the second terminal portions 13E of the copper wiring layer 13 is provided, The second connection portion 24 for external connection constituted by the solder connection portion.  As shown in Figure 12, The second connecting portion 24, It is composed of two segments of solder ball layer. However, as long as the height of the second connecting portion 24 can be set to be a certain level or more, Then φ is not limited to this configuration.  Copper wiring layer 13, The semiconductor wafer 15 and the first connecting portion 16 are sealed by the sealing resin portion 23. In addition, The second connecting portion 24 is exposed to the outside by the sealing resin portion 23. The second connecting portion 24 is exposed to a portion other than the sealing resin portion 23, For example, it is connected to a conductive member of an external machine, So, It is possible to electrically connect the semiconductor wafer 15 to an external machine.  The metal substrate 12 can use various metals. However, the metal substrate 12 is preferably made of φ stainless steel. The metal substrate 12 is made of stainless steel, The rigidity of the metal substrate 12 can be improved, The thickness of the metal substrate 12 is thinned. In addition, The heat of the semiconductor wafer 15 can be dissipated by the back surface of the metal substrate 12.  then, A method of manufacturing the package type semiconductor device 40 shown in Fig. 12 will be described with reference to Figs. 13(a) through (e).  First of all, The wiring member 10 for a semiconductor device is manufactured by the process shown in Figs. 6(a) to 6(d) (Fig. 13(a)). after that, The semiconductor wafer 15 is placed via the adhesive layer 14, It is fixed to the semiconductor wafer mounting portion 11A of the semiconductor device wiring member 1A (Fig. 13(b)). Thereafter, the first connecting portion 16 formed by bonding wires -27-201027699, The connection between each electrode 15A of the semiconductor wafer 15 and each of the first terminal portions 13D of the copper wiring layer 13 is performed (Fig. 13 (c)).  Thereafter, on each of the second terminal portions 13E of the copper wiring layer 13, The second connection portion 24 (solder ball) for external connection is separately provided (Fig. 13 (d)). After that, the copper wiring layer 13, The semiconductor wafer 15 and the first connecting portion 16 are sealed by the sealing resin portion 23, The semiconductor device 40 shown in Fig. 12 is formed (Fig. 13(e)).  As explained above, According to this embodiment, The conventional smaller semiconductor wafer 15 can be connected to an external machine. that is, According to this embodiment,  The connection between each electrode 15A of the semiconductor wafer 15 and the first terminal portion 13D of the copper wiring layer 13 is performed by the first connection portion 16 On each of the second terminal portions 13E of the copper wiring layer 13, The second connecting portion 24 for external connection is formed by the solder connecting portion. So, Even if the distance between the conductive members of the external machine is relatively wide, In the case where the distance between the electrodes 1 5 A of the semiconductor wafer 15 is relatively narrow (for example, 40 μm), The connection between the semiconductor wafer 15 and an external device can also be confirmed.  In addition, According to this embodiment, A copper wiring layer 13 exists between the first connecting portion 16 and the second connecting portion 24, therefore, And directly connecting the electrode 15A of the semiconductor wafer 15 to the second connecting portion 24 by a gold bonding wire, The manufacturing cost of the semiconductor device 40 can be reduced.  In addition, According to this embodiment, The metal substrate 12 is formed of a stainless steel and is more rigid than a substrate formed of polyimide. Easy to handle' and thinner. In addition, From the semiconductor wafer 15, -28-201027699 heat can be dissipated from the back side of the metal substrate 12.  Figure 6, Figure 9, Figure 9, Fig. 20 (described later) shows the wiring member 10 for a semiconductor device, Or the semiconductor device 40 shown in FIG. 12, It is individually cut away by a cutter under a multi-faceted state (not shown). but, Since the metal substrate 12 is formed of stainless steel, It is more difficult to cut a semiconductor device. This can be done by half etching or full uranium engraving. A cutting line portion having a wider blade edge is formed in advance on the metal substrate 12, To improve cutting efficiency.  φ is in each of the above embodiments, Not on the side of the copper wiring layer 13 of the insulating layer 11, On the other hand, the semiconductor wafer mounting portion 11A may be formed on the copper wiring layer 13. In this case, The semiconductor wafer 15 is placed on the semiconductor wafer mounting portion 11A via an insulating film (or paste).  (Third Embodiment) A third embodiment of the present invention will be described below with reference to Figs.  Fig. 16 is a schematic cross-sectional view showing a wiring structure of a semiconductor device according to a third embodiment of the present invention. Fig. 17 is a schematic cross-sectional view showing a composite wiring member for a semiconductor device according to a third embodiment of the present invention. Fig. 18 is a schematic cross-sectional view showing a modification of the wiring member for a semiconductor device according to the third embodiment of the present invention. Fig. 19 is a schematic cross-sectional view showing a semiconductor device according to a third embodiment of the present invention. (a) to (d) of FIG. 20 are diagrams showing a method of manufacturing a wiring member for a semiconductor device according to a third embodiment of the present invention. 21(a) to (f) are diagrams showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention. Figure 16-21, The same portions as those in the first embodiment shown in Fig. 1-1 are denoted by the same reference numerals.  -29- 201027699 First of all, The outline of the wiring member for a semiconductor device of the present embodiment will be described with reference to Fig. 16 . Again, in Figure 16, For the sake of convenience, the portion constituting the wiring member for a semiconductor device is represented by an imaginary line (two-dotted line).  As shown in Figure 16, The wiring member 1 for a wire-bonding type semiconductor device according to the present embodiment, The system has: For example, an insulating layer formed of polyimine; a metal substrate 12 disposed on one side of the insulating layer 11; And a copper wiring layer 13 disposed on the other side of the insulating layer 11. among them, Copper wiring layer 13, The system contains: a plurality of first terminal portions 13D, Electrodes 15A are electrically connected to the semiconductor wafer 15 respectively: a plurality of second terminal portions 13E, They are electrically connected to the inner lead portion 21 (external wiring member): And a plurality of wiring parts 13C, The first terminal portion 13D and the second terminal portion 13E are electrically connected, respectively.  The metal substrate 12 can use various metals. However, the metal substrate 12 is preferably made of stainless steel. The metal substrate 12 is made of stainless steel, The rigidity of the metal substrate 12 can be improved, The thickness of the metal substrate 12 is thinned.  A semiconductor wafer mounting portion 31 is formed on the copper wiring layer 13. On the half of the conductor wafer mounting portion 31, A semiconductor wafer 15 having a plurality of electrodes 15A disposed therearound may be placed. In this case, Semiconductor wafer 15, Is placed by the adhesive layer 14, It is fixed to the semiconductor wafer mounting portion 31. Between each electrode 15A of the semiconductor wafer 15 and each of the first terminal portions 13D of the copper wiring layer 13, The first connecting portions 16 formed by gold (Au) bonding wires can be connected.  In addition, Between each of the second terminal portions 13E of the copper wiring layer 13 and each of the inner lead portions 21 of the lead frame 20, The second connection portion 19 is connected to the electrical connection -30-201027699.  The semiconductor wiring member of this embodiment will be described below with reference to Fig. 17 . also, In Figure 17, For the sake of convenience, the imaginary line is formed outside the portion constituting the semi-composite wiring member (the dotted line at 2 dots is as shown in Fig. 17 The composite wiring member for a semiconductor device is composed of the following: The wiring member 10 for a semiconductor device described above;  The lead frame 20 of the wiring member 10 for a semiconductor device; A portion 19 for electrically connecting the second terminal portion 13E of the copper φ and the lead frame 20. The composite wiring member 10A for a semiconductor device, The electrode 15A of the semiconductor wafer 15 and the external wiring substrate are connected.  among them, The lead frame 20 has: a die pad 22 on which the semiconductor device 1 is mounted; And located outside the die pad 22 . also, A silver plating layer or an inner lead portion 21 (an external wiring member) of palladium (Pd) is provided on the lead portion 25.  #又, Die pad 22, Has: Central area 22a,  Semiconductor wafer 15; And the peripheral area 22b, Located in the central area of the week, It has substantially the same thickness as the lead portion 25. A slit hole 26 is provided between the central portion 22a and the peripheral portion 22b of the crystal grain, As explained later, The gas generated by the bonding agent for bonding the lead frame 20 of the semiconductor device wiring structure is arranged.  also, At least the central portion 22a of the die pad 22 is formed to be thinner by a method such as scribing. that is, The thickness of the central portion 22a is indicated by a composite conductor device.  10A, It is electrically connected to the wiring layer 13 and the second connection is used for electrical connection. (not shown). The lead portion of the wiring structure is plated. It is used to mount the P pad 22 other than 22a. The seam yak 1 〇 and the outer side are formed by the semi-uranium degree -31 - 201027699 which is thinner than the thickness of the lead portion 25 and the peripheral portion 2 2b. So, The semiconductor device 30 on which the semiconductor wafer 15 is mounted can be made thin.  In addition, The second connecting portion 19 is formed of a gold bonding wire. One of the ends is connected to the corresponding second terminal portion 13E, The other end is connected to the lead portion 21 inside the lead frame 20.  but, As shown in the modification of Fig. 18, While the respective electrodes 15A of the semiconductor wafer 15 are directed toward the copper wiring layer 13 side, The first connection portion 16A formed by bumps or solder balls may be connected to each other between the respective electrodes 15A of the semiconductor wafer 15 and the first terminal portions 13D of the copper wiring layer 13 (flip-chip bonding).  A description will be given of a semiconductor device including the above-described wiring member for a semiconductor device and a composite wiring member for a semiconductor device.  The semiconductor device 30 of FIG. 19, The wiring member 10 for a semiconductor device of Fig. 1 and the composite wiring member 10A for a semiconductor device of Fig. 17 are included.  that is, Semiconductor device 30, Has: Lead frame 20, It has a crystal pad 22; Wiring member 10 for semiconductor device, Placed on the die pad 22 of the lead frame 20, Electrically connected to the lead frame 20; The semiconductor wafer 15' is placed on the semiconductor wafer mounting portion 31 of the semiconductor device wiring member 1A, There is an electrode 15A.  Here, a plurality of conductive inner lead portions 21 are formed on the upper surface of the lead frame 20. Bonding the second connecting portions 19 formed by the wires, It is used to electrically connect each of the second terminal portions 13E of the copper wiring layer 13 and the corresponding inner lead portion 21. In addition, The first connection portion 16 formed by the bonding wires between the electrode 15A on the semiconductor wafer 15 and the first terminal portion 13D is electrically connected to 201027699. In addition, In a state where a part of the lead portion 25 of the lead frame 20 is exposed, Making the semiconductor wafer 15, Copper wiring layer 13, Lead frame 20,  The first connecting portion 16 and the second connecting portion 19 are resin-sealed by the resin sealing portion 23.  In addition, The structure of the die pad 22 is the same as that described in FIG. Therefore, the description is omitted.  also, In Figure 19, The length from the bottom surface of the die pad 22 to the lower φ surface of the sealing resin portion 23, And the length H2 of the wiring member 10 for semiconductor device to the upper surface of the sealing resin portion 23, The system is roughly the same length. So, In the moisture absorption test (reflow test), it is possible to prevent the semiconductor device 30 from being bent or cracked (as will be described later).  The action of the embodiment formed by the above configuration will be described below.  First of all, A method of manufacturing the wiring member 1 半导体 (Fig. 16) for a semiconductor device of the present embodiment will be described with reference to Figs. 20(a) to (d).  First of all, Prepare a metal substrate 12 made of stainless steel (Fig. 20 • (a)). after that, An insulating layer 11 made of polyimide is laminated on the metal substrate 12 (Fig. 20(b)).  after that, The copper layer 13A is formed on the insulating layer 11 by an additive method or a uranium engraving method (Fig. 20(c)). after that, By electrolytic plating or electroless plating, A plating layer 13B composed of, for example, a nickel (Ni) plating layer and a gold (Au) plating layer is formed on the copper layer 13A. Thus, the copper wiring layer 13 composed of the copper layer 13A and the plating layer 13B is formed (Fig. 20 (d)). at this time, At the same time, the first terminal portion 13D of the copper wiring layer 13 is formed, The second terminal portion 13E and the wiring portion 13C» are such that Can be made with an insulating layer 11, Metal substrate 12 and -33 - 201027699 The wiring member 10 for a semiconductor device of the copper wiring layer 13. In addition, A semiconductor wafer mounting portion 31 is formed on the copper wiring layer 13.  then, A method of manufacturing the semiconductor device (Fig. 19) of the present embodiment will be described with reference to Figs. 21(a) through 21(f).  First of all, The semiconductor device wiring member 1A is manufactured by the above-described construction shown in Figs. 20(a) - (d) (Fig. 21 (a)). after that, A lead frame 20 having an inner lead portion 21 and a die pad 22 is prepared, The wiring member 10 for a semiconductor device is placed on the die pad 22 of the lead frame 20 (Fig. 21 (b)). at this time, Wiring member 10 for semiconductor device, It is bonded to the die pad 22 using an adhesive. In this case, The surface of the wiring member 10 for a semiconductor device is formed to be flat. therefore, The wiring member 10 for a semiconductor device can uniformly press the die pad 22 in the plane. So, After bonding, A gap does not occur between the wiring member 10 for a semiconductor device and the die pad 22.  after that, The semiconductor wafer 15 is placed via the adhesive layer 14, While being attached to the semiconductor wafer mounting portion 31 of the semiconductor device wiring member 10 (Fig. 21 (c)), By bonding the ith connection 16 formed by the wires, The connection between each electrode 15A of the semiconductor wafer 15 and each of the first terminal portions 13D of the copper wiring layer 13 is performed (Fig. 21 (d)).  after that, a second connecting portion 19 formed by joining wires,  The connection between each of the second terminal portions 13E of the copper wiring layer 13 and the inner lead portions 21 of the corresponding lead frames 20 is performed (Fig. 21 (e)). after that, In a state where one part of the lead frame 20 (outer lead portion) is exposed, The wiring member 10 for the semiconductor device is used, Semiconductor wafer 15, The first connection -34- 201027699 16, Die pad 22, The second connecting portion 19 and the inner lead portion 21 are resin-sealed by the resin sealing portion 23, The semiconductor device 30 shown in Fig. 19 is formed (Fig. 21 (f)).  but, When the resin sealing of the sealing resin portion 23 is performed, The wiring member for the semiconductor device 1 and the die pad 22 are heated at approximately 180 °C. at this time, The bonding member for bonding the semiconductor device wiring member 1 and the die pad 22 is also heated. It is therefore possible to produce an organic gas from the binder. In addition, the water absorbed by the Φ adhesive is also heated to generate water vapor. Therefore, in the present embodiment, A slit hole 26 is disposed between the central region 22a of the die pad 22 and the peripheral region 22b. After the semiconductor device wiring member 10 or the semiconductor wafer 15 is mounted and fixed, or the sealing resin portion 23 is cured, The gas (organic gas and/or water vapor) generated by the binder is discharged to the outside through the slit hole 26. It does not remain in the sealing resin portion 23.  In addition, When the slit hole 26 is not provided, The gas (organic gas and/or water vapor) remains in the vicinity of the die pad 22 and the wiring member for the semiconductor device ® 1 ,. In this state, the sealing resin portion 23 is cured. So, The result of the moisture absorption test (reflow soldering test) is performed on the completed semiconductor device 30, It was found that there was swelling in the residual part of the gas. It is possible to cause cracks. In contrast, According to this embodiment, By providing the slit hole 26 in the die pad 22, The gas from the adhesive can be discharged to the outside,  When the moisture absorption test (reflow test) The semiconductor device 30 does not cause cracks.  As explained above, According to this embodiment, A small semiconductor wafer 15 which is finer than a conventional one can be mounted on the lead frame 20. -35- 201027699 That is, even in the case where the distance between the lead portions 2 i in the lead frame 2 is wide (for example, 130 μm), the distance between the electrodes 15A of the semiconductor wafer 15 is narrow (for example, 40 μm), The semiconductor wafer 15 can also be electrically connected to the inner lead portion 21 of the lead frame 20.  Further, according to the embodiment, The thickness of the central portion 22a in which at least the semiconductor wafer 15 is placed in the die pad 22 is formed to be thinner than the thickness of the lead portion 25. therefore, The semiconductor device 30 can be made thin.  Further, according to the embodiment, A slit hole 26 is provided between the central region Q 22a of the die pad 22 and the peripheral region 22b. The gas generated by the bonding agent for bonding the wiring member 10 for the semiconductor device and the lead frame 20 can be discharged to the outside by the slit hole 26. therefore, It is possible to prevent cracks in the semiconductor device 30 at the time of the moisture absorption test (reflow test).  also, According to this embodiment, The length from the bottom surface of the die pad 22 to the lower side of the sealing resin portion 23, The length from the copper wiring layer 13 of the wiring member for semiconductor device 1 to the upper surface of the sealing resin portion 23, Set to roughly the same length. that is, The volume of the sealing resin portion 23, The surface side and the back side of the semiconductor device 30 are substantially the same. result, When the moisture absorption test (reflow test) The sealing resin portion 23 is uniformly expanded on the front side and the back side. It is possible to prevent the semiconductor device 30 from being bent or cracked.  also, According to this embodiment, A copper wiring layer 13 exists between the first connecting portion 16 and the second connecting portion 18, therefore, And directly connecting the electrode 15A of the semiconductor wafer 15 to the inner lead portion 21 of the lead frame 20 by a gold bonding wire, The manufacturing cost of the semiconductor device 30 can be reduced.  -36- 201027699 Also, According to this embodiment, The metal substrate 12 is formed of stainless steel. It is more rigid and easier to handle than the substrate formed from polyimine. And the thickness can be thinner.  (Fourth embodiment) Hereinafter, A fourth embodiment of the present invention will be described with reference to Figs. 22-25.  Fig. 22 is a cross-sectional view showing the semiconductor device of the fourth embodiment of the present invention. Fig. 23 is a plan view showing a wiring member for a semiconductor device used in a semiconductor device according to a fourth embodiment of the present invention. Figs. 24(a) to (e) are diagrams showing a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. Figure 25 is a schematic cross-sectional view showing a modification of the semiconductor device according to the fourth embodiment of the present invention. The difference in the configuration of the fourth embodiment of Figs. 22-2 is that the second connecting portion 2 7A, 27B, The copper wiring layer 13 and the semiconductor wafer mounting portion 31 are configured, The other configuration is substantially the same as that of the second embodiment described above. In Figure 22_25, The same as in the second embodiment shown in Fig. 12 and Figs. 13(a) through 13(a), the same reference numerals will be given to the same parts, and the detailed description will be omitted.  As shown in Figure 22, The package type semiconductor device of the present embodiment 4〇,  The wiring member 10 for a semiconductor device described above is provided; And semiconductor wafer 15, The adhesive layer 14 is placed on the semiconductor wafer mounting portion 31 formed on the copper wiring layer 13 of the semiconductor device wiring member 1A.  A plurality of electrodes 15A.  Wiring member 10 for semiconductor device, The system has: Insulation layer U. A metal substrate 12 made of stainless steel and a copper wiring layer 13 are added. The copper wiring layer 13 includes a plurality of first terminal portions UD electrically connected to the electrodes 15A of the semiconductor wafer 15 by -37-201027699, a plurality of second terminal portions 13E for external connection, and a wiring portion 13C. The first terminal portion 13D and the second terminal portion 13E are electrically connected to each other. Further, each of the electrodes 15A of the semiconductor wafer 15 and each of the first terminal portions 13D of the copper wiring layer 13 are connected by a first connecting portion 16 formed of a gold bonding wire. Further, second connection portions 27A and Q27B for external connection including a solder connection portion are provided on each of the second terminal portions 13E of the copper wiring layer 13. Each of the second connecting portions 27A and 27B is made of a solder ball. As shown in FIG. 22, among the second connection portions 2A and 27B, the second connection portion close to the semiconductor wafer 15 (first terminal portion 13D) is indicated by reference numeral 27A, and is away from the semiconductor wafer 15 (first terminal portion 13D). The second connecting portion is indicated by reference numeral 27B. The copper wiring layer 13, the semiconductor wafer 15, and the first connecting portion 16 are sealed by the sealing resin portion 23. In this case, the top portions of the second connecting portions 27A and 27B are exposed to the outside by the sealing resin portion 23. The second portion of the second connecting portion 27A and 27B is exposed to the outside of the sealing resin portion 23, and is electrically connected to, for example, an electrically conductive member of an external device. Thus, the semiconductor wafer 15 and the external device can be electrically connected. . Various metals can be used for the metal substrate 12, but the metal substrate 12 is preferably made of stainless steel. By the fact that the metal substrate 12 is made of stainless steel, the rigidity of the metal substrate 12 can be increased, and the thickness of the metal substrate 12 can be thinned. Further, the heat of the semiconductor wafer 15 can be dissipated by the back surface of the metal substrate 12. Fig. 23 is a plan view showing a wiring member 10 for use in a semiconductor package -38 - 201027699 used in the semiconductor device 40 of the embodiment. As shown in FIG. 23, each of the plurality of second terminal portions 13E of the copper wiring layer 13 has a planar circular shape. Among the plurality of second terminal portions 13E of FIG. 23, the second terminal portion provided at a position close to the first terminal portion 13D is indicated by reference numeral 13Ei, and the second terminal portion provided at a position away from the first terminal portion 13D is Symbol 13 £2 is not shown in Fig. 23. Each of the wiring portions 13C of the copper wiring layer 13 has a crank portion 13H in the middle thereof. In addition, the connection wiring portion 13C' of the second terminal portion El of the first terminal portion 13D and the second terminal portion El (close to the first terminal portion 13D) is bypassed (the peripheral portion 131) so as to surround the second terminal portion E1. As described above, the following effects can be obtained by providing the crank portion 13H and the peripheral portion 131. In other words, when the second connecting portions 27A and 27B are formed by soldering on the second terminal portions Ε and E2, the molten solder flows along the wiring portion 13C. In this case, the solder flowing in the φ is moved away from the first terminal portion 13D by the crank portion 13H and the peripheral portion 131, so that the solder does not reach the first terminal portion 13D. On the other hand, when the crank portion 13H and the peripheral portion 131 are not provided, the flowing solder may reach the first terminal portion 13D. As a result, in the wire bonding process, the first connecting portion 16 (bonding wire) may not be connected to the first terminal portion 13D. Further, as shown in the modification of FIG. 25, the heat dissipation plate 29 may be attached to the back surface of the copper wiring layer 13 via the heat dissipation plate bonding layer 28. In this case, the heat dissipation plate adhesive layer 28 is composed of, for example, a die attachment film, and the through hole B39 is made of, for example, copper. With this configuration, the heat of the semiconductor wafer 15 can be dissipated to the outside through the heat dissipation plate 29, and the heat dissipation characteristics of the semiconductor device 40 can be further improved. Next, a method of manufacturing the package type semiconductor device 40 shown in Fig. 22 will be described with reference to Figs. 24(a) through (e). First, the wiring member 1b for a semiconductor device is manufactured by the process shown in Figs. 20(a) to (d) (Fig. 24(a)). Then, the second connection portions 27A and 27B φ (tin balls) for external connection are respectively provided on the second terminal portions 13E (the second terminal portions 13Ei and the second terminal portions E2) of the copper wiring layer 13 (Fig. 24). (b)). At this time, as described above, the wiring portion 13C is surrounded by the second terminal portion 13A, and the layout is reversed (Fig. 23). When the second connecting portions 27A and 27 are formed as described above, even if the solder flows along the wiring portion 13C, the solder does not reach the first terminal portion 13D. Thereafter, the semiconductor wafer 15 is placed and fixed on the semiconductor wafer mounting portion 31 of the semiconductor device wiring member 10 via the adhesive layer 14 (Fig. 24 (c)). Thereafter, the connection between each electrode 15A of the semiconductor wafer 15 and each of the first terminal portions 13D of the copper wiring layer 13 is performed by the first connection portion 16' formed by bonding wires (Fig. 24 (d)). Thereafter, the copper wiring layer 13, the semiconductor wafer 15, and the first connecting portion 16 are sealed by the sealing resin portion 23 to form the semiconductor device 40 shown in Fig. 22 (Fig. 24(e)). As described above, according to the present embodiment, the semiconductor wafer 15 which is smaller than the conventional one can be connected to an external device. In other words, according to the present embodiment, the connection between the electrodes 15A of the semiconductor wafer 15 and the first terminal portion 13D of the copper wiring layer 13 is performed by the first connecting portion 16, and each of the layers 13 of the copper wiring -40 - 201027699 The second terminal portions 13E are provided with second connection portions 27A and 27B for external connection including solder balls. In this way, even if the distance between the conductive members of the external device is relatively wide, and the distance between the electrodes 1 5 A of the semiconductor wafer 15 is relatively narrow (for example, 40 μm), the semiconductor wafer can be surely performed. 15 connection to external machines. Further, according to the present embodiment, since the copper wiring layer 13 is present between the first connecting portion 16 and the second connecting portions 27A and 27A, the electrode 15 and the second connection of the semiconductor wafer 15 are directly connected by the gold 0 bonding wire. Comparing the case of the parts 2 to 7 and 27, the manufacturing cost of the semiconductor device 40 can be reduced. Further, according to the present embodiment, the metal substrate 12 is formed of stainless steel, and is more rigid and easier to handle than the substrate formed of polyimide, and has a small thickness. Further, heat from the semiconductor wafer 15 can be dissipated by the back surface of the metal substrate 12. φ (Fifth Embodiment) A fifth embodiment of the present invention will be described below with reference to Figs. Fig. 26 is a schematic cross-sectional view showing a wiring member for a semiconductor device. Fig. 27 is a schematic cross-sectional view showing a composite wiring member for a semiconductor device of the embodiment. Fig. 28 is a plan view showing a composite wiring member for a semiconductor device and a semiconductor device of the embodiment. Fig. 29 is a schematic cross-sectional view showing the semiconductor device of the embodiment. Fig. 30 (a) - (f) are views showing a method of manufacturing a semiconductor device of the embodiment. In the fifth embodiment of Fig. 26-30, the same reference numerals as in the first embodiment shown in Fig. 1-1, and the third embodiment shown in Figs. 16-21 are denoted by the same reference numerals, and the detailed description thereof will be omitted. First, the outline of the wiring member for a semiconductor device of the present embodiment will be described with reference to Fig. 26 . Further, Fig. 26 shows a virtual line (two-dotted line) other than the portion constituting the wiring member for a semiconductor device for convenience. As shown in FIG. 26, the wiring member 1' for a wire-bonding type semiconductor device of the present embodiment includes, for example, an insulating layer 11 formed of polyimide, and a metal substrate 12 disposed on one side of the insulating layer 11; The copper wiring layer 13 on the other side of the insulating layer 11. The copper wiring layer 13 includes a plurality of first terminal portions 13D electrically connected to the electrodes 15A of the semiconductor wafer 15, and a plurality of second terminal portions 13E electrically connected to the inner lead portions 21, respectively. (External wiring member); and a plurality of wiring portions 13C for electrically connecting the first terminal portion 13D and the second terminal portion 13E. Various metals can be used for the metal substrate 12, but the metal substrate 12 is preferably made of stainless steel. Since the metal substrate 12 is made of stainless steel, the rigidity of the metal substrate 12 can be improved, and the thickness of the metal substrate 12 can be reduced.半导体 The semiconductor wafer mounting portion 31 is formed on the copper wiring layer 13. On the semiconductor wafer mounting portion 31, a semiconductor wafer 15 having a plurality of electrodes 15A provided around the periphery thereof can be placed. The composite wiring member for a semiconductor device of the present embodiment will be described below with reference to Figs. Further, in Fig. 27, for the sake of convenience, the portion constituting the composite wiring member for a semiconductor device is represented by an imaginary line (two-dotted line). As shown in FIG. 27, the composite wiring member 10A for a semiconductor device, the structure of the semiconductor device wiring member 10, and the lead frame 20 electrically connected to the semiconductor device wiring member 10; the second connection The portion 19' is for electrically connecting the second terminal portion 13E of the copper wiring layer 13 and the lead frame 20. The composite wiring member i〇A for a semiconductor device is used to electrically connect the electrode 15A of the semiconductor wafer 15 and an external wiring substrate (not shown). The lead frame 20 has a φ die pad 22 on which the wiring member for a semiconductor device 1 is placed, and a lead portion 25 which is located outside the die pad 22. Further, the lead portion 25 is provided with an inner lead portion 21 (an external wiring member) made of a silver plating layer or a palladium (Pd) shovel layer. Further, the die pad 22 has a central portion 22c corresponding to the semiconductor wafer 15 and a peripheral portion 22d located outside the central portion 22c, and a sealing resin inflow space 32 is formed between the central portion 22c and the central portion 22c. The central region 22c is connected to the peripheral edge region 22d via a hanging lead 34 disposed at four corners (see Fig. 28). Further, the peripheral region φ 22d is held in the lead frame 2 through the hanging leads 35 disposed at the four corners (see Fig. 28). In addition, the sealing resin inflow space 32 formed between the central region 22c and the peripheral edge region 22d is described later, and the inside thereof is poured into the sealing resin portion 23, and after curing, the adhesion between the sealing resin portion 23 and the lead frame 20 is improved. . In the present embodiment, the wiring member 10 for a semiconductor device is disposed in a region from the central region 22c of the die pad 22 to the peripheral region 22d, that is, as shown in FIG. It covers the entire area of the central portion 22c and the entire -43-201027699 area of the sealing resin inflow space 32, and covers a part of the peripheral area 22d, and is disposed. The wiring member for semiconductor device 1 is attached to the central region 22c and the peripheral region 22d of the die pad 22, and is bonded by the resin paste 33. As shown in FIG. 28, the resin paste 33 is attached to the die pad 22. The central region 22c and the peripheral region 22d are each coated in a plurality of dots. However, the resin paste 33 may be applied linearly in the central region 22c and the peripheral region 22d of the die pad 22 in this manner. As the resin paste 33, for example, a resin paste such as an epoxy resin, an acrylic resin, or a polyimide resin (additional paste @ material) can be used. Further, it is preferable that the plating pad 22 is applied with a plating layer at least in the central region 22c and the peripheral region 22d. Thus, by applying a plating treatment to the die pad 22, fine concavities can be formed on the surface of the die pad 22. Thus, when the resin paste 3 3 is applied, the outflow of the resin paste 3 3 can be suppressed. Further, the rolled copper ' used in the die pad 22 is formed in a groove in a certain direction, and the resin paste 3 3 may flow out along the groove. In response to this, by applying a plating treatment to the surface of the crystal pad 22, the groove can be buried, and the flow of the resin paste 3 3 can be suppressed. Such a plating layer may be, for example, a silver plating layer, a palladium plating layer, a gold plating layer or the like. Although it is not limited to a type, it is preferable to use a silver plating layer in terms of a cost surface. Further, as shown in Fig. 27, the thickness of the die pad 22 is formed to be thinner than the thickness of the lead portion 25. In this manner, the semiconductor device 30 on which the semiconductor wafer 15 is mounted can be made thinner. Further, the second connecting portion 19 is formed of a gold bonded wire. One of the ends is connected to the corresponding second terminal portion 13E, and the other end -44 - 201027699 is connected to the inner lead portion 21 of the lead frame 20. In the following, the semiconductor device having the above-described semiconductor device component and the semiconductor device composite wiring member will be described with reference to Figs. 28 and 29, and the sealing resin portion is omitted for convenience. The semiconductor device 30 of Figs. 28 and 29 includes the wiring member 10 for a semiconductor device of Fig. 26. That is, the semiconductor device 30 has: a wire frame 20' having a die pad 22; and a semiconductor device wiring structure φ 10' placed on the die pad 22 of the lead frame 20, electrically connected to the wire frame 20. In the semiconductor wafer mounting portion 31 of the semiconductor device wiring member 1A, the semiconductor wafer 15 having the electrode 15A is placed thereon, and the semiconductor wafer 15 is placed and fixed on the semiconductor wafer via the adhesive layer 14. The placing portion 3 1 is placed on the mounting portion 31. A plurality of conductive inner leads 21 are formed on the lead frame 20. Each of the second connecting portions 19 formed of the gold bonding wires is used to electrically connect the respective second terminal portions 13E of the copper wiring layer 13 and the corresponding inner leads φ21. Further, the electrode 15A on the semiconductor wafer 15 and the first terminal 13D are electrically connected to each other by a first connecting portion 16 composed of a gold bonding wire. Further, in a state in which one of the lead portions 25 of the lead frame 20 is exposed, the semiconductor wafer 15, the copper wiring layer 13, the lead frame 20, the first connection portion 16, and the second connection portion 19 are applied by a resin sealing portion. Resin sealed. The die pad 22 has a central region 22c' corresponding to the half wafer 15 and a peripheral region 22d which is located at the outer periphery of the central region 22c and is connected to the central region 22c' at the center of the central region 22 Body lead puller TUz.  〇 The connecting portion of the guide portion is divided between the guides 23 and -45 - 201027699 to form a sealing resin inflow space 3 2 . Further, the configuration of the die pad 22 has been described with reference to Figs. 27 and 28, and thus detailed description thereof will be omitted. Further, as shown in Fig. 29, the semiconductor device wiring member 10' is disposed in a region from the central region 22c of the die pad 22 to the peripheral region 22d. The wiring member 10 for a semiconductor device is bonded to the central region 22c and the peripheral region 22d of the die pad 22 by using the resin paste 33. This point has also been described using Figs. 27 and 28, and therefore the detailed description thereof will be omitted. The operation of the embodiment formed by the above configuration will be described below with reference to Figs. 20(a) through (d) and Figs. 30(a) through (f). First, the wiring member 1 for semiconductor device shown in Fig. 26 is formed (Fig. 30 (a)), and the manufacturing method will be described with reference to Figs. 20(a) to (d). Then, the lead frame 20 having the lead portion 25 and the die pad 22 is prepared, and the wiring member 10 for a semiconductor device is placed on the die pad 22 of the lead frame 20 (Fig. 30(b)). Further, it is preferable that at least the central region 22c and the peripheral region 22d of the die pad 22 are subjected to plating treatment in advance. In this case, the semiconductor device wiring member 10 is bonded to the central region 22c and the peripheral region 22d of the die pad 22 by using the resin paste 33. Specifically, the resin paste 33 is applied to, for example, a plurality of dots in the central region 22c and the peripheral region 22d' of the die pad 22. In this case, the resin paste 3 3 may be dropped little by little using a syringe (not shown) or the plurality of dots may be dropped at a time. Further, the resin paste 33 may be applied in a straight line -46 - 201027699. When applying in a straight line, it is only necessary to apply a resin paste by moving the syringe in a straight line. Thereafter, the semiconductor device wiring member 1 is placed on the central region 22c and the peripheral region 22d of the die pad 22. After that, the entire lead frame 20 on which the semiconductor device wiring member 1 is placed is heated to cure the resin paste 33, and the semiconductor device wiring member 10 is fixed to the die pad 22. After φ, the semiconductor wafer 15 is placed and fixed on the semiconductor wafer mounting portion 31 of the semiconductor device wiring member 10 via the adhesive layer 14 (Fig. 30 (c)), and is formed by bonding wires. The first connecting portion 16 connects the electrodes 15A of the semiconductor wafer 15 and the respective first terminal portions 13D of the copper wiring layer 13 (FIG. 30(d)). Thereafter, the second connection portion 19 composed of the bonding wires is connected to each of the second terminal portions 13E of the copper wiring layer 13 and the inner lead portion 21 of the corresponding lead frame 20 (FIG. 30(e)). . After φ, the semiconductor device wiring member 10, the semiconductor wafer 15, the first connection portion 16, the die pad 22, the second connection portion 19, and the inside are exposed in a state where one portion of the lead frame 20 (outer lead portion) is exposed. The lead portion 21 is resin-sealed by the resin sealing portion 23 to form the semiconductor device 30 shown in Fig. 29 (Fig. 30 (f)). At this time, the sealing resin inflow space 32 formed between the central portion 22c and the peripheral portion 22d flows into the sealing resin portion 23 before curing. In this manner, after the sealing resin portion 23 is hardened, the adhesion between the sealing resin portion 23 and the lead frame 20 can be improved. -47-201027699 As described above, when the semiconductor device wiring member 10 is mounted on the die pad 22, when the semiconductor wafer 15 is hardened or baked after mounting, and when the resin is sealed by the sealing resin portion 23, the semiconductor The device wiring member 1 and the die pad 22 are heated at a temperature of about 180 °C. At this time, the adhesive for bonding the semiconductor device wiring member 10 and the die pad 22 is also heated. Therefore, when moisture is contained in the adhesive, the moisture-absorbing water is heated to generate water vapor. On the other hand, in the present embodiment, the semiconductor device wiring member 10 and the die pad 22 are bonded by using the resin paste 33 φ. Such a resin paste 33 generally does not easily generate an organic gas and has low hygroscopicity. Therefore, the gas (organic gas and water vapor) from the resin paste 33 does not easily remain in the sealing resin portion 23. In addition, it is assumed that the sealing resin portion 23 is solidified while the gas remains in the vicinity of the die pad 22 and the semiconductor device wiring member 1 ,, and the moisture absorption test (reflow test) is performed on the semiconductor device 30 after completion. The residual part of the gas may swell, which may cause cracks. On the other hand, according to the present embodiment, as described above, the gas remaining in the sealing resin portion 23 can be reduced by using the resin paste © 33, and the semiconductor device 30 is not cracked when the moisture absorption test (reflow soldering test) is performed. Further, according to the present embodiment, the sealing resin inflow space 32 is formed between the central portion 22c of the die pad 22 and the peripheral edge region 22d, and the adhesion between the sealing resin portion 23 and the lead frame 20 can be improved. Thus, in the moisture absorption test (reflow test), cracks generated in the gap between the lower surface of the die pad 22 and the sealing resin portion 23 can be prevented. As described above, according to the present embodiment, the small semiconductor wafer 15 which is more conventionally finer than -48 - 201027699 (fine) can be mounted on the lead frame 20. That is, even if the distance between the lead portions 21 in the lead frame 20 is wide (for example, 130 μm), and the distance between the electrodes 15A of the semiconductor wafer 15 is narrow (for example, 40 μm), the semiconductor wafer 15 can be surely connected. The lead portion 21 is inside the lead frame 20. Further, according to the present embodiment, the thickness of the central portion 22c and the peripheral portion 22d of the die pad 22 is formed to be thinner than the thickness of the lead portion 25. φ Therefore, the semiconductor device 30 can be made thinner. Further, according to the present embodiment, the wiring member 10 for a semiconductor device is bonded to the central region 22c and the peripheral region 22d of the die pad 22 by using the resin paste 33. Further, a sealing resin inflow space 3 2 is formed between the central portion 22c and the peripheral portion 22d. In this way, in the moisture absorption test (reflow test), cracks in the semiconductor device 30 can be prevented. Further, according to the present embodiment, since the resin paste 33 is applied in a multi-dot or straight shape, the resin paste 33 can be uniformly applied to the central region φ 22c and the peripheral region 22d. Further, according to the present embodiment, the copper wiring layer 13' is present between the first connecting portion 16 and the second connecting portion 18, and thus the electrode 15A of the semiconductor wafer 15 and the lead frame 20 are directly connected by a gold bonding wire. In comparison with the case of the lead portion 21, the manufacturing cost of the semiconductor device 3 can be reduced. Further, according to the present embodiment, the metal substrate 12 is made of stainless steel and is more rigid than the substrate formed of polyacrylonitrile, is easy to handle, and has a small thickness. -49- 201027699 (Effect of the Invention) According to the present invention, the semiconductor wafer and the copper wiring layer are connected by the first connection portion, and the copper wiring layer and the lead frame are connected by the second connection portion. The connection between the inner lead portion ' of the lead frame having a wider pitch and the electrode of the semiconductor chip having a narrower pitch can be surely made. In this way, a semiconductor wafer which is known to be small can be mounted on the lead frame of the semiconductor device. Further, according to the present invention, before the package is mounted on the semiconductor device, the semiconductor wafer can be mounted in a state in which the semiconductor device wiring member or the semiconductor device composite wiring member is mounted. Further, according to the present invention, the copper wiring layer is provided between the first connecting portion and the second connecting portion, and the manufacturing cost can be reduced as compared with the case where the semiconductor wafer and the lead frame are directly connected by the bonding wires. Further, according to the present invention, the metal substrate is formed of stainless steel, and is more rigid, easier to handle, and thinner in thickness than the substrate formed of polyimide. In addition, heat from the semiconductor wafer can be dissipated by the back of the metal substrate ©. Further, according to the present invention, the semiconductor wafer has a terminal block portion electrically connected to a plurality of electrodes on the semiconductor wafer, and among the electrodes of the semiconductor wafer, for example, a power supply terminal can be integrally connected to the terminal block portion. In this way, the second connection portion can be reduced, and the total number of terminals in the semiconductor device can be reduced. In addition, the shape of the packaged semiconductor device can be reduced, and the number of packages in the lead frame can be increased, which can reduce the manufacturing cost of the semiconductor device. In addition, the composite wiring member for a semiconductor device is placed on a divided die pad which is slightly larger than the wiring member of the composite device-50-201027699 for a semiconductor device, and the composite wiring member for a semiconductor device is bonded to the die pad. The divided die pad can be configured as a GND block. In addition, a copper wiring layer is disposed under the semiconductor wafer via an insulating film (or paste) so that the die pad is larger than the size of the semiconductor wafer, and the die pad can be connected as a GND layer via wire bonding. In this case, the total number of terminals in the semiconductor device can be reduced. Φ [Brief Description of the Drawings] Fig. 1 is a schematic cross-sectional view showing a first embodiment of a wiring member (wire-connecting type) for a semiconductor device according to the present invention. Fig. 2 is a schematic plan view showing a first embodiment of the present invention. Fig. 3 is a schematic cross-sectional view showing a modification 1 (solder connection type) of the wiring member for a semiconductor device according to the first embodiment of the present invention. Fig. 4 is a schematic cross-sectional view showing a semiconductor device including a wiring member for a semiconductor device of Fig. 1; Fig. 5 is a schematic cross-sectional view showing a semiconductor device including the wiring member for a semiconductor device of Fig. 3; 6(a) to 6(d) are diagrams showing a method of manufacturing a wiring member for a semiconductor device. 7(a) to (f) are views showing a method of manufacturing the semiconductor device shown in Fig. 4. 8(a) to (f) are diagrams showing a method of manufacturing the semiconductor device shown in Fig. 5. -51 - 201027699 Fig. 9 is a schematic plan view showing a second modification of the wiring member for a semiconductor device according to the first embodiment of the present invention. Fig. 10 is a schematic plan view showing a modification 3 of the wiring harness for a semiconductor device according to the first embodiment of the present invention. Fig. 11 (a) is a schematic plan view showing a modification 4 of the wiring member for a semiconductor device according to the first embodiment of the present invention, and Fig. 11 (b) is a cross-sectional view taken along line A-A of Fig. 9 (a). Fig. 12 is a schematic cross-sectional view showing a second embodiment of the semiconductor device of the present invention. Fig. 13 (a) - (e) are diagrams showing a method of manufacturing a package type semiconductor device. Figs. 14(a) through 14(b) are diagrams showing a modification of the method of manufacturing the semiconductor device shown in Fig. 4. 15(a) to (f) are views showing a modification of the method of manufacturing the semiconductor device shown in Fig. 5. Figure 16 is a schematic cross-sectional view showing a wiring member for a semiconductor device according to a third embodiment of the present invention. Figure 17 is a schematic cross-sectional view showing a composite wiring member for a semiconductor device according to a third embodiment of the present invention. Fig. 18 is a schematic cross-sectional view showing a modification of the wiring member for a semiconductor device according to the third embodiment of the present invention. Fig. 19 is a schematic cross-sectional view showing a semiconductor device according to a third embodiment of the present invention. Fig. 20 (a) - (d) is a view showing a method of manufacturing a wiring member for use in a semiconductor package - 52 - 201027699 according to a third embodiment of the present invention. Fig. 21 (a) - (f) are views showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention. Figure 22 is a schematic cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention. Fig. 23 is a plan view showing a wiring member for a semiconductor device used in a semiconductor device according to a fourth embodiment of the present invention. Fig. 24 (a) - (e) is a view showing a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. Figure 25 is a schematic cross-sectional view showing a modification of the semiconductor device according to the fourth embodiment of the present invention. Figure 26 is a schematic cross-sectional view showing a wiring member for a semiconductor device used in a fifth embodiment of the present invention. Figure 27 is a schematic cross-sectional view showing a composite wiring member for a semiconductor device according to a fifth embodiment of the present invention. Fig. 28 is a schematic plan view showing a composite wiring member for a semiconductor device and a semiconductor device according to a fifth embodiment of the present invention. Fig. 29 is a schematic cross-sectional view showing the semiconductor device according to the fifth embodiment of the present invention (cross-sectional view taken along line B-B of Fig. 28). Fig. 3 (a) - (f) is a view showing a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention. [Description of main component symbols] 10: Wiring member for semiconductor device - 53 - 201027699 10A: Composite wiring member for semiconductor device 1 1 : Insulation layer 11A, 31 : Semiconductor wafer mounting portion 12 : Metal substrate 1 3 : Copper wiring layer 1 3 A : copper layer 1 3B : plating layer 13C : wiring portion _ 13D : first terminal portion 1 3 E : second terminal portion 14 : adhesive layer 1 5 : semiconductor wafer 1 5 A : electrode 16 : first connecting portion 18 , 19, 24, 27A, 27B: 2nd connection

20 :引線框架 G 21 :內引線部 22 :晶粒焊墊 23 :密封樹脂部 24 :第2連接部 25 :引線部 26 :縫隙孔 28 :散熱板黏接層 29 :散熱板 -54- 201027699 30、 40 :半導體裝置20: lead frame G 21 : inner lead portion 22 : die pad 23 : sealing resin portion 24 : second connecting portion 25 : lead portion 26 : slit hole 28 : heat sink bonding layer 29 : heat sink - 54 - 201027699 30, 40: semiconductor device

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Claims (1)

201027699 七、申請專利範困 1· 一種半導體裝置用配線構件，係用於電連接半導 體晶片上之電極與外部配線構件者；其特徵爲具備： 絕緣層； 配置於絕緣層之一側的金屬基板；及 配置於絕緣層之另一側的銅配線層； 在絕緣層之於銅配線層側或銅配線層上形成半導體晶 片載置部； @ 銅配線層，係包含：第1端子部，被連接於半導體晶 片上之電極；第2端子部，被連接於外部配線構件；及配 線部’用於連接第1端子部與第2端子部。 2. 如申請專利範圍第1項之半導體裝置用配線構 件，其中 金屬基板，係由不鏽鋼構成。 3. 如申請專利範圍第1項之半導體裝置用配線構 件，其中 @ 銅配線層’係具有：電連接於半導體晶片上之複數電 極的端子區塊部。 4. 一種半導體裝置用複合配線構件，係用於電連接 半導體晶片上之電極與配線基板者；其特徵爲 具備： 配線構件；及 電連接於該配線構件的引線框架； 配線構件係具有：絕緣層；配置於絕緣層之一側的金 -56- 201027699 屬基板；及配置於絕緣層之另一側的銅配線層； 在絕緣層之於銅配線層側或銅配線層上形成半導體晶 片載置部； 銅配線層，係包含：第1端子部，被連接於半導體晶 片上之電極；第2端子部，被連接於引線框架；及配線 部，用於連接第1端子部與第2端子部； 銅配線層之第2端子部與引線框架係藉由第2連接部 0 被電連接。 5. 如申請專利範圍第4項之半導體裝置用複合配線 構件，其中 金屬基板，係由不鏽鋼構成。 6. 如申請專利範圍第4項之半導體裝置用複合配線 構件，其中 第2連接部，係由焊錫構成。 7-如申請專利範圍第4項之半導體裝置用複合配線 φ 構件，其中 第2連接部，係由接合導線構成。 8. —種樹脂密封型半導體裝置，其特徵爲 具備： 配線構件，具有：絕緣層；配置於絕緣層之一側的金 屬基板；及配置於絕緣層之另一側的銅配線層；在絕緣層 之於銅配線層側或銅配線層上形成半導體晶片載置部；銅 配線層係包含：第1端子部，被連接於半導體晶片上之電 極；第2端子部，被連接於外部配線構件；及配線部，用 -57- 201027699 於連接第1端子部與第2端子部； 引線框架，電連接於該配線構件；及 半導體晶片，被載置於配線構件之半導體晶片載置 部，具有電極； 半導體晶片上之電極與第1端子部係藉由第1連接部 被電連接； 第2端子部與引線框架係藉由第2連接部被電連接； 在露出引線框架之一部分之狀態下，使半導體晶片、 ⑩ 銅配線層、引線框架、第1連接部及第2連接部藉由樹脂 密封部施予樹脂密封。 9. 一種樹脂密封型半導體裝置，其特徵爲 具備： 配線構件，具有：絕緣層；配置於絕緣層之一側的金 靥基板；及配置於絕緣層之另一側的銅配線層；在絕緣層 之於銅配線層側或銅配線層上形成半導體晶片載置部；銅 配線層係包含：第1端子部，被連接於半導體晶片上之電 Θ 極；第2端子部，被連接於外部配線構件；及配線部’用 於連接第1端子部與第2端子部；及 半導體晶片，介由黏接層被載置於該配線構件之半導 體晶片載置部，具有電極； 半導體晶片上之電極與第1端子部係藉由第1連接部 被電連接； 在銅配線層之第2端子部上設有外部連接用之第2連 接部； -58- 201027699 使銅配線層、半導體晶片及第1連接部藉由密封樹脂 部施予密封，第2連接部由密封樹脂部露出外方。 10. 如申請專利範圍第9項之樹脂密封型半導體裝 置，其中 第2連接部，係由焊錫構成。 11. 如申請專利範圍第8項之樹脂密封型半導體裝 置，其中 φ 金屬基板，係由不鏽鋼構成。 12. —種半導體裝置用複合配線構件，係用於電連接 半導體晶片上之電極與配線基板者；其特徵爲 具備： 配線構件；及 電連接於該配線構件之同時，用於載置配線構件的引 線框架； 配線構件係具有：絕緣層；配置於絕緣層之一側的金 φ 屬基板；及配置於絕緣層之另一側的銅配線層； 在銅配線層上形成半導體晶片載置部； 銅配線層，係包含：第1端子部，被連接於半導體晶 片上之電極；第2端子部’被連接於引線框架；及配線 部，用於連接第1端子部與第2端子部； 銅配線層之第2端子部與引線框架係藉由第2連接部 被電連接； 引線框架，係具有：載置配線構件的晶粒焊墊（die pad );及設於晶粒焊墊外方的引線部； -59- 201027699 晶粒焊墊之中至少載置半導體晶片的中央區域之厚 度，係較引線部之厚度爲薄。 13. 如申請專利範圍第12項之半導體裝置用複合配 線構件，其中 金屬基板，係由不鏽鋼構成。 14. 如申請專利範圍第12項之半導體裝置用複合配 線構件，其中 第2連接部，係由接合導線構成。 _ 15. 如申請專利範圍第12項之半導體裝置用複合配 線構件，其中 晶粒焊墊，係具有：中央區域，用於載置半導體晶 片；及周緣區域，位於中央區域外周，和引線部大略爲同 一厚度；在中央區域與周緣區域之間設有縫隙孔。 16. —種樹脂密封型半導體裝置，其特徵爲 具備： 配線構件，具有：絕緣層；配置於絕緣層之一側的金 〇 屬基板；及配置於絕緣層之另一側的銅配線層；在銅配線 層上形成半導體晶片載置部；銅配線層係包含：第1端子 部，被連接於半導體晶片上之電極；第2端子部’被連接 於外部配線構件；及配線部，用於連接第1端子部與第2 端子部； 引線框架，電連接於該配線構件之同時’用於載置配 線構件；及 半導體晶片，被載置於配線構件之半導體晶片載置 -60- 201027699 部，具有電極； 半導體晶片上之電極與第1端子部係藉由第1連接部 被電連接； 第2端子部與引線框架係藉由第2連接部被電連接； 在露出引線框架之一部分之狀態下，使半導體晶片、 銅配線層、引線框架、第1連接部及第2連接部藉由密封 樹脂部施予樹脂密封； φ 引線框架，係具有：載置配線構件的晶粒焊墊；及設 於晶粒焊墊外方的引線部； 晶粒焊墊之中至少載置半導體晶片的中央區域之厚 度，係較引線部之厚度爲薄。 17.如申請專利範圍第16項之樹脂密封型半導體裝 置，其中 晶粒焊墊，係具有：中央區域，用於載置半導體晶 片；及周緣區域，位於中央區域外周，和引線部大略爲同 ❿ 一厚度；在中央區域與周緣區域之間設有縫隙孔。 1 8 .如申請專利範圍第1 6項之樹脂密封型半導體裝 置，其中 晶粒焊墊底面至密封樹脂部下面爲止之長度，和配線 構件至密封樹脂部上面爲止之長度，係大略爲相同。 19. 一種樹脂密封型半導體裝置，其特徵爲 具備= 配線構件，具有：絕緣層；配置於絕緣層之一側的金 屬基板；及配置於絕緣層之另一側的銅配線層；在銅配線 -61 - 201027699 層上形成半導體晶片載置部；銅配線層係包含：第1端子 部，被連接於半導體晶片上之電極；第2端子部，被連接 於外部配線構件；及配線部，用於連接第1端子部與第2 端子部；及 半導體晶片，介由黏接層被載置於該配線構件之半導 體晶片載置部，具有電極； 半導體晶片上之電極與第1端子部係藉由第1連接部 被電連接； @ 在銅配線層之第2端子部上設有外部連接用之第2連 接部； 使銅配線層、半導體晶片及第1連接部藉由密封樹脂 部施予密封，第2連接部由密封樹脂部露出外方； 第2連接部係由焊錫形成； 第1連接部與第2連接部之連接用配線部，係以包圍 第2端子部的方式被迂迴佈局。 20. 如申請專利範圍第1 6項之樹脂密封型半導體裝 ◎ 置，其中 金屬基板，係由不鏽鋼構成。 21. —種半導體裝置用複合配線構件，係用於電連接 半導體晶片上之電極與配線基板者；其特徵爲 具備： 配線構件；及 電連接於該配線構件之同時，用於載置配線構件的引 線框架； -62- 201027699 配線構件係具有：絕緣層；配置於絕緣層之一側的金 屬基板；及配置於絕緣層之另一側的銅配線層； 在銅配線層上形成半導體晶片載置部； 銅配線層，係包含：第1端子部，被連接於半導體晶 片上之電極；第2端子部，被連接於引線框架；及配線 部，用於連接第1端子部與第2端子部； 銅配線層之第2端子部與引線框架係藉由第2連接部 φ 被電連接； 引線框架，係具有：載置配線構件的晶粒焊墊；及設 於晶粒焊墊外方的引線部； 晶粒焊墊，係具有：中央區域，對應於半導體晶片； 及周緣區域，位於中央區域外周之同時被連結於中央區 域，在其和中央區域之間形成密封樹脂流入空間； 配線構件，係配置於晶粒焊墊之中央區域至周緣區域 爲止之區域， # 配線構件，係至少在晶粒焊墊之中央區域及周緣區域 使用樹脂糊被黏接。 22. 如申請專利範圍第21項之半導體裝置用複合配 線構件，其中 金屬基板，係由不鏽鋼構成。 23. 如申請專利範圍第21項之半導體裝置用複合配 線構件，其中 樹脂糊，係以多點狀或直線狀被塗敷。 24. 如申請專利範圍第21項之半導體裝置用複合配 -63- 201027699 線構件，其中 晶粒焊墊之中，至少在中央區域及周緣區域被施予鎪 層處理。 25. —種樹脂密封型半導體裝置，其特徵爲 具備= 配線構件，具有：絕緣層；配置於絕緣層之一側的金 屬基板；及配置於絕緣層之另一側的銅配線層；在銅配線 層上形成半導體晶片載置部；銅配線層係包含：第1端子 部，被連接於半導體晶片上之電極；第2端子部，被連接 於外部配線構件；及配線部，用於連接第1端子部與第2 端子部； 引線框架，電連接於該配線構件之同時，用於載置配 線構件；及 半導體晶片，被載置於配線構件之半導體晶片載置 部，具有電極； 半導體晶片上之電極與第1端子部係藉由第1連接部 被電連接； 第2端子部與引線框架係藉由第2連接部被電連接； 在露出引線框架之一部分之狀態下，使半導體晶片、 銅配線層、引線框架、第1連接部及第2連接部藉由密封 樹脂部施予樹脂密封； 引線框架，係具有：載置配線構件的晶粒焊墊；及設 於晶粒焊墊外方的引線部； 晶粒焊墊，係具有：中央區域，對應於半導體晶片； 201027699 及周緣區域，位於中央區域外周之同時被連結於中央區 域，在其和中央區域之間形成密封樹脂流入空間； 配線構件，係配置於晶粒焊墊之中央區域至周緣區域 爲止之區域， 配線構件，係至少在晶粒焊墊之中央區域及周緣區域 使用樹脂糊被黏接。 26. 如申請專利範圍第25項之樹脂密封型半導體裝 ^ 置，其中 金屬基板’係由不鏽鋼構成。 27. 如申1^專利範圍第25項之樹脂密封型半導體裝 置，其中 樹脂糊，係以多點邱+ # _ # 狀或直線狀被塗敷。 28·如申5靑專利範圍帛25 I頁之樹脂密封型半導體裝 置，其中 晶粒焊墊之中，基，丨+ S少在中央區域及周緣區域被施予銨 φ 層處理。 -65-201027699 VII. Patent application 1 1. A wiring member for a semiconductor device for electrically connecting an electrode and an external wiring member on a semiconductor wafer; characterized by comprising: an insulating layer; a metal substrate disposed on one side of the insulating layer And a copper wiring layer disposed on the other side of the insulating layer; a semiconductor wafer mounting portion is formed on the copper wiring layer side or the copper wiring layer of the insulating layer; and the @ copper wiring layer includes: the first terminal portion An electrode connected to the semiconductor wafer; the second terminal portion is connected to the external wiring member; and the wiring portion ' is for connecting the first terminal portion and the second terminal portion. 2. The wiring member for a semiconductor device according to the first aspect of the invention, wherein the metal substrate is made of stainless steel. 3. The wiring member for a semiconductor device according to claim 1, wherein the @copper wiring layer has a terminal block portion electrically connected to a plurality of electrodes on the semiconductor wafer. A composite wiring member for a semiconductor device for electrically connecting an electrode and a wiring substrate on a semiconductor wafer, comprising: a wiring member; and a lead frame electrically connected to the wiring member; and the wiring member has: an insulation a gold-56-201027699 substrate disposed on one side of the insulating layer; and a copper wiring layer disposed on the other side of the insulating layer; forming a semiconductor wafer on the copper wiring layer side or the copper wiring layer of the insulating layer The copper wiring layer includes: a first terminal portion connected to the electrode on the semiconductor wafer; a second terminal portion connected to the lead frame; and a wiring portion for connecting the first terminal portion and the second terminal The second terminal portion of the copper wiring layer and the lead frame are electrically connected by the second connection portion 0. 5. The composite wiring member for a semiconductor device according to the fourth aspect of the invention, wherein the metal substrate is made of stainless steel. 6. The composite wiring member for a semiconductor device according to the fourth aspect of the invention, wherein the second connecting portion is made of solder. [7] The composite wiring φ member for a semiconductor device according to the fourth aspect of the invention, wherein the second connecting portion is formed of a bonding wire. 8. A resin-sealed semiconductor device comprising: a wiring member having: an insulating layer; a metal substrate disposed on one side of the insulating layer; and a copper wiring layer disposed on the other side of the insulating layer; a semiconductor wafer mounting portion is formed on the copper wiring layer side or the copper wiring layer; the copper wiring layer includes: a first terminal portion connected to the electrode on the semiconductor wafer; and a second terminal portion connected to the external wiring member And the wiring portion, the first terminal portion and the second terminal portion are connected by -57-201027699; the lead frame is electrically connected to the wiring member; and the semiconductor wafer is placed on the semiconductor wafer mounting portion of the wiring member; An electrode; the electrode on the semiconductor wafer and the first terminal portion are electrically connected by the first connection portion; the second terminal portion and the lead frame are electrically connected by the second connection portion; and a part of the lead frame is exposed The semiconductor wafer, the ten copper wiring layer, the lead frame, the first connection portion, and the second connection portion are resin-sealed by a resin sealing portion. A resin-sealed semiconductor device comprising: a wiring member; an insulating layer; a gold-iridium substrate disposed on one side of the insulating layer; and a copper wiring layer disposed on the other side of the insulating layer; The semiconductor wafer mounting portion is formed on the copper wiring layer side or the copper wiring layer, and the copper wiring layer includes a first terminal portion connected to the electric semiconductor on the semiconductor wafer, and a second terminal portion connected to the outside. a wiring member; and a wiring portion 'for connecting the first terminal portion and the second terminal portion; and the semiconductor wafer, wherein the semiconductor wafer is placed on the semiconductor wafer mounting portion of the wiring member via the adhesive layer, and has an electrode; The electrode and the first terminal portion are electrically connected by the first connection portion; the second terminal portion for external connection is provided on the second terminal portion of the copper wiring layer; -58- 201027699 The copper wiring layer, the semiconductor wafer, and The first connecting portion is sealed by the sealing resin portion, and the second connecting portion is exposed to the outside by the sealing resin portion. 10. The resin-sealed semiconductor device according to claim 9, wherein the second connecting portion is made of solder. 11. The resin-sealed semiconductor device according to claim 8, wherein the φ metal substrate is made of stainless steel. 12. A composite wiring member for a semiconductor device for electrically connecting an electrode and a wiring substrate on a semiconductor wafer, comprising: a wiring member; and electrically connected to the wiring member and for mounting a wiring member The wiring member includes: an insulating layer; a gold φ substrate disposed on one side of the insulating layer; and a copper wiring layer disposed on the other side of the insulating layer; and a semiconductor wafer mounting portion formed on the copper wiring layer The copper wiring layer includes: a first terminal portion connected to the electrode on the semiconductor wafer; a second terminal portion 'connected to the lead frame; and a wiring portion for connecting the first terminal portion and the second terminal portion; The second terminal portion of the copper wiring layer and the lead frame are electrically connected by the second connection portion; the lead frame has a die pad on which the wiring member is placed; and is disposed outside the die pad The lead portion of the square; -59- 201027699 The thickness of the central portion of the die pad on which at least the semiconductor wafer is placed is thinner than the thickness of the lead portion. 13. The composite wiring member for a semiconductor device according to claim 12, wherein the metal substrate is made of stainless steel. 14. The composite wiring member for a semiconductor device according to claim 12, wherein the second connecting portion is formed by a bonding wire. The composite wiring member for a semiconductor device according to claim 12, wherein the die pad has a central region for mounting the semiconductor wafer, and a peripheral region located at a periphery of the central region, and the lead portion is substantially It is the same thickness; a slit hole is provided between the central area and the peripheral area. 16. A resin-sealed semiconductor device, comprising: a wiring member having: an insulating layer; a metal substrate disposed on one side of the insulating layer; and a copper wiring layer disposed on the other side of the insulating layer; a semiconductor wafer mounting portion is formed on the copper wiring layer; the copper wiring layer includes: a first terminal portion connected to the electrode on the semiconductor wafer; a second terminal portion 'connected to the external wiring member; and a wiring portion for The first terminal portion and the second terminal portion are connected; the lead frame is electrically connected to the wiring member and used to mount the wiring member; and the semiconductor wafer is placed on the semiconductor wafer mounted on the wiring member -60-201027699 And having an electrode; the electrode on the semiconductor wafer and the first terminal portion are electrically connected by the first connection portion; the second terminal portion and the lead frame are electrically connected by the second connection portion; and a portion of the lead frame is exposed In the state, the semiconductor wafer, the copper wiring layer, the lead frame, the first connection portion, and the second connection portion are resin-sealed by the sealing resin portion; the φ lead frame has Die pads mounting the wiring member; and a lead portion provided on the outer die pad; thickness in the central area at least on the die pads of the semiconductor wafer, the thickness of the lead-based than the thin portion. 17. The resin-sealed semiconductor device according to claim 16, wherein the die pad has a central region for mounting the semiconductor wafer, and a peripheral region located at an outer periphery of the central region, and the lead portion is substantially the same ❿ a thickness; a slit hole is provided between the central area and the peripheral area. In the resin-sealed type semiconductor device of the first aspect of the invention, the length of the bottom surface of the die pad to the lower surface of the sealing resin portion and the length of the wiring member to the upper surface of the sealing resin portion are substantially the same. A resin-sealed semiconductor device comprising: a wiring member, comprising: an insulating layer; a metal substrate disposed on one side of the insulating layer; and a copper wiring layer disposed on the other side of the insulating layer; -61 - 201027699 A semiconductor wafer mounting portion is formed on the layer; the copper wiring layer includes: a first terminal portion connected to the electrode on the semiconductor wafer; a second terminal portion connected to the external wiring member; and a wiring portion And connecting the first terminal portion and the second terminal portion; and the semiconductor wafer is placed on the semiconductor wafer mounting portion of the wiring member via the adhesive layer, and has an electrode; and the electrode on the semiconductor wafer is coupled to the first terminal portion The first connection portion is electrically connected; @ the second terminal portion of the copper wiring layer is provided with a second connection portion for external connection; and the copper wiring layer, the semiconductor wafer, and the first connection portion are supplied by the sealing resin portion The second connecting portion is exposed to the outside by the sealing resin portion, and the second connecting portion is formed of solder. The connecting portion for connecting the first connecting portion and the second connecting portion is surrounded by the second terminal portion. Back layout. 20. The resin-sealed semiconductor device according to claim 16 wherein the metal substrate is made of stainless steel. A composite wiring member for a semiconductor device for electrically connecting an electrode and a wiring substrate on a semiconductor wafer, comprising: a wiring member; and electrically connected to the wiring member and for mounting the wiring member a lead frame; -62- 201027699 The wiring member has: an insulating layer; a metal substrate disposed on one side of the insulating layer; and a copper wiring layer disposed on the other side of the insulating layer; forming a semiconductor wafer on the copper wiring layer The copper wiring layer includes: a first terminal portion connected to the electrode on the semiconductor wafer; a second terminal portion connected to the lead frame; and a wiring portion for connecting the first terminal portion and the second terminal a second terminal portion of the copper wiring layer and the lead frame are electrically connected by the second connection portion φ; the lead frame has a die pad on which the wiring member is placed; and is disposed outside the die pad a lead pad; the die pad has a central region corresponding to the semiconductor wafer; and a peripheral region that is connected to the central region at the same time as the outer periphery of the central region, at the center thereof a sealing resin inflow space is formed between the regions; the wiring member is disposed in a region from the central region of the die pad to the peripheral region, and the #wiring member is made of resin paste at least in the central region and the peripheral region of the die pad. Bonding. 22. The composite wiring member for a semiconductor device according to claim 21, wherein the metal substrate is made of stainless steel. 23. The composite wiring member for a semiconductor device according to claim 21, wherein the resin paste is applied in a multi-point or linear shape. 24. The composite member for a semiconductor device according to claim 21, wherein the die pad is subjected to a ruthenium layer treatment at least in a central region and a peripheral region. 25. A resin-sealed semiconductor device comprising: a wiring member, comprising: an insulating layer; a metal substrate disposed on one side of the insulating layer; and a copper wiring layer disposed on the other side of the insulating layer; a semiconductor wafer mounting portion is formed on the wiring layer; the copper wiring layer includes: a first terminal portion connected to the electrode on the semiconductor wafer; a second terminal portion connected to the external wiring member; and a wiring portion for connecting the first portion a terminal portion and a second terminal portion; a lead frame electrically connected to the wiring member for mounting a wiring member; and a semiconductor wafer placed on the semiconductor wafer mounting portion of the wiring member and having an electrode; The upper electrode and the first terminal portion are electrically connected by the first connection portion; the second terminal portion and the lead frame are electrically connected by the second connection portion; and the semiconductor wafer is made in a state where one of the lead frames is exposed The copper wiring layer, the lead frame, the first connection portion, and the second connection portion are resin-sealed by the sealing resin portion; and the lead frame has a crystal on which the wiring member is placed a solder pad; and a lead portion disposed outside the die pad; the die pad has a central region corresponding to the semiconductor wafer; 201027699 and a peripheral region are connected to the central region while being located at the outer periphery of the central region, a sealing resin inflow space is formed between the central portion and the central region; the wiring member is disposed in a region from the central region of the die pad to the peripheral region, and the wiring member is made of resin at least in a central region and a peripheral region of the die pad. The paste is glued. 26. The resin-sealed type semiconductor device of claim 25, wherein the metal substrate is made of stainless steel. 27. The resin-sealed type semiconductor device according to claim 25, wherein the resin paste is applied in a multi-point pattern of ##_# or linear. 28. The resin-sealed semiconductor device of the pp. 25, pp. pp. 25, wherein the base, 丨+ S is applied to the central φ layer in the central region and the peripheral region. -65-
TW098123933A 2009-01-13 2009-07-15 A wiring device for a semiconductor device, a composite wiring member for a semiconductor device, and a resin-sealed semiconductor device TWI416688B (en)

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