201027213 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種電晶體結構，特別是關於一種可應用於液晶顯 示面板中下導板設計之晝素薄膜電晶體結構。 【先前技術】 在薄膜電晶體液晶顯示面板(TFT LCD)的製造中，區分為陣列 (Array)製程與彩色光阻(Color Filter)製程，其中於陣列製程中製作出用 以傳遞訊號之電歷控制元件薄膜電晶髏（Thin Film Transistors， TFT) ’以形成所須之電極基板。如第一圖所示為習知薄膜電晶體之結 ® 構示意圖，如圖所示，一第一金屬層10係做為閘極電極12，此第一 金屬層10上將形成一非晶矽層14與第一金屬層10部份相重疊；一 第二金屬層16係位於第一金屬層1〇之上，以形成一沒極電極18、一 源極電極20與一資料線22，此汲極電極18係為T字型狀，且將延伸 至非晶矽層14上與其部份相重疊；源極電極2〇係位於此非晶矽層14 上，呈現门字狀與汲極電極18對應，並且與縱向橫跨於第一金屬層 10之上的資料線相連接，此外，一畫素電極層24係位於汲極電極18 之上，並且透過一開洞26與汲極電極18相導通。 當於進辦膽程巾之黃光製程時，將相黃光機台於曝光時所 醫產生之些微震動，使曝光發生偏移現象，如第二圖所示，汲極電極18 的位置相較於第一圖將發生縱向往下偏移使得第二金屬層16形成之 汲極電極18與非晶石夕層14重叠部份之面積改變，如此將造成汲極電 極18與閘極電極^之間的寄生電容(Cgd>麵變化，進而導致畫素電 極電位因寄生電容(Cgd)存在所下降之電位（Feed 丁咖如砸啡） 將隨之而改變，這將使得液晶顯示面板的局部區域因此而發生色彩不 均(Mura)與閃爍(Flicker)等現象。 ^ 曰有鑑於此，本發明係針對上述該些困擾，以提出一種畫素薄膜電 晶體結構，以抵抗黃光機台曝光時所發生的偏差現象。 3 201027213 【發明内容】 本發明之主要目的係在提供一種畫素薄膜電晶體結構，其係具有 抵抗黃光製程時機台振動所造成的偏移’使得薄膜電晶體之汲極與閘 極之間的寄生電容(Cgd)得以固定，以使得加在畫素電極上的電壓為正 負相對稱，使直流位準之電壓降誤差降低到最小值。 本發明之又一目的係在提供一種畫素薄膜電晶體結構，其係將減 少液晶顯示面板局部區域的色彩不均(Mura)與閃爍(FHcker)現象發 生，使得液晶顯示面板之品質得以大幅提升。 籲金屬層形成閘極電極，此閘極電極係具有向外延伸之電極部；一絕緣 層形成於第-金屬層上，-非晶料係形成於絕緣層上並分別設置在 閘極極與電極部的上方；在此非晶⑦層上料形成—第二金屬層， ^第二金屬層係具有-祕_與—源極電極，雜電極係位於閉極 ，極上方之非_層上；極係分顺_電極上方及電極部上 為達到上述之目的，本發明提出之晝素薄膜電晶體結構係於第一 方之非晶矽層部分相重疊，並透過非晶矽層201027213 VI. Description of the Invention: [Technical Field] The present invention relates to a crystal structure, and more particularly to a halogen film transistor structure which can be applied to a lower guide plate design of a liquid crystal display panel. [Prior Art] In the manufacture of a thin film transistor liquid crystal display panel (TFT LCD), it is divided into an Array process and a color filter process, in which an electronic calendar for transmitting signals is produced in an array process. The thin film transistor (TFT) of the control element is formed to form a desired electrode substrate. As shown in the first figure, a schematic diagram of a conventional thin film transistor structure is shown. As shown in the figure, a first metal layer 10 is used as a gate electrode 12, and an amorphous germanium is formed on the first metal layer 10. The layer 14 is partially overlapped with the first metal layer 10; a second metal layer 16 is disposed on the first metal layer 1 , to form a gate electrode 18, a source electrode 20 and a data line 22, The drain electrode 18 is T-shaped and will extend over the amorphous germanium layer 14 to overlap with a portion thereof; the source electrode 2 is located on the amorphous germanium layer 14 and exhibits a gate-shaped and a gate electrode. 18 corresponds to and is connected to the data line vertically across the first metal layer 10. Further, a pixel electrode layer 24 is located above the gate electrode 18 and passes through a opening 26 and the drain electrode 18. The phase is turned on. When the yellow light process of the bile duct towel is introduced, the micro-vibration generated by the phase yellow light machine during exposure causes the exposure to shift, as shown in the second figure, the position of the drain electrode 18 The longitudinal offset of the first metal layer 16 is changed from that of the first metal layer 16 so that the area of the overlap between the drain electrode 18 and the amorphous layer 14 is changed, so that the gate electrode 18 and the gate electrode are caused. The parasitic capacitance between them (Cgd> surface change, which in turn causes the potential of the pixel electrode to drop due to the presence of parasitic capacitance (Cgd) (Feed, such as 砸 )) will change, which will make the liquid crystal display panel In this way, the phenomenon of color unevenness (Mura) and flicker (Flicker) occurs. ^ In view of this, the present invention is directed to the above-mentioned problems to propose a pixel thin film transistor structure to resist exposure of a yellow machine. The deviation phenomenon that occurs at the time. 3 201027213 SUMMARY OF THE INVENTION The main object of the present invention is to provide a pixel thin film transistor structure which has the offset caused by the vibration of the machine during the yellow light process, so that the thin film transistor汲The parasitic capacitance (Cgd) between the pole and the gate is fixed so that the voltage applied to the pixel electrode is positive and negative, and the voltage drop error of the DC level is reduced to a minimum. Providing a pixel thin film transistor structure, which reduces the occurrence of color unevenness (Mura) and flicker (FHcker) in a local region of the liquid crystal display panel, so that the quality of the liquid crystal display panel is greatly improved. An electrode, the gate electrode has an electrode portion extending outward; an insulating layer is formed on the first metal layer, and an amorphous material is formed on the insulating layer and disposed respectively above the gate electrode and the electrode portion; The amorphous 7 layer is formed into a second metal layer, the second metal layer has a secret source and a source electrode, and the impurity electrode is located on the non-layer of the closed pole and the upper pole; In order to achieve the above purpose, the halogen film crystal structure of the present invention overlaps the amorphous germanium layer portion of the first side and passes through the amorphous germanium layer.
【實施方式】[Embodiment]
面剖視圖’一第一金屬々3〇係做為一 ΐ::二Ξ:素結構其第-金屬層之閘極電極係 201027213 閘極電極32，此閘極電極32#具有向外拓展延伸之一電極部34，此 電極部34係為L字型狀。一絕緣層36係位於此一第一金屬層3〇上。 於此絕緣層36上係形成-非晶碎層38，且分別設置於閉極電極32與 電極部34上。一第二金屬層40形成於非晶梦層38上且具有一汲 極1：極42與-源極電極44，此源極電極44係位於閘極電極32上之 非晶石夕層38上，且為開口向上之n字型狀；此沒極電極42的一端係 縱向延伸至閘極電極32上之非晶㈣38上與源極電極44之之中心 位置相對應，並透過非晶石夕層38與閘極電極32部份相重番，以形成 -第-寄生電容(财未示）；献没極_42的另—端係橫向延伸至 ❿電極部34上之非晶石夕層38上，並透過非晶發層38與電極部34部份 相重4，以形成-第二寄生電細中未示）；此没極電極42與閉極電 極32部份相重疊的長度係等同於此汲極電極42與電極部34部份相 重昼的長度。此外，在此第二金屬層40之上將再形成絕緣層邡，且 於絕緣層36相對第二金屬層40之汲極電極42所在位置開設一孔洞 48 ’其後於絕緣層36上形成-畫素電極層46，畫素電極層46將透過 此孔洞48與第二金屬層40之汲極電極42相導通。另外亦有一掃 描線(圖中未示)及一資料線50分別與第一金屬層3〇之閉㈣極於及 第二金屬層40之源極電極42相連接。 ❹ #黃光製程因機台震動發生曝光偏移現象時，如第五圖所示，沒 極電極42的位置相較於第四圖將縱向往上偏移，使沒極電極42透過 非晶梦層38細極電極32部份相重4之面繼減，關時汲極電極 42透過非晶石夕層38與電極部34雜相重叠之面積將增加，將使得第 -電容之電容值減少，反之第二電容之電容值增加，如此的此消彼满 的補個係，將使第-寄线額第二寄生電容之電容量總和為定 值’不將因偏移改變，進而使汲極電極42與閘極電極32之間的寄生 電容(Cgd)得以維持固定。 承上所述為波極電極42分別縱向與橫向延伸至閉極電極％及電 極部34之上，且為發生縱向偏移的第一實施例。另外，間極_ %、 201027213 電極部34、汲極電極42與源極44分別所呈現的形狀與設置位置係可 改變。如第六圖所示為第二實施例，如囷所示，第-金屬層30之閘極 電極32係向左延伸電極部34,汲極電極42兩端分別橫向延伸至閘極 電極32及電極部34上之非晶讀％上，且與呈現η字糊口向右 之源極f：極44相對應。第七圖所示為本發明第二實施例發生偏移之示 意圖如圖所示’没極電極42係、橫向往左偏移，使没極電極42與電 極:34藉由非晶發層38部份相重疊面積增加，與閘極電極32藉由 非晶梦38部份相重^面誠少，而妓電容㈣總值職對固定。 第一實施例如第八圖所示，沒極電極42 —端延伸至閘極電極32 〇 之非曰曰石夕層38上，且末端為门字型狀，另一端透過非晶梦層38與 電極部34冑份相重整’源極電極44係為直條狀與汲極_ 42末端 之门字型狀的中心點對應。第九圖為本發明第三實施例發生橫向偏移 之示意圖’如騎示，汲極電極42橫向偏移，歧極電極42非门字 型狀的部份藉由非晶㈣38制極電極32相重4的面齡將縮減， 重叠面積縮減的部份係由與電極層34重叠雜增加轉份補足。 經由上述各實施例說明可知本發明係將第一金屬層30之閘極電 極32向外拓展一電極部34來做為閘極電極32的補償，以抵抗黃光 製程所發生偏移，使得第二金屬唐40之沒極電極42與閘極電極32 ❿之間形成的寄生電容(Cgd)將能於黃光製程發生偏移時仍保持定值。 以上所述之實施例僅係為說明本發明之技術思想及特點，其目的 在使熟習此項技藝之人士能夠瞭解本發明之内容並據以實施，當不能 乂之限定本發明之專利|^圍，即大凡依本發明所揭示之精神所作之均 等變化或修飾，仍應涵蓋在本發明之專利範圍内。 【圖式簡單說明】 第一圖為習知薄膜電晶體之結構示意圖。 第二圖為習知薄膜電晶體發生曝光偏移之結構示意圖。 第三(a)圖為本發明之結構剖視圖 201027213 第三(b)圖為本發明之a-A’區間之結構截面剖視圖， 第四圖為本發明之第一實施例的佈局結構示意圏。 第五圖為本發明第一實施例發生曝光偏移之示意圓。 第六圖為本發明之第二實施例的佈局結構示意圖。 第七圖為本發明第二實施例發生曝光偏移之示意圓。 第八圖為本發明之第三實施例的佈局結構示意圖。 第九圖為本發明第三實施例發生曝光偏移之示意圖。 【主要元件符號說明】 eThe cross-sectional view of a first metal 々 3 〇 is a ΐ:: Ξ: the gate structure of the first metal layer of the prime structure 201027213 gate electrode 32, the gate electrode 32# has an outward extension The electrode portion 34 has an L-shaped shape. An insulating layer 36 is located on the first metal layer 3〇. An amorphous layer 38 is formed on the insulating layer 36, and is disposed on the closed electrode 32 and the electrode portion 34, respectively. A second metal layer 40 is formed on the amorphous layer 38 and has a drain 1: a pole 42 and a source electrode 44. The source electrode 44 is on the amorphous layer 38 on the gate electrode 32. And the n-shaped shape of the opening upward; one end of the electrodeless electrode 42 extends longitudinally to the amorphous (four) 38 on the gate electrode 32 corresponding to the center position of the source electrode 44, and transmits through the amorphous stone The layer 38 is partially overlapped with the gate electrode 32 to form a -th parasitic capacitance (not shown); the other end of the donor pole _42 extends laterally to the amorphous layer on the ❿ electrode portion 34. 38, and through the amorphous layer 38 and the electrode portion 34 part of the weight 4 to form - the second parasitic capacitance is not shown); the length of the electrodeless electrode 42 and the closed electrode 32 overlap This is equivalent to the length in which the gate electrode 42 and the electrode portion 34 are partially overlapped. In addition, an insulating layer 将 is formed on the second metal layer 40, and a hole 48 ′ is formed in the insulating layer 36 opposite to the gate electrode 42 of the second metal layer 40, and then formed on the insulating layer 36. The pixel electrode layer 46, through which the pixel electrode layer 46 is to be conducted, is electrically connected to the drain electrode 42 of the second metal layer 40. Further, a scanning line (not shown) and a data line 50 are connected to the source electrode 42 of the second metal layer 40, respectively, to the first metal layer 3's (4). ❹ #黄光工艺 When the exposure shift occurs due to the vibration of the machine, as shown in the fifth figure, the position of the electrode 4 is shifted upward in the longitudinal direction compared with the fourth figure, so that the electrode 42 is transparent. The surface of the thin layer of the thin layer electrode 32 of the dream layer 38 is successively reduced. When the anode electrode 42 is turned off, the area overlapping the impurity layer of the amorphous layer 38 and the electrode portion 34 will increase, and the capacitance value of the first capacitor will be increased. Decrease, and vice versa, the capacitance of the second capacitor increases. Such a complementary system will make the sum of the capacitances of the second parasitic capacitance of the first-station line constant, which will not change due to the offset. The parasitic capacitance (Cgd) between the drain electrode 42 and the gate electrode 32 is maintained constant. The first embodiment in which the wave electrode 42 extends longitudinally and laterally to the closed electrode % and the electrode portion 34, respectively, is a longitudinal offset. Further, the shape and the position at which the electrode portion _%, 201027213, the electrode portion 34, the drain electrode 42, and the source electrode 44 are respectively present may be changed. As shown in the sixth embodiment, as shown in FIG. 2, the gate electrode 32 of the first metal layer 30 extends to the left extending electrode portion 34, and the two ends of the drain electrode 42 extend laterally to the gate electrode 32, respectively. The amorphous portion of the electrode portion 34 is on the % of reading, and corresponds to the source f: pole 44 which presents the n-word to the right. FIG. 7 is a schematic view showing the offset of the second embodiment of the present invention. As shown in the figure, the electrodeless electrode 42 is laterally shifted to the left, so that the electrodeless electrode 42 and the electrode 34 are formed by the amorphous layer 38. The overlap area of the part is increased, and the gate electrode 32 is partially reduced by the amorphous dream 38, and the tantalum capacitor (4) is fixed. In the first embodiment, as shown in the eighth figure, the end of the electrodeless electrode 42 extends to the non-sapphire layer 38 of the gate electrode 32, and the end is gate-shaped, and the other end passes through the amorphous layer 38 and The electrode portion 34 胄 phase reforming 'source electrode 44' is a straight strip shape corresponding to the center point of the gate shape of the end of the drain _42. The ninth figure is a schematic diagram of the lateral shift of the third embodiment of the present invention. As shown in the riding, the drain electrode 42 is laterally offset, and the portion of the parapolar electrode 42 is non-gate shaped by the amorphous (four) 38 electrode electrode 32. The face age of the phase weight 4 will be reduced, and the portion where the overlap area is reduced will be complemented by the overlap with the electrode layer 34. Through the above embodiments, the present invention discloses that the gate electrode 32 of the first metal layer 30 is extended outward by an electrode portion 34 as a compensation for the gate electrode 32 to resist the offset of the yellow light process, so that the first The parasitic capacitance (Cgd) formed between the electrode 42 of the second metal Tang 40 and the gate electrode 32 将 will remain constant when the yellow light process is shifted. The embodiments described above are only for explaining the technical idea and the features of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the contents of the present invention and to implement the patents of the present invention. Equivalent changes or modifications made by the spirit of the present invention should still be included in the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a schematic view of the structure of a conventional thin film transistor. The second figure is a schematic structural view of a conventional thin film transistor in which an exposure shift occurs. The third (a) diagram is a cross-sectional view of the structure of the present invention. 201027213 The third (b) is a cross-sectional view of the structure of the a-A' section of the present invention, and the fourth diagram is a schematic layout of the first embodiment of the present invention. The fifth figure is a schematic circle in which the exposure shift occurs in the first embodiment of the present invention. Figure 6 is a schematic view showing the layout of a second embodiment of the present invention. The seventh figure is a schematic circle in which the exposure shift occurs in the second embodiment of the present invention. Figure 8 is a schematic view showing the layout of a third embodiment of the present invention. The ninth figure is a schematic diagram showing the exposure shift occurring in the third embodiment of the present invention. [Main component symbol description] e
10第一金屬層 14非晶發層 18汲極電極 22資料線 26開洞 3〇第一金屬層 34電極部 38非晶矽層 42汲極電極 46畫素電極層， 50資料線 12閘極電極 16第二金屬層 20源極電極 24畫素電極層 32閘極電極 36絕緣層 40第二金屬層 44源極電極 48孔洞10 first metal layer 14 amorphous layer 18 drain electrode 22 data line 26 hole 3 〇 first metal layer 34 electrode portion 38 amorphous 矽 layer 42 电极 electrode 46 pixel electrode layer, 50 data line 12 gate Electrode 16 second metal layer 20 source electrode 24 pixel electrode layer 32 gate electrode 36 insulating layer 40 second metal layer 44 source electrode 48 hole