201025600 UMCD-2007-0547 27235twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件，且特別是有關於 一種高壓金氧半導體元件。 ' 【先前技術】 液晶顯示裝置(liquid crystal display，LCD)已經逐漸成 為顯示裝置的主流，由於具有重量輕、體積小、適於不 同尺寸應用及低輻射等優良特性，使得液晶顯示裝置特 ❿ 別適用作為如筆§己型‘電腦、手機及全球定位系統(Gpjg)等 可攜式電子裝置之顯示螢幕。 當液晶顯示裝置大量應用於可搆式電子裝置之中，則 隨著攜帶式應用電池容量之限制，具備低耗電量也成為 不可或缺的要求。但是隨著LCD面板尺寸的持續增加， LCD面板的功率消耗也會隨之增加。 一般而言’液晶顯示裝置的驅動器積體電路(driver 1C)所應用之南壓元件主要係採用高壓互補式金氧半導體 0 (CMOS)製程來製造’主要是利用隔離層的形成，以加大 源極/沒極區和閘極之間距，用以降低通道内的橫向電 場；或是在隔離層下方的漂移區與源極/汲極區下方的接 合區(grade region)進行淡離子摻雜，以減輕熱電子效應 (hot electron effects);因而提高源極/汲極區的接面崩潰電 壓’繼之使驅動電路的高壓元件能正常運作並提供足夠 南的電壓。 在實際的應用上，節省LCD驅動電路及LCD面板 的耗電而避免產生耗電量過大的問題是頗為迫切的。 5 201025600 UMUU~z007-0547 27235twf.doc/n 【發明内容】 有鑑於此，本發明的目的就是在提供一種金氧半導 體兀件，適用於液晶顯示器之驅動器積體電路。本發明 所提供具較低工作電壓的金氧半導體元件特別適合^置 於驅動器積體電路(driver 1C)高壓金氧半導體元件區域 中，或與尚壓金氧半導體元件搭配使用。201025600 UMCD-2007-0547 27235twf.doc/n IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor element, and more particularly to a high voltage MOS device. [Prior Art] Liquid crystal display (LCD) has gradually become the mainstream of display devices. Due to its light weight, small size, suitable for different size applications and low radiation, the liquid crystal display device is particularly difficult. It is suitable for use as a display screen for portable electronic devices such as computers, mobile phones and global positioning systems (Gpjg). When a large number of liquid crystal display devices are used in a configurable electronic device, with the limitation of the battery capacity of the portable application, it is an indispensable requirement to have low power consumption. However, as the size of the LCD panel continues to increase, the power consumption of the LCD panel will also increase. In general, the south voltage components used in the driver integrated circuit of the liquid crystal display device (driver 1C) are mainly manufactured by a high voltage complementary metal oxide semiconductor 0 (CMOS) process, which is mainly used to form an isolation layer to increase The distance between the source/nopole region and the gate is used to reduce the transverse electric field in the channel; or the light ion doping is performed in the drift region below the isolation layer and the grade region below the source/drain region. To mitigate the hot electron effects; thus increasing the junction breakdown voltage of the source/drain regions', which in turn enables the high voltage components of the driver circuit to function properly and provide a sufficiently south voltage. In practical applications, it is quite urgent to save the power consumption of the LCD driver circuit and the LCD panel to avoid excessive power consumption. 5 201025600 UMUU~z007-0547 27235twf.doc/n SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a metal oxide semiconductor device suitable for use in a driver integrated circuit of a liquid crystal display. The MOS device having a lower operating voltage provided by the present invention is particularly suitable for use in a region of a driver 1C high voltage MOS device or in combination with a MOS device.
本發明提出一種金氧半導體元件，包括具有—N型 深井區與至少一隔離結構的基底、設置於N型深井區中 的一 P型井區、設置於該基底上且位於該p型井區中的 閘極、至少一 N型延伸區、一 N型汲極區與—N型源 ，區以及—？型摻雜區。該N型延伸區S置於該p型井 區十而分雜_閘極兩縣底巾，而N魏極區與N i源極區刀別位於該閘極兩侧基底中而設置於該N型延 伸區中。此外’ p型摻顧設置於p型井區巾而與 源極區以隔離結構分隔開來。 、I 依照本發明的一較佳實施例所述，在上述之金氧 導體7G件中’抑型延伸區更包括_雙重換雜區。 墓舻依發明的一較佳實施例所述，在上述之金氡半 70 ，該N型延伸區之一側與該閘極對齊，而兮 伸以—側位於該隔離結構下方。或者，該= 如你二之側延伸至該閘極下方’而該N型延伸區另-側位於該隔離結構下方。 乃 導體依=發明的—較佳實施例所述，在上述之金氧半 兀 ，更包括間隙壁設置於該閘極兩側壁上， “型没極區與該N型源極區的〆側鄰接該間隙壁而 而 另 201025600 UMCU-Z007-0547 27235twf.doc/n 一侧鄰接該隔離結構。 依知、本發明的—較佳實施例所述，在上述之金氧半 導體兀件巾’該N觀伸區的摻减度祕型沒極 區或該N型源極區的摻雜濃度。 依照本發明的-較佳實施例所述，在上述之金氧半 導體兀件巾’該N型延伸區的深度大於該N型汲極 該N型源極區的深度。 一The invention provides a MOS device, comprising a substrate having a -N type deep well region and at least one isolation structure, a P-type well region disposed in the N-type deep well region, disposed on the substrate and located in the p-type well region The gate in the middle, at least one N-type extension, an N-type drain region and the -N source, zone and -? Type doped region. The N-type extension S is placed in the p-type well region, and the N-electrode region and the N i source region are located in the substrate on both sides of the gate. In the N-type extension zone. In addition, the p-type doping is disposed in the p-type well region and is separated from the source region by an isolation structure. I. In accordance with a preferred embodiment of the present invention, the sigma-type extension region further includes a _double-changing region in the gold-oxide conductor 7G member. According to a preferred embodiment of the invention, in the above-described gold dome 70, one side of the N-shaped extension is aligned with the gate, and the side of the extension is located below the isolation structure. Alternatively, the = if the side of your two extends below the gate 'and the other side of the N-type extension is below the isolation structure. In the preferred embodiment, in the above-mentioned gold-oxygen semiconductor, the spacer wall is further disposed on the sidewalls of the gate, and the "type non-polar region and the side of the N-type source region" Adjacent to the spacer and another side of the 201025600 UMCU-Z007-0547 27235twf.doc/n abutting the isolation structure. According to the preferred embodiment of the present invention, in the above-mentioned MOS wafer Doping concentration of the N-type stretching region or the doping concentration of the N-type source region. According to the preferred embodiment of the present invention, the N-type of the above-mentioned MOS wafer The depth of the extension region is greater than the depth of the N-type source region of the N-type drain.
依照本發明的一較佳實施例所述，在上述之金氧半 導體兀件中’更包括至少—N型摻雜區設置於該 深 井區中的基底中。 由於本發明所提出的金氧半導體元件具有提供較高 電位的P餅區位於㈣源極、雜區與基底之間，而 得以降低閘極與源極_電位差以及祕與源極間的電 位差’故可達到降低電壓範圍與節省耗電量之目的。 另一方面 由於電壓範圍降低，故本發明所提出的 金氧半導體元件設計之祕可較為寬鬆，元件之間的間 隔距離(pitd!)亦得崎減輪彳、元㈣局_。本發 金氧半導體元件中，更設置了 N型深井區以確保 ，性格離本發雜減壓範_錢半導體元件與 南壓半導體元件。 、八 此外’本發明之金氧半導體元件㈣造方法可輕易 正。至現打的互補式金氡半導體電晶體製程（CMOS ΡΠ)叫或雙擴散金氧半電晶體製程_〇S p_ss)中進 無需增加光罩即可完成本發0_金氧半導體元件結 構’因此不會增加額外的成本。 7 201025600 UMCD-2007-0547 27235twf.doc/n 為讓本發明之上述和其他目的、特徵和優點能更明 顯易Ιϊ，下文特舉較佳實施例，並配合所附圖式，作詳 細說明如下。 【實施方式】 圖1A〜圖1D所繪示為本發明一實施例之金氧半導體 電晶體元件的製造流程剖面圖。 請參照圖1A，首先提供一基底1〇〇。基底1〇〇例如 疋P型矽基底。接著’於基底100中形成N型深井區1〇2。 N型味井區1〇2的形成方法例如是以磷為摻質進行一個 離子植入製程而形成之。之後，於N型深井區1〇2中形 成P型井區104，且P型井區1〇4係被N型深井區1〇2 包圍。P型井區104的形成方法例如是以硼為摻質進行一 個離子植入製程而形成之。 並且，於N型深井區1〇2及p型井區中形成隔 離、、’。構101與103。於此技術領域具有通常知識者可輕易 得知，只要是可用以隔離的結構及材料均可應用於本發 • 明的隔離結構101 ’舉例來說，隔離結構101/103例如是 利用熱氧化法所形成的場氧化層或淺溝渠隔離結構，隔 離結構101/103的材質例如是氧化石夕。 然後，請參照圖1B，於基底100上形成閘極結構 110。閘極結構110為一堆疊結構包括閘介電層lu與多 晶矽閘極112。閘極110的形成方法例如是以熱氧化法形 成-氧化石夕層（未圖示）’並以臨場摻雜的化學氣相沈積製 程形成摻雜多晶矽層（未圖示），再進行微影及蝕刻製程而 形成。P遗後，可以閘極結構110作為罩幕，而於閑極結 8 201025600 UMCD-2007-0547 27235twf.doc/n 構uo之兩側與離隔離結構1G1之間各形成—N型 區106 °N型延伸區106係位於p型井區1〇4巾。N型延 伸區106的形成方法例如是以N型離子如鱗 而利用雙重摻雜程㈣成之。由於_極結構u(；作 為罩幕，所形成的N型延輕1% —般騎齊於閉極結 構110之關’但S，N型延伸區1〇6，亦可依照設計^ 要’以例如回火趨人之方式而向賴雜延伸出去 其部份位於閘極結構11〇與/或隔離結構1〇1之下方。 繼之’請參照1C ’於閘極110的側壁上形成間隙辟 120。間隙壁120的材質例如是氮切。間隙壁的形 成方法例如是纽基底⑽上形成—_壁材料層(未二 示），再進行-個贿刻製程而形成之。然後，可以閉^ 結構11Q與間隙壁12〇共同作為罩幕，而於間極結構m 上間隙壁120之兩侧與離隔離結構1〇1之間各形成一 n 型没極區⑽與-N型源極㊣_，而j_N^極區1〇8 與N型源極區1〇9是位於]^型延伸區1〇6之中而被^^ 延伸區106所包圍。 N型淡極區1〇8與N型源極區贈是鄰接至兩側隔 離結構1G1，但是亦可依電性設計需要㈣微側向延伸至 隔離結構ιοί下方一點。基本上，N型延伸區1〇6的深 度與範圍係大於N型汲極區108與N型源極區1〇9，但 N型延伸區1〇6摻雜濃度平均小於N型源/沒極區的摻雜 濃度。舉例而言，N型汲極區108或]^型源極區1〇9的 摻雜濃度例如約為l〇14_l〇i7cm-3。 選擇性地，在N型深井區102中遠離閘極11〇之兩 201025600 UMCD-2007-0547 27235twf.doc/nIn accordance with a preferred embodiment of the present invention, in the above-described metal oxide semiconductor element, a further comprising at least an N-type doped region is disposed in the substrate in the deep well region. Since the MOS device of the present invention has a P-cake region providing a higher potential between the (four) source, the impurity region and the substrate, the gate-source-potential difference and the potential difference between the source and the source are reduced. Therefore, the purpose of reducing the voltage range and saving power consumption can be achieved. On the other hand, since the voltage range is lowered, the secret of the design of the MOS device proposed by the present invention is relatively loose, and the distance between the components (pitd!) is also reduced by the rim and the quaternary (four). In the MOS device, an N-type deep well region is further provided to ensure that the character is different from the present invention. Further, the method of manufacturing the MOS device of the present invention can be easily performed. To the current complementary metal-iridium semiconductor transistor process (CMOS ΡΠ) or double-diffused MOS transistor process _〇S p_ss) can be completed without adding a mask to complete the 0_ MOS device structure Therefore no additional costs will be added. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the appended claims. . [Embodiment] FIG. 1A to FIG. 1D are cross-sectional views showing a manufacturing process of a MOS transistor according to an embodiment of the present invention. Referring to FIG. 1A, a substrate 1 is first provided. The substrate 1 is, for example, a P-type germanium substrate. Next, an N-type deep well region 1〇2 is formed in the substrate 100. The formation method of the N-type well zone 1〇2 is formed, for example, by an ion implantation process using phosphorus as a dopant. Thereafter, a P-type well region 104 is formed in the N-type deep well area 1〇2, and the P-type well area 1〇4 system is surrounded by the N-type deep well area 1〇2. The formation method of the P-type well region 104 is formed, for example, by performing an ion implantation process using boron as a dopant. Further, an isolation, " is formed in the N-type deep well area 1〇2 and the p-type well area. Structures 101 and 103. It is readily known to those skilled in the art that as long as the structure and materials that can be used for isolation can be applied to the isolation structure 101 of the present invention, for example, the isolation structure 101/103 utilizes, for example, thermal oxidation. The field oxide layer or the shallow trench isolation structure is formed, and the material of the isolation structure 101/103 is, for example, oxidized stone. Then, referring to FIG. 1B, a gate structure 110 is formed on the substrate 100. The gate structure 110 is a stacked structure including a gate dielectric layer lu and a polysilicon gate 112. The gate electrode 110 is formed by, for example, forming a oxidized stone layer (not shown) by thermal oxidation and forming a doped polysilicon layer (not shown) by a field-doped chemical vapor deposition process, and then performing lithography. And an etching process is formed. After the P, the gate structure 110 can be used as a mask, and the idle pole junction 8 201025600 UMCD-2007-0547 27235twf.doc/n is formed on both sides of the uo and the isolation structure 1G1 - the N-type region 106 ° The N-type extension 106 is located in the p-well zone 1 〇 4 towel. The formation method of the N-type extension region 106 is, for example, a double doping process (IV) using N-type ions such as scales. Due to the _ pole structure u (; as a mask, the N-type extension is 1% lighter than the closed-pole structure 110's but the S, N-type extension 1〇6, can also be designed according to the design Extending to the lag in a manner such as tempering, the portion thereof is located below the gate structure 11 〇 and/or the isolation structure 1 〇 1. Following 'Please refer to 1 C ' to form a gap on the sidewall of the gate 110 120. The material of the spacer 120 is, for example, nitrogen cutting. The method for forming the spacer is formed, for example, by forming a layer of -wall material (not shown) on the base substrate (10), and then forming a bribery process. Then, The closed structure 11Q and the spacer 12 are collectively used as a mask, and an n-type non-polar region (10) and a -N source are formed between the two sides of the spacer 120 on the interpole structure m and the isolation structure 1〇1. The positive positive _, and the j_N^ polar region 1〇8 and the N-type source region 1〇9 are located in the extension region 1〇6 and surrounded by the ^^ extension region 106. N-type pale-polar region 1〇 The 8 and N-type source regions are adjacent to the isolation structure 1G1 on both sides, but can also be extended according to the electrical design (4) to extend slightly below the isolation structure ιοί. Basically, the N-type extension The depth and range of the region 1〇6 are larger than the N-type drain region 108 and the N-type source region 1〇9, but the doping concentration of the N-type extension region 1〇6 is smaller than the doping concentration of the N-type source/no-polar region. For example, the doping concentration of the N-type drain region 108 or the source region 1〇9 is, for example, about l〇14_l〇i7cm-3. Optionally, away from the gate in the N-type deep well region 102. 11〇2 201025600 UMCD-2007-0547 27235twf.doc/n
側更可利關-群步卵時形成N 型摻雜區m的形嫌例如是以鱗為二二： 子植入製程而形成之，而深度約等於刑丁個離 10獅9之深度。N型摻雜區122例如= 及極/源極區 可透過該些外接職杨VDD (=為外接端點’ 至N型深井區⑽以幫助電性隔離。為錢電源襲） 再者，請參照圖1D，於遠離閘極u〇 與103之間的p型井區财帽成-P型摻雜 3雜r24的形成方法例如是以，為換：： 108/109之沬度。p型摻雜區124例如可 上述各型井區或摻雜區之形成步驟僅是;:接= ==域具有普通知識者可輕易推知，該順序 f步驟均可視元件設収製程需要更改。而上述金氧= ¥體兀件的製造方法可與現行的CMQS製料行整$ j增加光罩即可製造出本發明的金氧半導體元件: 案，、施例中乃是舉NM〇S元件作為例子，但並非限 案之製造方法僅限於此。 圖2A所緣示為本發明一實施例之金氧半導體元件 的剖面示意圖。圖2B所繪示為本發明一實施例之金氧 導體元件的部份上視示意圖。 π參照圖2A&2B，本發明的金氧半導體元件1〇例 如為NMOS包括基底100、Ν型深井區1〇2、ρ型井區 104、隔離結構101與103、閘極110與間隙壁120、Ν 型延伸區106、Ν型汲極區108、Ν型源極區109及ρ型 201025600 UMCU-2007-0547 27235twf.doc/n 摻雜區124。 從圖2B來看，主要係對應顯示圖2A中閘極ιι〇、Ν 型延伸區106、N型汲極區1〇8與n型源極區1〇9之相對 位置，隔離結構101與1〇3所定義出的主動區域2〇乃以 實線表示之。閘極結構110設置於基底1〇〇上，N型汲 極區108、N型源極區1〇9分設置於閘極結構n〇兩侧基 底中而鄰接隔離結構101，而N型延伸區106分位於閘The side is more pleasing - the formation of the N-type doping region m when the group of eggs is formed, for example, is formed by the scale of the two-part: sub-implantation process, and the depth is about equal to the depth of the lion. The N-type doping region 122, for example, and the pole/source region can pass through the external YANG VDD (= is an external terminal ' to the N-type deep well region (10) to help electrically isolate. For the power supply attack) Referring to FIG. 1D, the formation method of the p-type well region of the p-type well region away from the gates 〇 and 103 is, for example, a conversion of: 108/109. The p-type doping region 124 can be formed, for example, by the above-mentioned various types of well regions or doped regions; the connection === domain can be easily inferred by those having ordinary knowledge, and the sequence f steps can be changed according to the component setting process. The above method of manufacturing the gold oxide = ¥ body member can be used to manufacture the MOS device of the present invention by adding a mask to the current CMQS material preparation line: In the case, the example is NM〇S The components are taken as examples, but the manufacturing methods that are not limited are limited to this. Fig. 2A is a schematic cross-sectional view showing a MOS device according to an embodiment of the present invention. 2B is a partial top plan view of a gold oxide conductor element in accordance with an embodiment of the present invention. Referring to FIGS. 2A & 2B, the MOS device 1 of the present invention includes, for example, an NMOS including a substrate 100, a 深-type deep well region 1, 2, a p-type well region 104, isolation structures 101 and 103, a gate 110 and a spacer 120. Ν-type extension region 106, Ν-type drain region 108, Ν-type source region 109, and p-type 201025600 UMCU-2007-0547 27235 twf.doc/n doped region 124. 2B, the main position corresponds to the relative position of the gate ιι〇, the 延伸-type extension 106, the N-type drain region 1〇8 and the n-type source region 1〇9 in FIG. 2A, and the isolation structures 101 and 1 The active area 2 defined by 〇3 is indicated by a solid line. The gate structure 110 is disposed on the substrate 1 , and the N-type drain region 108 and the N-type source region 1〇9 are disposed in the substrate on both sides of the gate structure n〇 adjacent to the isolation structure 101, and the N-type extension region 106 points in the gate
極結構11〇兩侧棊底中、位於N型汲極區1〇8 N型源極 區109之下方且包圍n型汲極區1〇8、n型源極區1〇9。 N型沒極區刪、N型源極區1〇9並設置有接點(c〇n 130。 如圖2A所示，於遠離閘極11〇與隔離結構1〇1盥 103之間的P型井區104中具有p型摻雜區124，而基^ 100中的P型井區104包圍住N型延伸區1〇6、N型汲極 區108、N型源極區109與P型掺雜區124。此外，基底 1〇〇中的N型深井區1〇2完全包圍住j>型井區1〇4，而電 性上將P型井區104與基底100中的其他元件分隔開來。 對照於一般高壓NMOS元件電性操作模式，將源極 與基體接地GND而閘極與汲極電位為VDD (在此為系 統電源電壓）之情況，本發明之金氧半導體元件因具有p 型輕摻雜井區104而提高基體電位（p型井區可視為 NMOS的基體(bulk)而電位例如約為1/2VDD)，則N型 源，區109與P型摻雜區124之電位均為約1/2VDD，而 使得N型源極區1〇9與閘極ho之電位差降為1/2VDD， N型沒極區1〇8與n型源極區丨之電位差降為 11 201025600 UMCD-2007-0547 27235twf.doc/n 1/2VDD、而N型汲極區108與])型井區1〇4之電位差也 降為 1/2VDD。 因此本發明實施例之金氧半導體結構設計可降低工 作電壓（約從高電壓工作範圍降至中電壓工作範圍）， 並進而達到節省耗電量之目的。此外，因為降低電壓範 圍而使得元件設計之規格較為寬鬆，故元件之間的間隔 距離__得以縮減，進而幫助縮小元件佈局面積。 一时本發明之金氧半導體元件可取代部份設置於液晶顯 • 4 LCD驅動器積體電路中之-般高電壓元件，而達到 降低耗電量與節能之目的。 本發明金氧半導體元件中各膜層的材質與形成方 法，以及各摻雜區的形成方法已於前述金氧半導體元件 的製造方法中詳細介紹，於此不再贅述。 由於本發明所提出之金氧半導體元件的製造方法能 與現行的CMOS製程進行整合，*需要增加光罩即可製 造出本發_錢半導體元件，因此科增加額外的成 ❹ 本因此本案之金氧半導體元件可以與高壓元件區域 中之其他一般高壓元件—起製造；但是，本發明的金 半導體it件結構中，因為具有較高電位的p型丼區，因 此能有效降低工作電壓範圍並減少耗電量，而且，本 明的金氧半導體元件更可_ N魏井區而與不同^ 之其他高壓元件達到電性隔離。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和軏圍内，當可作些許之更動與潤飾，因此本發明 12 201025600 umcu-^007-0547 27235twf.doc/n 之保護範圍當視後附之申請專利範圍所界定者為準 【圖式簡單說明】 ’ 圖1A〜圖1D所繪示為本發明一實施例之金氧半 電晶體元件的製造流程剖面圖。 一 圖2Α所緣示為本發明一實施例之金氧车 _面$_。 斜物元件 圖2Β所繪示為本發明一實施例之金氧半導 部份上視示意圖。 70件的 【主要元件符號説明】 10 :金氧半導體元件 20 :主動區 100 ·基底 101、103 :隔離結構 102 : Ν型深井區 104 : Ρ型井區 106 : Ν型延伸區The pole structure 11 is located on the two sides of the bottom, located below the N-type drain region 109 of the N-type drain region and surrounds the n-type drain region 1〇8 and the n-type source region 1〇9. The N-type non-polar region is deleted, the N-type source region is 1〇9, and a contact is provided (c〇n 130. As shown in FIG. 2A, P between the gate 11〇 and the isolation structure 1〇1盥103 The well region 104 has a p-type doped region 124, and the P-well region 104 in the base 100 surrounds the N-type extension region 〇6, the N-type drain region 108, the N-type source region 109, and the P-type. Doped region 124. In addition, the N-type deep well region 1〇2 in the substrate 1〇〇 completely surrounds the j>-type well region 1〇4, and electrically divides the P-type well region 104 from other components in the substrate 100. Separated from the general high-voltage NMOS device electrical operation mode, the source and the substrate are grounded to GND and the gate and drain potentials are VDD (here, the system power supply voltage), and the MOS device of the present invention is With a p-type lightly doped well region 104 to increase the substrate potential (p-type well region can be considered as a bulk of NMOS and a potential is, for example, about 1/2 VDD), then N-type source, region 109 and P-type doped region 124 The potential is about 1/2 VDD, so that the potential difference between the N-type source region 1 〇 9 and the gate ho is reduced to 1/2 VDD, and the potential difference between the N-type non-polar region 1 〇 8 and the n-type source region 降 is 11 201025600 UMCD-2007-0547 27235twf. Doc/n 1/2VDD, and the potential difference between the N-type drain region 108 and the ]) well region 1〇4 is also reduced to 1/2 VDD. Therefore, the structure of the MOS structure of the embodiment of the present invention can reduce the working voltage (about from the high voltage working range to the medium voltage working range), and further achieve the purpose of saving power consumption. In addition, since the specification of the component design is looser because the voltage range is lowered, the distance __ between the components is reduced, thereby helping to reduce the layout area of the component. At the same time, the MOS device of the present invention can replace the high-voltage component which is partially disposed in the integrated circuit of the liquid crystal display 4 LCD driver, thereby achieving the purpose of reducing power consumption and saving energy. The material and formation method of each film layer in the MOS device of the present invention, and the method of forming each doped region have been described in detail in the above-described method for manufacturing a MOS device, and will not be described herein. Since the manufacturing method of the MOS device proposed by the present invention can be integrated with the current CMOS process, it is necessary to add a photomask to manufacture the semiconductor component of the present invention, so that the division adds an additional cost, so the gold of the case The oxygen semiconductor component can be fabricated together with other general high voltage components in the high voltage component region; however, in the gold semiconductor device structure of the present invention, since the p-type germanium region having a higher potential can effectively reduce the operating voltage range and reduce Power consumption, and, in addition, the MOS components of the present invention can be electrically isolated from other high voltage components of different sizes. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Invention 12 201025600 umcu-^007-0547 27235twf.doc/n The scope of protection is defined by the scope of the appended patent application. [FIG. 1A to FIG. 1D is an embodiment of the present invention. FIG. A cross-sectional view showing the manufacturing process of a gold-oxygen semi-transistor element. Figure 2 is a perspective view of a gold oxygen vehicle _ face $_ according to an embodiment of the present invention. Orthorect element Figure 2A is a top view of a portion of a gold-oxygen semiconductor portion according to an embodiment of the present invention. 70 pieces [Description of main component symbols] 10: MOS device 20: active region 100 · substrate 101, 103 : isolation structure 102 : 深 type deep well area 104 : Ρ type well area 106 : Ν type extension area
108 : Ν型汲極區 109 : Ν型源極區 110 :閘極 111 :閘介電層 112 :多晶矽閘極 120 :間隙壁 122 : Ν型摻雜區 124 : Ρ型摻雜區 130 :接點 13108: Ν-type drain region 109: Ν-type source region 110: gate 111: gate dielectric layer 112: polysilicon gate 120: spacer 122: Ν-type doping region 124: Ρ-type doping region 130: Point 13