201021658 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種具有嵌埋線路結構之電路板及其製 法，尤指一種具有细線距/線寬且表面均勻性佳之嵌埋線路 5 結構之電路板及其製法。 【先前技術】 > 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功 能、高性能的研發趨勢。為滿足半導體裝置高積集度 10 (Integration)及微型化（Miniaturization)的封裳需求，以供更 多主、被動元件及線路載接，承載半導體晶片之封裝基板 亦逐漸由雙層板演變成多層板（Multi-layer board)，俾在有 限的空間下，運用層間連接技術（Interlayer connection)來擴 大電路板上可供利用的線路佈局面積，藉此配合高線路密 15 度之積體電路（Integrated circuit)需要。 為符合半導體封裝件輕薄短小、多功能、高速度、高201021658 VI. Description of the Invention: [Technical Field] The present invention relates to a circuit board having an embedded circuit structure and a method of fabricating the same, and more particularly to an embedded circuit 5 structure having fine line pitch/line width and good surface uniformity. The circuit board and its method of manufacture. [Prior Art] > With the rapid development of the electronics industry, electronic products have gradually entered a multi-functional, high-performance research and development trend. In order to meet the requirements of high integration and miniaturization of semiconductor devices for more active and passive components and lines, the package substrate carrying semiconductor wafers has gradually evolved from double-layer boards. Multi-layer board, which uses Interlayer connection to expand the layout area available on the board in a limited space, so as to match the high line capacitance of 15 degrees. Integrated circuit). In order to meet the requirements of semiconductor package, light, short, versatile, high speed, high
I 線路密度及高頻化的開發方向，封裝基板已朝向細線路及 小孔徑發展。現有半導體封裝基板製程從傳統100微米之線 路尺寸，已縮減至現在的30微米以下，其中，包括導線寬 20 度（line width)及線路間距（space)等持續朝向更小的線路精 度進行研發。 為提高半導體封裝基板之佈線精密度，業界發展出一 種增層技術（built-up)，亦即在一電路板（circuit board)表面_ 利用線路增層技術交互堆疊多層介電層及線路層，並於該 4 201021658 ’I電層中開導電盲孔（c〇nductive via)以供上、下層線路之 間電性連接，而該線路增層製程係影響半導體封裝基 路密度的關鍵。 5 10 15 20 請參見圖1A至1E，係採用一例如半加成法 (Senn-addltlVeprocess，SAp)之線路增層製程。首先，如圖 1A所示，提供一表面具有第一線路層μ承載板ι〇;接著， 如圖靖示，於該承載板1〇上形成—第一介電層2〇，並利 用雷射鑽孔(Laser dHlling)等技術，於該第—介電層2〇中形 成盲孔21 ’以顯露出該承載板10上之第一線路層11;隨後， 如㈣所示，於該第-介電層2〇上以無電解鍵銅方式形成 -導電層30’且於該導電層3〇上形成一阻層4〇，而該阻層 40中形成有開槽區41，簡露出該導電層3Q之部份表面； 之後’如圖1D所示，藉由該導電層3()，於該阻層4〇之開槽 區41中電鍍形成第二線路層5〇a，且於該第一介電声之盲 孔2!中形斜電盲孔5%，以電性連接該承載板^之第一 線路層11 ;最後，如圖1E所示，移除該阻層及其所覆蓋之 導電層30。如此重複上述製程以形成介電層及線路層，即 可製成一具有多層線路之電路板。 惟’當電路板線路持續朝向更細小的線路精度發展 時’線路之厚度亦必須相對增加。據此，於半加成法之線 路增層製程中，必須形成具有足夠厚度之阻層’以利後續 形成八有足夠厚度之線路；然而，當阻層厚度增加時，易 發生阻層倒塌等問題，因而使半加成法之線路增層製程有 5 201021658 不易製作细線距/線寬之問題’同時，其線路厚度亦因此有 所限制。 5 10 15I Development direction of line density and high frequency, the package substrate has developed towards thin lines and small apertures. The existing semiconductor package substrate process has been reduced from the conventional 100 micron line size to the current 30 micron or less, including wire width and line spacing, which are continuously developed toward smaller line precision. In order to improve the wiring precision of the semiconductor package substrate, the industry has developed a built-up, that is, on a circuit board surface _ using a line build-up technology to alternately stack a plurality of dielectric layers and circuit layers, And in the 4 201021658 'I electrical layer open conductive hole (c〇nductive via) for the electrical connection between the upper and lower lines, and the line build-up process is the key to affect the semiconductor package base density. 5 10 15 20 Referring to Figures 1A through 1E, a line build-up process such as semi-additive (Senn-addltl Veprocess, SAp) is employed. First, as shown in FIG. 1A, a surface is provided with a first circuit layer μ carrier plate ι; then, as shown in the figure, a first dielectric layer 2 is formed on the carrier plate 1 and a laser is used. a technique such as drilling dHlling, in which a blind via 21' is formed in the first dielectric layer 2 to expose the first wiring layer 11 on the carrier 10; and then, as shown in (d), in the first A conductive layer 30' is formed on the dielectric layer 2, and a resist layer 4' is formed on the conductive layer 3, and a recessed region 41 is formed in the resist layer 40 to reveal the conductive a portion of the surface of the layer 3Q; then, as shown in FIG. 1D, a second wiring layer 5〇a is formed by plating in the trench region 41 of the resist layer 4 by the conductive layer 3(), and a dielectric blind hole 2! The medium-shaped oblique electric blind hole 5% is electrically connected to the first circuit layer 11 of the carrier board; finally, as shown in FIG. 1E, the resist layer is removed and covered Conductive layer 30. By repeating the above process to form a dielectric layer and a wiring layer, a circuit board having a multilayer wiring can be fabricated. However, the thickness of the line must also increase relatively as the circuit board continues to develop toward smaller line accuracy. Accordingly, in the line build-up process of the semi-additive method, a resist layer having a sufficient thickness must be formed to facilitate subsequent formation of a line having a sufficient thickness; however, when the thickness of the resist layer is increased, the resist layer collapses easily. The problem is that the semi-additive line build-up process has 5 201021658 and it is not easy to make the problem of fine line pitch/line width. At the same time, the thickness of the line is limited. 5 10 15
20 另一方面，業界亦發展一種嵌埋線路之線路增層方 法’請參見圖2A至2E。首先’如圖2A所示，提供一表面具 有第一線路層11之承載板10 ;接著，如圖2B所示，於該承 載板10上形成一第一介電層20,並於該第一介電層2〇中形 成一開槽區22及對應該開槽區22之複數盲孔21，以顯露出 該承載板10上之第一線路層11部份表面；隨後，如圖2匸所 示，於第一介電層20表面、第一線路層u之部份表面、該 開槽區22及該些盲孔21之内壁表面，形成一導電層％ ;之 後，如圖2D所示，藉由該導電層3〇,形成一金屬層5〇，以 覆蓋第一介電層20表面、開槽區22及盲孔21 ;最後，如圖 2E所不，以蝕刻或刷磨的方式，移除高度高於第一介電層 2〇表面之金屬層及導電層，以於開槽區22及盲孔2ι中分別 开’成第二線路層50a及導電盲孔5〇b。 因上述嵌埋線路之線路增層製程無需形成阻層，因此 不會有阻層倒塌等製程問題，適於製作细線距/線寬，且其 線路無厚度限制，可依客戶需求製作。然而，該製程於移 除=屬層㈣程中，由於不易均句移除未作為線路層及導 電盲孔之金屬| ’而使得線路層之表面均勻性不佳及厚产 1低不均的問題，如圖2E所示。尤其在大面積生產電路: 因金屬層移除不一致而導致線路表面均勻性不佳及厚 :::不均的問題更加嚴重。因此，目前虽需發展出一種 法，以改善上述習知製作線路之問題，並同時能簡 6 201021658 = ==:=板：速且大面積的生產具有良 【發明内容】 5 ❿ 10 15 ❹ 雷=發Γ之主要目的係在提供—種具有嵌埋線路結構之 電路板’其線路係經由直接鑛及化學鑛製程而形成於介電 ^中点藉此，線路可根據需求而製作為不同結構及金屬材 枓組成R時，藉由直接鍍及化學鑛製作線路於介電層中 可達成半加成法（SAP)無法生產之细線路設計，且可解決習 知嵌埋線路製法中之回咬（eteh_baek)製程所造成之線路表 面均勻性不佳及厚度高低不均問題。 為達成上述目的，本發明提供一種具有嵌埋線路結構 之電路板’包括一承載板，其至少一表面具有第一線路 層；一第一介電層，係設於承載板上，且具有一開槽區及 複數盲孔，其中該些盲孔係對應設置於該開槽區部分位 置，且貫穿第一介電層，以顯露該第一線路層之部份表面； 以及一金屬鍍層，係具有分別嵌埋於該開槽區及該些盲孔 中之第二線路層及複數第一導電盲孔，其中，第二線路層 係藉由該些第一導電盲孔而與第一線路層電性連接，而金 屬鍍層具有一直接艘把層、一化鍍金屬層及一化鍍鈀層， 直接鍵把層係設於開槽區及盲孔之内壁表面，化鑛金屬層 係設於直接鑛把層上，且填充開槽區及盲孔，化鍵纪層則 係設於化鑛金屬層上。在此’化鍍鈀層可提高金屬鍍層之 20 201021658 接點可靠度，解決化鍍金屬層因組成材料易碎所造成之接 點脆弱之問題。 此外’當欲於該電路板之第二線路層上接置電性連接 結構時，本發明之電路板更可包括一化鍍銅層於該化鍍鈀 5層上，以作為電性連接之界面；而當該電路板之第二線路 層係為結構表面時，為改善表面氧化所導致可靠度下降之 問題，本發明之電路板更可包括一化鍍金層於該化鍍鈀層 上’以保護化鑛纪層表面。 參 於本發明之具有嵌埋線路結構之電路板申，該承載板 10 可為一絕緣板或具有多層線路之電路板》 於本發明之具有嵌埋線路转構之電路板中，該化鍍金 屬層可由一種或不同金屬材料所構成，舉例而言該化鍍 金屬層可為一化鍍鎳層或由依序設於直接鍍鈀層上之一化 鍵銅層及一化鑛錄層所構成。 15 此外，本發明更提供一種製作上述電路板之方法，包 括.提供-承載板，其至少—表面具有第一線路層；形成 〇 —第一介電層於承載板上’其中第-介電層具有-開槽區 及複數盲孔’ a些盲孔係對應該形成於該開槽區開槽區部 分位置’且貫穿該第-介電層，以顯露第一線路層之部份 20表面；以及形成一金屬錢層於該開槽區及該些盲孔中，以 分別形成第二線路層及複數第一導電盲孔於該開槽區及該 些盲孔中，其中，第二線路層係藉由該些第一導電盲孔而 與第線路層電14連接’而金屬鍵層具有—直接錄把層、 -化鍍金屬層及-化鍍鈀層，直接鍍鈀層係形成於開槽區 201021658 及盲孔之内壁表面，化鍍金屬層係形成於直接鍍鈀層上， 且填充該開槽區及該些盲孔，而化舰層則係形成於化鍵 金屬層上。 於本發明之具有嵌埋線路結構之電路板及其製法中， 5復可包括-線路增層結構於該第一介電層及該金屬鐘層之 表面其中該線路增層結構係包括至少一第二介電層、至 ’’嵌埋於弟一介電層之第三線路層、及配置於第二介電 I中之複數第二導電盲孔’且該第三線路層係藉由：些第 二導電盲孔而與該金歧層電性連接。在此，線路增層結 10構最外層之第三線路層可具有複數電性接觸墊。 於本發明之具有嵌埋線路結構之電路板及其製法中， 復可包括一防焊層於線路增層結構之表面，其中防焊層具 有複數防焊層開孔，俾以顯露該些電性接觸墊。 據此，由於上述方法係藉由直接鍍及化學鍍直接於介 15電層中形成線路，其無需經由回咬製程，故可避免回咬製 料成線路層表面均勻性不佳及厚度高低不均之問題，同 _ 冑’由於上述方法係直接形成線路層於介電層中，故可避 免S知半加成法於製作细線路時所發生之阻層倒塌之問 題，解決半加成法不易製作细線路及線路厚度受限之缺失。 20 於本發明之電路板製法中，可藉由一遮蔽層，以控制 直接鍍鈀層僅形成於開槽區及盲孔之内壁表面。詳細地 說，可於形成直接鍍鈀層之前，先形成一遮蔽層（例如為一 ，層）於第一介電層表面，並顯露該開槽區及該些盲孔，接 著再形成直接鍍鈀層於該遮蔽層之表面、開槽區及盲孔之 201021658 内壁表面’最後再將該遮蔽層及覆蓋其上之直接鍍鈀層移 除’以使直接鍍鈀層僅形成於開槽區及盲孔之内壁表面。 或者’亦可藉由粗糙化製程，使第一介電層之開槽區及盲 孔内壁表面為一粗糙面，據此，直接鍍鈀層便僅形成於開 5 槽Q及盲孔之内壁表面。 本發明之電路板製法更可包括：形成一化鍍銅層於該 化鍍鈀層上，藉此，該化鍍銅層可作為接置電性連接結構 之界面。或者，本發明之電路板製法更可包括：形成一化 ❿ 鍍金層於該化鑛鈀層上，藉此，該化鍍金層可避免結構表 10 面氧化所導致可靠度下降之問題。 综上所述’本發明係藉由直接鍍及化學鍍製程形成線 路於介電層中，據此’本發明可根據需求生產不同結構及 金屬材料之線路。尤其，本發明所提供之製法無需回咬製 程，故可解決回咬製程導致線路層表面均勻性不佳及厚度 15 高低不均之問題，進而提高後續電路板製造良率。同時， 本發明所提供之製法適於製作细線路，且無線路厚度受限 ® 之問題，因而解決習知半加成法（SAP)不易製作细線路及線 路厚度受限之缺失。 2〇 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式’熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不门 的具體實施例加以施行或應用，本說明書中的各項細節亦 201021658 可基於不同觀點與應用，在不悖離本發明之精神下進行各 種修飾與變更。 實施例1 請參考圖3A至圖3F，係本實施例之具有嵌埋線路結構 5 之電路板製法流程示意圖。 首先，如圖3A所示，提供一承載板1〇，其至少一表面 具有第一線路層11。在此，該承載板1〇可為一絕緣板或具 有多層線路之電路板，而於本實施例中，該承載板1〇係為 • 一絕緣板。 10 接著，如圖3B所示，形成一第一介電層20於該承載板 10上，其中，該第一介電層2〇係藉由雷射鑽孔、電漿蝕刻、 或反應式離子蝕刻（RIE)等方式形成有一開槽區22及複數盲 孔21 ’而該些盲孔21係對應形成於該開槽區22部分位置， 且貫穿該第一介電層2〇,以顯露該第一線路層丨〗之部份表 15 面。 如圖3C所示’形成一遮蔽層7〇於該第一介電層2〇之表 Ο 面，並顯露該開槽區22及該些盲孔21，於本實施例中，該 遮蔽層70係為一薄銅層。之後，如圖3D所示，藉由直接鍍 製程’形成一直接鍍鈀層61於遮蔽層70表面、開槽區22及 20 盲孔21之内壁表面；隨後，再移除該遮蔽層及覆蓋其上之 直接銀把層61 ’如圖3E所示。據此，僅有開槽區22及盲孔 21之内壁表面形成有直接鍍鈀層61。 此外’本實施例亦提供另一實施態樣，其係於第一介 電層20形成有開槽區22及盲孔21後，再藉由粗糙化製程， 201021658 使開槽區22及盲孔21之内壁表面為粗糙面，如此便可直接 控制直接鑛纪層61僅形成於開槽區22及盲孔21之内壁表 面。 5 10 15 ❹ 20 最後，如圖3F所示’藉由化學鍍製程，依序形成一化 鑛金屬層62及一化鑛把層63於開槽區22及該些盲孔21中之 直接鍍鈀層61上，以分別形成第二線路層6〇a及複數第一導 電盲孔60b於該開槽區22及該些盲孔21中。於本實施例中， 該化鍍金屬層62係為化鍍鎳層62卜其係形成於該直接鍍鈀 層61上’且填充該開槽區22及盲孔21，而化鍍鈀層63係形 成於化鍍金屬層62上。在此’由於化鍵錄層621有接點易碎 之問題’因此’形成該化鐘纪層63於化艘鎳層621上可提高 接點可靠度。 據此’如圖3F所示’本實施例提供一種具有喪埋線路 結構之電路板，其包括：一承載板1〇，其至少一表面具有 第一線路層11 ; 一第一介電層20,係設於承載板丨〇上，且 具有開槽區22及複數盲孔21，其中該些盲孔21係對應設置 於該開槽區22部分位置，且貫穿該第一介電層2〇,以顯露 第一線路層11之部份表面；以及一金屬鑛層6〇，係具有分 別嵌埋於該開槽區22及盲孔21中之第二線路層60a及複數 第一導電盲孔60b，其中，第二線路層60a係藉由該些第一 導電盲孔60b而與該第一線路層11電性連接，而該金屬鍍層 60具有一直接鍍鈀層61、一化鍍金屬層62及一化鍍鈀層 63 ’直接鍍鈀層61係設於開槽區22及該些盲孔21之内壁表 12 201021658 面’化鍍金屬層62係設於直接鍍鈀層61上，且填充開槽區 22及該些盲孔21 ’化鍍鈀層63則係設於化鍍金屬層62上。 實施例2 請參見圖4，係為本實施例之具有嵌埋線路結構之電路 5 板剖不圖。本實施例之電路板製法與實施例1所述製法大致 相同，惟不同處在於，本實施例之電路板更形成有一化鍍 金層601於該化鍍鈀層63上。據此，該化鍍金層6〇1可保護 結構表面’改善結構表面氧化所導致後續基板製造或封裝 • 製程可靠度下降之問題。 10 實施例3 請參見圖5 ’係為本實施例之具有嵌埋線路結構之電路 板剖示圖。本實施例之電路板製法與實施例1所述製法大致 相同’惟不同處在於，本實施例之化鍍金屬層62係由依序 形成之化鍍銅層622及化鍍鎳層621所構成，且本實施例之 15 電路板更形成有一化鍍銅層602於該化鍍鈀層63上，以作為 接置電性連接結構之界面。 〇 實施例4 請參見圖6 ’係為本實施例之具有嵌埋線路結構之電路 板剖示圖。本實施例之電路板製法與實施例1所述製法大致 20 相同，惟不同處在於，本實施例之電路板更形成有線路增 層結構80及防焊層90。詳細地說，該線路增層結構80係形 成於第一介電層20及該金屬鍍層60之表面，其包括至少一 第二介電層81、至少一嵌埋於第二介電層81之第三線路層 82、及配置於第二介電層81中之複數第二導電盲孔83，其 13 201021658 ” 60: 82係藉由該些第二導電盲孔83而與該金屬 二曰連接’以三線路層82具有複數電性接觸墊 =，此外’該防焊層觸形成於線路增層結構8q之表面， 5 10 15 複數防焊層開孔91，俾以顯露該線路增層結構80之 ^接觸塾82卜於本實财，該第三線路層82及該些第二 導電盲孔83之形成方法與上述第二線路層及第一導電盲孔 形成方法相同。 此’本發日月係藉由直接鍍及化學鍍製程形成線路於 介電層中，其可根據需求生產不同結構及金屬材料之線 路。尤其’本發明所提供之製法無需回咬製程，故可解決 回咬製程導致線路層表面均句性不佳及厚度高低不均之問 題’進而提高後續電路板製造良率。同時，本發明所提供 之製法適於製作细線路，且無線路厚度受限之問題。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以中請專利範圍所述為準，而非僅限 於上述實施例。 【圖式簡單說明】 圖1A至1E係習知半加成法之線路增層製程示意圖。 20 圖2A至2E係習知嵌埋線路之線路增層製程示意圖。 圖3A至3F係本發明一較佳實施例之具有嵌埋線路結構之 電路板製法流程示意圖。 圖4係本發明一較佳實施例之具有嵌埋線路結構之電路板 剖示圖。 14 201021658 圖5係本發明另一較佳實施例之具有嵌埋線路結構之電路 板剖示圖。 圖6係本發明另一較佳實施例之具有嵌埋線路結構之電路 板剖圖〇 520 On the other hand, the industry has also developed a line build-up method for embedded lines. See Figures 2A through 2E. First, as shown in FIG. 2A, a carrier board 10 having a first circuit layer 11 is provided; then, as shown in FIG. 2B, a first dielectric layer 20 is formed on the carrier board 10, and the first A slotted area 22 and a plurality of blind holes 21 corresponding to the slotted area 22 are formed in the dielectric layer 2 to expose a portion of the surface of the first circuit layer 11 on the carrier board 10; subsequently, as shown in FIG. It is shown that a conductive layer % is formed on the surface of the first dielectric layer 20, a part of the surface of the first circuit layer u, the grooved area 22 and the inner wall surfaces of the blind holes 21; then, as shown in FIG. 2D, A conductive layer 3 〇 is formed to form a metal layer 5 覆盖 to cover the surface of the first dielectric layer 20, the trench region 22 and the blind via 21; finally, as shown in FIG. 2E, by etching or brushing, The metal layer and the conductive layer having a height higher than the surface of the first dielectric layer 2 are removed to form a second wiring layer 50a and a conductive blind via 5b in the trench region 22 and the blind via 2, respectively. Since the line-adding process of the embedded line does not need to form a resist layer, there is no process problem such as collapse of the resist layer, and it is suitable for making a fine line pitch/line width, and the line has no thickness limitation, and can be manufactured according to customer requirements. However, in the process of removing = genus layer (four), the surface uniformity of the circuit layer is poor and the thickness of the circuit layer is low and uneven due to the difficulty in removing the metal which is not used as the circuit layer and the conductive blind hole. The problem is shown in Figure 2E. Especially in large-area production circuits: The problem of poor uniformity of the line surface and thick ::: unevenness due to inconsistent removal of the metal layer is more serious. Therefore, at present, it is necessary to develop a method to improve the above-mentioned conventional production line problem, and at the same time, it can be simplified. 201021658 = ==:= plate: speed and large area production has good [invention content] 5 ❿ 10 15 ❹ The main purpose of Ray=ΓΓ is to provide a circuit board with an embedded circuit structure. The circuit is formed at the midpoint of the dielectric through direct ore and chemical processes. The line can be made different according to the needs. When the structure and the metal material 枓 composition R, a thin circuit design which cannot be produced by the semi-additive method (SAP) can be achieved in the dielectric layer by direct plating and chemical ore production lines, and can be solved in the conventional embedded circuit manufacturing method. Back grounding (eteh_baek) process caused by poor surface uniformity and uneven thickness. In order to achieve the above object, the present invention provides a circuit board having an embedded circuit structure, including a carrier board having at least one surface having a first circuit layer, and a first dielectric layer disposed on the carrier board and having a a slotted area and a plurality of blind holes, wherein the blind holes are correspondingly disposed at a portion of the slotted portion and penetrate the first dielectric layer to expose a portion of the surface of the first circuit layer; and a metal plating layer The second circuit layer and the plurality of first conductive blind holes respectively embedded in the slotted area and the blind holes, wherein the second circuit layer is connected to the first circuit layer by the first conductive blind holes Electrically connected, and the metal plating layer has a direct handle layer, a metallization layer and a palladium layer, and the direct key layer is disposed on the surface of the grooved area and the inner wall of the blind hole, and the metallized metal layer is set on The direct ore layer is placed on the layer, and the grooved area and the blind hole are filled, and the chemical bond layer is disposed on the metallized metal layer. Here, the palladium plating layer can improve the contact reliability of the metal coating layer 20 201021658, and solve the problem that the metal plating layer is weak due to the brittleness of the constituent materials. In addition, when the electrical connection structure is to be connected to the second circuit layer of the circuit board, the circuit board of the present invention may further comprise a copper plating layer on the palladium plating layer 5 as an electrical connection. Interface; when the second circuit layer of the circuit board is a structural surface, in order to improve the reliability caused by surface oxidation, the circuit board of the present invention may further include a gold plating layer on the palladium plating layer. To protect the surface of the ore layer. In the circuit board with embedded circuit structure of the present invention, the carrier board 10 can be an insulating board or a circuit board having multiple layers of lines. In the circuit board with embedded circuit structure of the present invention, the plating is performed. The metal layer may be composed of one or different metal materials. For example, the metallization layer may be a nickel plating layer or a layer of a bond copper layer and a mineral layer sequentially disposed on the direct palladium layer. . Further, the present invention further provides a method of fabricating the above circuit board, comprising: providing a carrier board having at least a surface having a first wiring layer; forming a germanium - a first dielectric layer on the carrier board - wherein the first dielectric The layer has a slotted area and a plurality of blind holes 'a a pair of blind holes are formed at a portion of the slotted portion of the slotted portion and penetrates the first dielectric layer to expose a portion of the surface of the first circuit layer 20 And forming a metal money layer in the slotted area and the blind holes to respectively form a second circuit layer and a plurality of first conductive blind holes in the slotted area and the blind holes, wherein the second line The layer is connected to the first layer conductor 14 by the first conductive blind vias, and the metal bonding layer has a direct recording layer, a metallization layer and a palladium plating layer, and the direct palladium layer is formed on the layer. The grooved area 201021658 and the inner wall surface of the blind hole are formed on the direct palladium plating layer, and the grooved area and the blind holes are filled, and the chemical ship layer is formed on the chemical bond metal layer. In the circuit board having the embedded circuit structure of the present invention and the method of fabricating the same, the circuit may include a line build-up structure on the surface of the first dielectric layer and the metal clock layer, wherein the line build-up structure includes at least one a second dielectric layer, a plurality of second conductive vias embedded in the second dielectric layer, and a plurality of second conductive vias disposed in the second dielectric I and the third circuit layer is: The second conductive blind holes are electrically connected to the gold disparity layer. Here, the third circuit layer of the outermost layer of the line build-up layer structure may have a plurality of electrical contact pads. In the circuit board having the embedded circuit structure of the present invention and the manufacturing method thereof, the composite layer may include a solder resist layer on the surface of the line build-up structure, wherein the solder resist layer has a plurality of solder mask opening holes to expose the electricity Sexual contact pads. Accordingly, since the above method directly forms a circuit in the dielectric layer by direct plating and electroless plating, it does not need to pass through a back-biting process, so that the back-biting material can be prevented from forming a uniformity of the surface layer of the circuit layer and the thickness is not high. The problem of the same, the same as _ 胄 'Because the above method directly forms the circuit layer in the dielectric layer, it can avoid the problem of the collapse of the resist layer which occurs when the S-semi-additive method is used to make the fine line, and solve the semi-additive method. It is not easy to make thin lines and the lack of thickness of the line. In the circuit board manufacturing method of the present invention, the direct palladium plating layer can be formed only on the surface of the inner wall of the grooved portion and the blind hole by a shielding layer. In detail, before forming a direct palladium plating layer, a shielding layer (for example, a layer) may be formed on the surface of the first dielectric layer, and the grooved region and the blind holes may be exposed, and then direct plating may be formed. The palladium layer on the surface of the shielding layer, the grooved area and the surface of the inner wall of the blind hole 201021658 'finally remove the shielding layer and the direct palladium layer covering thereon' so that the direct palladium layer is formed only in the grooved area And the inner wall surface of the blind hole. Or 'the roughening process can also make the grooved area of the first dielectric layer and the inner surface of the blind hole a rough surface, according to which the direct palladium layer is formed only on the inner wall of the open 5 slot Q and the blind hole. surface. The circuit board manufacturing method of the present invention may further comprise: forming a copper plating layer on the palladium plating layer, whereby the copper plating layer serves as an interface for attaching the electrical connection structure. Alternatively, the circuit board manufacturing method of the present invention may further comprise: forming a ruthenium-plated gold layer on the palladium layer of the ore, whereby the gold plating layer can avoid the problem of reliability degradation caused by oxidation of the surface of the structure. In summary, the present invention forms a line in a dielectric layer by direct plating and electroless plating, whereby the present invention can produce circuits of different structures and metal materials as needed. In particular, the method provided by the present invention does not require a bite process, so that the problem of poor uniformity of the surface of the circuit layer and unevenness of the thickness of the circuit layer can be solved by the bite process, thereby improving the subsequent board manufacturing yield. At the same time, the method provided by the present invention is suitable for making fine lines, and the problem of the thickness of the wireless path is limited, so that the conventional semi-additive method (SAP) is difficult to make thin lines and the thickness limitation of the line is limited. 2 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The present invention may be embodied or applied by other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention. Embodiment 1 Referring to FIG. 3A to FIG. 3F, a schematic diagram of a process for manufacturing a circuit board having an embedded circuit structure 5 according to this embodiment is shown. First, as shown in Fig. 3A, a carrier board 1 is provided having at least one surface having a first wiring layer 11. Here, the carrier board 1 can be an insulating board or a circuit board having a plurality of layers. In the embodiment, the carrier board 1 is an insulating board. 10, as shown in FIG. 3B, a first dielectric layer 20 is formed on the carrier 10, wherein the first dielectric layer 2 is laser-drilled, plasma-etched, or reactive. Etching (RIE) or the like to form a grooved region 22 and a plurality of blind holes 21', and the blind holes 21 are formed at a portion of the grooved portion 22, and penetrate the first dielectric layer 2〇 to reveal the Part 15 of the first circuit layer 丨. As shown in FIG. 3C, a masking layer 7 is formed on the surface of the first dielectric layer 2, and the slotted area 22 and the blind holes 21 are exposed. In this embodiment, the shielding layer 70 is formed. It is a thin copper layer. Thereafter, as shown in FIG. 3D, a direct palladium plating layer 61 is formed on the surface of the shielding layer 70, the inner wall surfaces of the grooved regions 22 and 20 blind holes 21 by a direct plating process; subsequently, the shielding layer and the covering are removed. The direct silver layer 61' thereon is shown in Figure 3E. Accordingly, only the surface of the inner wall of the grooved portion 22 and the blind hole 21 is formed with a direct palladium plating layer 61. In addition, this embodiment also provides another embodiment in which the first dielectric layer 20 is formed with the grooved region 22 and the blind hole 21, and then the grooved region 22 and the blind hole are formed by the roughening process, 201021658. The inner wall surface of 21 is a rough surface, so that the direct ore layer 61 can be directly controlled to be formed only on the inner wall surface of the grooved portion 22 and the blind hole 21. 5 10 15 ❹ 20 Finally, as shown in FIG. 3F, a direct plating of a metallized metal layer 62 and a mineralization layer 63 in the grooved region 22 and the blind holes 21 is sequentially formed by an electroless plating process. The palladium layer 61 is formed in the trench region 22 and the blind vias 21 to form a second wiring layer 6a and a plurality of first conductive vias 60b, respectively. In this embodiment, the metallization layer 62 is formed by depositing a nickel-plated layer 62 on the direct palladium-plated layer 61 and filling the grooved region 22 and the blind hole 21, and the palladium-plated layer 63 is formed. It is formed on the metallization layer 62. Here, the problem is that the contact key layer 621 has a problem that the contact is fragile, so that the formation of the chemical clock layer 63 on the nickel layer 621 can improve the contact reliability. According to this, as shown in FIG. 3F, the present embodiment provides a circuit board having a buried circuit structure, comprising: a carrier board having at least one surface having a first circuit layer 11; a first dielectric layer 20; The device is disposed on the carrier board and has a slotted area 22 and a plurality of blind holes 21, wherein the blind holes 21 are correspondingly disposed at a portion of the slotted area 22 and penetrate the first dielectric layer 2〇 a portion of the surface of the first circuit layer 11 is exposed; and a metal ore layer 6 is provided with a second circuit layer 60a and a plurality of first conductive blind holes respectively embedded in the slotted region 22 and the blind via 21 60b, wherein the second circuit layer 60a is electrically connected to the first circuit layer 11 by the first conductive blind vias 60b, and the metal plating layer 60 has a direct palladium plating layer 61 and a metallization layer. 62 and a palladium plating layer 63' The direct palladium plating layer 61 is disposed on the inner wall of the grooved portion 22 and the blind holes 21, and the surface of the metallization layer 62 is disposed on the direct palladium plating layer 61, and The filled grooved region 22 and the blind holes 21' of the palladium-plated layer 63 are provided on the metallization layer 62. Embodiment 2 Referring to FIG. 4, it is a circuit diagram of a circuit 5 having an embedded circuit structure of the present embodiment. The circuit board manufacturing method of this embodiment is substantially the same as that of the first embodiment, except that the circuit board of the present embodiment further forms a gold plating layer 601 on the palladium plating layer 63. Accordingly, the gold plating layer 6〇1 can protect the surface of the structure from improving the surface oxidation of the structure, resulting in subsequent substrate fabrication or packaging. 10 Embodiment 3 Referring to Figure 5 is a cross-sectional view of a circuit board having an embedded wiring structure of the present embodiment. The method for manufacturing the circuit board of the present embodiment is substantially the same as that of the first embodiment. The only difference is that the metallization layer 62 of the present embodiment is composed of a copper plating layer 622 and a nickel plating layer 621 which are sequentially formed. Moreover, the circuit board of the embodiment 15 further forms a copper plating layer 602 on the palladium-plated layer 63 to serve as an interface for the electrical connection structure.实施 Embodiment 4 Referring to Fig. 6 is a cross-sectional view of a circuit board having an embedded wiring structure of the present embodiment. The circuit board manufacturing method of this embodiment is substantially the same as that of the first embodiment, except that the circuit board of the present embodiment is further provided with a line build-up structure 80 and a solder resist layer 90. In detail, the line build-up structure 80 is formed on the surface of the first dielectric layer 20 and the metal plating layer 60, and includes at least one second dielectric layer 81 and at least one embedded in the second dielectric layer 81. a third circuit layer 82 and a plurality of second conductive blind vias 83 disposed in the second dielectric layer 81, wherein the 13 201021658 ” 60: 82 is connected to the metal via the second conductive vias 83 'The three-circuit layer 82 has a plurality of electrical contact pads =, in addition, the solder resist layer is formed on the surface of the line build-up structure 8q, 5 10 15 a plurality of solder resist openings 91, to reveal the line build-up structure The method of forming the third circuit layer 82 and the second conductive blind vias 83 is the same as the method for forming the second circuit layer and the first conductive blind vias. Sun and Moon form a circuit in the dielectric layer by direct plating and electroless plating process, which can produce different structures and metal material lines according to requirements. In particular, the method provided by the invention does not require a bite process, so the bite can be solved. The process leads to the poor uniformity of the surface of the circuit layer and the uneven thickness The problem is to further improve the subsequent board manufacturing yield. At the same time, the method provided by the present invention is suitable for making fine lines, and the thickness of the wireless path is limited. The above embodiments are merely examples for convenience of explanation, and the present invention claims The scope of the claims is based on the scope of the patent application, and is not limited to the above embodiments. [Simplified Schematic of the Drawings] Figures 1A to 1E are schematic diagrams of the circuit-adding process of the conventional semi-additive method. 20 Figure 2A 2A to 3F are schematic diagrams showing a process of manufacturing a circuit board having an embedded circuit structure according to a preferred embodiment of the present invention. FIG. 4 is a preferred embodiment of the present invention. FIG. 5 is a cross-sectional view of a circuit board having an embedded circuit structure according to another preferred embodiment of the present invention. FIG. 6 is another preferred embodiment of the present invention. Sectional view of a circuit board having an embedded circuit structure 〇 5
【主要元件符號說明】 10 承載板 20 第一介電層 22, 41 開槽區 40 阻層 5〇a, 60a 第二線路層 60 金屬鍵層 601 化鑛金層 61 直接鍍鈀層 621 化鍍鎳層 70 遮蔽層 81 第二介電層 821 電性接觸墊 90 防焊層 11 第一線路層 21 盲孔 30 導電層 50 金屬層 50b 導電盲孔 60b 第一導電盲孔 602, 622 化鍍銅層 62 化鑛金屬層 63 化链纪層 80 線路增層結構 82 第三線路層 83 第二導電盲孔 91 防焊層開孔 15[Main component symbol description] 10 carrier board 20 first dielectric layer 22, 41 slotted area 40 resistive layer 5〇a, 60a second wiring layer 60 metal bond layer 601 mineralized gold layer 61 direct palladium plating layer 621 plating Nickel layer 70 shielding layer 81 second dielectric layer 821 electrical contact pad 90 solder resist layer 11 first circuit layer 21 blind hole 30 conductive layer 50 metal layer 50b conductive blind hole 60b first conductive blind hole 602, 622 copper plating Layer 62 Mineralized Metal Layer 63 Chained Layer 80 Line Addition Structure 82 Third Circuit Layer 83 Second Conductive Blind Hole 91 Solder Mask Opening 15