TW201021640A - Coreless wiring substrate, semiconductor device and method of manufacturing the same - Google Patents

Coreless wiring substrate, semiconductor device and method of manufacturing the same Download PDF

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Publication number
TW201021640A
TW201021640A TW098124847A TW98124847A TW201021640A TW 201021640 A TW201021640 A TW 201021640A TW 098124847 A TW098124847 A TW 098124847A TW 98124847 A TW98124847 A TW 98124847A TW 201021640 A TW201021640 A TW 201021640A
Authority
TW
Taiwan
Prior art keywords
wiring
layer
via hole
electrode terminal
cross
Prior art date
Application number
TW098124847A
Other languages
Chinese (zh)
Other versions
TWI401000B (en
Inventor
Kentaro Mori
Shintaro Yamamichi
Hideki Sasaki
Daisuke Ohshima
Original Assignee
Nec Corp
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Publication date
Application filed by Nec Corp filed Critical Nec Corp
Publication of TW201021640A publication Critical patent/TW201021640A/en
Application granted granted Critical
Publication of TWI401000B publication Critical patent/TWI401000B/en

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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The present invention provides a coreless wiring substrate, semiconductor device and method of manufacturing the same with high yield and excellent reliability. A coreless wiring substrate 11 comprises: a plurality of laminated wiring layers and insulation layers; interconnections (17, 20 and 23) disposed on the wiring layers; vias (16, 19 and 22) disposed on the insulation layers and electrically connecting the upper and lower interconnections; a first electrode terminal 14 disposed on a first face, and a second electrode terminal 23 disposed on the opposite face. The pad pith of the first electrode terminal 14 is narrower than the pad pitch of the second electrode terminal 23; and the first electrode terminal 14 and the second electrode terminal 23 are electrically conducted through at least one of the interconnections or vias, and at least one of the vias or interconnections has a cross-sectional shape different from that of the vias or interconnections disposed on other insulation layers or wiring layers.

Description

201021640 六、發明說明： 【發明所屬之技術領域】 (關於相關申請案之記載) 7 a 士申清案主張先前的日本專利申請案2008-190101號(2_年 用1入1申)之優先權’前述先申請案之所有記_容，視為弓丨 用納入記載於本說明書。 本發明侧於無核心層基板及使用無核心層基板之半導體 置iif之製造綠。賴於多層無核心、層基板及制多層益核 心層基板之半導體裝置及其製造方法。 【先前技術】 近年來’電子設備要求小型化、高機能化、高性能化，因應 於此，半導體包裝體需要高密度構裝技術。以往，半導體 f 之^介基板主要使用具核心層之建成基板。但是，建成基板之貫 ^層孔(TH)、配、線寬相較於建成層之介層孔直徑、配線寬大了 ^倍’因此，其尺度差妨礙包裝體基板高速化、高密度微細配線 2、。且，於建成基板之單面，因為設置了在設計上不需要但是於 象造為防止翹曲之層，成為成本上升的要因。 、 ^以’為了實現半導體包裝體之高速化、高密度化及低成本 化，有人提出不具核心層之全層建成基板，即無核心層基板。 專利文獻1中，如圖11所示，記載：於端子接墊117之正上 方配置電元件連接祕墊115’藉由贱子接墊117往電元 用接墊115緩慢地使介層孔導體之直徑縮小，使得即使於上下之 介層孔導體之配置位置多少偏離時仍能提升連接可靠性之I核心 層配線基板。因此’端子接塾之間距與電元件連制接塾之 為相等。從圖11亦能理解到’以往，一般以建成基板疊層之樹脂， 於各層不會對於樹脂材料或樹脂厚加以改變。此係由於改變樹 脂，會造成疊層條件、介層孔形成條件、配線形成條件改 於處理成本、產量造成影響。 又，近年來，就達成半導體裝置之高雜化及高機能化，包 201021640 件於配線基板之半導體有从出内建半導體元 板mf-2直l’記載於核心層基板内建1c晶片之多層印刷基 [先前技術ϋ文獻3記載之多層印刷基板之剖面圊。 [專利文獻] ❿ [專利文獻1]日本特開2005-072328號公報 [專利文獻2]日本特開2〇〇1_339165號公報 [專利文獻3]日本特開2〇〇4_28871ι號公報 【發明内容】 [發明欲解決之問題] 又，上述專利文獻之各揭示納入本說明書作為引用。 ^具核心層之建成基板，由純^層基板之貫賴孔， 相較於建成層之介層孔直徑、配線寬大了數倍，因此，) 尺度差妨礙包裝體基板之高速化、高密度微細配線化 配線層巧職心層之無核心層基板，相對於建成基板，$言 化2密度微細配線化，蚁’由於係在支紐上逐次性地^ 層配線體之構造’ S此已知若層數增加，產量會以層數 ^ 化:與窄間距、多接腳之半導體元件連接之無核心層基板 =層化，因此以高產量實現多層化之無核心層基板係屬不^ 且，猶理或可靠性之觀點，要求代表介層孔之高度 "層孔直控之介層孔之縱橫比為丨左右。縱橫比為1以上 ^ 解電鑛於介層孔狀魏均厚能力惡化，會發生介層孔連接』 良。縱橫比為1以下時，電解電鍍於介層孔内之電鑛能力= 良好，但是採用樹脂厚係薄時，會有層間配線短路的顧慮。 如專利文獻1，使各層之樹脂厚為固定，當一旦窄間距更* 介層孔直徑之縱橫比會逐層劇烈變化，可能導致產量下: 201021640 連接於乍間距之半導體元件等的電極端子的接墊間距，必兩 相反面的電極端子更窄的間距。 而今較 又’於專利文獻2〜3，並未揭示因應於窄間距之無核心居芙 板、無核心層基板内建有半導體元件之半導體裝置。 曰土 本發明有鑑於上述問題而生，提供與窄間距、多接腳之 ΐίΐϊΐίίί心C能不使產量劣化而達成層數 =盾化〜產里、面可紐之配線基板及半導體裝置及其製造 〇 =，尽發明挺供於無核心層配線基板内建 ;====板中，能不使產量劣化 i造_產量、高可靠性之半導體裝置及其 [解決問題之方式] 本發明^ 1態樣(面相)之無核心層配線基板， 及將t前數酉己線層及絕緣層；設於前述配線層之配線； =^於_、七緣層且將前述絕緣層上下之前述配線電連接之介 設有K 置it電極端子，於前述第1表面之相反面 配線子2電Ϊ端子，介由前述 配線至少之—且有“ 而電導通，且前述介層孔或前述 不同的剖面形&其他絕緣層或配線層之介層孔或配線 間最小配線寬、配線 無核心層配另之半導體S置’特徵在於包含：前述 半導體元件。A，及連接於前述無核心層配線基板之至少-個 本!X明之又另—態樣的半導體裝置，包含：於表面具有電極 6 201021640 ίΐϊ-1彳Γ日上ί半導體元件；及無核—配線基板，内建前述 ίif牛i，、具有：疊層之多數配線層及絕緣層；設於前述 及設於前述絕緣層且將前述絕緣層上下之前述配 ίίϊ=層於表面設有外部連接端子，·特徵在於：前述 iif=埋ΐ於前述絕緣層’前述外部連接端子與前述電極端 前述介層孔至少其中之一而電導通，且前述絕 於前述半導體元件之表背面疊層，前述介層孔 層。配己線為ΐ同、有與設於其他絕緣層或配線層之介 ❹人.ΐ 本發^之其他態樣之無核心層配線基板之製造方法，包 艾居體縣麵，於支持體上職她線層及絕緣層及 線體；第2配線體形成步驟，於前述配線體上進 .除層及介層孔並戦_狀聽線體；及 . 特徵在於：重複前述第2配線體形成步驟〗次以上，於 二…1 2崎獅成倾，形成該步騎形成之配線體得 2==形狀、或介層孔剖面形狀係與該步驟實施前之步i 得到的配線體的配線剖面形狀、介層孔剖面形狀為不同的配線體。 又’本發明之另—紐之半導贼置之製造方法，特徵在於 驟：於前述製造方法所製造之無核心層配線基板裝載 又’本發明之其絲樣之半導體裝置之製造綠，特徵在於 包:以下步驟：於支持體上以電極軒形成面絲面裝載半導體 紐蓋前述半導體元件之絕緣層；形朋於將前述電極 =子/、外部連接端子電連接之介層孔與配線層；將前述支持體 去’形成内建有半導體元件之配線基板；於前述内建有半導體元 件t配線基板之表背面形成包含配線層之無核心層電路基板。 [發明之果] 依照本發明，於與窄間距、多接腳之半導體元件連接之叙核 心層基板之多層化，藉由使介層孔或前述配線至少其中之 201021640 造方法 i若從與半賴元件連接之電極㈣之層妙層為單位 ΐίΐ式加大介層孔剖面形狀、配線剖面形狀，則藉由壓低於 各邊界面，形狀的劇烈變化，可減小訊號反射、改善訊號品質。 又，藉由於無核心層基板之中内建半導體元件，能&供半導 體讀内建基板之高產量化、高可#性及低成本且簡易之製造方 法0 【實施方式】 (實施發明之形態） 關，本發明之實施形態，視需要參照圖式説明。本發明之一 實施形態之無核心層配線基板，若參照圖丨、圖13〜圖15χ，包含： 疊層之多數配線層（17、20、23)及絕緣層（15、18、21)，及設於配 線層之配線(17、20、23)，及設於絕緣層且將絕緣層上下之配線 (Π、20、23)電連接之介層孔(16、19、22);於第！表面設有第i 電極端子14，於第1表面之相反面設有第2電極端子幻，且第i 電極端子14之接墊間距較第2電極端子23之接墊間距為窄間距 之無核心層配線基板11中，第1電極端子14與第2電極端子B， 介由配線或介層孔至少其中之一電導通，介層孔(16、19、22)或配 線(17 γ 20、23)至少其中之一具有與設於其他絕緣層或配線層之介 層孔或配線不同之剖面形狀。依照上述無核心層配線基板，可依 據接墊間距之不同或對於各層要求之密度等的不同，於逐層得到 適當構成。 又，於上述無核心層基板，如圖1、圖14、圖15所示，能使 介層孔(16、19、22)之剖面形狀於第1電極端子14之最近接層"16 為最小。 又’上述無核心層基板中，如圖1、圖14、圖15所示，介層 孔(16、19、22)之剖面形狀可從第1電極端子14之最近捿層16 ^ 向第2電極端子23侧之層梯級地加大。階段數可視需要增加。 201021640 又，上述無核心層基板中，如圖工、圖14、圖15所示，介層 ϋ6二L9、22)之直徑及高度，可從第1電極端子14之最近接i 16朝向第2電極端子23侧之層梯級地加大。 垃协ΐ 1 ΐ述無核心層基板中，如圖卜圖14、圖15所示，從相 表面之絕緣層15朝向相接於第2表面之絕緣層21的介 I?, - :19、22)之剖面形狀可保持大致相似形狀而逐層加大。介 3孔南，相對於介層孔直徑之比率的縱橫比，希望為J左右。尤 二比超過3時，於介層孔内形成配線變難，縱橫比小於03 丨對於絕緣層厚度變得過大，會妨礙配線之高密 了使縱橫比在逐層儘可能均勻’當加大介層孔直 二時希望同時也加大介層孔高度(絕緣層厚度）。 Γ17、ΐπ’、ΐί無核心層基板中’如圖卜® 13、圖15所示，配線 良爭飞)之剖面形狀可定為在第1電極端子14之最近接層17 對;端子14連接窄間距之電子零件時，若以 作為最近接層17之配線，則可使用最近接層Π之 配3距，將較最近接層17更為靠第2電極端子23側 配線形狀加*，能使用較寬鬆間距的介層孔、 配線此成為低成本、高可靠性之無核心層基板。 線(π又於無核心層基板中，如圖卜5113、圖15所示，配 %向Hi之剖面形狀，可為從第1電極端子14之最近接層 朝向第2、電極端子23側之層成梯級式地加大。 無核心層基板中，如圖卜圖13〜圖15所示，介芦 端子23側之比起第1電極端子14側之直徑’在第2電i 介声孔之叫面开大之介層孔。尤其，使第2電極端子23側之 ==翁岐佩飯變化 ’減少訊號反射，並能改 201021640 21)不同之絕緣層。 偷另—實麵態半導體裝置，若參照® 2，包含： ΐιί 。土板31;連接於無核心層配線基板31之至少一個半 半導實裝置，_圖3、圖4，係 元件13 ;及内建半導體元H有^極端子14之1個以上半導體 心層配線餘件之無核心層配線基板3卜該無核 層;、18土、2n，層之多數酉己線層(17、20、23、33)及絕緣 i緣層（15、18 ’21、ϊΐ配線層之配線(17、20、23、33)，及設於 接之“牵、2G、23、33)電連 半«元件13埋設於絕缘# H 又有外部連接端子23 ; 介由配線(Π、20、外部連接端子23與電極端子^ 中之-電導通，且ί"層孔16、19、22、3G、32)至少其 疊層於半導體元件: 18、21)與配線層(17、2〇、23、33) 層之介層减崎為械設於其他職層或配線201021640 VI. Description of the invention: [Technical field to which the invention belongs] (Related to the relevant application) 7 a The Shishen Qing case claims the priority of the previous Japanese Patent Application No. 2008-190101 (2_year with 1 input and 1 application) The right of the above-mentioned first application is considered to be included in this specification. The present invention is directed to the manufacturing green of a coreless substrate and a semiconductor using a coreless substrate. A semiconductor device and a method of manufacturing the same according to a multilayer coreless substrate, a substrate, and a multilayer core substrate. [Prior Art] In recent years, electronic devices have been required to be miniaturized, highly functional, and high-performance. Therefore, semiconductor packages require high-density packaging technology. Conventionally, a semiconductor substrate has a built-in substrate having a core layer. However, the through hole (TH), the distribution, and the line width of the built-in substrate are twice as large as the via hole diameter and the wiring width of the built-up layer. Therefore, the difference in scale hinders the high speed and high-density fine wiring of the package substrate. 2,. Further, since the single side of the built-in substrate is provided with a layer which is not required in design but is formed to prevent warpage, it is a factor of cost increase. In order to achieve high speed, high density, and low cost of semiconductor packages, it has been proposed to build a full-layer substrate without a core layer, that is, a core-free substrate. In Patent Document 1, as shown in FIG. 11, it is described that the electrical component connection pad 115' is disposed directly above the terminal pad 117, and the via hole conductor is slowly made to the cell pad 115 by the die pad 117. The diameter is reduced, so that the I core layer wiring substrate of the connection reliability can be improved even when the arrangement positions of the upper and lower via hole conductors are somewhat deviated. Therefore, the distance between the terminals is equal to that of the electrical components. It can also be understood from Fig. 11 that in the past, a resin in which a substrate is laminated is generally used, and the thickness of the resin material or the resin is not changed in each layer. This is due to the change in the resin, which causes the lamination conditions, the formation conditions of the via holes, the wiring formation conditions to be changed to the processing cost, and the yield. In addition, in recent years, in order to achieve high-hybridization and high-performance of semiconductor devices, the semiconductors of 201021640 are printed on the wiring substrate, and the semiconductor chip mf-2 is directly described in the core layer substrate. Multilayer printing base [Prissing section of the multilayer printed substrate described in Document 3 of the prior art. [Patent Document 1] Japanese Laid-Open Patent Publication No. Hei. No. Hei. No. 2-339165. [Problems to be Solved by the Invention] Further, each of the above-mentioned patent documents is incorporated herein by reference. ^The built-in substrate with the core layer is made up of the pure-layer substrate, which is several times larger than the diameter of the via hole and the wiring of the built-up layer. Therefore, the difference in scale hinders the high speed and high density of the package substrate. The core-free substrate with a fine wiring layer and a hard-working layer, the density of the stencil 2 is finely wired with respect to the built-in substrate, and the ant's structure of the wiring body is successively on the sill. If the number of layers is increased, the yield will be determined by the number of layers: a core-free substrate connected to a narrow-pitch, multi-pin semiconductor device = stratification, so that a multi-layered substrate without high-yield is not available. Moreover, from the point of view of reliability or reliability, it is required to represent the height of the via hole. The aspect ratio of the via hole directly controlled by the layer hole is about 丨. The aspect ratio is 1 or more. ^ The power of the ore deposit is deteriorated in the pore-like Wei-thickness of the interlayer, and the pore-to-hole connection is good. When the aspect ratio is 1 or less, the electro-penetration ability of electroplating in the pores of the mesopores is good, but when the thickness of the resin is thin, there is a concern that the interlayer wiring is short-circuited. As disclosed in Patent Document 1, the resin thickness of each layer is fixed, and when the aspect ratio of the pore diameter is changed drastically by layer, the yield may be caused by the following: 201021640 The electrode terminal of the semiconductor element or the like connected to the pitch The pitch of the pads must be a narrower spacing between the opposite electrode terminals. Further, in Patent Documents 2 to 3, a semiconductor device in which a semiconductor element is built in a coreless board having a narrow pitch and a coreless substrate is not disclosed. The present invention has been developed in view of the above problems, and provides a wiring board and a semiconductor device with a narrow pitch and a multi-pin, which can achieve a number of layers without changing the yield. 〇 , , , , 尽 尽 尽 尽 尽 尽 尽 发明 发明 发明 发明 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = ^1 no-core layer wiring substrate of the aspect (face phase), and the wiring layer and the insulating layer before the t-layer; the wiring of the wiring layer; the wiring layer of the wiring layer; a wiring electrode is electrically connected to the wiring, and the wiring terminal 2 is electrically connected to the opposite surface of the first surface, and at least the wiring is electrically conductive, and the via hole or the foregoing Different cross-section shapes & other insulating layers or wiring layers, via holes or wirings, minimum wiring width, wiring without core layers, and other semiconductors are characterized by: the aforementioned semiconductor elements. A, and connected to the aforementioned coreless At least one of the layer wiring substrates A further semiconductor device comprising: an electrode having a surface on the surface of the semiconductor device; and a non-nuclear-wiring substrate having the built-in ίif cow i, having: a laminate a plurality of wiring layers and an insulating layer; and the external connection terminal provided on the surface of the insulating layer provided on the insulating layer and above and below the insulating layer, wherein the iif= is buried in the insulating layer 'The external connection terminal is electrically connected to at least one of the via holes of the electrode terminal, and the layer is laminated on the front and back surfaces of the semiconductor element, and the via layer is different. In the other insulation layer or the wiring layer, the manufacturing method of the core layer wiring substrate of the other aspect of the present invention, the package body of the Aiju County, the support layer and the insulation layer and the line The second wiring body forming step is performed on the wiring body to remove the layer and the via hole, and is characterized in that the second wiring body forming step is repeated ... 1 2 The singer lion is inclined to form this step The wiring body formed by riding has a 2== shape or a cross-sectional shape of the via hole, and a wiring body having a wiring cross-sectional shape and a cross-sectional shape of the via hole obtained in the step i before the step is performed. The manufacturing method of the semi-conducting thief set is characterized in that: the manufacturing of the non-core layer wiring substrate manufactured by the above manufacturing method and the manufacturing process of the wire-like semiconductor device of the present invention is characterized by the following: Step: loading an insulating layer of the semiconductor element on the support surface with a surface of the electrode on the support surface; forming a via hole and a wiring layer electrically connecting the electrode=sub/ and the external connection terminal; The body is formed to form a wiring board on which a semiconductor element is built, and a core-less circuit board including a wiring layer is formed on the front and back surfaces of the wiring board on which the semiconductor element t is built. [Invention] According to the present invention, multilayering of a core layer substrate connected to a narrow-pitch, multi-pin semiconductor element is achieved by using a via hole or a wiring of at least 201021640. The layer of the electrode connected to the component (4) is a unit of ΐ ΐ 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 加大 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Moreover, since the semiconductor element is built-in in the core-free substrate, the semiconductor read-in substrate can be produced with high yield, high availability, and low cost, and is easy to manufacture. [Embodiment] Mode) The embodiment of the present invention will be described with reference to the drawings as needed. A coreless wiring board according to an embodiment of the present invention includes a plurality of laminated wiring layers (17, 20, 23) and insulating layers (15, 18, 21), as shown in FIGS. 13 to 15B. And wirings (17, 20, 23) provided in the wiring layer, and via holes (16, 19, 22) which are provided on the insulating layer and electrically connect the wirings (Π, 20, 23) above and below the insulating layer; ! The ith electrode terminal 14 is provided on the surface, and the second electrode terminal is provided on the opposite surface of the first surface, and the pad pitch of the ith electrode terminal 14 is narrower than the pitch of the second electrode terminal 23. In the layer wiring substrate 11, the first electrode terminal 14 and the second electrode terminal B are electrically conducted through at least one of the wiring or the via hole, and the via hole (16, 19, 22) or the wiring (17 γ 20, 23) At least one of them has a cross-sectional shape different from a via hole or wiring provided in another insulating layer or wiring layer. According to the above-described coreless wiring board, it can be suitably formed layer by layer depending on the difference in the pitch of the pads or the density required for each layer. Further, in the coreless substrate, as shown in FIG. 1, FIG. 14, and FIG. 15, the cross-sectional shape of the via holes (16, 19, 22) in the nearest layer of the first electrode terminal 14 is "16". The smallest. Further, in the above-described coreless substrate, as shown in FIGS. 1, 14, and 15, the cross-sectional shape of the via holes (16, 19, 22) may be from the nearest layer 16 of the first electrode terminal 14 to the second layer. The layer on the side of the electrode terminal 23 is stepwise enlarged. The number of stages can be increased as needed. 201021640 Further, in the coreless substrate, as shown in FIG. 14 and FIG. 15, the diameter and height of the interlayer ϋ6 2 L9 and 22) can be from the nearest first 16 to the second of the first electrode terminal 14 The layer on the side of the electrode terminal 23 is stepwise enlarged. In the coreless substrate, as shown in FIG. 14 and FIG. 15, the dielectric layer 15 from the phase surface faces the dielectric layer 21 that is in contact with the second surface, and is: 19, 22) The cross-sectional shape can be maintained in a substantially similar shape and increased layer by layer. It is desirable that the aspect ratio of the ratio of the diameter of the via hole is about J. When the ratio is more than 3, it is difficult to form wiring in the via hole, and the aspect ratio is less than 03 丨. The thickness of the insulating layer becomes too large, which hinders the high density of the wiring and makes the aspect ratio as uniform as possible layer by layer. When the hole is straight, it is desirable to also increase the height of the via hole (the thickness of the insulating layer). In the Γ17, ΐπ', ΐί core-free substrate, the cross-sectional shape of 'Figure 234, Figure 15, the wiring is good, can be defined as the nearest layer 17 of the first electrode terminal 14; the terminal 14 is connected In the case of a narrow-pitch electronic component, the wiring of the nearest layer 17 can be used to increase the wiring shape of the nearest electrode layer 23 to the second electrode terminal 23 side. The use of a relatively loose pitch via hole and wiring makes this a low-cost, high-reliability, coreless substrate. The line (π is in the coreless substrate, as shown in FIG. 5113 and FIG. 15 , and the cross-sectional shape of the % to Hi can be from the nearest layer of the first electrode terminal 14 toward the second and second electrode terminals 23 side. The layer is stepped up. In the coreless substrate, as shown in FIG. 13 to FIG. 15, the diameter of the side of the first electrode terminal 14 is compared with the diameter of the side of the first electrode terminal 14 in the second electric i hole. In the case of the second electrode terminal 23 side, the change of the signal can be reduced by reducing the signal reflection and changing the insulation layer of 201021640 21 . Stealing another-real-state semiconductor device, if referring to ® 2, contains: ΐιί. The earth plate 31; at least one semi-semiconducting device connected to the coreless wiring substrate 31, _Fig. 3, Fig. 4, the element 13; and the built-in semiconductor element H having one or more semiconductor core wirings of the terminal 14 The coreless wiring board 3 of the remaining parts has the coreless layer; 18 soil, 2n, the majority of the layer of the layer (17, 20, 23, 33) and the insulating edge layer (15, 18 '21, ϊΐ Wiring of the wiring layer (17, 20, 23, 33), and electrical connection of the "lead, 2G, 23, 33" connected to the device. The component 13 is buried in the insulation #H and has an external connection terminal 23; Π20, the external connection terminal 23 and the electrode terminal ^ are electrically connected, and the λ<layer holes 16, 19, 22, 3G, 32) are laminated on at least the semiconductor element: 18, 21) and the wiring layer (17) , 2〇, 23, 33) The layer of the layer is reduced to the other layer or wiring

3 0、3?之上4半= 辭卞如圖3、4所示，介層孔(16、19、I 又，上述極軒14之最近接層最小。 可從電極端子14之圖3、4所示，介層孔之剖面形狀 B側!^^=«16、3〇)朝向表背面之外部連接端子 之最i接’如圖3、4所示，可從電極端子η 介層形狀為纽^Sit i3側之層’保持前述 為從電極端子U之最，斤<揉禺ri7圖3、4所不，配線剖面形狀可定 端子侧之叫 201021640 層緩慢加大 又 ，上述半導體裝置中，如圖3、4 距可定為較前述外部連接端子23之間距為窄間而子14之間 大之介層孔 子3攸施__子㈣之直徑較 2】^’上H導縣置巾，若參關3、4，錄絕緣層⑴、18、 )之中’可具有絕緣材料與其他 緣層(15、18、21)。 以、21)為不同之絕 〜又，上述半導體裝置t，將半導體元件之電極端子Μ 控封之絕緣層15與將半導體元件13之側 g 盘本藤心m Q域未分成電極端子14之表面 與+¥體讀13之侧面，但是，可_ ===犧，嶋細讓 措t*可在半導體元件之側面與表面形成不同的絕緣膜。 又，上述半導體裝置中，如圖4所示，半導體元件13之電極 端子14之表面設有金屬柱3〇，金屬柱30可作為介層孔的功能。 又，^發明之又另一實施形態之無核心層基板之製造方法， 如圖5所示，包含以下步驟：第丨配線體形成步驟，於支持體25 上开> 成由配線層17及絕緣層15及介層孔16構成之配線體(步驟結 束時圖5(b));第2配線體形成步驟，於該配線體上進一步形成配 線層(20)及絕緣層(18)及介層孔(19)，並形成疊層之新配線體(步驟 結束時圖5(c));及除去支持體(25)之步驟(步驟結束時圖5(d));重 複第2配線體形成步驟1次以上，且其中至少1次第2配線體形 成步驟’係形成該步驟新形成之配線體而得之配線體之配線剖面 形狀或介層孔剖面形狀係與由該步驟實施前之步驟而得之配線體 之配線剖面形狀、介層孔剖面形狀不同之配線體。 該至少1%欠第2配線體形成步驟，可較該步驟實施前之步驟 得到之配線剖面形狀、介層孔剖面形狀更加大配線剖面形狀、介 層孔剖面形狀者。又，於所有第2配線體形成步驟中，可加大配 11 201021640 線剖面形狀、加大介層孔剖面形狀者。 圖6^本之實麵態之半導财置之製造方法，如 ®少二#以下步驟：於利用上述無核心層配線基板之製造 〇層配線基板裝載半導體元件(步驟結束時圖 方法製造之無核, 6(e)) 又本叙明之又另一實施形態之半導體裝置製 ，包含以下步驟：於支持體25上端子Γ4 开:成霜i本！^裝载半導體兀件13(步驟結束時圖7(c)、圖9(c)); 議束咖聊圖^ 3〇)及配線層17(步魏接之介層孔(16、 成内建半㈣亓圖7(e)、圖_);除去支持體25，形 體元件13之配線从/=基板(圖_、圖1_;於内建半導 ΐ電^^it表背面形成包含配線層(2〇、23)之無核心 層電路基板(31)(步驟結束時圖8(g)、圖1〇⑼。 1G所示上述轉體裝置之製造方法巾，半導體 兀件13具有设於電極端子14之表面之 3〇且盘用1 形成將電極端子Η與外部連接端子r電連接之靜 =屬柱T之=’可包含:將絕緣層15的-部分= 〇 3〇鱼絕115iz=驟結束時圖9(f));及於露出之金屬柱 屬柱Μ娜細1G(g))，使金 中，ί除、10所示’上述半導體裝置之製造方法 牛驟持士體形成内建有半導體元件13之配線基板之 含町麵：形成 結束時圖7⑹或圖1G(g))。而連接表細之介層孔32之步驟(步驟 於圖9、1G所示上述半導體裝置之製造方法中， 9η!ν^ 上形成配線層33之步驟(步驟結束時圖7(b)或 上裝载半導體元件13之步驟(步驟結束時圖 5 ® (C))’可疋為在形成有配線層33之支持體25上裝載半導 12 201021640 體元件13之步驟。 「眘對於本發明之各實施形態’參照圖式更詳細説明。 [實施形態η 祕一圖/顯示實施形態〗之無核心層配線基板之剖面圖。如圖工 夕核心層配線基板’係由沒有核心層之全層建成層構成 ϋΓ層基板，設置有將與半導體元件連接之電極端子14及為 卜j連接端子之配線c(23)電連接之絕緣層Α(15)、介層孔Α(16)、 ❹ t、A(17)、絕緣層Β(18)、介層孔Β(19)、配線Β(20)、絕緣層 介層孔c(22)。圖1中，層數為3層，但不限於此，只要 ^夕數層可為任意層。本實施形射，定為配線層3層、絕緣層3 層0 s又’圖1中，電極端子14與絕緣層A(15)，大致成平面，但 是電極端子14也可較絕緣層A(15)更為凹陷或是突出。電極端子 • =與絕緣層A(15)大致成平面時，於該面連接其他配線基板或半 導體裝置時’容易連接。電極端子14比起絕緣層A(15)之表面更 • ，凹陷時，於該面形成焊球等時，絕緣層A(15)作為防鍍層之機 能，於僅於凹陷部分形成焊球等，可不需另外設置形成焊球用的 防鍍層圖案。電極端子14較絕緣層a(15)之表面更為突出時，可 因應於該面連接其他配線基板或半導體裝置時之窄間距化。又， 圖1中，外部連接端子23比起絕緣層c(21)更為突出，但是與電 極端子14與絕緣層A(15)之關係同樣’外部連接端子23可以與絕 緣層C(21)大致成平面’也可以比起絕緣層c(2i)更為凹陷。 又，圖1中，依照介層孔A(16)、介層孔B(19)、介層孔c(22) 之順序’介層孔剖面形狀加大，且依照配線A(17)、配線B(2〇)、 配線C(23)之順序配線剖面形狀加大，且依照電極端子14與配線 A(17)間之絕緣層a(15)、絕緣層B(18)、絕緣層C(21)之順序，絕 緣層增厚。介層孔剖面形狀、配線剖面形狀可視需要改變即可， 介層孔剖面形狀、配線剖面形狀任一者於任一層不同即可。 介層孔剖面形狀’代表介層孔之頂直徑與底直徑及高度。介 層孔剖面形狀之加大’如無特別限定，可僅於其中之1項以上加 13 201021640 士。以介層孔直徑較大者為介層孔之頂部，並以介 者定為介層孔之底部。希望介層孔之底側 近接層，以介層孔剖面形狀為相似的加大。又 相，於介層孔直徑的縱橫比為i左右。尤其，縱橫比超度 於;1層孔⑽成配線變得困難。以電解電 ^ 如 =::rrr於介層孔内之電: ^生=線不良。另-方面，當縱橫比不滿G3時，介層 對於絕緣層之厚度變得過大，妨礙配線之 二 Ο Γ過ϊίϊϊΐ。因此，為了使各層之介層孔之縱可ί 二轉介層孔高度也為相似形狀 又’配線剖面形狀，代表最小配線寬、 所謂配線規則及配線厚度，該等之中可以僅加大i以^ ϊίΐΐΐί ’ ΐΐϊΐ規則中’從窄間距、窄寬度往寬鬆間距。、 寬氣、寬度轉’崎厚巾，顯示從財往厚者轉 體元件之近接層，使配線剖面形狀緩慢加大。 ， ❹ Μ =達成高產量之半導體裝置，希望從接近電極端子η之声 起使;!層孔剖φ形狀、配線剖面雜分別緩慢增Α，於二 使絕緣層加厚。亦即，希望從雜端子14之近接 配 J從”距、窄寬度，寬鬆間距，寬鬆寬度、介層孔直 径在大直徑、介層孔南度亦即絕緣層厚度從薄者往厚者移 不限於此，可視需要改變。 一 又，藉由使配線規則從窄間距、窄寬度往寬鬆間距、 度、介層孔直徑從小直徑往大直徑、介層孔高度( ^ 往厚者移轉，能提升配線基板Η之可靠性。豕4)從厚者 、絕緣層A(l5)、絕緣層Β(18)、、絕緣層卿），例如由感光 非感光性有機材料形成，有機材料例如使用環氧樹脂、 松 酸醋樹脂、胺i旨丙烯酸S旨樹脂、聚g旨樹脂、苯盼樹脂、聚酿亞g 14 201021640 树月曰、BCB(表并環丁烯，benzocyclobutene)、PBO(聚苯并噚唾， 、料__#，或玻璃布絲軸纖維等形 分或不織布含浸環氧樹脂、環氧丙烯酸酯樹脂、胺酯丙烯 ^酉曰树知、聚酯樹脂、苯酚樹脂、聚醯亞胺樹脂、BCB(苯并環丁 婦 benzocyclobutene) ' PBO(聚苯并。等哇，p〇iybenzoxazole)、变 降莰烯樹脂等的材料。 ^ ^ ^又户各絕緣層，在上述有機材料以外，也可使用氮化發、鈦 ’鋇二氮化硼、鈦酸錯酸錯、碳化矽、塊滑石、氧化鋅等氧化物 $、氫氧化物系、碳化物系、碳酸鹽系、氮化物系、鹵化物系、 Θ W酸鹽系之陶瓷及上述陶瓷或玻璃等含於充填料之複合材料，或 奈米碳管、，鑽碳、聚對二曱苯基材料。 〆 為達成南產量半導體裝置，希望要求最微細介層孔直徑、配 線規則、薄絕緣層之半導體元件侧之電極端子之最近接層之絕緣 層，採用感光性樹脂，其次之層採用能以uv一YAG雷射形成介 層孔之非感光性樹脂，於要求最大介層孔直徑、最寬鬆配線規則、 厚絕緣層之外部連接端子之近接層之絕緣材，使用能以c〇2雷射 形成介層孔之含浸玻璃布等補強材之非感光性樹脂。藉由如此於 各層適當採用適於要求之配線規則、介層孔剖面形狀、絕緣層厚 之絕緣材料、處理，不僅能達成高產量，也能達成低成本。 ’又，藉由於各層改變絕緣材料，可期待各種效果。例如，藉 由於微細介層孔為必要之層採用低彈性絕緣材，可提升可靠性。 又，藉由於絕緣層厚之層採用高彈性率之絕緣材，能達成半導體 裝置之低翹曲化。本實施形態中，絕緣層A(15)、絕緣層B(18)、 絕緣層C(21)使用非感光性樹脂之環氧樹脂。 配線A(17)、配線B(20)、配線C(23)，使用選自例如銅、銀、 金、鎳、鋁、及鈀構成之族群中至少丨種金屬或以該等金屬為主 成分之合金。尤其，從電阻値及成本之觀點，希望以銅形成。本 實施形態中，配線A(17)、配線B(20)、配線C(23)使用銅。 介層孔A(16)、介層孔B(19)、介層孔c(22)，使用選自例如銅、 銀、金、鎳、鋁、及鈀構成之族群中至少丨種金屬或以該等為主 15 201021640 其’從電阻値及成本之觀點，希望由銅形成。本 只=態中，介層孔八⑽、介層孔叩9)、介層孔c(22)使用銅。 雷4 ίίΐί輕錄，設㈣料路之魏磁猶用之 電令，，電容器之介電體材料，宜為氧化欽、氧化叙、Α1203、 帅5等金屬氧化物，戰Sri-xTi〇3)、3 0, 3? Above 4 and a half = Remarks As shown in Figures 3 and 4, the via holes (16, 19, I, the nearest layer of the above-mentioned poles 14 are the smallest. Can be seen from the electrode terminals 14 in Figures 3 and 4. It is shown that the cross-sectional shape of the via hole is B side! ^^=«16, 3〇) The outermost connection terminal of the external connection terminal of the front and back sides is shown in Figs. 3 and 4, and the shape of the interlayer from the electrode terminal η can be ^Sit i3 side layer 'maintains the above from the electrode terminal U, kg <揉禺ri7 Figure 3, 4, the wiring cross-sectional shape can be fixed to the terminal side called 201021640 layer slowly increase again, in the above semiconductor device 3, 4 distance can be determined as the distance between the external connection terminal 23 is narrower and the distance between the sub-layers 14 is larger than the diameter of the hole __ sub (four) compared to the 2] ^ ' on the H guide county Towels, if involved in 3, 4, the insulating layer (1), 18, ) can have insulating material and other edge layers (15, 18, 21). Further, in the semiconductor device t, the insulating layer 15 for controlling the electrode terminal of the semiconductor element and the side of the semiconductor element 13 are not divided into the surface of the electrode terminal 14 With the side of the +¥ body reading 13, however, it is possible to form a different insulating film on the side and surface of the semiconductor element. Further, in the above semiconductor device, as shown in Fig. 4, the surface of the electrode terminal 14 of the semiconductor element 13 is provided with a metal post 3, and the metal post 30 functions as a via hole. Further, in the method of manufacturing a coreless substrate according to still another embodiment of the invention, as shown in FIG. 5, the step of forming a second wiring body is performed on the support 25 to form the wiring layer 17 and a wiring body comprising the insulating layer 15 and the via hole 16 (Fig. 5(b) at the end of the step); and a second wiring body forming step of further forming a wiring layer (20), an insulating layer (18) and a dielectric layer on the wiring body Layer hole (19), and forming a new wiring body laminated (Fig. 5 (c) at the end of the step); and the step of removing the support (25) (Fig. 5 (d) at the end of the step); repeating the second wiring body The forming step is one or more times, and at least one of the second wiring body forming steps is formed by forming the wiring body newly formed in the step, and the wiring cross-sectional shape or the via hole cross-sectional shape of the wiring body and the steps before the step is performed. The wiring body of the wiring body has a wiring cross-sectional shape and a cross-sectional shape of the via hole. The at least 1% of the second wiring body forming step can be made larger than the wiring cross-sectional shape and the via hole cross-sectional shape obtained by the step before the step, and the cross-sectional shape of the via hole and the cross-sectional shape of the via hole. Further, in all the second wiring body forming steps, it is possible to increase the cross-sectional shape of the 11 201021640 line and increase the cross-sectional shape of the via hole. Fig. 6 is a manufacturing method of the semi-conducting material of the real surface state, for example, the following steps: loading the semiconductor element on the germanium layer wiring substrate using the above-described coreless wiring substrate (the method is completed at the end of the step) Non-core, 6(e)) The semiconductor device according to still another embodiment of the present invention includes the following steps: the terminal Γ4 is opened on the support body 25: the frost is i! ^Load semiconductor device 13 (Fig. 7 (c), Fig. 9 (c) at the end of the step); discuss the chat chart ^ 3 〇) and the wiring layer 17 (steps of the Wei layer) (16, into the inner Build half (four) 亓 Figure 7 (e), Figure _); remove the support 25, the wiring of the body element 13 from the / = substrate (Figure _, Figure 1 _; on the inside of the built-in semi-conducting ^ ^ ^ The core layer circuit board (31) of the layer (2〇, 23) (Fig. 8(g), Fig. 1〇(9) at the end of the step. The manufacturing method towel of the above-mentioned turning device shown in Fig. 1G, the semiconductor element 13 is provided in 3 〇 of the surface of the electrode terminal 14 and the disk 1 is used to form a static connection of the electrode terminal Η to the external connection terminal r = ' can include: the portion of the insulating layer 15 = 〇 3 〇 鱼绝 115iz = at the end of the figure, Fig. 9(f)); and the exposed metal column is a column of the column 1A (g)), so that the gold is removed, 10 is shown as 'the above semiconductor device manufacturing method. The surface of the wiring substrate on which the semiconductor element 13 is built is formed: Fig. 7 (6) or Fig. 1G (g) at the end of formation. And the step of connecting the fine via holes 32 (steps in the manufacturing method of the semiconductor device shown in FIGS. 9 and 1G, the step of forming the wiring layer 33 on 9η!ν^ (step 7(b) or above at the end of the step) The step of loading the semiconductor element 13 (Fig. 5 ® (C)) at the end of the step is a step of loading the semiconductor element 13 of the semiconductor 12 on the support 25 on which the wiring layer 33 is formed. Each embodiment will be described in more detail with reference to the drawings. [Embodiment η Mystery diagram/display embodiment] A cross-sectional view of a coreless wiring board. As shown in the figure, the core layer wiring substrate is composed of a full layer without a core layer. The built-up layer constitutes a germanium substrate, and is provided with an insulating layer 15 (15) electrically connecting the electrode terminal 14 connected to the semiconductor element and the wiring c (23) connected to the terminal, and a via hole (16), ❹t , A (17), insulating layer Β (18), via hole Β (19), wiring Β (20), insulating layer via hole c (22). In Figure 1, the number of layers is 3 layers, but not limited to Therefore, as long as the layer can be any layer, the present embodiment is shaped as a wiring layer 3, an insulating layer 3 layer 0 s and in FIG. 1, the electrode terminal 14 and The insulating layer A (15) is substantially planar, but the electrode terminal 14 may be more concave or protruded than the insulating layer A (15). When the electrode terminal•= is substantially planar with the insulating layer A (15), the surface is When connecting another wiring board or a semiconductor device, it is easy to connect. The electrode terminal 14 is more than the surface of the insulating layer A (15). When a solder ball or the like is formed on the surface when the recess is formed, the insulating layer A (15) serves as an anti-plating layer. The function is to form a solder ball or the like only in the recessed portion, and it is not necessary to separately provide a plating resist pattern for forming a solder ball. When the electrode terminal 14 is more prominent than the surface of the insulating layer a (15), other wirings may be connected to the surface. In the case of the substrate or the semiconductor device, the pitch is narrowed. Further, in Fig. 1, the external connection terminal 23 is more protruded than the insulating layer c (21), but the relationship between the electrode terminal 14 and the insulating layer A (15) is the same as the external connection. The terminal 23 may be substantially planar with the insulating layer C (21) or may be more recessed than the insulating layer c (2i). In addition, in Fig. 1, according to the via hole A (16), the via hole B (19) The order of the via holes c (22) is increased in the cross-sectional shape of the via hole, and according to the wiring A (17), the wiring B (2 〇), The wiring C (23) has an increased wiring cross-sectional shape and is insulated in accordance with the order of the insulating layer a (15), the insulating layer B (18), and the insulating layer C (21) between the electrode terminal 14 and the wiring A (17). The layer thickness is increased. The cross-sectional shape of the via hole and the cross-sectional shape of the wiring layer may be changed as needed. Any one of the cross-sectional shape of the via hole and the cross-sectional shape of the via hole may be different in any layer. The cross-sectional shape of the via hole represents the top of the via hole. The diameter and the bottom diameter and height. The increase in the cross-sectional shape of the mesopores is not particularly limited, and may be added to only one of the above items by 13 201021640. The larger the pore diameter of the via is the top of the via, and the medium is defined as the bottom of the via. It is desirable that the bottom side of the via hole is similar to the proximal layer, and the cross-sectional shape of the via hole is similarly increased. In addition, the aspect ratio of the via hole diameter is about i. In particular, the aspect ratio is excessive; the wiring of the one-layer hole (10) becomes difficult. In the electrolysis of electricity such as =:: rrr in the pores of the pores: ^ raw = poor line. On the other hand, when the aspect ratio is less than G3, the thickness of the interlayer for the insulating layer becomes too large, which hinders the wiring. Therefore, in order to make the interlayer holes of the respective layers have a similar shape and a 'wiring cross-sectional shape, which represents the minimum wiring width, the so-called wiring rule and the wiring thickness, only i can be increased. In the ^ ϊίΐΐΐί ' ΐΐϊΐ rule 'from narrow pitch, narrow width to loose spacing. , wide air, width to 'small thick towel, showing the proximity layer from the rich to the thick body, so that the wiring cross-section shape slowly increases. , ❹ Μ = A semiconductor device that achieves high yield, it is desirable to start from the sound close to the electrode terminal η; the layer hole φ shape and the wiring profile are slowly increased, and the insulating layer is thickened. That is to say, it is desirable to pick up J from the proximity of the terminal 14 from "distance, narrow width, loose pitch, loose width, via diameter in the large diameter, and the south of the via, that is, the thickness of the insulating layer is shifted from thin to thick. Not limited to this, it can be changed as needed. Again, by making the wiring rules from narrow pitch, narrow width to loose pitch, degree, and via hole diameter from small diameter to large diameter, via hole height (^ to thicker, The reliability of the wiring substrate can be improved. 豕 4) From the thick, the insulating layer A (l5), the insulating layer 18 (18), and the insulating layer), for example, formed of a photosensitive non-photosensitive organic material, for example, an organic material is used. Epoxy resin, vinegar resin, amine i, acrylic resin, resin, polyg resin, benzene resin, poly granule g 14 201021640 eucalyptus, BCB (benzocyclobutene), PBO (poly) Benzopyrene, material __#, or glass cloth shaft fiber, etc., or non-woven fabric impregnated epoxy resin, epoxy acrylate resin, amine ester propylene, eucalyptus, polyester resin, phenol resin, poly醯imine resin, BCB (benzocyclobutene) 'PBO (poly And wow, p〇iybenzoxazole), a material such as a decene-reducing resin. ^ ^ ^ Each insulating layer, in addition to the above organic materials, can also be used for nitriding, titanium 'niobium boron nitride, titanium An acid such as an acid acid, a tantalum carbide, a talc, or a zinc oxide, a hydroxide, a carbide, a carbonate, a nitride, a halide, a ceramic, and the like. Glass or the like is contained in a filler-filled composite material, or a carbon nanotube, a carbon-impregnated, or a poly-p-phenylene phenyl material. In order to achieve a South-generation semiconductor device, it is desirable to require the finest pore diameter, wiring rules, and thin insulation. The insulating layer of the nearest layer of the electrode terminal on the semiconductor element side of the layer is made of a photosensitive resin, and the second layer is made of a non-photosensitive resin capable of forming a via hole by a uv-YAG laser, and the maximum via hole diameter is required. The most loose wiring rule and the insulating material of the adjacent layer of the external connection terminal of the thick insulating layer are non-photosensitive resins which can be used as a reinforcing material such as impregnated glass cloth which forms a via hole by c〇2 laser. Suitable for requirements Wiring rules, interlayer hole cross-sectional shape, insulating layer thickness of insulating material, and treatment can not only achieve high yield, but also achieve low cost. 'Also, by changing the insulating material in each layer, various effects can be expected. For example, by fine In the embodiment, the low-elastic insulating material is used as the necessary layer to improve the reliability. Further, since the insulating layer is made of a high-elasticity insulating material, the low warpage of the semiconductor device can be achieved. The insulating layer A (15), the insulating layer B (18), and the insulating layer C (21) are made of an epoxy resin of a non-photosensitive resin. Wiring A (17), wiring B (20), and wiring C (23) are used. At least a metal or an alloy containing the metal as a main component of a group consisting of, for example, copper, silver, gold, nickel, aluminum, and palladium. In particular, it is desirable to form copper from the viewpoint of resistance and cost. In the present embodiment, copper is used for the wiring A (17), the wiring B (20), and the wiring C (23). The via hole A (16), the via hole B (19), and the via hole c (22) are made of at least a metal selected from the group consisting of, for example, copper, silver, gold, nickel, aluminum, and palladium. These are mainly 15 201021640. From the point of view of resistance and cost, it is hoped to be formed by copper. In the only = state, the via hole (10), the via hole 9), and the via hole c (22) use copper. Lei 4 ίίΐί light record, set (four) material road Wei Wei still use the electric order, the dielectric material of the capacitor, should be oxidized Qin, oxidized, Α 1203, handsome 5 and other metal oxides, battle Sri-xTi〇3 ),

SrBi2Ta209 ^ Ο ίΐΪΪΪΐ介電體材料，亦可使用混合有無機材料或磁性材;斗 ^有機材料等。又，枓體元件或電容如外，也可設置分離零 依照本實施形態’於係與窄間距、多接腳之半導體元件連接 ^核心層配線基板的崎基板之多層化巾，達成配絲板之高 可靠性化。又，藉由從與半導體元件連接之電極接近 之層起緩忮地使介層孔剖面形狀、配線剖面形狀增大，並伴隨於 此加厚絕緣層’歸於各祕面之雜之劇 小 訊號反射、改善訊號品質。 [實施形態1之變形例1] 圖13顯示依照實施形態1之變形例1之無核心層配線基板之 剖面圖。圖13相較於圖丨，使絕緣層b(18a)、絕緣層C(21A)之 膜厚與絕緣層A(15)之膜厚大致相同而薄化。因此，可使無核心層❹ 配線基板全體薄型化。惟，配線B(2G)、配線c(23)之配&剖面^ 狀，與圖1同樣較配線A(17)為加大。以相對於窄間距之第}電極 端子14的最近接層配線層17作為引出(fan_〇ut)層將配線往外侧拉 出，可相較於配線層17，第2電極端子23側之配線層間距拉寬而 配線。因此，第1電極端子14儘管為窄間距，能使相對於第丨雷 極端子14為最近接層的配線層17以外之配線; 加大。順帶一提，相較於配線層17之最小配線寬、最小配線間隔 士 ΙΟμιη、厚度為ΙΟμϊη，能使配線層2〇、配線層23之最小配線 寬、最小配巧間隔為50μιη以上、厚度15Mm以上。又，由於使絕 緣層之膜厚雜’故介層孔B(19)、介層孔c(22)之介層孔剖面形 16 201021640 去縱橫比原形的方式而與介層孔a( 16)大致為同-形 ^依π該變形例’可使無核心層配線基板薄型化，又，能 ΐ iff端子13之最近接層的配線層17以外之配線層配線剖面 形狀加大，故能以低成本製造。 ❹ 又配線形成技術主要有減去法及加成法。減去法，係藉由 對於基板全面施用銅箔或鍍銅，並將不要部分除去(钱刻），藉此形 成電路之方法。相對於此，加成法係於不想形成電路之部分形成 防鍍層，於沒有防鍍層之部分利用電鍍形成電路之方法。減去法 與加成法若比較，由於減去法係以蝕刻形成配線，因此，會由於 蝕刻時發生之側向蝕刻使配線變細之現象，不適於微細配線形 成。另一方面，加成法由於以電鍍形成配線，因此，不發生侧向 蝕刻適於微細配線形成。又，處理成本，以減去法較加成法更為 低成本。因此，約L/S=50/5(^m以上之配線可使用減去法，更為 微細之配線可使用加成法。 . 、如上所述，若以相對於第1電極端子14最近接層之配線層17 作為引出層’則能僅將配線層17以加成法形成微細配線，且將配 線層17以外之配線層使用低成本之減去法形成。 [實施形態1之變形例2] 圖14顯示依照實施形態1之變形例2之無核心層配線基板之 剖面圖。圖14相較於圖1，配線B(20A)、配線C(23A)之配線剖 面形狀與配線A(17)大致相同。一般而言，為了以窄間距形成微細 配線’需要高精度之配線形成步驟，故容易提高成本。但是，當 不隨配線層改變配線形成步驟較安定且能以低成本製造之情形， 也可如圖14所示，於所有的配線層之配線使用可微細配線之配線 層。又，圖14中，為了防止配線B(20A)、配線C(23A)之配線電 阻相較於圖1增高，使配線B(20A)、配線C(23A)之配線較圖1之 配線寬為寬9惟，設計規則上之最小配線寬與配線A(17)相同。又， 配線B(20A)、配線C(23A)之最小配線間隔、配線厚度，與配線 A(17)相同。 [實施形態1之變形例3] 17 201021640 圖15顯示依照實施形態1之變形例3之無核心層配線基板之 剖面圖。圖15中’相對於圖1，於外部電極配線c(23)之面以露出 配線C(23)之一部分並覆蓋其餘部分之方式，形成抗焊層24。於該 變形例中，抗焊層24之材料使用感光性抗焊油墨。從抗焊層％ 開口之配線C(23)之表面’也可以選自由金、銀、銅、錫及焊藥材 料構成之族群中至少1種金屬或合金形成。該變形例中，係將厚 度3μιη之鎳及〇.5μιη之金依序疊層。又，抗焊層不僅可設置 於單面’也可設置於兩面。 [實施形態2] 圖2顯示實施形態2之半導體裝置之剖面圖。如圖2所示， 該實施形態之半導體裝置，係如圖15所示於無如層基板u之 電極端子14上裝載半導體元件13，並且以焊球41電連接無核心 層配線基板11與轉體元件13。無核心層配雜板^，由將灣 =子14與係與外部賴軒之輯c(23)予以電連接之絕緣層 A(15)、介層孔A(16)、配線A(17) '絕緣層B(18)、介層孔 配線B(20)、絕緣層C(21)、介層孔c(22)構成。又，以將配線 之-部分和之方式設置抗焊層24。又，抗焊層％，可以不僅是 =置於單面’也可設置於雙面。圖2巾，層數為3層，但不限於 Ϊ緣ϊΐί多數層可為任何層。本實施形態中，定為配線層3層: 又，園2中SrBi2Ta209 ^ Ο ΐΪΪΪΐ ΐΪΪΪΐ dielectric material, can also be mixed with inorganic materials or magnetic materials; Further, the body element or the capacitor may be provided with a separate layer according to the present embodiment, and the multilayered substrate of the sacrificial substrate of the core layer wiring substrate connected to the narrow-pitch and multi-pin semiconductor device is obtained. High reliability. Moreover, the cross-sectional shape of the via hole and the cross-sectional shape of the via are gradually increased from the layer close to the electrode connected to the semiconductor element, and the thickened insulating layer is attributed to the small signal of each secret surface. Reflect and improve signal quality. [Variation 1 of the first embodiment] Fig. 13 is a cross-sectional view showing a coreless wiring board according to a first modification of the first embodiment. In comparison with Fig. 13, the film thickness of the insulating layer b (18a) and the insulating layer C (21A) is made thinner than the film thickness of the insulating layer A (15). Therefore, the entire coreless wiring board can be made thinner. However, the wiring & cross-section of the wiring B (2G) and the wiring c (23) is larger than the wiring A (17) as in Fig. 1 . The wiring is pulled outward as a lead-out wiring layer 17 with respect to the first electrode terminal 14 of the narrow-pitch electrode terminal 14 as compared with the wiring layer 17, and the wiring on the second electrode terminal 23 side. The layer spacing is widened and wired. Therefore, although the first electrode terminal 14 has a narrow pitch, the wiring other than the wiring layer 17 which is the closest layer to the first thunder terminal 14 can be made larger. Incidentally, compared with the minimum wiring width of the wiring layer 17, the minimum wiring interval, and the thickness ΙΟμϊη, the wiring layer 2〇, the wiring layer 23 can be made to have a minimum wiring width, a minimum matching interval of 50 μm or more, and a thickness of 15 Mm. the above. Moreover, since the film thickness of the insulating layer is made, the via hole shape of the via hole B (19) and the via hole c (22) is removed from the original shape and the via hole a (16). In the case of the same example, the variation of the core layer wiring substrate can be made thinner, and the cross-sectional shape of the wiring layer other than the wiring layer 17 of the nearest layer of the iffiff terminal 13 can be increased. Low cost manufacturing. ❹ The wiring forming technology mainly has subtraction method and addition method. The subtraction method is a method of forming an electric circuit by applying copper foil or copper plating to a substrate in its entirety and not partially removing it. On the other hand, the additive method is a method in which a plating resist is formed in a portion where the circuit is not desired to be formed, and a circuit is formed by plating in a portion where the plating resist is not provided. Subtraction method In comparison with the addition method, since the wiring is formed by etching by subtracting the method, the wiring is thinned by lateral etching which occurs during etching, and is not suitable for fine wiring formation. On the other hand, since the addition method forms wiring by electroplating, lateral etching is not caused to be suitable for formation of fine wiring. Moreover, the cost of processing is much lower than the subtraction method. Therefore, the subtraction method can be used for the wiring of about L/S=50/5 (^m or more, and the addition method can be used for the finer wiring. As described above, if it is closest to the first electrode terminal 14, In the wiring layer 17 of the layer, as the extraction layer, only the wiring layer 17 can be formed into a fine wiring by an additive method, and the wiring layer other than the wiring layer 17 can be formed by a low-cost subtraction method. [Modification 2 of the first embodiment] Fig. 14 is a cross-sectional view showing a coreless wiring board according to a second modification of the first embodiment. Fig. 14 is a wiring cross-sectional shape of wiring B (20A) and wiring C (23A) and wiring A (17). In general, in order to form the fine wirings at a narrow pitch, a high-precision wiring forming step is required, so that the cost is easily increased. However, when the wiring layer is not changed with the wiring layer, the wiring forming step is stable and can be manufactured at low cost. As shown in Fig. 14, the wiring layer of the fine wiring may be used for the wiring of all the wiring layers. Further, in Fig. 14, in order to prevent the wiring resistance of the wiring B (20A) and the wiring C (23A) from being compared with the figure 1 Increase the wiring of wiring B (20A) and wiring C (23A) as compared with the wiring of Figure 1. The width is the width of 9. The minimum wiring width on the design rule is the same as that of the wiring A (17). The minimum wiring interval and wiring thickness of the wiring B (20A) and the wiring C (23A) are the same as those of the wiring A (17). [Modification 3 of the first embodiment] 17 201021640 Fig. 15 is a cross-sectional view showing a coreless wiring board according to a modification 3 of the first embodiment. In Fig. 15, 'with respect to Fig. 1, the external electrode wiring c (23) The solder resist layer 24 is formed to expose a portion of the wiring C (23) and cover the remaining portion. In this modification, the material of the solder resist layer 24 is made of a photosensitive solder resist ink. The wiring from the solder resist layer % opening The surface ' of C(23) may also be selected from at least one metal or alloy of a group consisting of gold, silver, copper, tin, and a flux material. In this modification, nickel and 〇.5 μmη having a thickness of 3 μm are used. Further, the solder resist layer may be provided not only on one side but also on both sides. [Embodiment 2] Fig. 2 is a cross-sectional view showing a semiconductor device according to Embodiment 2. As shown in Fig. 2, the implementation is as shown in Fig. 2 The semiconductor device of the form is shown on the electrode terminal 14 of the substrate u as shown in FIG. The semiconductor element 13 is mounted, and the core-free wiring substrate 11 and the rotating element 13 are electrically connected by the solder ball 41. The core layer is not provided with the board, and the bay is replaced by the bay and the external and the external Lai Xuan c(23) Insulation layer A (15), via hole A (16), wiring A (17) 'insulating layer B (18), via hole wiring B (20), insulating layer C (21), via layer to be electrically connected The hole c (22) is formed. Further, the solder resist layer 24 is provided in such a manner as to be part of the wiring. Further, the solder resist layer % can be set not only on one side but also on both sides. The number of layers is 3 layers, but it is not limited to the edge layer. Most layers can be any layer. In the present embodiment, the wiring layer is three layers:

/丨席扎到面形狀以介層孔Α(丨6)、介層 介層孔C(22)之順序加大，配線剖面形狀以配線a 、配 B(20)、配線C(23)之順序加大，並使絕緣層以電極端子μ鱼配 狀線剖面形狀，可視需要改變即可，介声孔 面形狀、配線剖面形狀任—者可在任—層為不 1^ 之材料、厚度也可視需要於各層改變即可。 、七緣， 直徑i底樣’介層孔剖面形_介層孔之: 可以僅=大二'要無特顧 工加人以"層孔直徑大者作為介層孔之] 18 201021640 部’介層孔直徑小者作為介層孔之底部。介層孔之底部側為窄間 距’因此希望底部侧成為與半導體元件之連接處。亦即〇圖2 所示，希望於電極端子14與絕緣層A(15)側裝载半導體元件。其 中，由訊號品質之觀點，希望從半導體元件之近接層起介層孔咅 面形狀以相似的加大。 配線剖面形狀係指：最小配線寬(頂直徑、底直徑）、配線間之 最小間距，所謂配線規則及配線厚度’該等之中可僅加大丨'以上。 配線剖面形狀之加大，係指於配線規則中，從窄間距、窄寬度移 轉到寬鬆間距、寬鬆寬度，配線厚中，從薄者往厚者移轉。希望 〇 從半導體元件之近接層，配線剖面形狀緩慢加大。 為了達成高產量半導體裝置，希望從接近電極端子14之層 起，介層孔剖面形狀、配線剖面形狀緩慢增大，伴隨於此，絕4 層增厚，亦即，從電極端子14之近接層起，配線規則從窄間距、 ，寬度往寬鬆’、寬鬆寬度移轉，介層孔直錄小直徑往大直 • 徑移轉，絕緣層(介層孔高度)從薄者往厚者移轉，但不限於此等。 又，藉由配線規則為從窄間距、窄寬度往寬鬆間距、寬鬆宽 =往=敏小直徑往大.移轉，絕緣層(介層以 k溥者在厚者移轉，能提升配線基板11之可靠性。 ίί體13 ’厚度可視目標半導體裝置之厚度調整。本實 辦H +導體元件13之厚度定為30〜50卿。圖2中，半導 一70件13之數係為1個，但也可為多數。 接，i使:二半ί體元件/3與無核心層配雜板11間之連 盥s η ^ ，但也可採用線接合方式。又，也可為晶片上 與曰曰片外周以模塑樹脂密封之構造。 〜曰月上 非感絕緣層Β(18)、絕緣層c(21) ’例如以感光性或 酸醋樹脂有機材料使用例如環氧樹脂、環氧丙3 樹脂、醋，脂、聚轉脂、苯紛樹脂、聚醯亞胺 P〇lybenZc)Xa7f^ ^ 細 Z〇Cyd〇butene)、PB0(聚苯并噚唑， 成之織布或不，或f璃布絲醯胺纖維等形 个、1邛中含改％虱樹脂、環氧丙烯酸酯樹脂、胺酯丙 19 201021640 烯咖0树脂、聚自旨樹脂、苯關脂、聚醯亞胺_旨、BCB(苯并變 丁稀 ’ be—tene)、PB0(聚苯并噚唑，p〇lybenz〇xaz : 聚降莰烯樹脂等之材料。 发又，各絕緣屬’除有機材料以外也可使用氮化石夕、鈦酸鎖、 氮化爛、鈦酸細复錯、碳化石夕、塊滑石、氧化辞等氧化物系 ?化物士、碳化物系、碳酸鹽系、氮化物系、鹵化物系、^酸鹽 土之陶纽上述喊或玻鱗含於填充料之複合材料，或奈米& 管、類鑽碳、聚對二甲苯基等材料。 -為了達成高產量之半導體裝置，希望要求最微細介層孔直 徑、配線酬、薄絕緣層之轉體元件侧之t極端子之最近接芦 之絕緣層，採贼光性樹脂，於其次之層採用能以界丫仏雷^ 形成介層孔之非感光性樹脂，於要求最大介層孔直徑、最寬鬆配 線規則、厚絕緣層之外部連接端子之近接層之絕緣材，採用能以 C〇2雷射形成介層孔之玻璃布等補強材含浸過之非感光性樹脂。 ^此，藉由於各層適當採用適於财之配親則、介層孔剖面形 狀、、絕緣層厚之絕緣機、處理，能補是賴高產量，也達成 板;Λ?太。 又，藉由於各層改變絕緣材料，能期待各種效果。例如，藉 由於微細介層孔為必要之層採用低彈性之絕緣材，能提升可靠 性。又，藉由於絕緣層厚之層採用高彈性率之絕緣材，可達成半 導體裝置之她曲化。本實施形態中，絕緣層A(15)、絕緣層 B(18)、絕緣層c(21)使用非感光性樹脂之環氧樹脂。 配線A(17)、配線B(20)、配線c(23)，使用例如由銅、銀、金、 ，、銘、尬構成之族群中至少！種金屬或以該料主成分之合 ^。尤其，從雜値及成本之誠’希望由細彡成。本實施形態 中’配線A(17)、配線B(20)、配線c(23)使用銅。 介層孔A(16)、介層孔B(19)、介層孔c(22)，使用例如由銅、 ，、金二鎳、銘、及㈣構成族群中至少丨種金屬或以該等為主 土为之&金。尤其，從電阻値及成本之觀點，希望由銅形成。本 只施形態中’介層孔A(16)、介層孔叩9)、介層孔c(22)使用銅。 201021640 分，ί严—c(23)之―部 ^層24之材料，使用_生抗7焊油中’抗 線C(23)之表面，也可由撰白Ά文抗知層24開口之配 群中至少1種金屬或合麵成。本實'施形族 及0·5μιη之金依序疊層。 〜、中將异度3μιη之鎳 電容Ϊ可設置轉麵錄賴㈣作用的 s!〇t ΖΓ〇2 ^ PZT(PbZr Ti 4 5 等金屬氧化物、BST(BaxSri-xTi〇3)、 構成電容器之介電It㈣，村娜 ί有機材料等。又’半導體元件或電容器 依照本實施形態，於裳載有窄間距、多接腳 半H成t導體裝置之高產量化、高可靠性化。又， Ϊΐί裝f有+導件之層起，緩慢地使介層孔剖面形狀、配 ί形狀增A，亚伴隨於此加厚絕緣層，能將於各邊界面之形 狀之劇烈變化減小，能減少訊號反射，改善訊號品 [實施形態3] 圖3顯示實施形態3之半導體裝置之剖面圖。 震置12 ’係轉體元件13之側面與具有電極端子14之面之 一部分與絕緣層A(15)相接，於電極端子14之表背面，設 電極端子14與半導體裝置12之外部連接端子配線c電之 介層孔A(l6)、配線Α(Π)、絕緣層即8)、介層孔 配 Β(20)、絕緣層C(21)、介層孔C(22)、介層孔D(32)、配線 深 又，以將配線C(23)—部分開口之方式，設置抗焊層24。 圖3中，層數夾隔著半導體元件13於表背面^ 3層，但是， =限於此等，只要為多數層可為任何層。本實施形態中，表背面 定為配線層3層、絕緣層3層。又’圖3中，介層^剖面形狀以 21 201021640 介層孔A(16)、介層孔B(19)、介層孔C(22)之順序加大，且配線剖 面形狀以配線A(17)、（配線D(33)、配線B(2〇)、配線c(23)之順序 加大，且絕緣層於電極端子14與配線A(17)間以絕緣層A(15)、、絕 緣層B(18)、絕緣層C(21)之順序增厚，但是介層孔剖面形狀、配 ^剖面形狀巾任-者在任—層為不_可。又，加大介層孔直經 %，希望隨著介層孔直徑加大而使絕緣層增厚。 : 介層孔剖面形狀，代表介層孔之頂直徑與底直徑及高度。介 層孔剖面形狀之加大，如無制限定，可僅於其巾之丨項以上加 士三以介層孔直徑較大者為介層孔之頂部，並以介層孔直徑較 ❿ 者，為介層孔之底部。輕介層孔之底纖為與窄間距之半導體 ΐΐί連Ϊ處。其巾’從峨品質之觀點，希望從半導體元件之 近接層，介層孔剖面形狀以相似的加大。 門之:ί Si剖面形狀’代表最小配線寬(頂直徑、底直徑）、配線 t I f 胃配線規則及配線厚度，該等之中可以僅加大1 产往、加大，代表配線規則中，從窄間距、窄寬 ί。ΐϋ轉ί鬆ί度移轉，配線厚中，顯示從薄者往厚者移 A n a 件之近接層’使配制面形狀緩慢加大。 ㈣產量之半導财置，希望從接近電極端子13之声 ❹ 使絕‘ί面慢增大，伴隨於/ 直= 需要改變。隨層厚度伙薄者往厚者雜，但不限於此，可視 度、距、窄寬度往寬鬆間距、寬鬆寬 能提升半導體裝ίϋ在靠t直徑、絕緣層從薄者往厚者移轉， 實施ί 體標之半導體裝置之厚度調整。本 導體，13之數為1個，但也二2。30〜50陴。圖3中’半 絕緣層A(l5)、絕緣層_、絕緣層C(21)，例如由感光性或 22 201021640 ίίίΐί有^料形成’有機材料例如使用縣樹脂、環氧_ = 酸醋樹脂、聚醋樹腊、苯麟脂、聚酿亞Ϊ 、曰 （本弁每丁烯，benzocyclobutene)、PBO(聚苯并n 、聚降③浠樹脂等，或玻璃布或芳醯胺纖維等形 ίηίΪ或Γ織布含浸環氧樹脂、環氧丙烯酸酯樹脂、胺酯丙烯 曰ί日、聚酯樹脂、苯朌樹脂、聚醯亞胺樹脂、BCB(苯并環 ^ ^aeydobmene)、PB〇(聚苯并嘮唾 _ 降莰烯樹脂等的材料。 J ^/ The shape of the mat is increased in the order of the via hole (丨6) and the via hole C(22), and the wiring cross-sectional shape is the wiring a, the B (20), and the wiring C (23). The order is increased, and the insulating layer is shaped by the electrode terminal μ fish line shape, and can be changed as needed. The shape of the sound hole surface and the cross-sectional shape of the wiring can be any material or thickness of the layer. It can be changed at each layer as needed. , seven edges, diameter i base 'medium hole profile shape _ mesopores: can only = the second year's no special care plus people to "large hole diameter as the mesopores" 18 201021640 The smaller the pore diameter of the mesopores is the bottom of the mesopores. The bottom side of the via hole is a narrow pitch ' so it is desirable that the bottom side be the junction with the semiconductor element. That is, as shown in Fig. 2, it is desirable to mount the semiconductor element on the electrode terminal 14 and the insulating layer A (15) side. Among them, from the viewpoint of signal quality, it is desirable to similarly increase the shape of the via hole from the close contact layer of the semiconductor element. The wiring cross-sectional shape means that the minimum wiring width (top diameter, bottom diameter), the minimum pitch between wirings, and the so-called wiring rule and wiring thickness ' may be increased by more than 丨'. The increase in the cross-sectional shape of the wiring refers to the shift from the narrow pitch and the narrow width to the loose pitch and the loose width in the wiring rule, and the thickness of the wiring is shifted from the thinner to the thicker. It is hoped that the cross-sectional shape of the wiring will gradually increase from the proximity layer of the semiconductor element. In order to achieve a high-output semiconductor device, it is desirable that the cross-sectional shape of the via hole and the cross-sectional shape of the wiring gradually increase from the layer close to the electrode terminal 14, and accordingly, the four layers are thickened, that is, from the vicinity of the electrode terminal 14. From the narrow pitch, the width to the loose ', the loose width shift, the via hole directly records the small diameter to the large straight diameter, the insulation layer (the interlayer hole height) shifts from the thinner to the thicker , but not limited to this. In addition, the wiring rule is from the narrow pitch, the narrow width to the loose pitch, the loose width = the small diameter to the small diameter, and the insulating layer (the interlayer is transferred by the thicker in the thicker layer, and the wiring substrate can be improved) Reliability of 11 ίί体13 'Thickness can be adjusted according to the thickness of the target semiconductor device. The thickness of the actual H + conductor element 13 is set to 30~50 qing. In Fig. 2, the number of semi-conducting one 70 pieces is 13 , but also can be a majority. Then, i makes: the two halves of the element /3 and the core layer of the matching board 11 between the 盥 s η ^, but can also use the wire bonding method. Also, can also be the wafer A structure in which the outer periphery of the cymbal sheet is sealed with a molding resin. The 非 上 upper non-sensitive insulating layer 18 (18), the insulating layer c (21) 'for example, a photosensitive or vinegar resin organic material such as epoxy resin, Epoxy propylene 3 resin, vinegar, fat, polyester, benzene resin, polyfluorene P〇lybenZc) Xa7f^ ^ fine Z〇Cyd〇butene), PB0 (polybenzoxazole, into a woven fabric or No, or f-glass cloth amide fiber, etc., 1邛 contains % 虱 resin, epoxy acrylate resin, amine ester C 19 201021640 olefin 0 resin, poly Resin, benzoic acid, polyimine, BCB (benzo-butadiene 'be-tene), PB0 (polybenzoxazole, p〇lybenz〇xaz: polydecene resin). In addition, each of the insulations may be used in addition to organic materials, such as nitride nitride, titanate lock, nitriding, fine titanate, carbonized stone, block talc, oxidation, etc. Department, carbonate, nitride, halide, or acid soil. The above-mentioned shout or glass scale is contained in the filler composite, or nano & tube, diamond-like carbon, poly-p-phenylene Materials such as - In order to achieve a high-yield semiconductor device, it is desirable to require the finest via hole diameter, wiring, and the insulating layer of the nearest terminal of the t-terminal on the side of the rotating element of the thin insulating layer. In the second layer, a non-photosensitive resin capable of forming a via hole with a boundary layer is used, and an insulating material for a proximal layer of an external connection terminal requiring a maximum via hole diameter, a loosest wiring rule, and a thick insulating layer is used. A non-inductive material that can be impregnated with a reinforcing material such as a glass cloth that forms a via hole with a C〇2 laser. Resin. ^ This, because each layer is properly used for the matching of the wealth, the shape of the pores of the interlayer, the insulation of the insulation layer, the treatment, can make up the high output, but also achieve the board; Further, various effects can be expected by changing the insulating material in each layer. For example, a low-elastic insulating material can be used for the layer in which the fine via hole is necessary, and reliability can be improved. Further, the layer having a thick insulating layer is highly elastic. In the present embodiment, the insulating layer A (15), the insulating layer B (18), and the insulating layer c (21) are made of an epoxy resin of a non-photosensitive resin. A (17), wiring B (20), and wiring c (23) use at least a group consisting of copper, silver, gold, gold, gold, gold, gold a metal or a combination of the main components of the material. In particular, from the hodgepodge and the cost of honesty, hope is made up. In the present embodiment, copper is used for the wiring A (17), the wiring B (20), and the wiring c (23). The via hole A (16), the via hole B (19), and the via hole c (22) are made of, for example, copper, gold, nickel, nickel, and (iv) at least a metal species in the group or The main soil is the & gold. In particular, it is desirable to form copper from the viewpoint of resistance and cost. In the present embodiment, copper is used for the "via hole A (16), the via hole 9) and the via hole c (22). 201021640 points, ί 严 - c (23) - the part of the layer 24 material, the use of _ raw anti-7 welding oil in the 'line C (23) surface, can also be written by the white Ά文 resistance layer 24 opening At least one metal or a combination of the groups. The real 'Shi shape family and 0. 5μιη gold are stacked in sequence. ~, the intermediate density of 3μιη nickel capacitor Ϊ can be set to transfer the surface of the four (s) s! 〇t ΖΓ〇 2 ^ PZT (PbZr Ti 4 5 and other metal oxides, BST (BaxSri-xTi〇3), constitute a capacitor Dielectric It (4), Murano Organic Materials, etc. In addition to the present embodiment, the semiconductor element or capacitor has a high yield and high reliability in a narrow-pitch, multi-pin half-H-t-conductor device. Ϊΐ 装 装 有 有 有 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Fig. 3 is a cross-sectional view showing the semiconductor device of the third embodiment. The side portion of the rotating body member 13 and a portion having the surface of the electrode terminal 14 and the insulating layer A are placed. (15) In the front and back of the electrode terminal 14, the electrode terminal 14 and the external connection terminal wiring c of the semiconductor device 12 are electrically connected to the via hole A (16), the wiring layer (Π), and the insulating layer (8). Interlayer hole Β (20), insulating layer C (21), via hole C (22), via hole D (32), wiring depth To the wiring C (23) - the opening portion, the solder resist layer 24 is provided. In Fig. 3, the number of layers is sandwiched by the semiconductor element 13 on the front and back layers, but = is limited to this, and any layer may be any layer. In the present embodiment, the front and back surfaces are defined as three layers of a wiring layer and three layers of an insulating layer. In FIG. 3, the cross-sectional shape of the interlayer layer is increased in the order of 21 201021640 via hole A (16), via hole B (19), and via hole C (22), and the wiring cross-sectional shape is wired A ( 17), (the wiring D (33), the wiring B (2 〇), and the wiring c (23) are sequentially increased, and the insulating layer is provided with an insulating layer A (15) between the electrode terminal 14 and the wiring A (17), The order of the insulating layer B (18) and the insulating layer C (21) is thickened, but the cross-sectional shape of the via hole and the shape of the cross-section of the cross-section are not included in the layer-by-layer. It is desirable to thicken the insulating layer as the diameter of the via hole is increased. : The cross-sectional shape of the via hole represents the top diameter and the bottom diameter and height of the via hole. The cross-sectional shape of the via hole is increased, if not limited, It can be used only for the top of the mesopores with the larger pore diameter than the top of the nibble. The bottom of the mesopores is the one with the smaller pore diameter. The bottom of the mesopores. The fiber is connected to the narrow-pitch semiconductor 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Table minimum wiring width (top diameter, bottom diameter), wiring t I f stomach wiring rules and wiring thickness, which can be increased by only 1 production, increase, representing the wiring rules, from narrow pitch, narrow width Ϊ́ϋ ί ί , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 13 ❹ ❹ ' ' ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί It can improve the thickness of the semiconductor device by the diameter of the t, the insulation layer from the thinner to the thicker, and the thickness adjustment of the semiconductor device of the body. The number of the 13 conductors is one, but also two 2.30~50陴 In Fig. 3, 'semi-insulating layer A (l5), insulating layer _, insulating layer C (21), for example, formed by photosensitive or 22 201021640 ίίίί, 'organic materials such as using county resin, epoxy _ = acid Vinegar resin, vinegar wax, benzophenone, polystyrene, hydrazine (benzine per butylene, benzocyclob Utene), PBO (polybenzoxene, polycondensation 3 浠 resin, etc., or glass cloth or linalin fiber, etc. ίηίΪ or Γ woven fabric impregnated epoxy resin, epoxy acrylate resin, amine acrylate 曰 日, Polyester resin, benzoquinone resin, polyimide resin, BCB (benzo ring ^ ^ aeydobmene), PB 〇 (polybenzoxene salicyl] decene resin, etc. J ^

又’各絕緣層’除有機材料以外也可使用氮切、鈦、 |太酸錯酸錯、碳化石夕、塊滑石、氧化鋅等氧化物系、、 Ϊ Ϊί、碳化物系、碳酸鹽系、氮化物系、鹵化物系、磷酸鹽 i之上述喊或玻璃等含於填充料之複合材料，或奈米i g、類鑽石反、聚對二曱苯基等材料。 A ❹In addition to the organic material, the 'insulating layer' may also be an oxide system such as nitrogen cut, titanium, | too acid wrong acid, carbon carbide, talc, zinc oxide, etc., Ϊ Ϊ, carbide, carbonate , nitride, halide, phosphate i, such as shouting or glass, or other composite materials contained in the filler, or nano ig, diamond-like reverse, poly-p-phenylene and other materials. A ❹

,為了達成高產量之半導體裝置，希望要求最微細介層孔直 徑、配線酬、、薄絕緣狀半導體元件側之電極端子之最近接声 之絕緣材制感絲獅，其:ϋ使祕以y^YAG雷射形& ^層，之非感光性麟，於要求最A介層孔直徑、最錄配線規 則、厚絕緣層之外部連接端子之近麟之絕緣材，採用能以co 雷射形成介層孔之玻璃布等補強材含浸過之非感光性樹脂。藉由2 如此適當採用適於各層要求之配線酬、介層孔麻形狀、^緣 層厚之絕緣獅、處理，碰能達成高產量，也能達成低成本: 又，藉由於各層改變絕緣材料，能期待各種效果。例如，藉 由於微細介層孔為必要之層採用低彈性之絕緣材，能提升可^ 性。又，藉由於絕緣層厚之層採用高彈性率之絕緣材，可達成半 導體裝置之低翹曲化。本實施形態中，絕緣層A(15)、絕緣層 B(18)、絕緣層C(21)使用非感光性樹月旨之環氧樹脂。 、曰 配線A(17)、配線B(20)、配線C(23)、配線D(33)，使用例 ，由銅、銀、金、鎳、鋁、及鈀構成之族群中至少丨種金屬或以 5亥等為主成分之合金。尤其，從電阻値及成本之觀點，希望由銅 形成。本實施形態中，幣線A(n)、配線B(2〇)、配線c(23)、配 23 201021640 線D(33)使用銅。 介層孔A(16)、介層孔B(19)、介層孔c(22) '介層 自例如銅、銀、金、鎳、銘、及輯成乂族群;(？ 為主成分之合金。尤其，從電阻値及成本之觀點 ^望由銅形成。本實施形態中，介層孔Α(16)、介層孔Β(19)、介 層孔C(22)、介層孔d(32)使用銅。 v、ΐ導體裝置12之最頂面’以露出外部電極配線C(23)之-部 覆蓋其餘部分之方式’形成抗焊層24。本實郷態中，抗焊 曰之材料’使用感光性抗焊油墨。從抗焊層24開口之配線 選自金、銀、銅、錫及焊藥材料構成之^群^ 少^種至屬或合金形成。本實施形態中，將厚度3μιη之錄及〇 5 之金依序疊層。 ^ 雷^可層之所望位置’設置發揮電路之雜訊猶器作用的 。構成電容器之介電體材料，宜為氧化鈦、氧化组、Ai々3、 ΖϋΓ〇2、Hf〇2或灿2〇5等金屬氧化物、㈨、 =T(=ZrxTil_x〇3)或 PLZT(pbi ΜΖΓχΤί〗A)等 r lzTaj)9等Βι系層狀化合物較佳。但，ogxg、〇<y<1。又就 之介電體材料，亦可使用混合有無機材料或磁性材料 件。料等。又’半導體元件或電容器以外，也可設置分離零 又，亦可使半導體裝置12之半導體元件13之電極端子Μ 體元件13之侧面之絕緣材變化，於半導體元件13之侧面 ί 由Λ半導體元件13之侧面使用高剛性絕緣 不此使半導體裝置12低翹(曲化，提升可靠性。 道躺Ϊ照本實施形態，於峨窄間距、多接腳之半導體元件之半 造並f置之半導體元件内建基板之多層化中，達成半導體元件内 ίίΪ之高產量化、高可#性化。又，藉由從與半導體元件接近 曰起緩慢地使介層孔剖面形狀、配線剖面形狀增大，並伴隨於 12絕緣層’能將於各邊界面之形狀之劇烈變化減*，能減小 D心射，改善汛號品質。又，由於在半導體元件之兩面設置相 24 201021640 故能達成低魅曲化。又’本構造，由 因此可將其他半導體元件或電子零件 同構成之無核心層配線層， 於兩面均有外部連接端子， 裝載於雙面。 [實施形態4] 圖4顯示實施形態4之半導體裝置之剖面圖。圖*之 裝置12，於半導體元件13之側面及具電極端子14之面至少兑中 一部分與絕緣層A(15)相接，於電極端子14上設有金屬柱3〇了且 於電極端子14之表背面，設有將電極端子14與係半導體裝置口 之外部連接端子的配線C(23)電連接之配線A(17)、絕緣層 介層孔B(19) '配線B(20)、絕緣層C(21)、介層孔c(22)、介芦 D(32)、配線D(33)。又，以將配線C(23)一部開口之方式設& 層24。圖4中，層數夾隔著半導體耕13，表#面為3層， 限於此等，只要是多數層可為任何層。本實施形態中，表背面定 為配線層3層、絕緣層3層。該實施形態4中，實施形_ 3之介 層孔A(16)取代為金屬柱3G，但是該金屬柱3G，作為連^電極二 子14與配線A(17)之介層孔的作用。 又，圖4中，介層孔剖面形狀依金屬柱3〇、介層孔B(l9)、介 層孔C(22)順序加大，且配線剖面形狀依配線A(l7) (In order to achieve a high-yield semiconductor device, it is desirable to require the most fine-layer via hole diameter, wiring compensation, and the recently connected sound of the electrode terminal on the side of the thin-insulated semiconductor element to sense the silk lion, which is: ^YAG laser shape & ^ layer, non-photosensitive lin, in the outer layer of the outer diameter of the interface hole, the most recording wiring rule, the thick insulation layer of the external connection terminal, the use of co laser A non-photosensitive resin impregnated with a reinforcing material such as a glass cloth forming a via hole. By using 2 as appropriate for the wiring of the layers, the shape of the hole, the thickness of the hole, the thickness of the insulating lion, the treatment, the bump can achieve high output, but also achieve low cost: In addition, due to the change of insulation materials I can expect various effects. For example, it is possible to improve the reliability by using a low-elasticity insulating material as a layer necessary for the fine mesopores. Further, since the insulating layer is made of a layer having a high insulating layer, the low warpage of the semiconductor device can be achieved. In the present embodiment, the insulating layer A (15), the insulating layer B (18), and the insulating layer C (21) are made of an epoxy resin which is not photosensitive.曰 wiring A (17), wiring B (20), wiring C (23), wiring D (33), use examples, at least one of the group consisting of copper, silver, gold, nickel, aluminum, and palladium Or an alloy containing 5 hai as the main component. In particular, it is desirable to form copper from the viewpoint of resistance and cost. In the present embodiment, copper is used for the coin line A (n), the wiring B (2 〇), the wiring c (23), and the line 23 201021640 line D (33). Interlayer hole A (16), mesoporous hole B (19), mesoporous hole c (22) 'interlayer from, for example, copper, silver, gold, nickel, Ming, and series into a group of scorpions; (? In particular, it is formed of copper from the viewpoint of resistance and cost. In the present embodiment, the via hole (16), the via hole (19), the via hole C (22), and the via hole d (32) The use of copper v. The top surface of the conductor device 12 is formed to form the solder resist layer 24 in such a manner that the portion of the external electrode wiring C (23) is exposed to cover the remaining portion. In the actual state, the solder resist is The material 'uses a photosensitive solder resist ink. The wiring from the opening of the solder resist layer 24 is selected from the group consisting of gold, silver, copper, tin, and a solder material, and is formed of a genus or an alloy. In the present embodiment, The thickness of 3μιη and the gold of 〇5 are laminated in sequence. ^ The position of the desired layer of the layer can be set to function as a noise device for the circuit. The dielectric material constituting the capacitor should be titanium oxide or oxidation group. , metal oxides such as Ai々3, ΖϋΓ〇2, Hf〇2 or 灿2〇5, (9), =T(=ZrxTil_x〇3), or PLZT (pbi ΜΖΓχΤί〗A), etc. r lzTaj)9, etc. The compound is preferred. However, ogxg, 〇<y<1. Further, as the dielectric material, an inorganic material or a magnetic material may be used. Materials and so on. Further, in addition to the semiconductor element or the capacitor, the separation of the zeros may be provided, and the insulating material on the side of the electrode terminal body element 13 of the semiconductor element 13 of the semiconductor device 12 may be changed, and the side surface of the semiconductor element 13 may be made of a semiconductor element. The use of high-rigidity insulation on the side of the 13 does not cause the semiconductor device 12 to be low-profiled (curvature, improve reliability). In the present embodiment, the semiconductor device is fabricated in a narrow pitch and multi-pin semiconductor device. In the multilayering of the built-in substrate of the device, the high-yield and high-yield of the semiconductor device are achieved, and the cross-sectional shape of the via hole and the cross-sectional shape of the via are slowly increased by being close to the semiconductor device. With the 12-insulation layer', the sharp change in the shape of each boundary surface can be reduced, the D-heart shot can be reduced, and the quality of the nickname can be improved. Moreover, since the phase 24 201021640 is provided on both sides of the semiconductor element, the low can be achieved. The enchantment is also a structure in which a coreless wiring layer which can be formed by other semiconductor elements or electronic components is provided, and external connection terminals are provided on both sides, and are mounted on [Embodiment 4] Fig. 4 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. The device 12 of Fig. 4 is provided with at least a part of the surface of the semiconductor element 13 and the surface of the electrode terminal 14 and the insulating layer A (15). In connection with the electrode terminal 14, a metal post 3 is provided on the front and back surfaces of the electrode terminal 14, and a wiring A for electrically connecting the electrode terminal 14 to the wiring C (23) of the external connection terminal of the semiconductor device port is provided. (17) Insulation layer via hole B (19) 'Wiring B (20), insulating layer C (21), via hole c (22), dielectric reed D (32), wiring D (33). The layer 24 is provided in such a manner that the wiring C (23) is opened at one portion. In Fig. 4, the number of layers is sandwiched by the semiconductor tiller 13, and the surface of the surface #3 is three layers, and is limited to any layer as long as it is a plurality of layers. In the present embodiment, the front and back surfaces are defined as three layers of a wiring layer and three layers of an insulating layer. In the fourth embodiment, the via hole A (16) of the form _3 is replaced by the metal pillar 3G, but the metal pillar 3G, As a mesoporous hole of the electrode 2 and the wiring A (17), in FIG. 4, the cross-sectional shape of the via hole is based on the metal pillar 3, the via hole B (19), and the via hole C (22). ) the order is increased, Cross-sectional shape of the wiring by the wiring A (l7) (

配線B⑽、配線C(23)順序加大，_端子14與』線心：^)依 絕緣層A(15)、絕緣層B(18)、絕緣層C(21)順序膜厚增厚，但是， 介層孔剖面形狀、配線剖面形狀任1以上，在各層不同即可 介層孔剖面形狀，代表介層孔之頂直徑與底直徑及高度。介 層孔剖面形狀之加大，如無特別限定，可僅於其中之τ項二上加 大三以介層孔直徑較大者為介層孔之頂部’並以介層孔直徑較小 者疋為介層孔之底部。希望介層孔之底侧成為與窄間距之半導體 元件的連接處。其中’從訊號品質之觀點，希望從半導體元件之 近接層，介層孔剖面形狀以相似的加大。。 配線剖面形狀係指：最小配線寬(頂直獲、底直徑）、配線間之 間距、所謂配線規則及配線厚度，該等之中可僅加大丨以上。配 線剖面形狀之加大，係指於配線規則中，從窄間距、窄寬度移轉 25 201021640 势J見鬆間距、寬鬆寬度，配線厚中，從薄者往厚者移轉。希望從 半導體元件之近接層，配線剖面形狀緩慢加大。 為了達成高產量半導體裝置，希望從接近半導體元件13之層 起)介層孔剖面形狀、配線剖面形狀缓慢增大，伴隨於此，絕^ 厚，亦即’從半導體元件13之近接層起，配線規則從窄間距、 ，寬度往寬鬆間距、寬鬆寬度移轉，介層孔直徑從小直徑往大直 徑移轉，絕緣層從薄者往厚者移轉，但不限於此等。 人精田配綠規則為從窄間距、窄寬度往寬鬆間距、寬鬆寬 度移轉，介層孔直徑從小直徑往大直徑移轉，絕緣層從薄2 者移，’能提升半導體裝置12之可靠性。 導體元件13，厚度可視目標半導體裝置之厚度調整。 施形態中，半導體元件13之厚度定為3〇〜5〇μιη。圖4中^ 體元件13之數係為丨個，但也可為多數。 絕緣層A(15)、、絕緣層B(18)、絕緣層c(21)，例如以感光性 ^感光性有機材料形成’有機材料使關如環氧樹脂、環氧 m醋丙，酸酯樹脂、聚酯樹脂、*酚樹脂、_亞： 曰、CB(苯并環丁婦，benzocyclobutene)、PBO(聚苯并噚唑， 匕、聚降1烯樹脂等’或玻璃布絲§驗纖維等形 不Ϊ布中含浸環氧樹脂、環氧丙烯酸酯樹脂、胺酯丙 --s ’ a、聚酯樹脂、苯酚樹脂、聚醯亞胺樹脂、(苯并 ' PBO(^#ofo±'p〇lyb—le)' h π又各邑緣層，除有機材料以外也可使用氮化矽、鈦酸鋇、 鈦錯、碳化秒、塊滑石、氧化鋅等氧化物系氯 減玻麟含於填紐之複合材料，或奈米碳 官、類鑽碳、聚對二甲苯基等材料。 τ 丁反 和、量之半導體裝置，希望要求最微細介層孔直 之絕緣# 半導體元件侧之電極端子之最近接層 、’、曰木感光性樹脂，於其次之層採用能以uv-YAG雷射 26 201021640 形成介層孔之非感光性樹脂，於要求最大介層孔直徑、最寬鬆配 線規則、厚絕緣層之外部連接端子之近接層之絕緣材，採用能以 c〇2雷射形成介層孔之玻璃布等補強材含浸過之非感光性樹脂。 如此，於各層適當採用適於要求之配線規則、介層孔剖面形狀、 絕緣層厚之絕緣材料、處理，能不僅是達成高產量，也達成低成 本0 _ ❹ 又，藉由於各層改變絕緣材料，能期待各種效果。例如，藉 由於微細广層孔為必要之層採用低彈性之絕緣材，能提升可靠 性。又，藉由於絕緣層厚之層採用高彈性率之絕緣材，可達成半 導體裝置之低龜曲化。本實施形態中，、絕緣層A(15)、絕緣戶 B(18)、絕緣層c(21)使用非感光性樹脂之環氧樹脂。 配線A(17)、配線b(20)、配線C(23)、配線D(33)，使用例如 金、錄、銘、及輯成之族群中至少1種金屬或以該 ?為^/刀之合金。尤其’從電阻値及成本之觀點，希望由銅形 態中’配線Α(17)、配線Β(2〇)、配線C(23)、配線 =射L B(19)、介層孔C(22)、介層孔D(32)，使用例如由銅、 二及1^所構成族群中至少1種金屬或以該等為主 眚二二ί °ίί ’從電阻値及成本之觀點，希望由銅形成。本 =二ΪΙΓ，介層孔c(22)、介層孔_使用銅。 八ΐίϊϊ置之取頂面，以露出外部電極配線c(23)之-部 =亚覆纽餘部分之方式’形成抗料24。本實施形態中，抗 使^感光性抗焊油墨。從抗焊層24開口之配線 中自金、銀、銅、錫及焊藥材料構成之族群 電六$可;斤望位置’設置發揮電路之雜訊過遽器作用的 S f介電體材料，宜為氧化欽、氧化组、Α1Α、 卿卿㈣或孔ZT(Pbl_yLayZ讯綱^^ 27 201021640The wiring B (10) and the wiring C (23) are sequentially increased, and the _ terminal 14 and the "wire core: ^) are thickened in thickness in the order of the insulating layer A (15), the insulating layer B (18), and the insulating layer C (21), but The cross-sectional shape of the via hole and the cross-sectional shape of the interconnect layer may be one or more, and the cross-sectional shape of the via hole may be different in each layer, and represents the top diameter and the bottom diameter and height of the via hole. The shape of the cross-section of the mesopores is increased, and if it is not particularly limited, it may be increased by only three of the τ terms, and the larger the pore diameter of the via is the top of the via hole, and the diameter of the via hole is smaller.疋 is the bottom of the via. It is desirable that the bottom side of the via hole be a junction with a narrow pitch semiconductor element. Among them, from the viewpoint of signal quality, it is desirable to similarly increase the cross-sectional shape of the via hole from the vicinity of the semiconductor element. . The wiring cross-sectional shape refers to the minimum wiring width (top straightening, bottom diameter), the spacing between the wirings, the so-called wiring rule, and the wiring thickness, and may be increased by more than 丨. The increase in the cross-sectional shape of the wiring means that it is transferred from the narrow pitch and the narrow width in the wiring rule. 25 201021640 The potential J sees the loose pitch, the loose width, and the wiring thickness is transferred from the thinner to the thicker. It is desirable that the cross-sectional shape of the wiring is gradually increased from the vicinity of the semiconductor element. In order to achieve a high-output semiconductor device, it is desirable to gradually increase the cross-sectional shape of the via hole and the cross-sectional shape of the wiring from the layer close to the semiconductor element 13, and accordingly, it is thick, that is, 'from the close-up layer of the semiconductor element 13, The wiring rules are shifted from a narrow pitch, a width to a loose pitch, a loose width, a via hole diameter is transferred from a small diameter to a large diameter, and the insulating layer is transferred from a thinner to a thicker, but is not limited thereto. The rule of human fine field and green is to shift from narrow pitch, narrow width to loose pitch and loose width. The diameter of the via hole is transferred from small diameter to large diameter, and the insulating layer is moved from thin to thin, which can improve the reliability of the semiconductor device 12. Sex. The thickness of the conductor element 13 can be adjusted depending on the thickness of the target semiconductor device. In the embodiment, the thickness of the semiconductor element 13 is set to 3 〇 to 5 〇 μιη. The number of the physical elements 13 in Fig. 4 is one, but it may be a plurality. The insulating layer A (15), the insulating layer B (18), and the insulating layer c (21) are formed, for example, of a photosensitive organic material, such as an epoxy resin, an epoxy vinegar, an acid ester resin, or the like. Polyester resin, *phenol resin, _ sub: bismuth, CB (benzocyclobutene, benzocyclobutene), PBO (polybenzoxazole, hydrazine, polyethylene resin, etc.) or glass cloth § fiber Impregnated epoxy resin, epoxy acrylate resin, amine ester C-s ' a, polyester resin, phenol resin, polyimine resin, (benzo-PBO (^#ofo±'p〇) Lyb-le)' h π and each edge layer, in addition to organic materials can also be used tantalum nitride, barium titanate, titanium wrong, carbonized seconds, talc, zinc oxide and other oxides Newcomer composite material, or nano carbon official, diamond-like carbon, parylene, etc. τ Ding anti-sum, the amount of semiconductor devices, it is desirable to require the most fine layer of holes straight insulation # semiconductor element side of the electrode terminal Recently, the contact layer, ', eucalyptus photosensitive resin, in the second layer, can use the uv-YAG laser 26 201021640 to form the via hole non-photosensitive The resin is impregnated with a reinforcing material such as a glass cloth which can form a via hole with a c〇2 laser in a contact layer which requires a maximum via hole diameter, a loosest wiring rule, and an external connection terminal of a thick insulating layer. Non-photosensitive resin. In this way, it is possible to use not only the wiring rules suitable for the required wiring rules, the cross-sectional shape of the via hole, and the insulating layer thickness of the insulating layer, but also the high-yield and low-cost 0 _ ❹ Since each layer changes the insulating material, various effects can be expected. For example, a low-elastic insulating material can be used for the layer which is necessary for the fine and wide-layered holes, and the reliability can be improved. Moreover, the insulating layer is made of a high-elasticity insulating layer. In the present embodiment, the insulating layer A (15), the insulator B (18), and the insulating layer c (21) are made of an epoxy resin of a non-photosensitive resin. (17), wiring b (20), wiring C (23), and wiring D (33), for example, at least one metal of the group of gold, recorded, inscribed, and composed, or an alloy of the same Especially, from the point of view of resistance and cost, hope In the copper form, for example, 'wiring Α (17), wiring Β (2 〇), wiring C (23), wiring = shot LB (19), via hole C (22), via hole D (32), for example, It is desirable to form copper from at least one metal of the group consisting of copper, two, and 1^ or from the viewpoint of resistance and cost from the viewpoint of cost and cost. Ben = two turns, mesopores c (22), the via hole _ uses copper. The top surface of the octagonal layer is formed to expose the portion 24 of the external electrode wiring c (23) to form the resist material 24. In this embodiment, Resistant to photosensitive solder resist ink. From the wiring of the anti-welding layer 24, the group of electricity consisting of gold, silver, copper, tin and solder materials can be used for six months. The material of the S f dielectric material is preferably oxidized, oxidized, Α1Α, qingqing (four) or pore ZT (Pbl_yLayZ Xun ^^ 27 201021640

Bi系層狀化合物較佳。但，0么幻、吟<ι。又，就 + 士ί谷器之介電體材料，亦可使用混合有無機材料或磁性材料 有機材·。又’半導體元件或電容器以外，也可 仵0 盘半ί體體裝置12之半導體元件13之電極端子14面 ^體件13之側面之絕緣材變化，於半導體元件丨3之侧面 =用^剛性絕緣材。藉由於半導體耕13之侧面使用高剛性絕緣 ，月b使半導體裝置12低趣曲化，提升可靠性。 Θ 道辦本實施形態，於内建窄間距、多接腳之半導體元件之半 魅4、置ί半導體讀喊基板之多層化中，達成半導體元件内 夕之⑥產量化、高可靠性化。又’藉由從與半導體元件接近 ^起緩慢地使介層孔剖面形狀、配線剖面形狀增大，並伴 緣層’能將於各邊界面之形狀之顧變化減小，能減小 miit，善訊m ’由於在半導體元件之兩面設置相 问構成之無核心層配線層，故能達成低翹曲化。 :彻元件13之電極端子14上之金屬柱30作為介=將= Ϊ極端子14與外部連接端子之電連接，於設置絕緣層後不需將= 介層孔開口’故可消除因為小直徑介層孔造成之連 ❹ i 辟，可達成高可靠性、高產量之半導體=。 兀件或電子零件裝載於雙面。 導體 [實施形態5] 圖5齡實獅態5之無核^層喊基板之製妨 ，。依照本實施形態之製造方法，能製造實施職i之 ς圏 15)之無核心層配線基板。 】3(圖 屬ϊί ’ j5⑻所示準備支持體25。支持體25可為樹月旨、金 屬、玻璃、矽等任何材料或該等的組合。 ^ 其次，如圖5(b)所示，於支持體25上形成由電極 緣層A(15)、介層孔入⑽、配線A(17)構成之_體。 、，、邑 絕緣層A(l5)例如由感光性或非感光性有機材料形成，有機 28 201021640 用環氧樹脂、環氧丙烯酸轉脂、細旨丙烯酸輯脂、 聚酉曰树脂、苯酚樹脂、聚醯亞胺樹脂、BCB(苯并環丁 be，Cy，butene)、PB0(聚苯㈣唾，p〇lybenz〇xaz〇ie) 1 或芳醯胺纖維等形成之織布或不織布含浸環 婦酉夂醋樹脂、胺醋丙烯酸醋樹脂、聚酯樹脂、苯 轉月曰、聚_胺職、BCB(苯并環丁婦，benz〇cyd〇bu ㈣唾’⑽冲⑽聚降获稀樹脂等的材料。又， ，、、，邑緣層’在上述有機材料以外’也可使贱化⑪、鈦酸顧、氮 化^鈦酸錯酸錯、碳化石夕、塊滑石、氧化鋅等氧化物系 ' 氣氧 ❹化物糸、碳化物系、碳酸鹽系、氮化物系、_化物系、_^系 i陶ίίΐ相竞或玻璃等含於充填料之複合㈣，或奈米碳 官、，鑽石反、聚對二甲苯基(paryiene)等材料。 ❿f層Ϊ法’設計傳遞模塑法、壓_成模塑法、印刷法、直 -f空疊合、旋轉塗佈法、模塗法、簾塗法等。本實施开i 態中，以真空疊合形成環氧樹脂。 ' 之後’於絕緣層A(15)形成成為介層孔A(16)之孔。孔於絕緣 j、A(15)使用感光性材料時，以光微影形成。絕緣層a⑽使用非 感光性材料，或感光性材料且圖案解像度低之材料時，孔以雷射 ^法、乾式姓刻法或噴擊(blast)法形成。本實施形態中，使用雷 f加工法。其次’於孔内充填例如選自銅、銀、金、鎳、鋁、及 群Λ至少1種金屬或以該等為主成分之合金，形成介 填方法’以電解電鑛、無電解電鑛、印刷法、熔融 通°又’也可利用於成為介層孔之位置預先形成 ^電用柱後’形成絕緣層，並以研磨等削刮絕緣層之表面，露出 通電用柱並形成介層孔之方法。 β 4·配線^(17) ’利用減去法、半加成法或全加成法等方法开)成。 ’去法”設置在基板上之銅紅軸所望贿之防鑛層，將 =要的銅n侧後，娜防鍍層而得所望酿之方法。半加成法， ^以無電解電鍍法、濺錢法、CVD(chemical vap〇r deposition)法等 形成供電層後’形成開口於所望圖案之防鑛層，並於防鍍層開口 29 201021640 部内利用電解緩法使金屬析出，除去防鍍層触顺 ，π 所望配線圖案之方法。全加成法係於基板上使無電解麵& = 附後，以防鍍層形成圖案，並將該防鍍層殘留作為絕緣膜，^ 媒活化，利用無電解電鍍法於絕緣膜之開口部使金屬析出， 得到所望配線圖案之方法。配線Α⑼，係使用例如選自銅、^、 金、鎳、鋁、及鈀構成之族群中至少丨種金屬或以該等為主成^八 之合金。尤其，從電阻値及成本之觀點，希望由銅形成。 刀 其次，如圖5(c)所示，形成絕緣層B(18)、介層孔B(19)、配 線B(20)、絕緣層C(21)、介層孔c(22)、配線C(23)、抗焊層24。 疊層之層之配線剖面形狀、介層孔剖面形狀、絕緣層厚，希望比❹ 起圖5(b)之絕緣層A(15)、介層孔A(16)、配線A(17)更為加大或加 厚。又，於小直徑介層孔或微細配線為必要之層中，希望介層孔 开>成使用UV雷射，配線形成使用半加成法，於能以大直徑介層 孔或I鬆寬度、寬鬆間距之配線因應之層中，介層孔形成希望利 用紫外線照射得到光介層孔或使用C〇2雷射，配線形成希望使用 減去法。如此，藉由依照配線剖面形狀、介層孔剖面形狀、絕緣 -層厚之變化，分別選用裝置、處理、絕緣材，能提升多層化之產 量並達成低成本。本實施形態中，如圖5(c)所示，層數定為3層， 但不限於此。本實施形態中，於連接半導體元件之最近接層（第i 層)之介層孔形成、配線形成，使用uv雷射及半加成法，以下之 層（第2層以下)中，使用c〇2雷射及減去法。第1層之介層孔直徑 為頂直徑25μιη、底直徑15μιη、L/S為ΙΟμτη/ίΟμπ!。第2層以下 之介層孔直徑為：頂直徑80μηι、底直徑70jjm、L/S為50μπι/5〇μιη。 又，絕緣層厚係第1層約20μιη，第2層以下約50μιη。 其次’如圖5(d)所示，除去支持體25。 藉由採本實施形態，能以良好效率製作連接窄間距、多接腳 之半導體元件的無核心層配線配線基板11。又，配線基板11 ’隨 著層數增加，配線剖面形狀、介層孔剖面形狀加大，且絕緣層厚 增厚，藉由因應於此選擇適當的裝置、處理、絕緣材，町達成高 產I、南可靠性之配線基板11。 30 201021640 [實施形態6] 圖6顯不實施雜6之半導體裝置之製造方法之步。依 照本貫施形態之圖6(a)至⑹所示製造方法，可製造實 2)之半導《置。 (1S1 首先，如圖6⑻所示準備支持體25。支持體％可為樹脂、金 屬、玻璃、發等任一材料或該等的組合。 其次如圖6(b)所示，於支持體25上形成由電極端子14、絕緣 層A〇5) '介層孔A(16)、配線A(17)構成之配線體。 絕緣層巧5)例如由感光性或非感光性有機材料形成，有機材 料例如使用魏樹脂、環氧丙烯_旨樹脂、胺g旨㈣咖旨樹脂、 聚酯樹脂、苯酚樹脂、聚醯亞胺樹脂、BCB(苯并環丁 benzocydobutene)、PB0(聚苯并嘮唑，ρ_⑽咖此）、聚 烯樹脂H綱布或絲胺纖料形成之織布或不織 氧樹脂、環氧丙烯酸醋樹脂、胺醋丙稀酸輯脂 二 麟脂、聚酿亞胺樹脂、BCB(苯并環丁烯，be㈣cycl〇=本 ’PGlybenZGXaZGle)、科__等的材料。^， ^、邑緣層，在上述有機材料以外，也可使用氮化秒、鈦酸顧、氮 t '塊滑石、氧化鋅等氧化物系 鲁 石反化物系、碳酸鹽系、氮化物系、齒化物系、磷酸鹽系 i ίίΐ述或玻f等含於充填料之複合材料，或奈米ί 吕j鑽石反、聚對一甲苯基(paiylene)等材料。 層Ϊ法設計有傳遞模縣、壓_賴魁、印刷法、真 :製产5疊合、旋轉塗佈法、模塗法、簾塗法等4實施ί 心中，％乳树脂以真空疊合形成。 孔於^於Α(15)之設置置介層孔Α(16)之位置形成孔。 ’細紐獅成。絕緣層 時，？丨以^材枓或為感光性材料且圖案解像度低之材料 使用帝射、乾式蝴法射擊法形成。本實施形態中， 紹、I釦^4、法。/、次，於孔内充填例如由選自銅、銀、金、鎳、 ’ ’冓成之族群中至少1種金屬或以該等為主成分之合金， 31 201021640 進充填。方法以電解電# '無電解_、印刷法、 形成通電用柱後1形成絕緣層 ，括 zjj ^ 肖:、 使通電用柱露出，並形成介層孔之方法。相刮、、、巴緣層之表面， 、配線Α(17)，_減去法、半加成法或全加成 減去法，係於基板上設置之賴上形賴望 芦 ，，電鑛法、輕法、CVD(化學氣相沉積，— dep融on)法專形成供電層後，形成開口於所望圖案之防鍍戶，於 防鑛層開π勒细電解魏法使金屬析$，除去防鍍層^將供 圖案之方法。全加成法，係於基“使無The Bi-based layered compound is preferred. However, 0 illusion, 吟 < ι. In addition, as for the dielectric material of the + 谷谷谷, it is also possible to use an organic material mixed with an inorganic material or a magnetic material. Further, in addition to the semiconductor element or the capacitor, the insulating material of the side surface of the electrode terminal 14 of the semiconductor element 13 of the semiconductor device 13 of the body device 12 may be changed to the side of the semiconductor element 丨3. Insulation material. By using high-rigidity insulation on the side of the semiconductor cultivator 13, the monthly b makes the semiconductor device 12 less interesting and improves reliability. In the present embodiment, in the multilayering of the semiconductor device in which the narrow pitch and the multi-pin are built, the semiconductor device is printed in the multilayered circuit, and the production of the semiconductor device is achieved in the future. Further, by gradually increasing the cross-sectional shape of the via hole and the cross-sectional shape of the wiring from the vicinity of the semiconductor element, the edge layer can reduce the shape of each boundary surface, thereby reducing miit. Since the good news m' has a core-free wiring layer formed on both sides of the semiconductor element, low warpage can be achieved. The metal post 30 on the electrode terminal 14 of the component 13 is electrically connected to the external connection terminal of the electrode terminal 14 and is not required to be opened after the insulating layer is disposed. The high-reliability, high-yield semiconductor = can be achieved by the mesopores. The parts or electronic parts are mounted on both sides. Conductor [Embodiment 5] Figure 5: The lion-like state of the 5th lion state According to the manufacturing method of the present embodiment, it is possible to manufacture the coreless wiring board of the ς圏 15). 3) The support 25 is prepared as shown in Fig. 。ί ' j5 (8). The support 25 may be any material such as a tree, a metal, a glass, a crucible, or the like. ^ Next, as shown in Fig. 5(b), A body composed of an electrode edge layer A (15), a via hole (10), and a wiring A (17) is formed on the support 25. The insulating layer A (l5) is made of, for example, photosensitive or non-photosensitive organic. Material formation, organic 28 201021640 Epoxy resin, epoxy acrylate transester, fine acrylic resin, polyfluorene resin, phenol resin, polyimine resin, BCB (benzo ring, be, butene), PB0 (polystyrene (tetra) saliva, p〇lybenz〇xaz〇ie) 1 or arylamine fiber or the like formed of woven or non-woven fabric impregnated ring 酉夂 酉夂 vinegar resin, amine vinegar acrylic vinegar resin, polyester resin, benzene to menstruation , _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ It can also make oxides such as sulphuric acid, titanic acid, nitriding, titanic acid, acid, strontium, talc, and zinc oxide. Carbide, carbonate, nitride, _ _ _ _ ^ i ί ί ί 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 含 或 或 含 含(paryiene) and other materials. ❿f layer method 'design transfer molding method, pressure-forming molding method, printing method, straight-f empty lamination, spin coating method, die coating method, curtain coating method, etc. This implementation In the open state, the epoxy resin is laminated by vacuum. 'After', a hole which becomes the via hole A (16) is formed in the insulating layer A (15). When the photosensitive material is used for the insulating j and A (15) When the insulating layer a (10) is made of a non-photosensitive material or a photosensitive material and has a low pattern resolution, the holes are formed by a laser method, a dry type method or a blast method. In the form, a Ray F processing method is used. Secondly, the hole is filled with, for example, copper, silver, gold, nickel, aluminum, and at least one metal of the group or an alloy containing the same as the main component to form an intercalation method. Electrolytic ore, electroless ore, printing method, and melting pass can also be used to form a dielectric hole in advance. After the column, the insulating layer is formed, and the surface of the insulating layer is scraped by polishing or the like to expose the pillar for energization and to form a via hole. β 4·Wiring^(17) 'Using subtraction method, semi-additive method or full Addition method and other methods are opened. The 'go method' is set on the copper-red shaft on the substrate, and the anti-mine layer is expected to be bribed. Method, after forming a power supply layer by electroless plating, splashing, CVD (chemical vap〇r deposition), etc., 'forms an anti-mine layer that opens in a desired pattern, and utilizes electrolysis in the anti-plating opening 29 201021640 A method of precipitating a metal to remove the plating resist and π looking at the wiring pattern. The full addition method is applied to the substrate so that the electroless surface & = is attached to prevent the plating layer from forming a pattern, and the plating resist remains as an insulating film, and the medium is activated, and the electroless plating method is used to open the opening portion of the insulating film. A method in which a metal is deposited to obtain a desired wiring pattern. The wiring raft (9) is made of, for example, at least a metal selected from the group consisting of copper, gold, nickel, aluminum, and palladium, or an alloy thereof. In particular, it is desirable to form copper from the viewpoint of resistance and cost. Next, as shown in FIG. 5(c), the insulating layer B (18), the via hole B (19), the wiring B (20), the insulating layer C (21), the via hole c (22), and the wiring are formed. C (23), solder resist layer 24. The cross-sectional shape of the wiring layer, the cross-sectional shape of the via hole, and the thickness of the insulating layer are preferably more than the insulating layer A (15), the via hole A (16), and the wiring A (17) of Fig. 5 (b). To increase or thicken. Further, in a layer in which a small-diameter via hole or a fine wiring is necessary, it is desirable that the via hole is opened to use a UV laser, and the wiring is formed using a semi-additive method to enable a large-diameter via hole or I loose width. In the layer where the wiring of the loose pitch is required, the formation of the via hole is desired to obtain the photo via hole by ultraviolet irradiation or the C〇2 laser is used, and the wiring formation is desirably used. In this way, by selecting the device, the treatment, and the insulating material in accordance with the change in the cross-sectional shape of the wiring, the cross-sectional shape of the via hole, and the thickness of the insulating layer, the throughput of the multilayer can be increased and the cost can be reduced. In the present embodiment, as shown in FIG. 5(c), the number of layers is set to three, but the present invention is not limited thereto. In the present embodiment, the via hole is formed and the wiring is formed in the nearest layer (i-th layer) to which the semiconductor element is connected, and the uv laser and the semi-additive method are used, and the following layer (the second layer or lower) is used. 〇 2 laser and subtraction method. The via hole diameter of the first layer is a top diameter of 25 μm, a bottom diameter of 15 μm, and L/S is ΙΟμτη/ίΟμπ!. The pore diameter of the second layer or less is: a top diameter of 80 μm, a bottom diameter of 70 jjm, and an L/S of 50 μm λ/5 〇 μηη. Further, the thickness of the insulating layer is about 20 μm in the first layer and about 50 μm in the second layer. Next, as shown in Fig. 5(d), the support 25 is removed. According to the embodiment, the coreless layer wiring substrate 11 to which the semiconductor elements having the narrow pitch and the plurality of pins are connected can be formed with good efficiency. In addition, as the number of layers increases, the wiring board 11' increases the cross-sectional shape of the wiring and the cross-sectional shape of the via hole, and the thickness of the insulating layer is increased. By selecting an appropriate device, process, and insulating material, the town achieves high yield. , South reliability wiring board 11. 30 201021640 [Embodiment 6] FIG. 6 shows a step of manufacturing a semiconductor device in which the hybrid 6 is implemented. According to the manufacturing method shown in Figs. 6(a) to (6) of the present embodiment, the semi-conductive "" of the actual 2) can be manufactured. (1S1 First, the support 25 is prepared as shown in Fig. 6 (8). The support % may be any material such as resin, metal, glass, hair, or the like, or a combination thereof. Next, as shown in Fig. 6 (b), on the support 25 A wiring body composed of the electrode terminal 14 and the insulating layer A 〇 5) 'via hole A (16) and wiring A (17) is formed thereon. The insulating layer 5) is formed, for example, of a photosensitive or non-photosensitive organic material, and the organic material is, for example, a Wei resin, an epoxy propylene resin, an amine resin, a polyester resin, a phenol resin, or a polyimine. Resin, BCB (benzocyclobutene benzocydobutene), PB0 (polybenzoxazole, ρ_(10) coffee), olefinic resin H fabric or silk fibroin fiber woven or non-woven resin, epoxy acrylate resin , amine acetoacetate, lipid, linoleum, styrene, BCB (benzocyclobutene, be (tetra) cycl 〇 = this 'PGlybenZGXaZGle), __ and other materials. ^, ^, 邑 edge layer, in addition to the above organic materials, nitrite second, titanate, nitrogen t 'block talc, zinc oxide and other oxide-based ruthenium, carbonate, nitride system A material such as a toothed system, a phosphate system, or a composite material such as glass frit, or a material such as nano-ru-ru-diamond or pa-ene. The layer Ϊ method is designed to transfer mold county, pressure _ Lai Kui, printing method, true: production 5 stack, spin coating method, die coating method, curtain coating method, etc. 4 implementation, the core resin is vacuum laminated form. The hole is formed at a position where the layer hole (16) is disposed in the hole (15). 'Thin lions into. When insulating,?材料 枓 枓 枓 枓 为 为 为 为 为 感光 感光 感光 感光 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ In the present embodiment, the method is as follows: In addition, the pores are filled with, for example, at least one metal selected from the group consisting of copper, silver, gold, nickel, and ruthenium or an alloy containing these as a main component, and 31 201021640 is filled. The method comprises the steps of: forming an insulating layer by electrolytic electrolysis, electroless printing, forming a current-carrying column, and forming a dielectric layer, and forming a via hole. The surface of the scraper, the edge layer, the wiring layer (17), the _ subtraction method, the semi-additive method or the full addition subtraction method, which is set on the substrate and is placed on the substrate. After the mineralization method, light method, CVD (chemical vapor deposition, dep-melting on) method is formed to form the power supply layer, the anti-plating household opening in the desired pattern is formed, and the anti-mineral layer is opened by the TiO2 electrolysis method to cause the metal to be analyzed. , remove the anti-plating layer ^ will be the method of the pattern. Full-addition method

Iff „ 鋪用無轉電鍍絲絕_之開口部使 金屬析出，藉此得到駿配線圖案之方法。配線A(17)，例如使用 由選自銅、銀'金、鎳、鋁、及鈀構成之族群中至少】種金屬或 以該等為域分之合金。尤其，從電喊及成本之觀點，希望以 銅形成。Iff „ a method of depositing a metal by depositing a metal in the opening of the non-transfer plating wire. The wiring A (17) is, for example, made of copper, silver, gold, nickel, aluminum, and palladium. At least one of the metals in the group or the alloy in which the particles are divided. In particular, it is desirable to form copper from the viewpoint of electric shouting and cost.

其次，如圖6(c)所示，形成絕緣層B(18)、介層孔B(1配 B(20)、絕緣層C(21)、介層孔C(22)、配線c(23)、抗焊層％。疊 層之層之配線剖面形狀、介層孔剖面形狀、絕緣層厚，希望比起 圖6(b)之絕緣層A(15)、介層孔八(16)、配線A(17)為加大或加厚。 又，於小直徑介層孔或微細配線為必要之層中，希望介層孔形成 使用紫外線照射得到光介層孔或使用UY雷射，配線形成使^半 加成法，於能以大直徑介層孔或寬鬆寬度、寬鬆間距之配線因應 之層中，希望介層孔形成使用C〇2雷射，配線形成使用減去法。 如此，依照配線剖面形狀、介層孔剖面形狀、絕緣層厚之變化選 擇使用之裝置、處理、絕緣材，能達成多層化中之產量提升及低 成本。本實施形態中’如圖6(c)所示，層數定為3層，但是不限 於此。本實施形態中，於連接半導體元件之最近接層（第丨層)之介 層孔形成、配線形成，使用UV雷射與半加成法，以下之層（第2 32 201021640 廣以下)中，使用c〇2雷射及減去法。第i層之介層孔直 直徑25卿、底直徑、L/s為1〇μΐΏ/1〇μιη。第2層以二'义 層孔直徑定為頂直徑80μιη、底直徑70μιη、L/S為SOjim/SOLm/1 又，絕緣層厚定為第1層約2〇μπι、第2層以下為5〇叫。 其次，如圖6(d)所示’除去支持體25。 其次，如圖6(e)所示，在無核心層配線基板12之電極 上介由焊球41覆晶接合於半導體元件13。之後，於H4 =之無核心層配線基板U與半導體元件13 樹月 ❿ 仏底填樹脂42，目的為減小與半導觀件13間之月曰 =焊球41賴。科41只妓具魏確鑛封度 之微j 填底填_42 °焊球41 ’係由焊藥材料構成 之微小球’彻電鍍法、球轉印、_法形成 =Next, as shown in FIG. 6(c), an insulating layer B (18) and a via hole B (1 with B (20), an insulating layer C (21), a via hole C (22), and a wiring c (23) are formed. ), the solder resist layer %. The wiring cross-sectional shape of the laminated layer, the via hole cross-sectional shape, and the insulating layer thickness are desirably compared with the insulating layer A (15) and the via hole (16) of FIG. 6(b). Wiring A (17) is thickened or thickened. Also, in a layer where a small-diameter via hole or fine wiring is necessary, it is desirable to form a via hole using ultraviolet light to obtain a photo via hole or use a UY laser to form a wiring. In the layer which can be used for the wiring of large-diameter via holes or loose widths and loose pitches, it is desirable to use a C〇2 laser for the via hole formation, and the wiring is formed using the subtraction method. In the case of the wiring cross-sectional shape, the cross-sectional shape of the via hole, and the thickness of the insulating layer, the device, the processing, and the insulating material are selected, and the yield increase and the low cost in the multilayering can be achieved. In the present embodiment, 'as shown in Fig. 6(c) The number of layers is set to three, but is not limited thereto. In the present embodiment, the via holes are formed and connected to the nearest layer (the second layer) of the semiconductor element. Formation, using UV laser and semi-additive method, the following layer (2 32 201021640 or less), using c〇2 laser and subtraction method. The i-th layer of the mesopores straight diameter 25 qing, bottom diameter L/s is 1〇μΐΏ/1〇μιη. The second layer is defined by the diameter of the two 'layer holes' as the top diameter 80μιη, the bottom diameter 70μιη, L/S is SOjim/SOLm/1, and the thickness of the insulation layer is 1 layer is about 2 〇μπι, and the second layer is 5 〇. Next, as shown in Fig. 6(d), the support 25 is removed. Next, as shown in Fig. 6(e), the core-free wiring substrate 12 is provided. The electrode is flip-chip bonded to the semiconductor element 13 via the solder ball 41. Thereafter, the core layer wiring substrate U and the semiconductor element 13 are filled with the resin 42 at the bottom of the H4 = for the purpose of reducing the semi-conductive object. 13 months 曰 = solder ball 41 赖. Section 41 妓 确 确 确 矿 矿 矿 矿 矿 矿 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 42 42 42 42 41 41 41 41 41 41 41 41 41 41 41 41 Printing, _ law formation =

藥或無敗焊·料射麵。親樹H ΐ 材料構成，將半導體元件13以焊球41連接後充填。又， ’已記載覆晶接合所得半導體元件13 <連接_，m， 也可利用打線連結來連接。依以上步驟，^ ^ 導體裝置(圖2)。 /娜』I作實施形態2之半 ❹ 塑，可體疋件13之方式形成樹脂模塑。樹脂模 之半導體的^材料構成，以覆蓋裝載 塑法、壓縮形成模塑法、或印刷法等設置'。以使用模具之傳遞拉 腳之施形態’能以良好效率製作裂載有窄間距、多接 腳之+V體兀件的半導體裝置12{)又，伴 心層配線基板U之顺胸„，w轉體裝置12之無核 大，絕靜卿= 數增 線剖面形狀、介層孔剖面形狀加 ΐ達因應於此選擇適當的裝置、處理、絕緣材， T違成间產里、咼可罪性之半導體裝置 [實施形態7] =7及圖8顯示本發明之實施形態 法之步驟圖。依照圖7⑻〜⑹及圖 之牛*體裂置之衣仏方 製造實施形態3(圖^導體裝1 W ' (幻所示之製造方法’可 33 201021640 百先如圖7⑻所不，準備支持體25。 金屬、玻璃、石夕等任-材料日人25 了為秘月曰 用於㈣減” #合。域體25上，宜設有 用於裝載+¥體讀13之位置標記。 辨識，且能發揮作為位置桿纪之功要疋月bM间精度 #全屬，X刹田二f i: f 者即可，即使於支持體25上 支持體25為厚度〇.5mm之銅板，於支持_ 施幵入t中， 作為位置標記。 職於支持體25上以電解電鏡鎳(5哗) 其次’於圖7(b)形成配線d(33)。 ❹ 其次’如圖7(c)所示’於設有位置標記之 謂面朝上之狀態搭載半導體元件13佶俨 于體25上以所 本實施形態中，係内建之半導體元件° 、接缝為1000〜2_接腳之窄間距、多接腳之半為導體= 其次，如圖7(d)所示，疊層絕緣層a〇5)，使得 之電極端子14面與側面同時被覆蓋。 導-凡件3 絕緣層A(15)例如由感光性或非感光性有機材料形 轉，樹脂1環氧丙軸旨樹脂、職丙雜旨樹Ϊ 樹知、本酚樹脂、聚醯亞胺樹脂、BC s ❹ triobre)、PB0(聚苯并十坐，po1細職滅 3，布絲雜纖轉形成之織布料織布含Ϊ環 乳树鈿、裱氧丙烯酸酯樹脂、胺酯丙烯酸酯樹脂、 紛=二聚巧亞胺樹脂、BCB(苯并環丁烯七nzocyclobme曰⑽ PBO(聚笨并十坐，p〇iybenzoxaz〇ie)、聚降获嫌 各絕緣層，在战錢·㈣，也可又， 化硼、鈦酸锆酸鉛、碳化石夕、塊滑石、氧化辞等氧化、、、^ 化物系:、碳化物系、碳酸鹽系、氮化物系、_化物系 之陶寬及上述陶莞或玻璃等含於充填料之複合材肖太^ 管、類鑽碳、聚對二曱苯基(parylene)等材料。 次不木反 制ΐΐίί以傳遞模塑法、壓縮形成模塑法、印刷法、直空擠 製、真空$合 '旋轉塗佈法、模塗法、簾塗料設置ς， 34 201021640 態中，環氧樹脂以真空疊合形成。 又’圖7(d)中，半導體元件J3 描 相同絕緣層八⑽覆蓋，但是，也可將子二面與侧面係以 面與侧面以不同材質之絕緣材覆蓋。於之電ΐ端子 元件13之側面高度大致與半導 材二使传於+導體 ❹ 其夂，如圖7(e)所示，為了將半導體元件13上之 4 與外子電連接，形成介層孔Α⑽、配線Α(17)。子 Γίΐΐ以15)使用感光性材料時，以光微影形成。i緣層Α(⑸ 使用非感光性材料，或感光性材料且 之材θ 雷射加工法。其次，於孔内充填由例如選自銅mi用 =構成之族群中至少丨種金屬或以該等為主成分的合金、， 參 ^6)。充填方法，以電解電鍵、無電解電鍍、印刷法1 f金屬吸服等進行。又，域騎觀之位^先=|電= 絕开研磨等，藉此削刮絕緣層之表面，使通電 用柱露出形成介層孔之方法也可使用。 ^線5(17)，侧減去法、半加成法或全加成法等方法形成。 ίίί 置於基板上_羯上形成所望圖案之防鍛層並姓 編後’將防鍍層_得到所望_之方法。半加成法， t、電解電鍍法、濺鍍法、CVD(chemicalvapordeposition)法等形 成^電層後，形成開口為所望圖案之防鑛層，於防鏡層開口部内 ^解電鑛法使金屬析出’除去防鍍層後將供電層侧，得到所 酉己線圖案之方法。全加成法，係於基板上使無電解電鏡觸媒吸 以防鍍層形成圖案，並將該防鍍層殘留作為絕緣膜，將觸 苇活化，利用無電解電鍍法使於絕緣膜之開口部使金屬析出，藉 35 201021640 所望配線圖案之方法。配線A(17) ’例如使用選自由銅、銀、 至、銘、她構紅鱗巾至少1種麵或以鱗為主成分 之合金。尤其，從電阻値及成本之觀點，宜以銅形成。 其次’如圖8(f)所示，除去支持體25。 其-人’如圖8(g)所不，於半導體元件13之表背面依照絕緣層、 配、、’ 丨層孔形成之步驟，形成電路基板。此時，希望疊層之層 的配線剖面形狀、介層孔剖面形狀、絕緣層厚缓慢加大或力曰^厚: 又，於小直徑介層孔或微細配線為必要之層中，介層孔形成希望 使，紫外_射制光介層孔或使用UY雷射，配線形成希望使 用半加成法’於能以大直徑介層孔或寬鬆寬度、寬鬆間距之配線 因應之層中，介層孔形成希望使用c〇2雷射，配線形成希望使用 減去法β如此，依照配線剖面形狀、介層孔剖面形狀、絕緣層厚 之變化，分別選用裝置、處理、絕緣材，可達成於多層化之產量 提升及低成本。本實施形態中，如圖8(g)所示，表背面的層數各 為3層，但不限於此，只要是將層設置於半導體元件13之表背面 即可。又，本實施形態中，半導體元件之最近接層（第丨層)的介層 孔开>成、配線形成，使用UV雷射及半加成法，以下之層（第2層 以下）中’使用C〇2雷射及減去法。第1層介層孔直徑定為頂直徑 25μιη、底直徑15μπι、L/S為ΙΟμπι/ΙΟμπι。第2層以下之介層孔直 徑定為頂直徑80μιη、底直徑70μιη、L/S為50μιη/50μιη。又，絕❹ 緣層厚，於第1層約20μιη，2層以下為5〇μηι。 其次’於上層配線C(23)上形成抗焊層24之圖案。抗焊層24， 係為了展現半導體裝置12之表面電路保護及難燃性而形成。材料 由環氧系、丙烯酸系、胺酯系、聚醯亞胺系有機材料構成，視需 要也可添加無機材料或有機材料之填料。又，半導體裝置12也可 不設置抗焊層24。從配線C(23)之抗燁層24開口之表面，也可由 選自金、銀、銅、錫及焊料構成之族群中至少1種金屬或合金形 成。本實施形態中’係於配線C(23)之表面依序疊層厚度3μιη之 鎳及0.5μηι之金。 藉由採用本實施形態，能將窄間距、多接腳之半導體元件内 36 201021640 建，以良好效率製作具多數層之半導體裝置12。x，半_裝置 12隨著層數增加，配線剖面形狀、介層孔剖面形狀加大，絕^層 增厚，藉由因應於此選擇適當裝置、處理、絕緣材，可達成高產 量、高可靠性之半導體裝置12。 [實施形態8] 圖9及圖1〇顯示本發明之實施形態8之半導體裝置之製造方 ί之步f圖。如圖9⑻〜(Q及圖10(g)〜(i)所示製造方法，可製造 貫施形態4(圖4)之半導體裝置。Medicine or non-destructive welding material surface. The eutectic H ΐ material is constructed, and the semiconductor element 13 is connected by solder balls 41 and filled. Further, the semiconductor element 13 <connecting_, m obtained by flip chip bonding may be connected by wire bonding. According to the above steps, ^ ^ conductor device (Figure 2). /Na"I is half of the embodiment 2 ❹ plastic, can form a resin molding by means of the body member 13. The material of the semiconductor of the resin mold is configured to cover the mounting method, the compression molding method, or the printing method. In the form of the transfer of the foot using the mold, the semiconductor device 12 having a narrow pitch and a multi-pin +V body member can be fabricated with good efficiency. Further, the core layer wiring substrate U is smooth. w 转 装置 装置 12 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 转 转 转 转 转 转 转 转 转 转 转 转 转 转 转 转 转 转 转 转 转 转 转 转 转 转 转 转 转Sinusoidal semiconductor device [Embodiment 7] = 7 and Fig. 8 shows a step diagram of an embodiment of the present invention. According to Fig. 7 (8) to (6) and the cow body of the figure, the manufacturing method 3 (Fig. Conductor mounting 1 W ' (The manufacturing method shown in the magic can be 33 201021640. First, as shown in Figure 7 (8), the support body 25 is prepared. Metal, glass, Shi Xi, etc. - Material Japanese 25 is used for the secret moon (4) Subtraction #合。 On the domain body 25, it is better to have a position marker for loading +¥ body reading 13. Identification, and can be used as a position of the pole of the squad, the accuracy of the bM interval #全属, X 刹田二fi : f is sufficient, even if the support 25 on the support 25 is a copper plate having a thickness of 〇5 mm, in the support _ Shi 幵 into t, as Place the mark on the support body 25 with electrolytic electron microscope nickel (5哗) Next 'form the wiring d(33) in Fig. 7(b). ❹ Next 'as shown in Fig. 7(c)' In the embodiment, the semiconductor element 13 is mounted on the body 25, and in the present embodiment, the built-in semiconductor element °, the seam is 1000~2_the narrow pitch of the pin, and the half of the pin is Conductor = Next, as shown in Fig. 7(d), the insulating layer a 5) is laminated so that the surface and the side surface of the electrode terminal 14 are simultaneously covered. The conductive layer A (15) is, for example, photosensitive or Non-photosensitive organic material transformation, resin 1 epoxy propylene shaft resin, 丙 杂 旨 Ϊ Ϊ Ϊ Ϊ, phenol resin, poly phthalimide resin, BC s ❹ triobre), PB0 (polybenzos Po1 fine-duty 3, woven fabric weaving with woven silk fabric containing Ϊ ring 乳 钿, 裱 丙烯酸 acrylate resin, amine acrylate resin, = = dimeric imine resin, BCB (benzo Cyclobutene seven nzocyclobme 曰 (10) PBO (poly stupid and ten-seat, p〇iybenzoxaz〇ie), poly-suppression of the various insulating layers, in the war money (four), but also, boron, lead zirconate titanate, Oxidation, talc, oxidation, and other oxidation, and chemical systems: carbide, carbonate, nitride, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Xiao Tai ^ tube, diamond-like carbon, poly-p-phenylene (parylene) and other materials. Sub-wood anti- ΐΐ ίί transfer molding, compression molding, printing, direct extrusion, vacuum 'Rotary coating method, die coating method, curtain coating setting ς, 34 201021640 state, epoxy resin is formed by vacuum lamination. Further, in Fig. 7(d), the semiconductor element J3 is covered with the same insulating layer VIII (10), but the sub-surface and the side surface may be covered with an insulating material of a different material. The height of the side surface of the terminal member 13 is substantially the same as that of the semiconductor material, and as shown in FIG. 7(e), in order to electrically connect the 4 on the semiconductor element 13 to the external one, a dielectric layer is formed. Layer hole Α (10), wiring Α (17). When the photosensitive material is used as 15), it is formed by photolithography. i edge layer Α ((5) using a non-photosensitive material, or a photosensitive material and the material θ laser processing method. Secondly, the hole is filled with at least a metal selected from, for example, a group selected from copper mi = or An alloy such as a main component, cf. 6). The filling method is carried out by electrolytic electric bonding, electroless plating, printing method, 1 f metal suction, and the like. Further, it is also possible to use a method in which the surface of the insulating layer is scraped off so that the surface of the insulating layer is exposed to form a via hole. ^ Line 5 (17), formed by side subtraction, semi-additive or full addition. Ίίί placed on the substrate _ 形成 on the formation of the anti-forging layer of the desired pattern and the name of the _ _ the anti-plating layer _ get the desired method. After semi-additive method, t, electrolytic plating method, sputtering method, CVD (chemical vapordeposition) method, etc., an anti-mine layer having an opening as a desired pattern is formed, and an electric ore method is used in the opening portion of the anti-mirror layer to make the metal A method of extracting the side of the power supply layer after removing the plating layer to obtain a pattern of the drawn line. In the full addition method, the electroless electrophotographic lens is sucked on the substrate to prevent the plating layer from being patterned, and the anti-plating layer remains as an insulating film, the contact is activated, and the opening of the insulating film is made by electroless plating. The metal is deposited, and the method of wiring pattern is expected by 35 201021640. The wiring A (17) ' is, for example, an alloy selected from at least one surface of a copper, silver, ray, ray, or her red scale towel or a scale-based composition. In particular, it is preferably formed of copper from the viewpoint of resistance and cost. Next, as shown in Fig. 8 (f), the support 25 is removed. As shown in Fig. 8(g), the human body is formed on the front and back surfaces of the semiconductor element 13 in accordance with the steps of forming an insulating layer, a spacer, and a via hole. At this time, it is desirable that the cross-sectional shape of the wiring layer, the cross-sectional shape of the via hole, and the thickness of the insulating layer are gradually increased or the thickness is thick: in addition, in the layer where the small-diameter via hole or the fine wiring is necessary, the via layer It is desirable for the formation of pores to be made by UV-ray-forming via holes or UY lasers, and wiring formation is desired to use a semi-additive method in layers that can be interconnected with large-diameter via holes or loose widths and loose pitches. It is desirable to use a c〇2 laser for layer hole formation, and it is desirable to use a subtraction method. Therefore, according to the cross-sectional shape of the wiring, the cross-sectional shape of the via hole, and the thickness of the insulating layer, the device, the treatment, and the insulating material are respectively selected. Multi-layered production increases and low cost. In the present embodiment, as shown in Fig. 8(g), the number of layers on the front and back sides is three, but the present invention is not limited thereto, and the layer may be provided on the front and back surfaces of the semiconductor element 13. Further, in the present embodiment, the via hole of the nearest layer (the second layer) of the semiconductor element is formed and formed by wiring, and the UV laser and the semi-additive method are used, and the following layers (below the second layer) are used. 'Use C〇2 laser and subtraction method. The first layer of the via hole has a diameter of 25 μm, a bottom diameter of 15 μm, and an L/S of ΙΟμπι/ΙΟμπι. The pore size of the second layer or less is set to a top diameter of 80 μm, a bottom diameter of 70 μm, and an L/S of 50 μm/50 μm. Further, the thickness of the insulating layer is about 20 μmη in the first layer and 5〇μηι in the second layer or less. Next, a pattern of the solder resist layer 24 is formed on the upper wiring C (23). The solder resist layer 24 is formed to exhibit surface circuit protection and flame retardancy of the semiconductor device 12. The material is composed of an epoxy-based, acrylic-based, urethane-based, or poly-imide-based organic material, and an inorganic material or an organic material filler may be added as needed. Further, the semiconductor device 12 may not be provided with the solder resist layer 24. The surface of the opening of the anti-caries layer 24 of the wiring C (23) may be formed of at least one metal or alloy selected from the group consisting of gold, silver, copper, tin, and solder. In the present embodiment, nickel having a thickness of 3 μm and gold of 0.5 μm are laminated in this order on the surface of the wiring C (23). According to this embodiment, it is possible to form a semiconductor device 12 having a plurality of layers with good efficiency in a semiconductor device having a narrow pitch and a plurality of pins. x, half_device 12 increases with the number of layers, the cross-sectional shape of the wiring, the cross-sectional shape of the via hole is increased, and the thickness of the via layer is increased. By selecting appropriate devices, processes, and insulating materials, high yield and high can be achieved. Reliability of the semiconductor device 12. [Embodiment 8] Fig. 9 and Fig. 1 are a view showing a step of manufacturing a semiconductor device according to an eighth embodiment of the present invention. As shown in Figs. 9(8) to (Q and Figs. 10(g) to (i), the semiconductor device of the fourth embodiment (Fig. 4) can be manufactured.

魯 首先如圖9(a)所示，準備支持體25。支持體25可為樹脂、金 屬、玻璃、料任-材料或該等植合。支持體25上，宜設置用 =載半導體元件13之位記，置標記，只魏以高精度辨 ，即可，且發揮作為位置標記之功能，即使支持體2S上使金屬析 出，仍能以濕式蝕刻或機械加工設置凹部。本實施形熊中，支持 支持體25上以電解^^錄(5_ 其次，於圖9(b)上形成配線d(33)。 其次，如圖9⑹所示’於設有位置標記之支持體25上，以面 ，上的狀驗餅導體元件13，使得電極軒14為頂面。裝載之 半導體元件13之電極端子14上設有金屬柱3〇。金屬柱3〇於後 驟發揮作為介層孔之魏。本實施形態中，伽建之半導體元件 13之接墊間距為20〜150μιη、接腳數為1〇00〜2〇〇〇接腳之窄 =多接腳之半導體元件13。金屬柱為銅柱，口直徑為3 ; 度 15μπι。 「 圖9(d)所* ’疊層絕緣層Α(15)，使半導體元件13 之電極端子14面及側面同時被覆蓋。 絕緣層Α(15)例如由感光性或非感光性有機材料形 如使用&氧樹脂、環氧丙湘“旨細旨、胺S旨丙烯咖旨樹脂、 聚酯樹脂、苯酚樹脂、聚醯亞胺樹脂、BCB(苯并環丁 =nZocyclobutene)、PB〇(聚苯并十坐，⑽ybenz〇xaz〇^ $ 烯樹脂等，或《布絲li胺纖料形成之織布或不織布含浸環 37 201021640 氧樹脂、環氧丙烯酸酯樹脂、胺酯丙烯酸酯樹脂、聚酯樹脂、笨 紛樹脂^〒醢亞胺樹脂、BCB(苯并環丁烯，benzocyclobutene)、 PBO(聚苯并噚唑’ polybenzoxazole)、聚降莰烯樹脂等的材料。又， 各絕緣層，在上述有機材料以外，也可使用氮化矽、鈦酸鋇、氮 化硼:鈦酸錯酸鉛、碳化矽、塊滑石、氧化鋅等氧化物系、、氫氧 化物系、碳化物系、碳酸鹽系、氮化物系、鹵化物系、磷酸鹽系 之陶瓷及上述陶瓷或玻璃等含於充填料之複合材料， 管、類鑽碳、聚對二曱苯基(parylene)等材料。 〇 ，疊層方法’以傳遞模塑法、壓縮形成模塑法、印刷法、真空 擠，、真空疊合、旋轉塗佈法、模塗法、簾塗法等設置。本g 形態中，環氧樹脂以真空疊合形成。 槐+又，實施形態8亦為已於實施形態7朗之方法為同 ，方法，可於半導體元件13之金屬柱形成面與侧面使㈣質不同 其次，如圖9(e)所示，為了連接半導體元件13之表 成介層孔D(32)。 y 其次，如圖9(f)所示，將絕緣層A(15)除去直到露出半 =3之金屬柱30。除去方法，使料磨、研削、濕式侧、乾 钮刻、拋光研磨等。本實施形態使用研削裝置。 〇 其次，如圖10(g)所示，為了將半導體元件13上之 =外部連接端子電連接’形成配線a(17)。如此，藉由使金屬 表面從絕緣層A(15)露出，不必於絕緣層A(15)進行要求位置 ^度^微細孔加工，而設置連接電極端子14與配線A(i7)的介芦 ^量藉此’可提升_窄間距接墊間距之轉體元件13的處理^ 料ΐ線H彻減去法、半加成法或全加錢等方法形成。 ΐΐ」板上設置之銅紅形成所望_之防鍍層，_ 不要銅力後’將⑽層獅，得到所望_之方法。半^ wttTt 1 ' CVD(chemical vapor depositioi)^^ 域供電層I’形·所賴賴口之_層，於防鍍層開口^ 38 201021640 除去贿層後，侧供電層，得 附後，以防i層护成円宏加成法係於基板上使無電解電鍍觸媒吸 活化，利用^雷案’使該防鍍層殘f作為絕緣膜，將觸媒 =配法r絕緣膜之開口部使金屬析出，藉此得 I呂、及域成之族群中至少銀'金'鍊、 #立，你㈣μΓΓ 種金屬如該等為主成分之合金。 尤八從電阻敍成本之觀點，希望由銅形成。 其次，如圖10(h)所示，除去支持體25。 ❹ 配線了 戶i不’於半導體元件13之表背面依照絕緣層、 配線叫面开:狀/入2驟形成電路基板。此時’希望疊層之層之 if 、 剖面形狀、絕緣層厚緩慢加大或增厚。又， 紫外、後田配線為必要之層中，希望介層孔形成使用 Πΐίri層孔或使用uv雷射’配線形成使用半加成 孔或寬鬆寬度、寬鬆間距之配線能因應之層中， =望二層孔形成使用c〇2雷射，配線形成使用減去法。如此，依 形狀、介層孔剖面形狀、絕緣層厚之變化，分別選用 魯 i二f;、fi材’能達成多層化之產量提升’及低成本。本 只施A悲中’如圖10(1)所示，表背面的層數各為3層，但不限於 此，層設置於半導體树〗3之表f面即可。又，本實施形離中， 之最近接層(第1層)的介層孔形成、配線形成，使用 71射及半加成法，以下之層(第2層以下)使用co2雷射及減去 法。苐1層之介層孔直徑，頂直徑25μιη、底直徑15μιη、L/s為 ΙΟμιη/ΙΟμιη。第2層以下之介層孔直徑為頂直徑8一、底直徑 70μιη、L/S為50μιη/50μιη。又，絕緣層厚，第！層為約2〇 第 2層以下為50μπι。 f次，於最上層配線C(23)上形成抗焊層24之圖案。抗焊層 24、’、係為了展，半導體裝置12之表面電路保護及難燃性而形成。 材料，由環氧系、丙烯酸系、胺酯系、聚醯亞胺系有機材料構成， 視耑要也可添加無機材料或有機材料之填料。又，半導體裝置12 也可不設置抗焊層24。配線C(23)從抗焊層24開口之表面二可以 39 201021640 由選自金、銀、銅、錫及焊料構成之族群中至少丨種金屬或合金 形成。本實施形態中，於配線C(23)之表面依序疊層厚度3μιη之 鎳及0.5μηι之金。 藉由採用本實施形態’能内建窄間距、多接腳之半導體元件， 有效率地製作具多數層之半導體裝置12。又，半導體裝置12伴隨 2數增加，配線剖面形狀、介層孔剖面形狀加大，絕緣層厚增厚， 藉^因應於此選擇適當裝置、處理、絕緣材，可達成高產量、高 可罪性’半導體裝置12。又，由於在半導體元件13上設置作為介 f孔功此的金屬柱30，因此，配線Α(ι7)與電極端子14之連接可 靠性提升，二次構裝可靠性提升。 以上，係依照實施例說明本發明，但本發明不僅限於上述實 施例之構成，當然包含該技術領域中具通常知識者可得於本發明 之範圍的各種變形、修正。 本發明之所有揭示(含申請專利範圍)之範疇内，或依據其基本 咬，可改變、調整實施形態、實施例。又，在本發明之申 圍之範,内’可有各種揭示要素之多樣組合或選擇。即， ίίΐ备然包含為該技術領域中具通常知識者可依照含申請專利 祀圍在内騎有揭示、技術思想制各種變形、修正。 【圖式簡單說明】 ，^員，本發明之—實施形態之無核心、層配線基板之剖面圖 二，Τ本發明之—實施形態之半導體裝置之剖面圖。 圖4 另—實施形態之半導體裝置之剖面圖。 /不，發月之又另一實施形態之半導體裝置之剖面圖。 製造方法本剌之—實卿態之無批層配線基板々 法之ί驟tHe)顯林發日把—實細彡態之半賴裝置之製幻 方法本翻實制H抖财置之㈣ 201021640 顯示圖7所示步驟圖之後半。 方法之步發明之實施賴之轉魏置之製造 j^g)〜(i)顯示圖9所示步驟圖之後半。 圖 _示習知之多層配線基板之剖面圖。 _示習知之電子零件内建型多層基板之剖面圖。 板之i面^。林發明之實施形態1之變_ 1之無核心層配線基 Ο 板之示本發明之實施形態1之變形例2之無核心、層配線基 板之示本發明之實卿態1之變侧3之細細層配線基 【主要元件符號說明】 參 11 12 13 14 15 16 17 18 19 11Α 18Α 19Α 20、 20Α 21、 21Α 22、 22Α 23、 23Α 24 25 26 無核心層配線基板 半導體裝置 半導體元件 電極端子 絕緣層 介層孔 配線Α(配線層） 絕緣層 介層孔 配線B(配線層） 絕緣層 介層孔C 配線C(配線層、外部連接端子 抗焊層' 支持體 接著層 弟2電極端子） 41 201021640 30 金屬柱(介層孔） 31 電路基板 32 介層孔 33 配線、配線層 41 焊球 42 底填樹脂 115 電元件連接用接墊 117 端子接墊Lu First, as shown in Fig. 9(a), the support 25 is prepared. The support 25 can be a resin, a metal, a glass, a material-material or such a planting. It is preferable to set the position of the semiconductor element 13 on the support body 25, and to mark it, and only Wei can be distinguished by high precision, and can function as a position mark, even if the metal is deposited on the support 2S, The recess is wet etched or machined. In the present embodiment, the supporting body 25 is electrolyzed (5_ next, the wiring d (33) is formed on FIG. 9(b). Next, as shown in FIG. 9(6), the support is provided with the position mark. On the 25th, the pie conductor element 13 is inspected on the surface, so that the electrode 14 is the top surface. The electrode terminal 14 of the mounted semiconductor element 13 is provided with a metal post 3〇. The metal post 3 is used as a reference. In the present embodiment, the semiconductor element 13 of the galvanic structure has a pad pitch of 20 to 150 μm, the number of pins is 1 〇 00 〜 2 〇〇〇, and the pin is narrow = the multi-pin semiconductor element 13. The metal post is a copper post having a port diameter of 3 degrees and a degree of 15 μm. The laminated insulating layer 15 (15) of Fig. 9(d) is such that the surface and the side surface of the electrode terminal 14 of the semiconductor element 13 are simultaneously covered. (15) For example, a photosensitive or non-photosensitive organic material is used in the form of &oxy resin, epoxy propylene, "amine propylene resin", polyester resin, phenol resin, polyimine resin. , BCB (benzocyclobutane = nZocyclobutene), PB 〇 (polybenzoxene, sitting, (10) ybenz〇xaz〇^ $ olefin resin, etc., or "dispellent Woven fabric or woven fabric impregnated ring 37 201021640 Oxygen resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, sinister resin, BCB (benzocyclobutene, benzocyclobutene ), PBO (polybenzoxazole 'polybenzoxazole), polypyrene resin, etc. Further, in the insulating layer, in addition to the above organic materials, tantalum nitride, barium titanate, boron nitride: titanium may also be used. An oxide system such as lead acid hydride, tantalum carbide, talc, or zinc oxide; a hydroxide system, a carbide system, a carbonate system, a nitride system, a halide system, a phosphate ceramic, and the above ceramic or glass. Such as composite materials filled with fillers, tubes, diamond-like carbon, parylene, etc. 〇, lamination method 'by transfer molding, compression molding, printing, vacuum extrusion , vacuum lamination, spin coating, die coating, curtain coating, etc. In this g form, the epoxy resin is formed by vacuum lamination. 槐+ again, embodiment 8 is also in the embodiment 7 The method is the same, the method can be applied to the semiconductor component 13 The metal pillar forming surface and the side surface are made different in (4) quality, as shown in Fig. 9(e), in order to connect the semiconductor element 13 to form a via hole D (32). y Next, as shown in Fig. 9(f), The insulating layer A (15) is removed until the metal pillar 30 of half = 3 is exposed. The removal method is to grind, grind, wet side, dry button, polish, etc. This embodiment uses a grinding device. 10(g), in order to electrically connect the = external connection terminal on the semiconductor element 13 to form the wiring a (17). Thus, by exposing the metal surface from the insulating layer A (15), it is not necessary to be in the insulating layer A ( 15) Performing the required position ^ degree ^ micro hole processing, and setting the connection electrode terminal 14 and the wiring A (i7) of the amount of the reed amount by the 'supplemental _ narrow pitch pad spacing of the rotating element 13 processing ΐ Line H is formed by subtracting the method, semi-additive method, or adding all the money. Ϊ́ΐ 铜 铜 设置 设置 设置 设置 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上 板上Half ^ wttTt 1 ' CVD (chemical vapor depositioi) ^ ^ domain power supply layer I ' shape · depends on the _ layer, in the anti-plating opening ^ 38 201021640 After removing the bribery layer, the side power supply layer, have to attach, in case The i layer is protected by a macro-addition method on the substrate to activate the electroless plating catalyst, and the anti-plating layer residual f is used as an insulating film by using the "Thunder" method, and the opening of the catalyst = matching r insulating film is made. The metal is precipitated, thereby obtaining at least the silver 'gold' chain, the group of the group, and the alloy of the metal such as these. From the point of view of the cost of resistance, Yu Ba hopes to be formed of copper. Next, as shown in FIG. 10(h), the support 25 is removed.配线 The wiring is not formed on the front and back sides of the semiconductor element 13 in accordance with the insulating layer and the wiring. At this time, the if, the cross-sectional shape, and the thickness of the insulating layer of the layer to be laminated are slowly increased or thickened. In addition, UV and Houtian wiring are necessary layers. It is desirable to form via holes or use uv lasers to form wiring using semi-addition holes or loose widths and loose pitches. The two-layer hole is formed using a c〇2 laser, and the wiring is formed using a subtraction method. In this way, depending on the shape, the cross-sectional shape of the via hole, and the thickness of the insulating layer, Lu i 2 f; and fi material can achieve a multi-layered yield increase and low cost. As shown in Fig. 10 (1), the number of layers on the back side of the watch is three layers, but the layer is not limited thereto, and the layer is provided on the surface f of the semiconductor tree. Further, in the present embodiment, the via layer of the nearest layer (first layer) is formed and formed by wiring, and the 71-emission and semi-additive method are used, and the following layers (below the second layer) are co2 laser and subtracted. Go to the law. The interlayer pore diameter of the 苐1 layer, the top diameter of 25 μm, the bottom diameter of 15 μm, and the L/s are ΙΟμιη/ΙΟμιη. The pore diameter of the second layer or less is a top diameter of 8, a bottom diameter of 70 μm, and an L/S of 50 μm / 50 μm. Also, the insulation layer is thick, the first! The layer is about 2 〇 and the second layer is 50 μm. f times, a pattern of the solder resist layer 24 is formed on the uppermost wiring C (23). The solder resist layers 24, ' are formed to protect the surface circuit of the semiconductor device 12 and the flame retardancy. The material is composed of an epoxy-based, acrylic-based, urethane-based, or poly-imide-based organic material, and an inorganic material or a filler of an organic material may be added as needed. Further, the semiconductor device 12 may not be provided with the solder resist layer 24. The wiring C (23) may be formed from the surface of the opening of the solder resist layer 24 by a metal or an alloy of at least one selected from the group consisting of gold, silver, copper, tin, and solder. In the present embodiment, nickel having a thickness of 3 μm and gold of 0.5 μm are laminated on the surface of the wiring C (23) in this order. According to the present embodiment, it is possible to efficiently fabricate a semiconductor device 12 having a plurality of layers by incorporating a semiconductor device having a narrow pitch and a plurality of pins. In addition, as the number of semiconductor devices 12 increases, the cross-sectional shape of the wiring and the cross-sectional shape of the via hole increase, and the thickness of the insulating layer increases. Therefore, it is possible to achieve high yield and high suspicion by selecting appropriate devices, processes, and insulating materials. 'Semiconductor device 12. Further, since the metal post 30 is provided as the dielectric member 13 on the semiconductor element 13, the reliability of the connection between the wiring raft (1) and the electrode terminal 14 is improved, and the secondary assembly reliability is improved. The present invention has been described with reference to the embodiments, but the present invention is not limited to the above-described embodiments, and various modifications and changes can be made without departing from the scope of the invention. The embodiments and examples can be changed or adjusted within the scope of all the disclosures of the present invention (including the scope of the patent application). Further, various combinations or selections of various disclosed elements are possible within the scope of the invention. That is to say, ίίΐ is included in the technical field, and the person who has the usual knowledge can perform various deformations and corrections in accordance with the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. Fig. 4 is a cross-sectional view showing another embodiment of the semiconductor device. / No, a cross-sectional view of another embodiment of the semiconductor device of the month. The manufacturing method of this — — 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实 实201021640 shows the second half of the step chart shown in Figure 7. Method Steps The implementation of the invention is based on the manufacture of the device. j^g)~(i) shows the second half of the step diagram shown in Figure 9. Figure _ shows a cross-sectional view of a multilayer wiring board. _ Show the cross-section of the multi-layer substrate built into the electronic parts. The i-face of the board ^. In the first embodiment of the present invention, the coreless layer wiring board of the second modification of the first embodiment of the present invention is shown in the modified side of the present invention. Thin layer wiring base [Main component symbol description] Reference 11 12 13 14 15 16 17 18 19 11Α 18Α 19Α 20, 20Α 21, 21Α 22, 22Α 23, 23Α 24 25 26 Coreless wiring substrate semiconductor device semiconductor device electrode Terminal insulating layer via wiring layer (wiring layer) Insulation layer via wiring B (wiring layer) Insulation layer via hole C wiring C (wiring layer, external connection terminal solder resist layer) Support body layer 2 electrode terminal 41 201021640 30 Metal column (via hole) 31 Circuit board 32 Via hole 33 Wiring, wiring layer 41 Solder ball 42 Underfill resin 115 Electrical component connection pad 117 Terminal pad

4242

Claims (1)

201021640 七、申請專利範圍： 1. 一種無核心層配線基板， 包含.經4:層之多數配線層及絕緣層；設置於該配線層之 H ’設置於舰緣層且_絕緣層上下之該配線電連接之介 肩孔； 志/ίϊ線ί板的？ 1表面設置有第1電極端子，於該第1 距第2電極端子;該第1電極端子之接塾間 距比s亥第2電極jr而子之接墊間距為窄間距； 其特徵在於： ’ β M電極端子與該第2電極端子介由該配線或該介層孔 之至少其中之一而電導通； 曰几 ΜβΪίΐ孔ίΐ配線至少其中之一，具有與設置於其他絕緣 層或配線層之7|層孔或配線為不同之剖面形狀。 2. 如申請專利範圍第！項之無核心層配線基板，其中，該介声孔 狀’於該第1電極端子之最近接層為最小。曰 • 3·如申請專利範圍第1項之無核心層配線基板，其中，該介声孔 之剖面形狀，從該第1電極端子之导W垃思細二二够滑孔 子側之層依梯級式加大^之最近接層朝向該第2電極端 4. ^請圍第3項之無核心層配線基板，其中，該介層孔 電極端子之最近接層朝向該第2電極 專^㈣第4項之無核心層配線基板，其中，從與該第 ^表面相接之絕緣層朝向與該第2表面相接之絕緣層，該介^ 孔之剖面形狀保持大致相似形狀逐層加大。 曰 6. 如申請專利範圍第1項之無核心層配線基板，其中，該配 剖面形狀於該第1電極端子之最近接層為最小。 … 7. 如申請專利範圍第i項之無核心層配線基板，其中，該 1面，狀’從該第1電極端子之最近 極端 侧之層，依梯級式加大。 * 于 8·如申請專利範圍第！項之無核心層配線基板，其巾，該介層孔， 43 201021640 $該第2電極端子側之直徑健第丨電極端子歡直徑為大之 介層孔。 圍第1至8項中任—項之無核心層配線基板，其 ，^夕絕緣層之中’具有絕緣材料與其他絕緣層不同的絕 緣層。 1〇.如t明^利細第9項之無核心層配線基板，其中，該絕緣層 彈，邊第1電極端子之最近接層朝向該第2電極端子 側之層成梯級式的增高。 U. 圍第1至8項中任一項之無核心層配線基板，其 〇 η 電極端子之接墊間距為5μπι以上200,以下。 12.-種半¥體裝置，包含：申請拥範圍第us項巾任一項之 配，基板’及連接於該無核心層配線基板之該第1電 極编子的至少1個半導體元件。 13·如申請專繼圍第12項之轉縣置，其巾， =熔點金屬或導電性樹脂其中任一材料，覆晶接合於該配 綠卷才反。 14. ί圍ί12項之轉體裝置’其中，該半導體元件， 板用要為金之材料的金屬線，以線接合方式連接於該配線基 15. —種半導體裝置， 包含： i個以上之半導體元件，於其表面具有電極端子；及 無核心層配線基板，係内建該半導體元件，i呈 層之多數配線層及絕緣層；設置於該配線層 該絕緣層且將該絕緣層上下之該配線電連接之介層孔； 核心層配線基板之表面設有外部連接端子； s 其特徵在於： 電極 端子’介由該配線或該介層孔至少其中之 該^導體元件埋設於魏緣層，該外部雜端子與該 -而電導通， 該絕緣層與該配線層疊層於該半導體元件之表背面， 44 201021640 16 赠他絕緣層 17.如申5月專利範圍第15項丰 面形狀，從該電極端子之置，其中，該介層孔之剖 子側之層依梯級式力1 層朝向表背面之該外部連接端 18·如申請專利範圍第I?項 ❹ 之最近接層躺該外部連接該電極端子 保持大致相似形狀逐層加^侧之層，該介層孔之剖面形狀 19.如申請專利範圍第15項之 甘士斗占 形狀於極軒之最近，，、中’該配線之剖面 H請ίϋ圍第15項之半導體裳置，其中，該配線之剖面 侧最近接層朝向表背面之該外部連接端子 此=申請專利範圍第15項之半導 間距較該外部連接端子之_騎^/、中对私子之 以.如申請專利範圍第15項之丰邕 23 子側之直徑比起該電^孔，該 15^項巾任—項之半導麟置，其中， 層^數絕緣層之巾，具有絕緣材料與其他絕緣層不同的絕緣 範圍第15至22項中任—項之半導體裝置，其中， 導體^元狀;密狀輯賴將該半 利範圍第15至22項中任—項之半導體裝置，复中， ======細細表背㈣ 6^=1^利粑圍第15至22項中任—項之半導體裝置，其中， q電極端子之間距，為5μιη以上200μ!η以下。 、， 45 201021640 27·如申請專利範圍第15至22項中任一項之半導體裝置，其中， 該半導體元件之該電極端子之表面設有金屬柱，該金屬柱係作 為該介層孔之功能。 28. —種無核心層配線基板之製造方法， 包含：第1配線體形成步驟，於支持體上形成由配線層、 絕緣層及介層孔所構成之配線體；及第2配線體形成步驟，於 該配線體上進一步形成配線層、絕緣層及介層孔，且形成疊層 之新配線體；及除去該支持體之步驟； 其特徵為更包含下列步驟： 重複該第2配線體形成步驟！次以上，其中至少1次第2 ⑬ 配線體形成步驟’係形成不同剖面形狀的配線體之步驟；該步 驟，形成之配線體的配線剖面形狀或介層孔剖面形狀，與該步 驟貫施前之步驟所得到之配線體之配線剖面形狀、介層孔剖面 形狀為不同。 29. 如申請專利範圍第28項之無核心層配線基板之製造方法，其 =，重複該第2配線體形成步驟丨次以上，且其中至少丨次^ -第2配線體形成步驟，係形成不同剖面形狀的配線體之步驟； 該步驟新形成之配線體的配線剖面形狀，及介層孔剖面形狀， 與由該步驟實施前之步驟得到配線體之配線剖面形 剖面形狀為不同。 θ ❹ 3〇. j半導體裝置之製造方法，特徵在於具有以下步驟：於利用 申睛專利範圍第28或29項之無核心層配線基板之製造方法製 造之無核心層配線基板，裝載半導體元件。 、 31.如=請專利範圍第3〇項之半導體裝置之製造方法，其中，該 半導體7G件與該無核心層配線基板間之連接為舰八二”201021640 VII. Patent application scope: 1. A coreless wiring board comprising: a majority of wiring layers and insulating layers of 4: layers; H' disposed on the wiring layer is disposed on the ship's edge layer and above and below the insulating layer Wiring the electrical connection to the shoulder hole; Zhi / ϊ ϊ line ί plate? The first electrode terminal is provided on the surface of the first electrode terminal, and the pitch of the first electrode terminal is narrower than the pitch of the second electrode jr of the first electrode terminal; and the feature is: The β M electrode terminal and the second electrode terminal are electrically connected via at least one of the wiring or the via hole; at least one of the wirings of the wiring and the wiring layer; and having a wiring layer disposed on the other insulating layer or the wiring layer 7|Layer holes or wires are of different cross-sectional shapes. 2. If you apply for a patent scope! The coreless wiring board of the item, wherein the dielectric layer is the smallest adjacent layer of the first electrode terminal.曰• 3· The non-core layer wiring substrate according to the first aspect of the patent application, wherein the cross-sectional shape of the mesoporous hole is guided by the first electrode terminal, and the layer of the sliding hole side is stepped. The nearest layer of the type is increased toward the second electrode end 4. Please surround the core layer wiring board of the third item, wherein the nearest layer of the via electrode terminal faces the second electrode (four) A four-layer core-less wiring board in which an insulating layer that is in contact with the second surface faces an insulating layer that is in contact with the second surface, and a cross-sectional shape of the via hole is increased in a substantially similar shape layer by layer. 6. The coreless wiring board of claim 1, wherein the cross-sectional shape is the smallest in the nearest layer of the first electrode terminal. 7. The non-core layer wiring board according to the item i of the patent application, wherein the one side, the shape of the layer from the most extreme side of the first electrode terminal is stepwise increased. * On 8 · If you apply for a patent scope! The core-free wiring board of the item, the towel, the via hole, 43 201021640 $ The diameter of the second electrode terminal side is the diameter of the interlayer electrode. A coreless wiring board according to any one of items 1 to 8, wherein the insulating layer has an insulating layer different from the other insulating layers. In the case of the coreless wiring board of the ninth item, the layer of the first electrode terminal is stepped up toward the second electrode terminal side. U. The core-less wiring board according to any one of items 1 to 8, wherein the η η electrode terminal has a pad pitch of 5 μm or more and 200 or less. 12. A device for manufacturing a semiconductor device comprising: a substrate ???a substrate, and at least one semiconductor element connected to the first electrode splicing of the coreless wiring substrate. 13. If you apply for the 12th item of the county, the towel, = the melting point metal or the conductive resin, the flip-chip bonding to the green roll is reversed. 14. The device of claim 12, wherein the semiconductor component is connected to the wiring substrate by wire bonding using a metal wire to be a gold material, comprising: i or more a semiconductor device having an electrode terminal on a surface thereof; and a core-free wiring substrate, wherein the semiconductor element is built in, i is a plurality of wiring layers and an insulating layer; and the insulating layer is disposed on the wiring layer and the insulating layer is upper and lower The wiring layer is electrically connected to the via hole; the surface of the core layer wiring substrate is provided with an external connection terminal; s characterized in that: the electrode terminal is embedded in the Wei edge layer via at least one of the wiring or the via hole The external impurity terminal is electrically connected to the semiconductor terminal, and the insulating layer and the wiring layer are laminated on the front and back sides of the semiconductor component, 44 201021640 16 to give him an insulating layer 17. For example, in the shape of the 15th item of the May patent scope, From the electrode terminal, wherein the layer on the side of the cross-section of the via hole faces the external connection end 18 of the front and back sides according to the step force 1 layer. The outer layer is connected to the outer electrode, and the electrode terminal maintains a layer of a substantially similar shape layer by layer. The cross-sectional shape of the via hole is 19. The shape of the glycoside in the fifteenth item of the patent application is in the nearest to the pole, 'The section of the wiring H is the semiconductor skirt of the 15th item, wherein the outermost layer of the cross-section side of the wiring faces the external connection terminal on the back side of the watch. This is the semi-conductive pitch of the 15th item of the patent application. The connection terminal is _ riding ^ /, in the middle of the private child. If the diameter of the 23 side of the 邕 23 of the patent application scope is compared with the electric hole, the 15^ item towel is the semi-guided a semiconductor device having a plurality of layers of insulating layers and having an insulating material different from that of the other insulating layers, wherein the conductor is in the form of a conductor, wherein the conductor is in a shape of a conductor; The semiconductor device of any of the items 15 to 22, in the middle, the ====== detail back (4) 6^=1^, the semiconductor device of any of items 15 to 22, wherein , q The distance between the electrode terminals is 5μηη or more and 200μ!η or less. The semiconductor device according to any one of claims 15 to 22, wherein the surface of the electrode terminal of the semiconductor element is provided with a metal pillar as a function of the via hole. . 28. A method of manufacturing a coreless wiring board, comprising: a first wiring body forming step of forming a wiring body including a wiring layer, an insulating layer, and a via hole on a support; and a second wiring body forming step Further forming a wiring layer, an insulating layer, and a via hole on the wiring body, and forming a new wiring body; and removing the support; and further comprising the steps of: repeating the formation of the second wiring body step! One or more times, at least one of the second 13th wiring body forming step' is a step of forming a wiring body having a different cross-sectional shape; in this step, the wiring cross-sectional shape or the via hole cross-sectional shape of the wiring body formed, and the step before the step The wiring cross-sectional shape of the wiring body obtained in the step and the cross-sectional shape of the via hole are different. 29. The method of manufacturing a coreless wiring board according to claim 28, wherein the second wiring body forming step is repeated one or more times, and at least the second wiring body forming step is formed. The step of the wiring body having different cross-sectional shapes; the wiring cross-sectional shape of the wiring body newly formed in this step, and the cross-sectional shape of the via hole are different from the cross-sectional shape of the wiring of the wiring body obtained by the step before the step is performed. θ ❹ 〇 〇 j j 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体The method of manufacturing a semiconductor device according to the third aspect of the invention, wherein the connection between the semiconductor 7G device and the coreless wiring substrate is a ship" _將半導體元件以其電極端子形成面為表面，f ，而裝載於支持 半導體元件與該無核心層配線基板間之連接為覆 .一種半導體裝置之製造方法，包含以下步驟： 46 201021640 形成覆蓋該半導體元件之絕緣層； 與配=肋職電_子卿料接斜錢接之介層孔 ϊίϊίί體並形成内建半導體元件之配線基板；及 線層狀配縣板之表麵，形成包含配 半導;J之製造方法，其中，該 形成用於山 子之表面的金屬柱’ Λ 與轉外·^驟'^端子與外部連接端子電連接之介層孔 ❹雜之部分除去，使得該金 驟；於該露出之金屬柱與該絕緣層之表面，形成配線層之步 —屬柱係作為介層孔之功能。 j驟更包含形成夾隔著該半= 二之= ® * 2 +任—項之半導體裝置之製造方 上裳载半導#'_成有該配線層之支持體 八 、圖式： 47a semiconductor device having a surface on which the electrode terminal is formed as a surface, f, and a connection between the supporting semiconductor element and the coreless wiring substrate is covered. A method of manufacturing a semiconductor device includes the following steps: 46 201021640 forming a cover The insulating layer of the semiconductor component; and the wiring substrate of the built-in semiconductor component; and the surface of the line layered county plate are formed and matched with the interlayer dielectric layer a semiconductor manufacturing method in which a portion of a mesoporous portion which is formed by a metal post of a surface for a mountain and is electrically connected to an external connection terminal is removed, so that the gold is removed. The step of forming a wiring layer on the exposed metal pillar and the surface of the insulating layer is a function of a pillar. The j-thin further comprises a semiconductor device formed by sandwiching the half = two = ® * 2 + any - the semiconductor device is mounted on the semi-conductor #'_the support layer having the wiring layer.
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