TW201015703A - Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS) - Google Patents

Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS) Download PDF

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TW201015703A
TW201015703A TW98132926A TW98132926A TW201015703A TW 201015703 A TW201015703 A TW 201015703A TW 98132926 A TW98132926 A TW 98132926A TW 98132926 A TW98132926 A TW 98132926A TW 201015703 A TW201015703 A TW 201015703A
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Taiwan
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diode
steering
tvs
transient voltage
layer
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TW98132926A
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Chinese (zh)
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TWI437691B (en
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Madhur Bobde
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Alpha & Omega Semiconductor
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Abstract

A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.

Description

201015703 六、發明說明： 【發明所屬之技術領域】 [0001]本發明涉及一種暫態電壓抑制器（TVS)的電路配置和製 造方法。更確切地說，本發明涉及一種優化配置整合控 向二極體，以便降低暫態電壓抑制器（TVS)電容的改良 電路配置和製造方法。 [先前技術]201015703 VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to a circuit configuration and a manufacturing method of a transient voltage suppressor (TVS). More specifically, the present invention relates to an improved circuit configuration and method of fabrication for optimizing the configuration of integrated steering diodes to reduce transient voltage suppressor (TVS) capacitance. [Prior technology]

❹ [0002]暫態電壓抑制器（TVS)通常用於保護積體電路免受由於 大意疏忽造成積體電路過電壓帶來的損害。積體電路的 設計是在電壓的正常範团内工作〇然而靜電放電（ESD) 、電快速瞬變和閃電、未铕壓等情況 ，都會對電路造成嚴重損害(TVS)裝 置就是為了當上述電壓問保遂4體電路的功 能免受損害。由於積遞電路對於過電歷的損害十分敏感 ，因此當與積體電路_同工作的蓼置增加f，那麼更加 需要暫態電麈抑制器電壓抑制器（ TVS)典型應用於USB電源護、數位視頻界 面、高速乙太網、筆記本邊器和平面顯示器等 方面。 第1A-1圖為傳統的帶有二極體陣列的暫態電壓抑制器（ TVS)，用於高帶寬資料匯流排的靜電放電（ESD)保護 。暫態電壓抑制器（TVS)陣列包括一個主穩壓二極體， 同高端控向二極體和低端控向二橾體一起工作。高端控 向二極體同電壓源Vcc相連，低端控命二極體同接地端 GND相連，一個輸入/輸出端連接高端和低端控向二極體 。穩壓二極體尺寸較大，可作為從高歷端即Vcc端，到接 HQ»' 098132926 表單蹁號A0101 第4頁/共42頁 ’ 201015703 地電壓端即Gnd端之間的雪崩二極體◊當在一個輸入/輸 出（丨/〇)端加上正電壓時，高端二極體提供正相偏壓， 並被大的Vcc-Gnd二極體箝位，例如穩壓二極體。高端和 低端控向二極體尺寸設計得很小，是為了降低輸入/輸出 (I/O)電容，以此減少類似於高速乙太網應用中的高速 線路上的***損耗。 隨著工業的發展，控向二極體與穩壓二極體整合在一起 。第1A-2圖和第ia-3圖為控向二極體與穩壓二極體整合 ❻ 的圖示。高端和低端端子從外面不可見。第1A 2圖為高 圖。二極體單 但在内部，高 。内電路同第1A-1面中·❹ [0002] Transient Voltage Suppressors (TVS) are commonly used to protect integrated circuits from damage caused by inadvertent overvoltages in integrated circuits. The integrated circuit is designed to operate within the normal range of voltage. However, electrostatic discharge (ESD), electrical fast transients, lightning, and uncompressed conditions can cause serious damage to the circuit (TVS) device. Ask the function of the protection 4 body circuit to be protected from damage. Since the accumulation circuit is very sensitive to the damage of the over-current calendar, when the device with the integrated circuit _ increases the f, it is more necessary to use the transient power suppressor voltage suppressor (TVS), which is typically applied to the USB power supply. Digital video interface, high-speed Ethernet, notebook edge and flat panel display. Figure 1A-1 shows a conventional transient voltage suppressor (TVS) with a diode array for electrostatic discharge (ESD) protection of high-bandwidth data busses. The Transient Voltage Suppressor (TVS) array includes a main regulated diode that works with the high-side steering diode and the low-side steering diode. The high-side steering diode is connected to the voltage source Vcc, and the low-side control diode is connected to the ground GND, and one input/output terminal is connected to the high-end and low-side steering diodes. The voltage regulator diode is large in size and can be used as the avalanche dipole between the Gnd terminal and the HQ»' 098132926 form nickname A0101 Page 4 / Total 42 pages 201015703 Body When a positive voltage is applied to an input/output (丨/〇) terminal, the high-side diode provides a positive phase bias and is clamped by a large Vcc-Gnd diode, such as a regulated diode. The high-side and low-side control diodes are designed to be small in size to reduce input/output (I/O) capacitance, which reduces insertion loss on high-speed lines similar to those in high-speed Ethernet applications. With the development of the industry, the control diode is integrated with the voltage regulator diode. Figure 1A-2 and Figure ia-3 show the integration of the directional diode and the voltage regulator diode. The high end and low end terminals are not visible from the outside. Figure 1A 2 is a high figure. Diode single but internal, high. The internal circuit is the same as the 1A-1 side.

g電容的穩 丨壓二極體 同。輸入/輪 端控向二極體和低端控向二極饉與單向的穩壓二極 體整合示意 壓二極體， 整合在一起 出（I/O)端子為陰極，接地端GND為陽極，電壓源vccThe stable voltage of the g capacitor is the same as that of the diode. The input/wheel end control diode and the low-end control diode are integrated with the unidirectional voltage regulator diode to indicate the voltage diode, and the integrated (I/O) terminal is the cathode, and the ground GND is Anode, voltage source vcc

端為内化的，從外面不可見。第1A_3圖為高端控向二極 體和低端控向二極體同一 電路整合的 示意圏。:但是’如果用於代化應用，配有 這種整合方式的保護電路iQ丨超 出設計面積 而 且，必須精心地儀化設計，在電容和控向二極體的正相 偏壓之間找到最佳的平衡點， 位元。 以獲得較好的整體電屋籍 第1B圊為傳統的暫態電壓抑制器（TVS)電路圖，第1 1圖為暫態電壓抑制器（TVS)電路實際裝置的橫斷面 圖，即按照互補金屬氡化物半導體（CM〇s)製作工视 將暫態電壓抑制器（TVS)電路做出積體電路晶片。， 第1B-1圖所示，使用互補金屬氧化物半導體（CMQs正如 098132926 表單編號A0101 第5頁/共42頁 製 0983394958 201015703 作工藝生產二極體、NPN和PNP電晶體，在半導體襯底上 ，二極體和電晶體會橫向延伸。因此，通過裝置設計和 配置生成的暫態電壓抑制器（TVS)電路將在襯底上佔據 較大的面積。要想縮小如第^—1圖所示的，被暫態電壓 抑制器（TVS)電路保護的電子裝置絕非易事。 本專利的發明者將待審專利申請US 11/6〇6, 602中的暫 態電壓抑制器（TVS)電路，用第1C圖所示的裝置配置做 了改進’提出了一種新的暫態電壓抑制器（TVS)電路。 本申請為部份接續申請案（CIP)，要求聲明申請 毫 11/606, 602的優先權》本專利申請特此引用專利申請 11/6〇6, 6〇2中的公開說明^以辦參:考H等、1C@為在〆個 P襯底/N—外延層結内形成$每^秦有J典壓二極體 的暫態電壓抑制器(TVS ) 士 第 所 示，由於主 穩壓二極體和高端二極體是縱向延伸的，減少了所占的 面積’所以暫態電壓抑制器（TVS)電路有了明顯的改進 。此電路使用兩個_入/輪—潟#戌套相應的高 端和低端二極體對，但高♦端ϋ體中每個區域的 . 導電類型卻是相反的。高碱控體還與帶有隔離溝 道絕緣溝的主穩壓二極體絕緣，這就避免了因大意疏忽 而造成橫向寄生電晶體的開啟。 儘管如此，仍然需要減小高端和低端控向二極體所占的 面積。而且，還要進一步降低控向二極體的電容。因此 ’有必要通過新的結構佈局和製作方法，設計和改進裝 置配置方法。新的裝置配置和製作方法，還必須考慮外 延層的設計優化工藝，可控的摻雜濃度和外延層厚度， 098132926 以便在降低電容和保持適當的齋納擊穿電壓之間找到最 表單編號 AG1G1 % 6 42 S 0983394958-0 201015703 好的平衡點。 因此’電路料和裝置製造領域，必__的、改良 的電路配置和製作卫藝方法，以解決上述難題。更確切 地說，有必要改良暫態電壓抑制器（TVS)電路，為可搗 式電子裝置，提供帶有低電容和良好的電Μ位元的、 低成本、高密度的暫態電壓抑制器（TVs)電路。 【發明内容】 . [0003] ❹ Ο 因此本發明一方面是用尚端二極體、低端二極體作為 控向二極體，改良暫態電壓抑制器（TVS)的結構配置。 控向二極體對與主穩壓二極髖配合，其中高端二極趙、 低端二極邀和主穩壓二極是的縱向二 極艘。高嶙上極體與主穩麼暫態電麼 抑制器C TVS )所占面積明祕*本發明改 良後的暫態電壓抑制器（TVS)保護的電子裝置進一步小 型化。本發明所述的低成本的暫態電壓抑制器（TVS)電 路能夠通過很小的矽片尺芩抑制器（TVS )保護，克服和解決了上#置和暫態電壓抑 制器（tvs)裝置製造方法與困難。 另外，本發明另一方面是用包括高端控向二極體和低端The end is internalized and is not visible from the outside. Figure 1A_3 shows the integration of the high-side steering diode and the low-side steering diode in the same circuit. : But 'if used for generation applications, the protection circuit iQ丨 with this integrated method is beyond the design area and must be carefully designed to find the most between the capacitor and the positive phase bias of the steering diode. Good balance point, bit. To obtain a better overall electrical house number 1B is a conventional transient voltage suppressor (TVS) circuit diagram, and FIG. 1 is a cross-sectional view of the actual device of the transient voltage suppressor (TVS) circuit, that is, complementary The metal telluride semiconductor (CM〇s) fabrication process uses a transient voltage suppressor (TVS) circuit to make an integrated circuit chip. , as shown in Figure 1B-1, using a complementary metal-oxide-semiconductor (CMQs as 098132926 Form No. A0101, page 5/42-page 0893394958 201015703) to produce diodes, NPN and PNP transistors on a semiconductor substrate The diode and the transistor will extend laterally. Therefore, the transient voltage suppressor (TVS) circuit generated by the device design and configuration will occupy a large area on the substrate. To reduce the image as shown in Fig. The electronic device protected by the transient voltage suppressor (TVS) circuit is not an easy task. The inventor of the present patent is pending the transient voltage suppressor (TVS) in US Patent Application No. 11/6, 6,602. The circuit, improved with the device configuration shown in Figure 1C, proposes a new Transient Voltage Suppressor (TVS) circuit. This application is a partial continuation application (CIP) requiring a declaration of 11/606. Priority of 602. This patent application hereby cites the disclosure of the patent application 11/6〇6, 6〇2, for the reference: test H, etc., 1C@ is in a P substrate/N-epitaxial layer Forming a transient voltage suppressor (TVS) for each of the Q-type voltage diodes It is shown that since the main regulator diode and the high-voltage diode are longitudinally extended, the occupied area is reduced, so the transient voltage suppressor (TVS) circuit has been significantly improved. This circuit uses two_in/ Wheel-Peak #戌 sets the corresponding high-end and low-end diode pairs, but the high conductivity type is opposite in each area of the body. The high alkali control body is also insulated with trench isolation trenches. The main regulator diode is insulated, which avoids the inadvertent opening of the lateral parasitic transistor. However, it is still necessary to reduce the area occupied by the high-end and low-side control diodes. Reducing the capacitance of the steering diode. Therefore, it is necessary to design and improve the device configuration method through new structural layout and fabrication methods. The new device configuration and fabrication method must also consider the design optimization process of the epitaxial layer, which is controllable. Doping concentration and epitaxial layer thickness, 098132926 to find the best form number between reducing capacitance and maintaining proper Zina breakdown voltage. AG1G1 % 6 42 S 0983394958-0 201015703 Good balance point. So 'circuit And in the field of device manufacturing, it is necessary to improve the circuit configuration and fabricating methods to solve the above problems. More specifically, it is necessary to improve the transient voltage suppressor (TVS) circuit, which is a portable electronic device. A low-cost, high-density transient voltage suppressor (TVs) circuit with low capacitance and good electrical potential is provided. [Abstract] [0003] Therefore, one aspect of the present invention is The polar body and the low-end diode are used as the steering diode to improve the structural configuration of the transient voltage suppressor (TVS). The steering diode pair is matched with the main voltage regulator two-pole hip, wherein the high-end diode Zhao, the low-end diode and the main regulator diode are longitudinal diodes. What is the area of the sorghum upper body and the main stable? The suppressor C TVS) occupies the area of the secret * The improved transient voltage suppressor (TVS) protected electronic device is further miniaturized. The low-cost transient voltage suppressor (TVS) circuit of the present invention is capable of overcoming and solving the above-mentioned and transient voltage suppressor (tvs) devices with a small chip size suppressor (TVS) protection. Manufacturing methods and difficulties. In addition, another aspect of the invention is to include a high-end steering diode and a low-end

控向二極艎的控向二極體對，改良暫態電壓抑制器（TVS )的結構配置。控向二極體與主穩壓二極體酪合，其中 高端二極體、低端二極體和主穩壓二極體都是半導體襯 底中的縱向二極體。與平行結構相比，縱向二極體結構 要求晶片尺寸更小，因為它們的頂面上僅有一面端子， 而平行裝置結構的頂面兩面都有端子。 098132926 本發明另一方面是每一個二極體都是頂面上有一個單端 表單編號A0101 第7頁/共42頁 0983394958-0 201015703 子，並且底面上也有-個端子，這就避免了頂面兩面有 端子帶來的不良的影響。所述的縱向二極體不同於頂面 兩面都有端子的結構，這就限制了在頂面附近從一個端 子到另-個端子的平行電流，從而帶來更高的串聯電阻 。相比㈣言’本發_裝置縱向㈣流_面和底面 端子之間，將電流傳到半導體裏，因此串聯電阻更低， 最大電流密度更高，裝置的性能大幅提升。 本發明的另-方面是用高端二極體、低端二極體作為控 向二極體，與半導體襯底中的主穩壓二極體連接，改良 暫態電壓抑制器（TVS)的，耩配置。通過輕摻雜位於卜 錄埋層（NBL) *淺P+區臂向結構帶來 的較好的鑛滅’本發明_^^#顯著地降 低結電容。重摻雜型掩步提高n-型 掩埋層（NBL)的擴散電流。Controlled two-pole pairs of the two-pole, improved structural configuration of the transient voltage suppressor (TVS). The steering diode is combined with the main regulator diode, wherein the high-end diode, the low-side diode, and the main regulator diode are longitudinal diodes in the semiconductor substrate. Longitudinal diode structures require smaller wafer sizes than parallel structures because they have only one terminal on the top surface and the top surface of the parallel device structure has terminals on both sides. 098132926 Another aspect of the present invention is that each of the diodes has a single-ended form number A0101 on the top surface, page 7/42 pages 0893394958-0 201015703, and there is also a terminal on the bottom surface, which avoids the top. There are bad effects caused by the terminals on both sides of the surface. The longitudinal diode has a structure different from the top surface on both sides, which limits the parallel current from one terminal to the other terminal near the top surface, resulting in higher series resistance. Compared with (4), the current direction (four) flow between the _ surface and the bottom terminal, the current is transmitted to the semiconductor, so the series resistance is lower, the maximum current density is higher, and the performance of the device is greatly improved. Another aspect of the present invention is to use a high-side diode and a low-side diode as a steering diode to connect with a main voltage regulator diode in a semiconductor substrate to improve a transient voltage suppressor (TVS).耩 Configuration. The present invention _^^# significantly reduces the junction capacitance by lightly doping the better mineralization of the structure located in the shallow buried P+ region of the buried layer (NBL). The heavily doped type of masking increases the diffusion current of the n-type buried layer (NBL).

Q 本發明的另一方面是用南端一極體、低端二極想作為控 向二極體’與半:導逋槻底連接，改良 暫態電壓抑制器（TVS)爲端二極體、低端 二極體和主穩壓二極體都底中的縱向二極體 ，因此沒有表面電流。如上所述，由於本發明的縱向二 極體結構具有較低的串聯電阻（導致更低的功率耗散） 以及更好的電流擴散，因此本發明所述的暫態電壓抑制 器（TVS)裝置的耐用性得到了改善和提高。 本發明的另一方面是用高端二極體、低端二極體作為控 向二極體，與半導體襯底中的帶有N +摻雜掩埋層（NBL) 的主穩壓二極體連接，改良暫態電壓抑制器（TVS)的結 構配置。按此配置，由於重摻雜的N+摻雜掩埋層（NBL) 098132926 表單编號A0101 第8頁/共42頁 0983394958-0 201015703 會通過寄生縱向PNP電晶體，抑制電晶體動作，因此裝置 的性能得到了改善。該寄生縱向PNP電晶趙為從一個I/O 端到另一個I/O端所形成寄生晶閘管（pNPN)結構的一部 分。一個較弱的PNP電晶體將確保在要求vcc和Gnd端處 於浮接狀態的應用時，寄生晶閘管不開啟。 ❹ 本發明的另一方面是用高端二極體、低端二極體作為控 向二極體，與半導體襯底中的帶有N+摻雜掩埋層（NBL) 的主穩壓二極體連接，改良暫態電壓抑制器（TVS)的結 構配置。結電容強烈依賴於摻雜濃度，若將摻雜濃度降 低一個數量級，結電容會降低70彤。 在一個較佳實施例中，本發明L介淨、了*態電壓抑制 (TVS)裝置’配置在半導髅取成個低端控向 —極體和—·.個高端控向二極禮，邊圭’械麽土極艘相連， 以抑制暫態電壓。與所述的穩壓二極體相連的所述的低 端控向二極體和高m控向二極體置於半導體襯底中，每 一個都是二極體槻底中的媲涵減少了暫態 電壓抑制（TVS)裝置所占在一個典型實施 例t，高端控向二極體和餐在縱向方向上相互 重疊，進一步減少了暫態電壓抑制（TVS)裝置所占的橫 向面積。在另一典型實施例中，穩壓二極體還包括源極 下面的一個掩埋源極-摻雜區域。在一個典型實施例中， 在掩埋源極摻雜層和一較高摻雜濃度的淺襯底摻雜區之 間，高端控向二極體還包括一個輕摻雜襯底摻雜的外延 層以獲得高端控向二極體的低結電容。在另一典型實施 例中，高壓電極位於半導體襯底的頂面上，低壓電極位 098132926 於半導體襯底的底面上，通過與作為縱向二極體的穩壓 表單編號A0101 第9頁/共42頁 0983394958-0 201015703 二極體相連的低端控向二極體和高端控向二極體傳導電 流，這就完全消除了半導體橫向的表面電流。在另一典 型實施例中，在源極下的深掩埋源極摻雜區消除了由開 通半導體襯底中寄生雙極電晶體引起的鎖閂。在另一典 型實施例中，暫態電壓抑制（TVS)裝置的縱向二極體位 於具有輕襯底摻雜濃度的外延層内，降低對應的外延層 厚度的電容，以優化高端和低端控向二極體的擊穿電壓 。在另一典型實施例中，可通過自動摻雜形成具有最大 源極摻雜濃度的掩埋源極摻雜區，無需擴散，並且符合 縱向齊納擊穿電壓的要求。 在另一較佳實施例中，本發明還介紹了一種用作積體電 路（1C)的電子裝置，其中所冷的電子裝置還包括一個 暫態電壓抑制（TVS)裝置，以抑制電子裝置中的暫態電 壓。暫態電壓抑制（TVS)裝置位於半導體襯底上，包括 與主穩壓二極體相連的低端控向二極體和高端控向二極 體，以抑制暫態電壓》與主穩壓二極體相連的低端控向 二極體和高端控向二極體位於半導體襯底中，在其中構 成了一個縱向PN結，即縱向二極體^，因此減少了暫態電 壓抑制（TVS)裝置所占的橫向區域。在一典型實施例中 ，高端控向二極體和穩壓二極體在縱向方向上相互重疊 ，進一步減少了暫態電壓抑制（TVS)裝置所占的橫向區 域。在另一典型實施例中，穩壓二極體還包括一個在源 極區域下的掩埋源極-摻雜區。在另一典型實施例中，在 掩埋源極摻雜層和一較高摻雜濃度的淺襯底掺雜區之間 ，高端控向二極體還包括一個輕摻雜襯底摻雜的外延層 以獲得高端控向二極體的低結電容。在另一典型實施例 098132926 表單編號A0101 第10頁/共42頁 0983394958-0 201015703 ❺ [0004] 098132926 中同電極位於半導體襯底的頂面上低壓電極位於 導概底的底面上’通過與作S縱向二極體的穩壓二 =相連的低端控向二極體和高端控向二極體傳導電流 k就〜全消除了半導趙橫向的表面電流。在另一典型 施例+在源極下的深掩埋源極摻雜區消除了由開通 半導體襯底中寄生雙極電晶想引起的鎖問。在另一典型 實施例中’暫態電壓抑制（TVS)裝置的縱向二極體位於 ^有輕襯轉雜濃度料延層中，降低對躺外延層厚 電谷以優化高端和低端控向二極體的擊穿電壓。 在另典型實施例中，可通過自動接雜形成具有最大源 極摻雜濃度的掩埋源極摻且符合縱 向齊納擊穿電屋的要求。 本發明還介紹了 一種帶有集成暫態電TVS )電路 的電子裝置製造方法。該方法包括-個使用標準的DMOS 製造工藝來製作縱向PN結的工序 ，起到與縱向穩壓二極 體相連的低端控向二極體的作用，以 減小暫態電壓抑制（m)雜向區域。 閱讀以下各種㈣和®形^01!継實施例的詳細說明 後’對於本領域的技術人員，本發明的這些以及其他情 況和優勢將顯而易見。 【實施方式】 參考第2圖’本發明暫態電壓抑制器（TVS) 100的等效電 路的側向橫斷面示圖。暫態電壓抑制器（TVS) 100形成 於重摻雜P+半導體襯底105上，一個底部P—外延層110 一1和一個頂部P —外延層110-2構成P雙層外延層110 ’ 位於重摻雜P+半導體襯底105上，半導體襯底1〇5的底面 表單編號A0101 第11頁/共42頁 0983394958-0 201015703 098132926 上的皮面金屬10】’作為接地端。暫態電廢抑制器（ΤΜ )100包括一個ρ+區高端控向二極體和穩壓二極體的重 叠區，-個深度擊穿電壓（ν觸發植入層115，植入ρ +摻雜離子，其巾植人層115位於底部外延m — i和頂 驗源極區125下面謝掩埋層i2G之間。㈣二極體 從掩埋層120延伸至底部外延層110-!。淺P +植入區 130形成在頂部p 一外延層11〇一2的頂面附近以增強同 輸入/輸出U/Ο)金屬焊接點135的電接觸。頂面大部分 被氧化絕緣層145覆蓋，留有開口允許-焊接點14〇和N +源極區域125接觸’在高端二㈣和漏二極體重昼區 中’輸入/輸出（I/O)金^^十植入區 130相接觸；在暫態電壓抑右側，-個輸入/輪出Π/0)金屬為為，爹仏二極體的源極區域125’相接觸。輪人/於山γτ/Λ、 獬入/輸出（I/O)金屬焊接點135和輸入/輸出（I/G)錢辉接點135，可以在第三個方向 上相連接。料源.極掃哼奠—_|，高端二極體 位於缺口内從頂部P —外延+掩埋層12〇的 位置。低端二極體位於從，到雙層外延層 110的位置。暫態電壓抑制器（TVS) 1〇〇還包括隔離溝 道150將低端控向二極趙隔離高端二極想及與其重曼連接 在-起的穩壓二極體。從淺P +植入區以及卜外延區ιι〇 -2在它下面的部分，到N +掩埋層m，•然後到12〇下面 的卜外延層m-卜有一個寄生縱向PNP電晶艘。通過 高度換雜N +掩埋層120，避免了電晶想動作。寄生縱向 PNP電晶體是寄生1&gt;_晶開管的—部分’形成在輸入/ 輸出（I/O)金&gt;1焊接點135和135’之間的半導體區域 ...... 第12頁/共42頁 ❹ ❹ 表單編號A0101 0983394958-0 201015703 内。一個較弱的PNP電晶體將確保在要求將Vcc和Gnd端 處於浮接狀態的應用時，寄生晶閘管不開啟。一般要求 控向二極體不能被擊穿，因此穩壓二極體的擊穿電壓要 遠小於控向二極體的擊穿電壓。VBD觸發層將穩壓二極體 的擊穿電壓控制在一個符合要求的較小值上。 第3圖為本發明另一種可用的暫態電壓抑制器（TVS) ❹ 100’的橫斷面示圖。深度擊穿電壓（VBD)觸發層 115’由掩膜植入在高端控向二極體下面形成缺口，以避 免高摻雜層直接在高端控向二極艘下面，除此之外，暫 態電壓抑制器（TVS) 與第2圈所示的暫態電壓抑制 器（T V S ) 10 0結構相似。涵.疏忽大意造 成P —外延層110 — 2在p + € 面部#的摻雜濃 度升高的觀。祕域的低的水準 上’以獲得如下所述的低電容。第4圖為本發明的另一種 可用的暫態電壓抑制器（TVS) 100”的橫斷面示圖。N +Q Another aspect of the present invention is to use a south-end one-pole body and a low-end diode as a control diode to connect with a half-guide bottom, and to improve a transient voltage suppressor (TVS) as an end diode. The low-end diode and the main regulator diode are both longitudinal diodes in the bottom, so there is no surface current. As described above, the transient voltage suppressor (TVS) device of the present invention is provided because the vertical diode structure of the present invention has a lower series resistance (resulting in lower power dissipation) and better current spreading. The durability has been improved and improved. Another aspect of the present invention uses a high-end diode and a low-side diode as a steering diode to be connected to a main voltage regulator diode with an N + -doped buried layer (NBL) in a semiconductor substrate. , Structural configuration of the improved transient voltage suppressor (TVS). According to this configuration, the heavily doped N+ doped buried layer (NBL) 098132926 Form No. A0101 Page 8 / Total 42 pages 0893394958-0 201015703 will suppress the transistor action through the parasitic vertical PNP transistor, so the performance of the device Got an improvement. The parasitic longitudinal PNP is a part of the parasitic thyristor (pNPN) structure formed from one I/O terminal to the other I/O terminal. A weaker PNP transistor will ensure that the parasitic thyristor does not turn on when the application requiring the vcc and Gnd terminals to be in a floating state.另一方面 Another aspect of the present invention uses a high-end diode and a low-side diode as a steering diode to be connected to a main voltage regulator diode with an N+ doped buried layer (NBL) in a semiconductor substrate. , Structural configuration of the improved transient voltage suppressor (TVS). The junction capacitance is strongly dependent on the doping concentration. If the doping concentration is reduced by an order of magnitude, the junction capacitance is reduced by 70 彤. In a preferred embodiment, the present invention provides a low-end steering-polar body and a high-end steering diode. , Biangui 'arms and earth are connected to each other to suppress transient voltage. The low-side control diode and the high-m control diode connected to the voltage stabilizing diode are placed in a semiconductor substrate, each of which is reduced in the bottom of the diode The transient voltage suppression (TVS) device occupies a typical embodiment t, and the high-side steering diode and the meal overlap each other in the longitudinal direction, further reducing the lateral area occupied by the transient voltage suppression (TVS) device. In another exemplary embodiment, the voltage stabilizing diode further includes a buried source-doped region below the source. In an exemplary embodiment, between the buried source doped layer and the higher doped concentration shallow substrate doped region, the high side steering diode further includes a lightly doped substrate doped epitaxial layer Get the low junction capacitance of the high-side steering diode. In another exemplary embodiment, the high voltage electrode is on the top surface of the semiconductor substrate, and the low voltage electrode is located on the bottom surface of the semiconductor substrate through the voltage regulator form number A0101 as a vertical diode. Page 0893394958-0 201015703 The diode-connected low-side steering diode and the high-side steering diode conduct current, which completely eliminates the lateral surface current of the semiconductor. In another exemplary embodiment, the deep buried source doped region under the source eliminates latching caused by opening parasitic bipolar transistors in the semiconductor substrate. In another exemplary embodiment, the vertical diode of the transient voltage suppression (TVS) device is located in an epitaxial layer having a light substrate doping concentration, and the capacitance of the corresponding epitaxial layer thickness is reduced to optimize high-end and low-end control. Breakdown voltage to the diode. In another exemplary embodiment, a buried source doped region having a maximum source doping concentration can be formed by autodoping without diffusion and meeting the requirements of the longitudinal Zener breakdown voltage. In another preferred embodiment, the present invention also provides an electronic device for use as an integrated circuit (1C), wherein the cooled electronic device further includes a transient voltage suppression (TVS) device for suppressing the electronic device. Transient voltage. The transient voltage suppression (TVS) device is located on the semiconductor substrate, and includes a low-end control diode and a high-side steering diode connected to the main voltage regulator diode to suppress the transient voltage and the main regulator II. The low-side control diode and the high-side steering diode connected to the body are located in the semiconductor substrate, forming a longitudinal PN junction, ie, a longitudinal diode, thus reducing transient voltage suppression (TVS) The lateral area occupied by the device. In an exemplary embodiment, the high side steering diode and the voltage stabilizing diode overlap each other in the longitudinal direction, further reducing the lateral area occupied by the transient voltage suppression (TVS) device. In another exemplary embodiment, the voltage stabilizing diode further includes a buried source-doped region under the source region. In another exemplary embodiment, between the buried source doped layer and the higher doped concentration shallow substrate doped region, the high side steering diode further includes a lightly doped substrate doped epitaxial region. The layer achieves a low junction capacitance of the high side steering diode. In another exemplary embodiment 098132926 Form No. A0101 Page 10 / Total 42 page 0893394958-0 201015703 ❺ [0004] 098132926 The same electrode is located on the top surface of the semiconductor substrate and the low voltage electrode is located on the bottom surface of the guide bottom. The voltage regulation of the S longitudinal diode = the connected low-side control diode and the high-side steering diode conduct current k - completely eliminates the lateral surface current of the semi-conductor. The deep buried source doped region under another exemplary embodiment + at the source eliminates the lock caused by the parasitic bipolar transistor in the open semiconductor substrate. In another exemplary embodiment, the longitudinal diode of the 'transient voltage suppression (TVS) device is located in the light-diffused heterogeneous material extension layer, and reduces the thickness of the epitaxial layer to optimize the high-end and low-end steering. The breakdown voltage of the diode. In another exemplary embodiment, the buried source source having the largest source doping concentration can be formed by automatic doping and meets the requirements of the vertical Zener breakdown house. The present invention also introduces an electronic device manufacturing method with an integrated transient electric TVS circuit. The method includes a process of fabricating a longitudinal PN junction using a standard DMOS fabrication process, functioning as a low-side steering diode connected to a vertical regulator diode to reduce transient voltage suppression (m) Miscellaneous area. These and other aspects and advantages of the present invention will become apparent to those skilled in the <RTIgt; [Embodiment] Referring to Fig. 2, a side cross-sectional view of an equivalent circuit of a transient voltage suppressor (TVS) 100 of the present invention is shown. A transient voltage suppressor (TVS) 100 is formed on the heavily doped P+ semiconductor substrate 105, and a bottom P-epitaxial layer 110-1 and a top P-epitaxial layer 110-2 form a P double epitaxial layer 110' On the doped P+ semiconductor substrate 105, the bottom surface of the semiconductor substrate 1〇5 is numbered A0101. Page 11/42 pages 0893394958-0 201015703 098132926 The leather metal 10' is used as the ground terminal. The transient electric waste suppressor (ΤΜ) 100 includes an overlap region of a high-voltage steering diode and a voltage stabilizing diode of the ρ+ region, a depth breakdown voltage (ν triggering the implant layer 115, implanting ρ + doping The impurity ions, the implant layer 115 is located between the bottom epitaxial m_i and the top detector source region 125, and between the buried layer i2G. (4) The dipole extends from the buried layer 120 to the bottom epitaxial layer 110-! Implant region 130 is formed adjacent the top surface of top p-epitaxial layer 11 - 2 to enhance electrical contact with input/output U/Ο metal pads 135. The top surface is mostly covered by the oxidized insulating layer 145, leaving an opening permitting - solder joint 14 〇 and N + source region 125 contact 'in the high-end two (four) and drain dipole weight 昼 area 'input / output (I / O) The gold ^^10 implanted region 130 is in contact; on the right side of the transient voltage, the - input/round Π/0) metal is, and the source region 125' of the germanium diode is in contact. The wheel/Yushan γτ/Λ, the in/out (I/O) metal solder joint 135 and the input/output (I/G) Qianhui junction 135 can be connected in the third direction. Source. Extremely broom - _|, the high-end diode is located in the gap from the top P - epitaxy + buried layer 12 〇 position. The low side diode is located from the position to the double epitaxial layer 110. The Transient Voltage Suppressor (TVS) 1〇〇 also includes an isolation channel 150 that isolates the low-end control diode to the high-end diode and connects it to the voltage regulator diode. From the shallow P + implanted region as well as the epitaxial region ιι〇 -2 in the lower part of it, to the N + buried layer m, and then to the underlying epitaxial layer m-b has a parasitic longitudinal PNP cell. By electrically changing the N + buried layer 120, the electromorphic action is avoided. The parasitic longitudinal PNP transistor is a parasitic 1&gt;_a portion of the crystal open tube formed in the semiconductor region between the input/output (I/O) gold &gt; 1 solder joints 135 and 135'... Page / Total 42 pages ❹ 表单 Form number A0101 0983394958-0 201015703. A weaker PNP transistor will ensure that the parasitic thyristor does not turn on when an application is required to place the Vcc and Gnd terminals in a floating state. Generally, the control diode cannot be broken down, so the breakdown voltage of the regulator diode is much smaller than the breakdown voltage of the steering diode. The VBD trigger layer controls the breakdown voltage of the Zener diode to a small value that meets the requirements. Figure 3 is a cross-sectional view of another available transient voltage suppressor (TVS) ❹ 100' of the present invention. The deep breakdown voltage (VBD) trigger layer 115' is implanted under the high-side control diode by a mask to form a gap to avoid the highly doped layer directly under the high-end control pole, in addition to the transient The voltage suppressor (TVS) is similar in structure to the transient voltage suppressor (TVS) 10 0 shown in the second lap. Han. Inadvertently, the effect of P-epitaxial layer 110-2 on the doping concentration of p + € Facial # is increased. The low level of the secret domain is on to obtain a low capacitance as described below. Figure 4 is a cross-sectional view of another available transient voltage suppressor (TVS) 100" of the present invention.

掩埋層120’ t有帶缺口，，療凌:擊_遞:ifvBD)觸發層 II5，’就在兩段N +掩埋屢12(^〗¥間，而不是在N +掩埋層120’下面，除此之外，#態電壓抑制器（tvS )100”與第2圖和第3圖分別所示的暫態電壓抑制器（ TVS) 100和暫態電壓抑制器（TVS) 100’結構相似。 第5A圖和第5B圓分別為按照第iB—1圖和第1B —2囷所示 的暫態電壓抑制器（TVS)結構佈局的俯視圖。如第5八圖 所示，主穩壓二極體與高端二極體分別位於不同區域上 。相比之下，如第5B圖所示，高端二極體與穩壓二極體 重疊’因此第5B圖中的暫態電壓抑制器（TVS) 1〇〇所占 面積’與第5A圖中的暫態電壓抑制器（TVs) 1〇〇相比要 098132926 表單换號A0101 第13頁/共42頁 0983394958-0 201015703 小得多。 第6圖為電容等效電路的橫斷面示圖，用來計算穩壓二極 體(：7分別與高端二極體CHe和低端二極體C,。相結合的總電 容。假設Cz遠大於CHS或，總電容CT()tai可以表示為： CTotal - aPNP*(CHS) + CLS + C(Pad) 其中αρΝρ為由P —外延層110 — 2、N +掩埋層120和P —外 延層110 —1組成的縱向PNP電晶體發射極到集電極的增益 ，（：（Pad)爲焊接點電容。根據上式，為了獲得暫態電壓 抑制器（TVS)的低電容，必須降低高端控向二極體的電 容〇HS和低端控向二極jt:的重容cls。由於cz遠大於chs， ® 並與cHS並聯，㈣㈣為突 變Ν + /Ρ-結的耗盡寬度\的縱向二極體 ’耗盡寬度沿豎直方向’ 應該與耗盡 寬度%—樣大β但是，P層深度不應該超過w太多，否則 將引起二極體的正向.陴不必要的增加《對於突變N +和The buried layer 120't has a gap, and the treatment: hit _ hand: ifvBD) trigger layer II5, 'just in the two sections N + buried repeatedly 12 (^〗 ¥, not under the N + buried layer 120', In addition to this, the #state voltage suppressor (tvS) 100" is similar in structure to the transient voltage suppressor (TVS) 100 and the transient voltage suppressor (TVS) 100' shown in Figs. 2 and 3, respectively. 5A and 5B are top views of the transient voltage suppressor (TVS) structure layout shown in Fig. 1B-1 and 1B-2, respectively. As shown in Fig. 5, the main regulator diode The body and the high-end diode are respectively located in different regions. In contrast, as shown in FIG. 5B, the high-end diode overlaps with the voltage regulator diode. Therefore, the transient voltage suppressor (TVS) in FIG. 5B is shown. The area occupied by 1〇〇 is much smaller than the transient voltage suppressor (TVs) 1第 in Figure 5A. 098132926 Form change number A0101 Page 13/42 page 0893394958-0 201015703 much smaller. A cross-sectional view of the capacitor equivalent circuit used to calculate the total capacitance of the regulated diode (7, respectively, combined with the high-side diode CHe and the low-side diode C.) Cz Far greater than CHS or, the total capacitance CT() tai can be expressed as: CTotal - aPNP*(CHS) + CLS + C(Pad) where αρΝρ is derived from P—epitaxial layer 110 — 2, N + buried layer 120 and P — epitaxial The potential of the vertical PNP transistor from the layer 110-1 to the collector, (: (Pad) is the solder joint capacitance. According to the above formula, in order to obtain the low capacitance of the transient voltage suppressor (TVS), the high-end control must be reduced. To the capacitance of the diode 〇 HS and the low-end control to the dipole jt: the weight of the cls. Since cz is much larger than chs, ® and parallel with cHS, (four) (four) is the Ν Ρ + / Ρ - knot depletion width \ portrait The diode 'depletion width along the vertical direction' should be the same as the depletion width %-like large β. However, the depth of the P layer should not exceed too much w, otherwise it will cause the positive polarity of the diode. For mutations N + and

p _ 結，結電容 c j 和::||_ 電u g I c.= a (n )1/2 11； Property V = α (ΝΑ)&quot;3/4* 〇p _ junction, junction capacitance c j and :::||_ electric u g I c.= a (n )1/2 11; Property V = α (ΝΑ)&quot;3/4* 〇

BD 其中，Ν &amp;為Ρ區的推雜濃度’ ΝΡΤ為非穿通型擊穿電壓。 當摻雜濃度降低時，控向二極體的電容隨擊穿電麼的升 高而降低’第8圖表示結電容0』隨摻雜濃度的變化情況， 第9圖表示外延層申的耗盡寬度\隨摻雜濃度的變化情況 。如第8圖所示，結電容Cj隨摻雜濃度的增大而增大。因 此，可以通過為P—外延層110 —2選取一個較低的摻雜濃 度，然後利用上述摻雜濃度，根據第9圖所示的耗盡層厚 度的寬度，找到P —外延層110 —2的最佳厚度，來優化暫 098132926 表單編號A0101 第14頁/共42頁 0983394958-0 態電壓抑制器（TVS)。對於高端二極體，P +植入區130 和N-型掩埋層（NBL) 120之間會形成電容，因此，它們 之間的P—外延層11 0 — 2區域的垂直距離應與耗盡寬度相 匹配，這樣才能獲得低電容。上述垂直距離還應該接近 耗盡寬度，以避免引起二極體的正向電壓不必要的增加 。對於低端二極體，從源極區域125’到槻底105直接的 垂直距離應該與耗盡寬度（考慮到外延層110 — 1和110 — 2的摻雜濃度）大致匹配。第一外延層110 — 1的厚度也應 該考慮低端二極體的耗盡寬度和它與高端二極體之間的 距離；如果襯底105過於靠近高端二極體，襯底105中的 部分摻雜物可能或擴散到第二外延層110 — 2的區域中接 觸植入物130下面，並引起第二外延層110 — 2中的摻雜濃 度升高，導致高端二極體的電容升高。在一個較佳實施 例中，P—外延層110 —1和110 — 2的摻雜濃度將盡可能 地保持在較低的水準，以確保控向二極體中獲得低電容 ' ^ t ί 。上述的在源極區域125下淹掩娌層120，被植入， 最大劑量、最小擴散，通過一锋自、知摻雜過程，同時滿 足縱向穩壓二極體的擊穿電壓善汆&lt; 第10Α圖至第10D圖展示了一種在和第3圖中的裝置100’ 相似的裝置中，形成Ν-型掩埋層（NBL)的方法。第10Α 圖為在重摻雜的Ρ +襯底105上，生長一層輕摻雜的第一 Ρ-外延層110-1。第10Β圖為使用一種掩膜植入（圖中 沒有給出掩膜），以便形成Ν +植入區121。第10C圖表示 一種注入物擴散Ν +植入區121，以形成Ν-型掩埋層（ NBL) 120。在第10C圖中，為使用另一種掩膜植入（圖 中沒有給出掩膜），以便在Ν +植入區121下方，形成Ρ + 表單編號Α0101 第15頁/共42頁 201015703 VBD觸發植入層〗15’ 。第10D圖為在第一p —外延層lio —1上生長一層第二P—外延層110 — 2。14_型掩埋層（ NBL) 120輕微擴散到第二外延層11〇 —2中。 雖然本發明詳細介紹了現有的較佳實施例，但並不能以 此局限本發明的範圍。例如’半導體區域的導電類型可 以變換，即P型區域可以用N型區域代替，反之亦然。在 這種情況下’高端二極體和低端二極體的位置應該互換 ;而且半導體頂端的電壓應該更低，底端的電壓應該更BD where Ν &amp; is the doping concentration of the germanium region ΝΡΤ is the non-punch-through breakdown voltage. When the doping concentration decreases, the capacitance of the steering diode decreases as the breakdown voltage increases. [Figure 8 shows the junction capacitance 0 as a function of the doping concentration. Figure 9 shows the consumption of the epitaxial layer. Width = change with doping concentration. As shown in Fig. 8, the junction capacitance Cj increases as the doping concentration increases. Therefore, the P-epitaxial layer 110-2 can be found by selecting a lower doping concentration for the P- epitaxial layer 110-2 and then using the above doping concentration to obtain the thickness of the depletion layer thickness shown in FIG. The optimal thickness is optimized for the temporary 098132926 Form No. A0101 Page 14 of 42 Page 0893394958-0 State Voltage Suppressor (TVS). For the high-end diode, a capacitance is formed between the P + implant region 130 and the N-type buried layer (NBL) 120, and therefore, the vertical distance between the P-epitaxial layer 11 0-2 regions between them should be depleted. The widths match so that low capacitance is achieved. The above vertical distance should also be close to the depletion width to avoid causing an unnecessary increase in the forward voltage of the diode. For the low side diode, the direct vertical distance from the source region 125' to the bottom 105 should substantially match the depletion width (considering the doping concentrations of the epitaxial layers 110-1 and 110-2). The thickness of the first epitaxial layer 110-1 should also take into account the depletion width of the low-side diode and its distance from the high-end diode; if the substrate 105 is too close to the high-end diode, the portion of the substrate 105 The dopant may or diffuse into the region of the second epitaxial layer 110-2 under the contact implant 130 and cause an increase in the doping concentration in the second epitaxial layer 110-2, resulting in an increase in the capacitance of the high-end diode. . In a preferred embodiment, the doping concentrations of the P- epitaxial layers 110-1 and 110-2 will be kept as low as possible to ensure a low capacitance '^t ί' in the steering diode. The above-mentioned underlying source region 125 floods the germanium layer 120, is implanted, the maximum dose, the minimum diffusion, passes through a front self-known doping process, and simultaneously satisfies the breakdown voltage of the vertical voltage regulator diode. Figures 10 through 10D illustrate a method of forming a Ν-type buried layer (NBL) in a device similar to device 100' in Figure 3. Figure 10 is a diagram of a lightly doped first germanium-epitaxial layer 110-1 on a heavily doped germanium + substrate 105. Figure 10 is a mask implantation (no mask is shown) to form the Ν + implant region 121. Figure 10C shows an implant diffusion Ν + implant region 121 to form a Ν-type buried layer (NBL) 120. In Fig. 10C, in order to use another mask implant (no mask is given in the figure), under the Ν + implant area 121, Ρ + form number Α 0101 page 15 / total page 42 201015703 VBD trigger Implant layer 〖15'. 10D is a second P- epitaxial layer 110-2 grown on the first p-epitaxial layer lio-1. The 14_type buried layer (NBL) 120 is slightly diffused into the second epitaxial layer 11〇-2. Although the present invention has been described in detail with reference to the preferred embodiments of the present invention, it is not intended to limit the scope of the invention. For example, the conductivity type of the semiconductor region can be changed, that is, the P-type region can be replaced with an N-type region, and vice versa. In this case, the position of the high-end diode and the low-side diode should be interchanged; and the voltage at the top of the semiconductor should be lower, and the voltage at the bottom should be more

高。閱讀上述公開說明書之後，各種修改和變換，對於 本領域的技術人員無疑顯而異見β因，此，我們要求以附 上的申請專利範圍，來限 改和變換》 【圖式簡單說明】high. After reading the above-mentioned disclosure, various modifications and changes will be apparent to those skilled in the art. Therefore, we require that the scope of the attached patent application be limited to the modification.

的所有修 [0005]第1Α — 1圖表示配有二極體陣列的傳統暫態電壓抑制（ tvs)電路’通常用於靜電放電（ESD)保護。All of the repairs [0005] Figure 1 shows that a conventional transient voltage suppression (tvs) circuit with a diode array is typically used for electrostatic discharge (ESD) protection.

第1A —2圖和第1A —3圈分矣1¾¾無三^艘與穩壓二極體 整合在一起，以便在舉.向丨南备♦態電壓抑制（TVS )二極體獲得低電容的示 第1B圖為傳統暫態電壓抑制（TVS)電路的標準電路圖， 第1B-1圖、第1B-2圖和第ιΒ_3圖為暫態電壓抑制器 (TVS)電路實際裝置的橫斷面視圖，即按照互補金屬氧 化物半導體（CMOS)製作工藝，將暫態電壓抑制器（ns )電路做出積體電路晶片。 第ic圖為配有二極體的暫態電M抑制器（TVS)電路，作 為縱向二極體，以減小暫態《抑㈣（TVS)電路的尺 寸0 098132926 表單編號A0101 第16真/共42頁 0983394958-0 201015703 ❹ 第2圖至第4圖為穩壓二極體與高端和低端控向二極體集 成的橫斷面試圖，用來說明配有N +掩埋層和隔離溝道的 暫態電壓抑制器（TVS)裝置的電路，以形成本發明所述 的縱向暫態電壓抑制器（TVS)二極體陣列，減小二極體 陣列所占的面積。 第5A圖至第5B圖為暫態電壓抑制器（TVS)裝置佈局的頂 視圖，以說明實施本發明的縱向二極體陣列所要求的減 小的面積。 第6圖為配有N —掩埋層（NBL) TVS齊納的暫態電壓抑制 器（TVS)電路的電容部分的橫斷面示圖。 第7圖為控向二極體的低電容設計示意囷，以優化本發明 中的設計參數。 第8圖為結電容隨突變N + -P結的摻雜濃度ND的變化曲線。 第9圖為耗盡寬度WD隨突變N+-P結的摻雜濃度ND的變化 曲線。 '4： , — Π, 第10A圖至第10D圖為N +摻雑掩埋層（NBL)和觸發植入 層的形成橫斷面示圖。 …' [0006] 【主要元件符號說明】 I/O 輸入/輸出 101 背面金屬 105 重摻雜P+半導體襯底 110雙層外延層 110-1 '110-2 P—外延層 120、120’ N-型掩埋層 098132926 115 植入層 表單編號A0101 第17頁/共42頁 0983394958-0 201015703 125 130 135 140 145 150 115' 100 CLS CHS WD 121 P +植入區 135’ 金屬焊接點 V c c焊接點 氧化絕緣層 隔離溝道 觸發層 100， 、 100” 、 TVS 低端二極體 高端二極體 耗盡寬度 N +植入區 125, N +源極區域 暫態電壓抑制器 _ 嶋 ❹ 098132926 表單編號A0101 第18頁/共42頁 0983394958-0Figure 1A-2 and Figure 1A-3 of the 矣13⁄43⁄4 无3^ ship are integrated with the voltage regulator diode to obtain low capacitance in the ♦ 电压 电压 电压1B is a standard circuit diagram of a conventional transient voltage suppression (TVS) circuit, and 1B-1, 1B-2, and ιΒ_3 are cross-sectional views of a practical device of a transient voltage suppressor (TVS) circuit. That is, in accordance with a complementary metal oxide semiconductor (CMOS) fabrication process, a transient voltage suppressor (ns) circuit is used to make an integrated circuit chip. The ic diagram is a transient electrical M suppressor (TVS) circuit with a diode as a vertical diode to reduce the size of the transient "fourth (TV)) circuit. 0 098132926 Form No. A0101 16th true / Total 42 pages 0893394958-0 201015703 ❹ Figure 2 to Figure 4 are cross-section attempts to integrate a regulated diode with a high-end and low-side control diode to illustrate the presence of an N + buried layer and isolation trench The circuitry of the Transient Voltage Suppressor (TVS) device of the track forms the longitudinal transient voltage suppressor (TVS) diode array of the present invention to reduce the area occupied by the diode array. 5A through 5B are top views of a transient voltage suppressor (TVS) device layout to illustrate the reduced area required to implement the vertical diode array of the present invention. Figure 6 is a cross-sectional view of the capacitive portion of a transient voltage suppressor (TVS) circuit equipped with an N-buried layer (NBL) TVS Zener. Figure 7 is a schematic diagram of the low capacitance design of the steering diode to optimize the design parameters of the present invention. Figure 8 is a graph showing the relationship between the junction capacitance and the doping concentration ND of the abrupt N + -P junction. Figure 9 is a graph showing the variation of the depletion width WD with the doping concentration ND of the abrupt N+-P junction. '4: , — Π, Figures 10A through 10D are cross-sectional views of the N + Erbium-Doped Buried Layer (NBL) and the trigger implant layer. ...' [0006] [Major component symbol description] I/O input/output 101 back metal 105 heavily doped P+ semiconductor substrate 110 double epitaxial layer 110-1 '110-2 P- epitaxial layer 120, 120' N- Buried layer 098132926 115 Implant layer form number A0101 Page 17 / Total 42 page 0893394958-0 201015703 125 130 135 140 145 150 115' 100 CLS CHS WD 121 P + implanted area 135' Metal solder joint V cc solder joint oxidation Insulation isolation channel trigger layer 100, , 100" , TVS low-end diode high-end diode depletion width N + implant region 125, N + source region transient voltage suppressor _ 嶋❹ 098132926 Form No. A0101 Page 18 of 42 page 0893394958-0

Claims (1)

201015703 七 3 ❹ 申請專利範圍： 種位於半導體襯底上的暫態電壓抑制器（τπ)裝置， 其特徵在於，包括： 一與主穩壓二極體相連接的控向二極體對，以抑制暫態電 壓其中所述控向二極體對的每一控向二極體都與主穩壓 -極體相連’作為半導體襯底中的縱向二極艘構成一個PN 結，以此減小暫態電壓抑制器（TVS)裝置所占的橫向面 積，並且其中所述控向二極體對包括一個高端控向 二極體 和一個低端控向二極艘。 如申明專利氣圍第1項所述的暫態電愿抑制器（TVS)裝 置，其特徵_ :所述㈣健向二極 體和穩壓二_沿縱向相互^ M g t M 抑制器(m)裝置所占的^▲。肩’’ .如申請專利範圍第2項所述的暫態電愿抑制器（TVS)裝 置，其特徵在於：所述穩气二極淳在一源極區域下面，還 包括-嗰掩埋源極摻雜區，她编磁極摻雜區也是 所述控向二極趙對中的第結的-部分。 .如申請專利範圍第3項所述-壓抑制器裝 置’其特徵在於：所述控向二極體對中的第一個控向二極 體還包括-個婦雜襯底外延層，該外延層位於一個掩埋 源極換雜層和一個具有更高摻雜濃度的淺襯底掺雜區之間 ，以使所述控向二極體對中的第一個控向二極體獲得低電 容0 .如申清專利範圍第2項所述的暫態電壓抑制器（TVS )裝 置，其特徵在於：所述控向二極體對中的第二個控向二極 098132926 表單編號A0101 第19頁/共42頁 0983394958-0 201015703 體由一源極區域到它下面的外延層之間形成，其中所述的 第二個控向二極體並不與穩壓二極體縱向重疊。 6 .如申請專利範圍第3項所述的暫態電壓抑制器（TVS)裝 置，其特徵在於：在所述的源極摻雜區下麵的所述的掩埋 的源極摻雜區是重摻雜的，以阻止半導體襯底中的寄生雙 極電晶體導通。 7 .如申請專利範圍第3項所述的暫態電壓抑制器（TVS)裝 置，其特徵在於：暫態電壓抑制器（TVS)裝置的縱向二 極體位於具有輕襯底摻雜濃度的外延層中，以減小電容， 其有一相應的外延層厚度以優化高端和低端控向二極體正 向電阻和結電容。 8 .如申請專利範圍第3項所述的暫態t壓抑制器（TVS)裝 置，其特徵在於：所述的源極摻雜區為N型，所述控向二 極體對中的第一個控向二極體為高端控向二極體，所述控 向二極體對中的第二個控向二極體為低端控向二極體。 9 .如申請專利範圍第2項所述的暫態電壓抑制器（TVS)裝 置，其特徵在於：至少一個隔離講道，用於隔離所述控向 二極韹對中的第二個控向二極&amp;和與穩壓二極體重疊的所 述控向二極體對中的第一個控向二極體。 10. —種暫態電壓抑制器（TVS)裝置的製備方法，其特徵在 於： 製備一與一個縱向穩壓二極體相連的縱向控南二極體對， 以減小暫態電壓抑制器（TVS)裝置所占的橫向面積，其 中所述的控向二極體對包括一個高端控向二極體和一個低 端控向二極體。 11 .如申請專利範圍第10項中所述的製備方法，其特徵在於： 098132926 表單編號A0101 第20頁/共42頁 0983394958-0 201015703 所述製備與所述的主縱向穩壓二極體相連的所述縱向控向 二極體對的步驟，還包括沿縱向相互重疊製備控向二極體 對中的第一個控向二極體以及穩壓二極體以進一步減小暫 態電壓抑制器（TVS)裝置所占的橫向面積。 12.如申請專利範圍第11項中所述的製備方法，其特徵在於， 其中還包括一步：為所述的穩壓二極體，製備在源極區域 下麵的掩埋的源極掺雜區。 13 .如申請專利範圍第12項中所述的製備方法，其特徵在於： 製備控向二極體對中所述的第一個控向二極體還包括在掩 埋的源極摻雜層和具有較高摻雜濃度的淺襯底摻雜區之間 ，形成輕摻雜襯底摻雜外延層，以使所述的第一個控向二 極體獲得低電容和良好的觸點 14 .如申請專利範圍第12項中所述的製備方法，其特徵在於， 還包括：在半導體襯底上，製備兩個外延層，其中掩埋的 源極摻雜區位於所述的兩個外延層的結點處。 15 .如申請專利範圍第12項中所述的製:備方法*其特徵在於： ^ 所述的在源極摻雜區下麵製備所述的掩.埋的源極摻雜區的 ❿ 步驟中，還包括重摻雜掩埋的源極摻雜區，以消除半導體 襯底中的寄生雙級電晶體的開啟。 16. 如申請專利範圍第12項中所述的製備方法，其特徵在於， 還包括：將暫態電壓抑制器（TVS)裝置的所述的縱向二 極體，設置在具有輕襯底摻雜濃度的外延層中以減小電容 ，其有一相應的外延層厚度以優化高端和低端控向二極體 的正向電阻和結電容。 17. 如申請專利範圍第12項中所述的製備方法，其特徵在於： 源極摻雜為N型，控向二極體對中所述的第一個控向二極 098132926 表單編號A0101 第21頁/共42頁 0983394958-0 201015703 18 . 19 . 20 . =:向二極體’所述的第二個控向二極體為低端控 ^申請專㈣圍川射所私製備料， 還包括：麵述料導倾底W少-_離溝道， 用於隔離所述控向二極體對中的第二個控向二極體和與穩 壓二極體重4的所述控向二極艘對中的第-個控向二極體 Ο 如申請專概®㈣項巾所料製備枝，_ 製備-個掩埋㈣極__ “麵料半導體概底上 生長一個第—外延層，在所逑的[外私上形成掩膜植 入源極摻雜物，在所述的苐4外 層。 . 如申請專利範園第12項中201015703 VII 3 申请 Patent Application Range: A transient voltage suppressor (τπ) device on a semiconductor substrate, comprising: a pair of steering diodes connected to a main voltage regulator diode, Suppressing a transient voltage in which each of the steering diodes of the pair of steering diodes is connected to the main regulator-pole as a PN junction as a longitudinal pole in the semiconductor substrate, thereby reducing The lateral area occupied by the transient voltage suppressor (TVS) device, and wherein the pair of steering diodes includes a high side steering diode and a low side steering diode. A transient electric power suppressor (TVS) device according to the first aspect of the invention, characterized in that: (4) the living diode and the voltage regulator _ along the longitudinal direction ^ M gt M suppressor (m ) The device occupies ^▲. A transient electrical suppressor (TVS) device according to claim 2, wherein the steady-state diode is below a source region, and further includes a 嗰 buried source In the doped region, her magnetic pole doping region is also the part of the junction of the steering diode. The pressure suppressor device of claim 3, wherein the first steering diode of the pair of steering diodes further comprises a matte substrate epitaxial layer, The epitaxial layer is between a buried source impurity exchange layer and a shallow substrate doped region having a higher doping concentration to obtain a lower of the first steering diode of the pair of steering diodes Capacitor 0. The transient voltage suppressor (TVS) device according to claim 2, characterized in that: the second steering diode of the pair of steering diodes is 098132926, form number A0101 19 pages/total 42 pages 0893394958-0 201015703 The body is formed between a source region and an epitaxial layer below it, wherein the second steering diode does not vertically overlap the voltage stabilizing diode. 6. The transient voltage suppressor (TVS) device of claim 3, wherein the buried source doped region under the source doped region is heavily doped Miscellaneous to prevent parasitic bipolar transistor conduction in the semiconductor substrate. 7. The transient voltage suppressor (TVS) device of claim 3, wherein the longitudinal diode of the transient voltage suppressor (TVS) device is located at an epitaxial layer having a light substrate doping concentration. In the layer, to reduce the capacitance, it has a corresponding epitaxial layer thickness to optimize the high-side and low-side steering diode forward resistance and junction capacitance. 8. The transient t-pressure suppressor (TVS) device of claim 3, wherein the source doping region is N-type, and the steering diode pair is One of the steering diodes is a high-side steering diode, and the second steering diode of the pair of steering diodes is a low-side steering diode. 9. The transient voltage suppressor (TVS) device of claim 2, wherein: at least one isolated sermon is used to isolate a second steering of the pair of steering diodes a second polarity &amp; and a first steering diode of the pair of steering diodes overlapping the voltage stabilizing diode. 10. A method of fabricating a transient voltage suppressor (TVS) device, characterized by: preparing a pair of longitudinally-controlled south diodes connected to a longitudinally-regulated diode to reduce a transient voltage suppressor ( TVS) The lateral area occupied by the device, wherein the pair of steering diodes includes a high-side steering diode and a low-side steering diode. 11. The preparation method as recited in claim 10, wherein: 098132926 Form No. A0101, page 20/42, 0893394958-0, 201015703, said preparation being connected to said main longitudinally-regulated diode The step of longitudinally controlling the pair of diodes further comprises preparing the first steering diode and the voltage stabilizing diode of the pair of steering diodes in the longitudinal direction to further reduce transient voltage suppression. The lateral area occupied by the device (TVS) device. 12. The method of preparation of claim 11, wherein the method further comprises the step of: preparing the buried source doped region under the source region for the stabilizing diode. 13. The preparation method as recited in claim 12, wherein: the first steering diode described in the preparation of the pair of steering diodes further comprises a buried source doped layer and Between the shallow substrate doped regions having a higher doping concentration, a lightly doped substrate doped epitaxial layer is formed to obtain a low capacitance and a good contact 14 of the first steering diode. The preparation method as described in claim 12, further comprising: preparing two epitaxial layers on the semiconductor substrate, wherein the buried source doped regions are located in the two epitaxial layers At the junction. 15. The method as described in claim 12, wherein: the method of preparing the buried source-doped region under the source doping region is as follows: A heavily doped buried source doped region is also included to eliminate the turn-on of the parasitic bipolar transistor in the semiconductor substrate. 16. The method of preparation of claim 12, further comprising: disposing said longitudinal diode of a transient voltage suppressor (TVS) device on a light substrate doped The concentration of the epitaxial layer is reduced to have a corresponding epitaxial layer thickness to optimize the forward resistance and junction capacitance of the high side and low side steering diodes. 17. The preparation method according to claim 12, wherein the source is doped to an N-type, and the first dimming diode of the pair of steering diodes is 098132926. Form No. A0101 21 pages/total 42 pages 0893394958-0 201015703 18 . 19 . 20 . =: The second steering diode described in the 'diode' is a low-end control application (4). The method further includes: a surface material guiding bottom W is less - _ away from the channel, is used for isolating the second steering diode of the pair of steering diodes and the control of the voltage regulator diode 4 To the second control of the two poles, such as the application of the special (4) towel preparation, _ preparation - a buried (four) pole __ "the growth of a fabric - the epitaxial layer Forming a mask implant source dopant on the external [private], in the outer layer of the crucible 4. As in the application for patent paradigm 12 個第二外延 其特徵在於， 還包括：通過挑選一個外延層的低摻雜濃度，來獲得低結 電容；並通過抵選所述的外延層厚度，來滿足所述的高端 和低端控向二極體的耗盡^隍士 和低端控向二 極體 V·' ；tf Ο Θ 21 . 如申請專利範圍第20項中所方法，其特徵在於： 所述優化暫態電壓抑制器（TVS)裝置的所述的高端和低 端控向二極體的步驟’還包括挑選所述的外延層的所述的 厚度，以避免升高所述的高端和低端控向二極體的正向電 22 098132926 阻。 .一種位於半導體襯底上的暫態電壓抑制器（TVS)裝置， 其特徵在於，包括： 一種第一導電類型的襯底，其頂部生長一雙層外延層 ，該外延層包括生長在襯底上的一第一導電類型的第一外 表單編號A0101 第22頁/共42頁 0983394958-0 201015703 延層，和生長在第一外延層上的一第—導電類型的第二外 延層； 連接縱向穩壓二極體的縱向控向二極想，其中所述的這對 控向二極體包括一個高度控甸二極體和一個低端控向二極 Mb · m， 一個第二·導電類型的重摻榦的掩埋層，在第一和第二外延 層的之間，其中所述的穩壓二極體位於從掩埋層到第一外 延層之間； ❹ ❹ 一個位於掩埋層上面的第二導電類型的源極區域，將掩埋 層連接到第二外延層上表面，其_在源極區域裏有缺口， 使得控向二極體對中的第_^個;控咸於第，〜 層與掩埋層之間，並與穩壓並且 另一個源極區域，使得控極二個控向二極 . 體形成於該另一源極畢域和所述雙層外延區之間。 23 .如申請專利範圍第22項中所述的暫態電壓抑制器（TVS) 裝置，其特徵在#，:::藝下面的第一導 電類型的:擊赛電壓觴^廣》h ❹ny 2 4 .如申請專利範圍第2 3項中電壓抑制器（TVS) 裝置，其特徵在於：所述的擊穿電壓觸發層有一個缺口， 觸發層並不在所述控向二極韹對中的第一個控向二極體下 面。 25 .如申請專利範圍第23項中所述的暫態電壓抑制器（TVS) 裝置，其特徵在於：所述的掩埋層有一個缺口，其中擊穿 電麈觸發層位於缺口中》 26 .如申請專利範圍第22項中所述的暫態電壓抑制器（TVS) 裝置，其特徵在於：第一導電類型為P型，第二導電類型 098132926 表單編號 A0101 第 23 頁/共 42 頁 0983394958-0 201015703 為N型，其中所述控向二極體對中的第一個控向二極體為 高端二極體，所述第二個控向二極體為低端二極體。 27 .如申請專利範圍第22項中所述的暫態電壓抑制器（TVS) 裝置，其特徵在於：保持雙層外延層的最少摻雜，以便在 所述控向二極體中獲得低電容，根據控向二極體的耗盡寬 度和正向電阻，來優化其中第一外延層的厚度和第二外延 層的厚度。 098132926 表單編號A0101The second epitaxial feature is further characterized by: obtaining a low junction capacitance by selecting a low doping concentration of an epitaxial layer; and satisfying the high-end and low-end steering by rejecting the thickness of the epitaxial layer The diode depletion and the low-end control diode V·'; tf Ο Θ 21 . The method of claim 20, characterized in that: the optimized transient voltage suppressor ( The step of the high-side and low-side steering diodes of the TVS) device further includes selecting the thickness of the epitaxial layer to avoid raising the high-end and low-side steering diodes Forward power 22 098132926 resistance. A transient voltage suppressor (TVS) device on a semiconductor substrate, comprising: a substrate of a first conductivity type having a double epitaxial layer grown on top of the substrate, the epitaxial layer comprising a substrate grown on the substrate a first outer form number of a first conductivity type A0101 page 22 / a total of 42 pages 0893394958-0 201015703 extended layer, and a second epitaxial layer of a first conductivity type grown on the first epitaxial layer; The longitudinally controlled dipole of the voltage stabilizing diode, wherein the pair of steering diodes comprises a height control dipole and a low end dipole Mb · m, a second conductivity type a heavily doped buried layer between the first and second epitaxial layers, wherein the stabilizing diode is located between the buried layer and the first epitaxial layer; ❹ ❹ a portion above the buried layer The source region of the second conductivity type connects the buried layer to the upper surface of the second epitaxial layer, and has a gap in the source region, so that the first to the opposite of the pair of diodes is controlled; Between the layer and the buried layer, and with voltage regulation and another The source regions are such that the two control dipoles of the gate are formed between the other source and the double epitaxial region. 23. A transient voltage suppressor (TVS) device as claimed in claim 22, characterized in that the first conductivity type under #::::Art: hitting voltage 觞^广》h ❹ny 2 4. The voltage suppressor (TVS) device of claim 23, wherein the breakdown voltage triggering layer has a gap, and the triggering layer is not in the pair of the steering diodes. A controllable diode below. 25. The transient voltage suppressor (TVS) device of claim 23, wherein the buried layer has a notch, wherein the breakdown trigger layer is located in the gap. 26 A transient voltage suppressor (TVS) device as claimed in claim 22, wherein the first conductivity type is P type, the second conductivity type is 098132926, form number A0101, page 23/42, 0893394958-0 201015703 is an N-type, wherein the first steering diode of the pair of steering diodes is a high-end diode, and the second steering diode is a low-end diode. 27. A transient voltage suppressor (TVS) device as claimed in claim 22, wherein: maintaining a minimum doping of the double epitaxial layer to achieve low capacitance in the steering diode The thickness of the first epitaxial layer and the thickness of the second epitaxial layer are optimized according to the depletion width and the forward resistance of the steering diode. 098132926 Form No. A0101 第24頁/共42頁Page 24 of 42 0983394958-00983394958-0
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