TW201011383A

TW201011383A - Active array substrate, liquid crystal dislay panel and method for manufacturing the liquid crystal dislay panel

Info

Publication number: TW201011383A
Application number: TW97135016A
Authority: TW
Inventors: Yung-Chih Chen; Chun-Hsin Liu; Po-Yuan Liu
Original assignee: Au Optronics Corp
Priority date: 2008-09-12
Filing date: 2008-09-12
Publication date: 2010-03-16
Also published as: TWI421568B

Abstract

An active array substrate, a liquid crystal display panel and method of manufacturing the same are provided. The active array substrate includes a base, a pixel array, an inner test circuit and an outer test branch line. The pixel array including a plurality of conductive lines is disposed on the base. The inner test circuit is electrically connected with a portion of the conductive lines. The outer test branch line is directly connected with the portion of the conductive lines.

Description

201011383 九、發明說明：【發明所屬之技術領域】本發明係關於-種主動陣列基板、液晶顯示面板及製造液晶顯示面板之方法。係特別關於一種應用於主動陣列基板之測試電路，可以提高測試能力以及減少測試時誤判的機率。、 ❹ 【先前技術】近年來因平面顯示器具有輕薄短小之優點，而廣為使用。一般而言，平面顯示器具有主動陣列基板主動陣列基=包括複數主動元件呈現陣列排列，主動元件係與對應的資料線、掃描線及畫素電極電性連接。〜欲顯示影像時，將資料訊號藉由資料線傳送至每一主動疋件’然後藉由掃描線傳送致能訊號給主動元件藉以開啟主動TL件將一列資料訊號傳送至一列晝素電極接下來關閉該列主動元件’之後開啟主動元件下一列主動元件， _重複此触至所有列狀址為止。然而’若有某些或某一列主動元件因線路瑕疵或元件不穩定之問題而未致'能，便會導致訊號傳送有問題，導致無法正常顯像，是故，藉由在平面顯示器製造過程中測試或修理瑕症線路或元件便可獲得產量之增加以及縮短整體製程時間。【發明内容】 201011383 鑑於前述，本發明的目可提高測觀力，•測試時=^_列基板，板動陣列基板，可==:車上述主動陣列基 ❹ 括提供-_母板，面板之方法’該方法包及外測被雷改、k母板具有彼此獨立之内測試電路以別第-以及第-7 M在形成液日日日層之步驟之前以及之後分以確热液日ί 程序’達到獨立且完整之測試目的， ^>1題：㈤^面板是否有顯*區⑽路之短職斷路之為，本&明之上述和其他目的特徵和優點能更明顯 ’域舉實施例’並配合所附圖式細說明如下0 籲【實施方式】第1圖為本發明之陣列母板。帛2八_2〇圖為本發明之策k液晶顯示面板之方法。 ^第1圖所示’陣列母板1〇包括基底1〇〇、畫素陣列一測試模組T1以及第二測試模組τ2。畫素陣列 »又置於该基底1〇〇上，晝素陣列1〇1包括複數導線以數晝素單元U。該些導線包括複數掃描線12以及複貝料線13 ’畫素單元u包括主動元件15以及畫素電極 201011383 14，母一主動元件ι5係與對應的掃描線a、資料線a以及畫素電極14電性連接。第一測試模組T1係與該些掃描線12電性連接，第一測試模組T1包括内測試電路13〇以及外測試電路丨4〇,須特別注意的是，外測試電路140係跟内測試電路13()獨立設置而藉由外測試分支線141與掃描線12直接連接。基底 1〇〇在位於内測試電路130以及外測試電路14〇之間的位 ❹置具有_線L’_以後續形成主動陣列基板之切割用。第二測試模組T2係與該些資料線13電性連接第二、J»式模、、·且Τ2包括内測试電路11 〇以及外測試電路1，須 =別注J的$ ’外測試電路120係跟内測試電路11〇獨2 設置而藉由外測試分支線121與資料線13直接連接。基底 100在位於内測試電路110以及外測試電路12〇之間二位置具^切割線L’係用以後續形成主動陣列基板之切割用。明參照第2A圖至第2D圖，係用以說明本發明製造液晶顯示面板之方法。 & 如第2A圖所示’提供一陣列母板10，陣列母板10 之構造如上述說明。藉由外測試電路12〇及/或外測試電路 140傳送至少—外測試訊號給該晝素陣列ι〇ι以執行一第 -測試程序，帛—測試料之作業將於之後詳細說明。接下來，如第2B圖所示，切割該陣列母板1〇外測試電路120、140之至少一部分脫離該晝素陣列^ 以形成主動陣列基板10,。其中該陣列母板1〇具有一切割線L位於該内測試電路11〇(13〇)以及該外測試電路 201011383 120(140)之間’其中該切割該陣列母板1〇以將該外測試電路120(140)之至少一部分脫離該晝素陣列1〇1之步驟係包括沿該切割線L切割該陣列母板1〇。主動陣列基板i〇,包括基底100、畫素陣列1〇1、内測試電路13〇、11〇以及外201011383 IX. Description of the Invention: [Technical Field] The present invention relates to an active array substrate, a liquid crystal display panel, and a method of manufacturing a liquid crystal display panel. In particular, a test circuit applied to an active array substrate can improve test capability and reduce the chance of misjudgment during testing. ❹ [Prior Art] In recent years, flat-panel displays have been widely used because of their advantages of lightness, thinness, and shortness. In general, a flat panel display has an active array substrate active array base = including a plurality of active components presenting an array arrangement, and the active component is electrically connected to corresponding data lines, scan lines, and pixel electrodes. ~ When the image is to be displayed, the data signal is transmitted to each active component through the data line. Then the active signal is transmitted to the active component by the scan line to enable the active TL device to transmit a column of data signals to a column of pixel electrodes. After the active element of the column is turned off, the next active component of the active component is turned on, and _ repeats the touch to all column addresses. However, if some or a certain set of active components are not enabled due to the problem of line defects or unstable components, it will cause problems in signal transmission, resulting in failure to display properly. Therefore, in the manufacturing process of flat panel displays. In the test or repair of snoring lines or components, you can increase the output and shorten the overall process time. SUMMARY OF THE INVENTION 201011383 In view of the foregoing, the object of the present invention can improve the viewing power, and the test substrate = ^_ column substrate, the plate array substrate, can be ==: the above-mentioned active array base of the vehicle includes -_ mother board, panel The method of the method and the external test is performed by the lightning correction, the k-mother board has independent test circuits, and the first and the -7 M are formed before and after the step of forming the liquid daily layer. ί The program 'achieves an independent and complete test purpose, ^>1: (5) ^The panel has a short-term break in the area of the *10 (10) road, and the above and other purpose features and advantages of this & The embodiment will be described in detail with reference to the accompanying drawings. FIG. 1 is an embodiment of the present invention. The 帛 2 八〇 diagram is a method of the present invention for a liquid crystal display panel. ^ Array mother board 1 shown in Fig. 1 includes a substrate 1 画, a pixel array, a test module T1, and a second test module τ2. The pixel array is again placed on the substrate 1 , and the pixel array 1〇1 includes a plurality of wires to count the unit U. The wires include a plurality of scan lines 12 and a double-shell line 13'. The pixel unit u includes an active element 15 and a pixel electrode 201011383 14. The mother-active element ι5 is associated with a corresponding scan line a, a data line a, and a pixel electrode. 14 electrical connection. The first test module T1 is electrically connected to the scan lines 12, and the first test module T1 includes an inner test circuit 13A and an outer test circuit 丨4〇. It should be specially noted that the outer test circuit 140 is followed by The test circuit 13() is independently provided and directly connected to the scan line 12 by the external test branch line 141. The substrate 1 is disposed between the inner test circuit 130 and the outer test circuit 14A with a _ line L'_ for subsequent formation of the active array substrate for cutting. The second test module T2 is electrically connected to the data lines 13 and the second, J»-mode, and the Τ2 includes the inner test circuit 11 〇 and the outer test circuit 1, and must be tested for the external test. The circuit 120 is connected to the internal test circuit 11 and is directly connected to the data line 13 by the external test branch line 121. The substrate 100 is disposed between the inner test circuit 110 and the outer test circuit 12A with a cutting line L' for subsequent cutting of the active array substrate. Referring to Figures 2A through 2D, there is shown a method for fabricating a liquid crystal display panel of the present invention. & An array of mother boards 10 is provided as shown in Fig. 2A, and the configuration of the array mother board 10 is as described above. At least the external test signal is transmitted to the pixel array ι〇ι by the external test circuit 12 and/or the external test circuit 140 to perform a first test procedure, and the operation of the test material will be described in detail later. Next, as shown in Fig. 2B, at least a portion of the outer test circuit 120, 140 of the array mother board 1 is detached from the pixel array to form the active array substrate 10. The array mother board 1 has a cutting line L between the inner test circuit 11 (13〇) and the outer test circuit 201011383 120 (140) 'where the array of the array board is cut to test the outer test The step of disengaging at least a portion of the circuit 120 (140) from the pixel array 1〇1 includes cutting the array mother board 1 along the cutting line L. The active array substrate i〇 includes a substrate 100, a pixel array 1, and an internal test circuit 13〇, 11〇 and

測試分支線14卜121。晝素陣列1〇1設置於該基底1〇〇上，畫素陣列包括複數導線以及複數晝素單元丨丨。該些導線包括複數掃描線12以及複數資料線13,晝素單元u包括主動元件15以及畫素電極14,每一主動元件15係與對應的掃描線12、資料線13以及畫素電極14電性連接。内測試電路110、130係分別與該複數資料線13以及複數掃描線 12電性連接。外測試分支線141、12丨係分別與該複數掃描線12以及該複數資料線13直接連接。須特別注意的是，外測試分支線141、121係與内測試電路11〇、13〇獨立嗖置而分別與對應的導線連接，所以在執行第—職程序或是之後的第二測試程序時，内測試電路uTest branch line 14 123. The pixel array 1〇1 is disposed on the substrate 1 , and the pixel array includes a plurality of wires and a plurality of pixel units. The wires include a plurality of scan lines 12 and a plurality of data lines 13. The unitary unit u includes an active element 15 and a pixel electrode 14, each active element 15 being electrically connected to a corresponding scan line 12, data line 13 and pixel electrode 14. Sexual connection. The inner test circuits 110 and 130 are electrically connected to the plurality of data lines 13 and the plurality of scan lines 12, respectively. The outer test branch lines 141, 12 are directly connected to the complex scan line 12 and the complex data line 13, respectively. It should be noted that the external test branch lines 141, 121 are separately connected to the internal test circuits 11A, 13A and are respectively connected to the corresponding wires, so when the first job program or the subsequent second test program is executed , internal test circuit u

電路12〇、H。並不，互相影響而獨立運作 '、二: 測試時誤判的機率。疋文便降低然後’如第2C圖所示，軸液晶層3〇於該主動陣列基板10以及-對向基板2〇之間，其中之内測試電路130被暴露出來。令乂丨刀敢後稽田叆円測試電路13〇傳送，畫素_以執行-第二測試程序:第^ 之作業將於之後詳細說明 H式程序便完成液晶顯示面板丨。，4 圖所示’ 201011383 第3A圖為本發明之第一測試模組之第一實施例。第 3B圖以及第3C圖分別為本發明之第—職模組沿剖面線 A-A’所繪製之第一例以及第二例剖面圖。第一測試模組丁1包括内測試電路130以及外測試電路 140 〇外測試電路140包括至少一外測試訊號線142以及外 ❹測試訊號模組140卜外測試訊號線I42係藉由外測試分支 ^⑷與該複數掃描、線12中之該部分直接連接外測試訊號模組1401係與該至少一外測試訊號線142電性連接。在經過切割該陣列母板1〇之步驟後，外測試分支線141會保留於主動陣列基板1〇,内。在進行第一測試程序時，外測試訊號係依序經由外測试汛號模組1401、外測試訊號線142以及外測試分支線141 傳送至掃描線12,以測試晝素陣列令之各元件是否正常運作。因為外測試電路140係與内測試電路13〇獨立設置’故在進行第一測試程序時，並不會受到内測試電路丨3〇的影響’也就是說’若内測試電路13〇内有瑕疵或是元件故障時’也不會影響到第一測試程序之運作。内測試電路130包括内測試閘極線131、内測試閘極訊號模組1301、複數測試開關135、複數内測試訊號線132 以及内測試訊號模組1302。内測試閘極訊號模組1301與該内測試閘極線131連接。測試開關135舉例而言係為N 型薄膜電晶體或是P型薄膜電晶體。測試開關135具有閘 201011383 極135a、源極135b以及汲極135c，測試開關135之閘極 135a係與該内測試閘極線131電性連接，該些測試開關135 之汲極135c係分別與該掃描線12對應連接，内測試訊號線132藉由内測試分支線133分別與該些測試開關135之源極135b對應連接。内測試閘極訊號模組1301包括閘極訊號墊1301a以及關閉訊號墊1301b。内測試訊號線132 係與内測試訊號模組1302連接。然而，也可依設計者需 ❺ 求’將内測試訊號模組1302以及外測試訊號模組1401整合為單一訊號源，也就是說，内測試訊號線132以及外測試訊號線142係連接至相同的訊號源，換句話說，内測試電路130與外測試分支線141並聯。在進行第二測試程序時，藉由該閘極訊號墊1301a傳送一開啟訊號給該些測試開關135，該開啟訊號之電壓約為20伏至30伏，然後或同時藉由該内測試訊號模組 1302、内測試訊號線132、内測試分支線133以及測試開關135將内測試訊號傳送至掃描線12，以測試晝素陣列101 ❹ 中之各元件是否正常運作。然後，藉由該關閉訊號塾1301b 傳送一關閉訊號給該些測試開關135，該關閉訊號之電壓約為-5伏至-ίο伏。經由形成液晶層之步驟前後分別藉由第一以及第二測試程序’可更加確保晝素陣列1〇1中之各元件以及線路之運作是否正常。請參考第3B圖，第3B圖為本發明之第一測試模組 T1沿第3A圖之剖面線A_A’所繪製之第一例。外測試訊號 201011383 線142以及内測試閘極線131可同時以相同導電材料形成在基^ 1〇〇上，絕緣層151係形成於外測試訊號線142、内測忒閘極線131以及基底1〇〇上，之後，可選擇性同時以相同導電材料將内測試訊號線132以及外測試分支線 141形成於絕緣層151上，然後，全面形成保護層ι52，接下來，去除部份保護層152以及部分絕緣層151以形成接觸洞hl、h2分別暴露出外測試訊號線142以及外測試分支 ❿線141，最後，形成導電層150於保護層152上以及接觸洞h卜h2内用以電性連接外測試訊號線142以及外測試分支線141。導電層15〇之材料舉例係為氧化銦或氧化鋅等透明導電材料，但並不侷限。請參考第3C圖，第3C圖為本發明之第一測試模組 T1沿第3A圖之剖面線A_A，所繪製之第二例。外測試訊號線142以及内測试閘極線131可同時以相同導電材料形成在基底100上，絕緣層151係形成於外測試訊號線142、内測试閘極線131以及基底100上，之後，去除部份絕緣 ❹ 層151以形成接觸洞h3暴露出部分外測試訊號線142，然後，可選擇性同時形成内測試訊號線132以及外測試分支線141於絕緣層ι51上，其中外測試分支線141係藉由接觸洞h3與外測試訊號線142電性連接，而内測試訊號線 132係不與外測試分支線141和外測試訊號線142連接，最後，全面形成保護層152。第4圖為本發明之第一測試模組之第二實施例。與第一測试模組之第一實施例不同的是，内測試訊號線以及外 201011383 測试mi说線均被分成奇偶兩組。外測試電路140包括外測試奇訊號線143、外測試偶訊號線144、以及外測試奇訊號墊1402以及外測試偶訊號墊 1403 。在進行第一測試程序時，外測試訊號係包括外測試奇訊號以及外測試偶訊號。外測試奇訊號係依序經由外測試奇訊號墊1402、外測試奇訊號線143以及外測試奇分支線 141a傳送至掃描線12a，以測試晝素陣列101中之各元件是否正常運作。外測試偶訊號係依序經由外測試偶訊號墊 1403、外測試偶訊號線丨44以及外測試偶分支線141b傳送至掃描線12b，以測試畫素陣列1〇1中之各元件是否正常運作。因為外測試電路140係與内測試電路130獨立設置，故在進行第一測試程序時，並不會受到内測試電路130的影響’也就是說，若内測試電路130内有瑕疵或是元件故障時’也不會影響到第一測試程序之運作。内測試電路130包括内測試閘極線131、内測試閘極訊號模組1301、複數測試開關135、複數内測試訊號線以及内測試訊號模組。内測試閘極訊號模組1301與該内測試閘極線131連接，測試開關135具有閘極135a、源極135b 以及汲極135c ’測試開關135之閘極135a係與該内測試閘極線131電性連接’該些測試開關I%之汲極135c係分別與該掃描線12a、12b對應連接。内測試訊號線包括内測試奇訊號線134以及内測試偶訊號線136，分別藉由内測 12 201011383 試奇分支線133a、内測試偶分支線133b與該些測試開關 135之源極135b對應連接。内測試閘極訊號模組13〇1包括閘極訊號墊1301a以及關閉訊號墊13〇lb。内測試訊號線132係與内測試訊號模組連接。内測試訊號模組包括内測試奇訊號墊1303以及内測試偶訊號墊丨3〇4。内測試奇訊號墊1303與該内測試奇訊號線134連接，内測試偶訊號墊1304與該内測試偶訊號線136連接，其中該内測試奇分 ❹ 支線133a以及内測試偶分支線133b係為交錯排列。在進行第二測試程序時’藉由該閘極訊號墊13〇1&傳送一開啟訊號給該些測試開關135，該開啟訊號之電壓約為20伏至30伏’然後或同時藉由該内測試奇訊號塾 1303、内測試奇訊號線134、内測試奇分支線133a以及測試開關135將内測試奇訊號傳送至掃描線12a，以測試畫素陣列101中之對應各奇數列之各元件是否正常運作。然後’藉由該關閉訊號墊1301b傳送一關閉訊號給該些測試開關135 ’該關閉訊號之電壓約為-5伏至-10伏。接下來， ❹ 藉由該閘極訊號墊1301a傳送一開啟訊號給該些測試開關 135 ’該開啟訊號之電壓約為20伏至30伏，然後或同時藉由該内測試偶訊號墊1304、内測試偶訊號線136、内測試偶分支線13 3 b以及測試開關13 5將内測試偶訊號傳送至掃描線12b’以測試畫素陣列101中之對應各偶數列之各元件是否正常運作。然後，藉由該關閉訊號墊1301b傳送— 關閉訊號給該些測試開關135 ’該關閉訊號之電壓約為_5 伏至-10伏。 13 201011383 經由形成液晶層之步驟前後分別藉由第一以及第二測試程序，可更加確保晝素陣列101中之各元件以及線路之運作是否正常。本發明之第二測試模組之構造可仿照本發明之第— 測試模組之第一實施例，其相異處僅第二測試模組係連接至資料線13,其餘運作原理及測試方式與本發明之第—測试模組之第一實施例相似，在此不贅述。 ❹ 第5圖為本發明之第二測試模組之另一例。如第5圖所不第二測試模組T2包括内測試電路11〇以及外測試電路 120。 ° 外測試電路120包括外測試紅色訊號線124、外測試綠色訊號線126、外測試藍色訊號線128、外測試訊號模組、外測試紅色分支線122R、外測試綠色分支線122G以及外測試藍色分支線122B。外測試訊號模組包括外測試紅色訊號墊1201R、外測試綠色訊號墊12〇1G以及外測試藍色訊號墊1201B，外測試紅色訊號墊12〇1R與該外測試紅 β 色訊號線124連接，外測試綠色訊號墊1201G與該外測試綠色訊號線126連接，外測試藍色訊號墊12〇丨8與該外測試藍色訊號線128連接，其中分別與該外測試紅色訊號線 124、該外測試綠色訊號線126以及與該外測試藍色訊號線 128連接之該些資料線13R、13G、13Β係為依序排列。 ^ 在進行另一第一測試程序時，外測試訊號係包括外測试紅色訊號、外測試綠色訊號以及外測試藍色訊號。外測试紅色訊號係依序經由外測試紅色訊號墊12〇1R、外測試 201011383 紅色訊號線124以及外測試紅色分支線122R傳送至資料線13R’以測試晝素陣列101中對應紅色之行之各元件是否正常運作。外測試綠色訊號係依序經由外測試綠色訊號塾1201G、外測試綠色訊號線126以及外測試綠色分支線 122G傳送至資料線13〇’以測試晝素陣列1〇1中對應綠色之行之各元件是否正常運作。外測試藍色訊號係依序經由外測試藍色訊號墊1201B、外測試藍色訊號線128以及外馨測試藍色分支線122B傳送至資料線13B，以測試晝素陣列101中對應綠色之行之各元件是否正常運作。因為外測試電路120係與内測試電路110獨立設置，進行此另一第一測試程序時，並不會受到内測試電路 _的影響’也就是說，若内測試電路110内有瑕疵或是几件故障時，也不會影響到此另一第一測試程序之運作。 ffr内剛試電路110包括内測試閘極線112、内測試閘極 U莫組11〇1、複數測試開關ill、複數内測試訊號線以 _ 間/則喊訊號模組。内測試閘極訊號模組1101與該内測試 ^ °線112連接’測試開關ηι具有閘極llla、源極lllb /及極111c，測試開關m之閘極nla係與該内測試 112電性連接，該些測試開關111之汲極111c係分包^亥貪料線13R、13G以及13B對應連接。内測試訊號線内Ί剛試紅色訊號線114、内測試綠色訊號線116以及 13= °式藍色訊號線118，分別藉由内測試紅色分支線 ΐ33β内剩試綠色分支線133G以及内測試藍色分支線，、該些測5式開關Π1之源極111 b對應連接。内測試 15 201011383 閘極訊號模組1101之構造以及運作原理與第一測試模組 T1之内測試閘極訊號模組13〇1類似，在此不贅述。内測 έ式sfL號模組包括内測試紅色訊號塾11 〇2R、内測試綠色訊號墊1102G以及内測試藍色訊號墊11〇2B。内測試紅色訊號塾1102R與邊内測試紅色訊號線114連接，内測試綠色訊號墊1102G與該内測試綠色訊號線116連接，内測試藍色訊號墊1102B與該内測試藍色訊號線118連接，其中該内測试紅色分支線133R、内測試綠色分支線U3G以及内測試藍色分支線133B係為依序交錯排列。在進行另一第二測試程序時，藉由該内測試閘極訊號模組1101傳送一開啟訊號給該些測試開關m，該開啟訊號之電壓約為20伏至30伏，然後或同時藉由該内測試紅色訊號塾1102R、内測試紅色訊號線114、内測試紅色分支線133R以及測試開關in將内測試紅色訊號傳送至資料線13R，以測試晝素陣列1〇ι中之對應各紅色行之各元件是否正常運作。然後，藉由該内測試閘極訊號模組1101 ❷ 傳送一關閉訊號給該些測試開關111，該關閉訊號之電壓約為-5伏至-10伏。接下來，藉由該内測試閘極訊號模組 1101傳送一開啟訊號給該些測試開關U1，該開啟訊號之電壓約為20伏至30伏，然後或同時藉由該内測試綠色訊號塾U02G、内測試綠色訊號線116、内測試綠色分支線 133G以及測試開關U1將内測試綠色訊號傳送至資料線 13G’以蜊試晝素陣列ι〇1中之對應各綠色行之各元件是否正常運作。然後，藉由該内測試閘極訊號模組11〇1傳送 ❹ ❿ 201011383 給該些測試_⑴，該關閉訊號之電㈣為租1101值、伏。然f吏同樣地’藉由該内測試閘極訊號模之電壓約開啟訊號給該些測試開關111，該開啟訊號 ====同時藉由該内測試藍色 t一、色汛谠線118、内測試藍色分支線13B，以二111 #_賴&訊號傳送至資料 =常=姆陣列1〇1中之對應各藍色行之各元件僖送一MPi 然後，藉由該内測試閘極訊號模組1101 約為：：該些測試開關111 ’該關閉訊號之電屢及成f晶層之步驟前後分別藉由此另一第一以 101 、 π色行之各元件以及線路之運作是否正常。上述開關7L件舉例係為薄膜電晶例為金屬導電材料，對向基板舉例為彩色係熟悉該領域人士所能輕易了解。似土本ί明之内外測試電路係為單獨設置，故可提高二LT則試時誤判的機率且可以測試顯示區内的試程序之後’外測試電路及其部分走線會切^卜几成測雖然本發明已以實施例揭露如上然其並之㈣領域中具有通常知識者，在不脫離本範圍内’當可作些許之更動與潤飾，因此本U之賴_當視後社巾請專利範_界定 17 201011383 準。【圖式簡單說明】第1圖係為本發明之陣列母板；第2A-2D圖為本發明之製造液晶顯示面板之方法；第3A圖為本發明之第一測試模組之第一實施例；第3B圖以及第3C圖分別為本發明之第一測試模組沿剖面線A - A ’所繪製之第一例以及第二例剖面圖；第4圖為本發明之第一測試模組之第二實施例；以及第5圖為本發明之第二測試模組之另一例。【主要元件符號說明】參 9 11 ο ο ο ο 1 IX 11 11 Ί1 110 1102R 1102G 1102B 111 111a 液晶顯不面板陣列母板主動陣列基板基底畫素陣列畫素單元内測試電路内測試紅色訊號墊内測試綠色訊號墊内測試藍色訊號墊測試開關閘極 18 201011383Circuit 12〇, H. No, interact independently and operate independently. 'II: The probability of misjudgment during testing. The text is lowered and then, as shown in Fig. 2C, the axial liquid crystal layer 3 is interposed between the active array substrate 10 and the opposite substrate 2, wherein the test circuit 130 is exposed.乂丨稽稽稽稽稽叆円叆円叆円稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽稽Figure 4 shows the first embodiment of the first test module of the present invention. 3B and 3C are respectively a first example and a second cross-sectional view of the first working module of the present invention taken along section line A-A'. The first test module 1 includes an inner test circuit 130 and an outer test circuit 140. The outer test circuit 140 includes at least one outer test signal line 142 and an outer test signal module 140. The outer test signal line I42 is externally tested. ^(4) The external test signal module 1401 is electrically connected to the at least one external test signal line 142 directly connected to the portion of the complex scan and line 12. After the step of cutting the array mother board, the outer test branch line 141 is retained in the active array substrate 1''. When the first test procedure is performed, the external test signal is sequentially transmitted to the scan line 12 via the external test squall module 1401, the outer test signal line 142, and the outer test branch line 141 to test the components of the enamel array. Is it working properly? Since the external test circuit 140 is independently set with the internal test circuit 13', when the first test program is performed, it is not affected by the internal test circuit '3〇, that is, if there is a flaw in the test circuit 13 Or when the component fails, it will not affect the operation of the first test program. The internal test circuit 130 includes an internal test gate line 131, an internal test gate signal module 1301, a plurality of test switches 135, a plurality of internal test signal lines 132, and an internal test signal module 1302. The inner test gate signal module 1301 is connected to the inner test gate line 131. The test switch 135 is exemplified by an N-type thin film transistor or a P-type thin film transistor. The test switch 135 has a gate 201011383 pole 135a, a source 135b and a drain 135c. The gate 135a of the test switch 135 is electrically connected to the inner test gate line 131. The drains 135c of the test switches 135 are respectively associated with the gate 135c. The scan lines 12 are connected in series, and the inner test signal lines 132 are respectively connected to the source electrodes 135b of the test switches 135 by the inner test branch lines 133. The inner test gate signal module 1301 includes a gate signal pad 1301a and a turn-off signal pad 1301b. The inner test signal line 132 is connected to the inner test signal module 1302. However, the internal test signal module 1302 and the external test signal module 1401 can be integrated into a single signal source, that is, the inner test signal line 132 and the outer test signal line 142 are connected to the same. The signal source, in other words, the inner test circuit 130 is connected in parallel with the outer test branch line 141. During the second test procedure, the gate signal pad 1301a transmits an enable signal to the test switches 135. The voltage of the turn-on signal is about 20 volts to 30 volts, and then or simultaneously by the internal test signal mode. The group 1302, the inner test signal line 132, the inner test branch line 133, and the test switch 135 transmit the internal test signal to the scan line 12 to test whether the components in the pixel array 101 are functioning properly. Then, the shutdown signal 塾1301b transmits a shutdown signal to the test switches 135, and the voltage of the shutdown signal is about -5 volts to - ί volts. Whether the operation of each element and the line in the pixel array 1〇1 is ensured by the first and second test procedures before and after the step of forming the liquid crystal layer, respectively. Please refer to FIG. 3B. FIG. 3B is a first example of the first test module T1 of the present invention taken along the section line A_A' of FIG. 3A. The external test signal 201011383 line 142 and the inner test gate line 131 can be simultaneously formed on the substrate with the same conductive material, and the insulating layer 151 is formed on the outer test signal line 142, the internal test gate line 131, and the substrate 1 Then, afterwards, the inner test signal line 132 and the outer test branch line 141 are selectively formed on the insulating layer 151 with the same conductive material, and then the protective layer ι52 is completely formed, and then the partial protective layer 152 is removed. And a portion of the insulating layer 151 to form the contact holes hl, h2 respectively exposing the outer test signal line 142 and the outer test branch line 141. Finally, the conductive layer 150 is formed on the protective layer 152 and in the contact hole hb h2 for electrical connection. The outer test signal line 142 and the outer test branch line 141. The material of the conductive layer 15 is exemplified by a transparent conductive material such as indium oxide or zinc oxide, but is not limited. Please refer to FIG. 3C. FIG. 3C is a second example of the first test module T1 of the present invention taken along the section line A_A of FIG. 3A. The outer test signal line 142 and the inner test gate line 131 can be simultaneously formed on the substrate 100 with the same conductive material. The insulating layer 151 is formed on the outer test signal line 142, the inner test gate line 131, and the substrate 100. The portion of the insulating layer 151 is removed to form a contact hole h3 to expose a portion of the outer test signal line 142. Then, the inner test signal line 132 and the outer test branch line 141 are selectively formed on the insulating layer ι51, wherein the outer test branch The line 141 is electrically connected to the external test signal line 142 through the contact hole h3, and the inner test signal line 132 is not connected to the outer test branch line 141 and the outer test signal line 142. Finally, the protective layer 152 is completely formed. Figure 4 is a second embodiment of the first test module of the present invention. Different from the first embodiment of the first test module, the inner test signal line and the outer 201011383 test mi line are divided into two groups of parity. The outer test circuit 140 includes an outer test odd signal line 143, an outer test even signal line 144, and an outer test odd signal pad 1402 and an outer test even signal pad 1403. When the first test procedure is performed, the external test signal includes an external test odd signal and an external test even signal. The external test odd signal is sequentially transmitted to the scan line 12a via the external test odd signal pad 1402, the outer test odd signal line 143, and the outer test odd branch line 141a to test whether the components in the pixel array 101 are operating normally. The external test even signal is sequentially transmitted to the scan line 12b via the external test even signal pad 1403, the external test even signal line 44 and the external test even branch line 141b to test whether the components in the pixel array 1〇1 are operating normally. . Since the external test circuit 140 is independently provided from the inner test circuit 130, it is not affected by the inner test circuit 130 when the first test program is performed. That is, if there is flaw or component failure in the inner test circuit 130. Time does not affect the operation of the first test program. The internal test circuit 130 includes an internal test gate line 131, an internal test gate signal module 1301, a plurality of test switches 135, a plurality of internal test signal lines, and an internal test signal module. The inner test gate signal module 1301 is connected to the inner test gate line 131. The test switch 135 has a gate 135a, a source 135b, and a drain 135c. The gate 135a of the test switch 135 and the inner test gate line 131. Electrically connected 'the test switches I% of the drain 135c are respectively connected to the scan lines 12a, 12b. The inner test signal line includes an inner test odd signal line 134 and an inner test even signal line 136, which are respectively connected to the source 135b of the test switches 135 by the internal test 12 201011383 test odd branch line 133a and the inner test even branch line 133b. . The inner test gate signal module 13〇1 includes a gate signal pad 1301a and a turn-off signal pad 13〇1b. The inner test signal line 132 is connected to the inner test signal module. The internal test signal module includes an inner test odd signal pad 1303 and an inner test even signal pad 3丨4. The inner test odd signal pad 1303 is connected to the inner test odd signal line 134, and the inner test even signal pad 1304 is connected to the inner test even signal line 136, wherein the inner test odd branch line 133a and the inner test even branch line 133b are Staggered. During the second test procedure, 'the gate signal pad 13〇1& transmits an enable signal to the test switches 135, the voltage of the turn-on signal is about 20 volts to 30 volts' and then simultaneously The test odd signal 塾 1303, the inner test odd signal line 134, the inner test odd branch line 133a, and the test switch 135 transmit the inner test odd signal to the scan line 12a to test whether each component of the corresponding odd column in the pixel array 101 is working normally. Then, by turning off the signal pad 1301b, a shutdown signal is sent to the test switches 135'. The voltage of the shutdown signal is about -5 volts to -10 volts. Next, 传送 transmitting an open signal to the test switches 135 by the gate signal pad 1301a, the voltage of the turn-on signal is about 20 volts to 30 volts, and then simultaneously testing the even signal pads 1304, The test even signal line 136, the inner test even branch line 13 3 b, and the test switch 13 5 transmit the inner test even signal to the scan line 12b' to test whether the components of the corresponding even columns in the pixel array 101 are functioning normally. Then, the off signal is transmitted to the test switches 135' by the off signal pad 1301b. The voltage of the off signal is about _5 volts to -10 volts. 13 201011383 By the first and second test procedures before and after the step of forming the liquid crystal layer, it is possible to further ensure the operation of each element and line in the pixel array 101. The second test module of the present invention is constructed in accordance with the first embodiment of the first test module of the present invention. The difference is that only the second test module is connected to the data line 13, and the remaining operating principles and test methods are The first embodiment of the first test module of the present invention is similar and will not be described herein. ❹ Figure 5 is another example of the second test module of the present invention. As shown in Fig. 5, the second test module T2 includes an inner test circuit 11A and an outer test circuit 120. ° The external test circuit 120 includes an external test red signal line 124, an external test green signal line 126, an external test blue signal line 128, an external test signal module, an external test red branch line 122R, an external test green branch line 122G, and an external test. Blue branch line 122B. The external test signal module includes an external test red signal pad 1201R, an external test green signal pad 12〇1G, and an external test blue signal pad 1201B. The external test red signal pad 12〇1R is connected to the external test red β color signal line 124. The external test green signal pad 1201G is connected to the external test green signal line 126, and the external test blue signal pad 12〇丨8 is connected to the external test blue signal line 128, wherein the external test red signal line 124 and the outer test respectively The test green signal line 126 and the data lines 13R, 13G, and 13 connected to the external test blue signal line 128 are sequentially arranged. ^ When performing another first test procedure, the external test signal includes an external test red signal, an external test green signal, and an external test blue signal. The external test red signal is sequentially transmitted to the data line 13R' via the external test red signal pad 12〇1R, the outer test 201011383 red signal line 124 and the outer test red branch line 122R to test the corresponding red line in the pixel array 101. Whether each component is working properly. The external test green signal is sequentially transmitted to the data line 13〇 via the external test green signal 塾1201G, the outer test green signal line 126, and the outer test green branch line 122G to test the corresponding green lines in the pixel array 1〇1. Whether the component is working properly. The external test blue signal is sequentially transmitted to the data line 13B via the external test blue signal pad 1201B, the external test blue signal line 128, and the externally tested blue branch line 122B to test the corresponding green line in the pixel array 101. Whether the components are working properly. Because the external test circuit 120 is independently set from the inner test circuit 110, when the other first test program is performed, it is not affected by the internal test circuit _ that is, if there is a flaw or a few in the inner test circuit 110 In the event of a failure, it will not affect the operation of this other first test procedure. The ffr inner test circuit 110 includes an inner test gate line 112, an inner test gate Um group 11〇1, a plurality of test switches ill, and a plurality of inner test signal lines with an _between/speak signal module. The inner test gate signal module 1101 is connected to the inner test ^ ° line 112. The test switch ηι has a gate 111la, a source 111b and a pole 111c, and the gate nla of the test switch m is electrically connected to the inner test 112. The bucks 111c of the test switches 111 are connected to each other by the packets 13R, 13G and 13B. In the inner test signal line, the red signal line 114, the inner test green signal line 116, and the 13=° blue signal line 118 are respectively tested by the inner test red branch line ΐ33β, the green branch line 133G and the inner test blue. The color branch line is connected to the source 111 b of the 5 type switch Π1. The internal test 15 201011383 The structure and operation principle of the gate signal module 1101 is similar to the test gate signal module 13〇1 in the first test module T1, and will not be described here. The internal test έsfL module includes an internal test red signal 塾11 〇2R, an internal test green signal pad 1102G, and an internal test blue signal pad 11〇2B. The inner test red signal 塾1102R is connected to the in-edge test red signal line 114, the inner test green signal pad 1102G is connected to the inner test green signal line 116, and the inner test blue signal pad 1102B is connected to the inner test blue signal line 118. The inner test red branch line 133R, the inner test green branch line U3G, and the inner test blue branch line 133B are sequentially staggered. During the second test procedure, the internal test gate signal module 1101 transmits an enable signal to the test switches m. The voltage of the turn-on signal is about 20 volts to 30 volts, and then simultaneously The inner test red signal 塾1102R, the inner test red signal line 114, the inner test red branch line 133R, and the test switch in transmit the inner test red signal to the data line 13R to test the corresponding red lines in the pixel array 1〇ι Whether the components are working properly. Then, the internal test gate signal module 1101 传送 transmits a shutdown signal to the test switches 111, and the voltage of the shutdown signal is about -5 volts to -10 volts. Next, the internal test gate signal module 1101 transmits an open signal to the test switches U1. The voltage of the turn-on signal is about 20 volts to 30 volts, and then the green signal 塾U02G is simultaneously tested by the inner test. The inner test green signal line 116, the inner test green branch line 133G, and the test switch U1 transmit the inner test green signal to the data line 13G' to test whether the components of the corresponding green lines in the pixel array ι〇1 are operating normally. . Then, the internal test gate signal module 11〇1 transmits ❹ ❿ 201011383 to the test _(1), and the power (4) of the shutdown signal is rented 1101 value, volt. However, the voltage is about to turn on the test switch 111 by the voltage of the internal test gate signal mode, and the turn-on signal ==== while the blue test t1 and the color line 118 are tested by the inner test. The inner test blue branch line 13B is sent to the data by the two 111 #_赖 & signal to the data = constant = the corresponding blue line of each of the arrays 1〇1, and then an MPi is sent, and then the inner test is performed. The gate signal module 1101 is about:: the test switches 111', the step of turning off the signal and the step of forming the f-layer are respectively carried out by the other first element of the 101, π color line and the line Is it working properly? The above-mentioned switch 7L is exemplified by a thin film electro-crystal, which is a metal conductive material, and the opposite substrate is exemplified by a color system which can be easily understood by those skilled in the art. Like the internal and external test circuit of the local limming, it can be set separately, so it can improve the probability of misjudgment when the two LTs are tested and can test the test procedure in the display area. 'The external test circuit and some of its traces will be cut. Although the present invention has been disclosed by way of example in the above-mentioned (4) field, it is possible to make a few changes and refinements without departing from the scope of the present invention. Fan_Definition 17 201011383 Standard. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an array mother board of the present invention; FIG. 2A-2D is a method for manufacturing a liquid crystal display panel of the present invention; FIG. 3A is a first embodiment of a first test module of the present invention; Example 3B and FIG. 3C are respectively a first example and a second example cross-sectional view taken along the section line A - A ' of the first test module of the present invention; FIG. 4 is the first test mode of the present invention; The second embodiment of the group; and the fifth figure is another example of the second test module of the present invention. [Main component symbol description] Ref. 9 11 ο ο ο ο 1 IX 11 11 Ί1 110 1102R 1102G 1102B 111 111a Liquid crystal display panel array mother board active array substrate base pixel array pixel unit test circuit test red signal pad Test green signal pad test blue signal pad test switch gate 18 201011383

lllb 111c 112 114 116 118 12、 12a、12b 120Lllb 111c 112 114 116 118 12, 12a, 12b 120

1201R1201R

1201G1201G

1201B 1211201B 121

122R122R

122G122G

122B 124 126 128 13、 13R、13G、13B 130 1301 1301a 1301b 1302 源極汲極内測試閘極線内測試紅色訊號線内測試綠色訊號線内測試藍色訊號線掃描線外測試電路外測試紅色訊號墊外測試綠色訊號墊外測試藍色訊號墊外測試分支線外測試紅色分支線外測試綠色分支線外測試藍色分支線外測試紅色訊號線外測試綠色訊號線外測試藍色訊號線資料線内測試電路内測試閘極訊號模組閘極訊號墊關閉訊號墊内測試訊號模組 19 201011383122B 124 126 128 13, 13R, 13G, 13B 130 1301 1301a 1301b 1302 Source Drain Test Gate In-Line Test Red Signal Line Test Green Signal Line Test Blue Signal Line Scan Line Test Outside Circuit Test Red Signal Outside the mat test green signal pad test blue signal pad outside test branch line test red branch line test green branch line test blue branch line test red signal line test green signal line test blue signal line data line In-test circuit test gate signal module gate signal pad off signal pad test signal module 19 201011383

131 内測試閘極線 132 内測試訊號線 133 内測試分支線 133a 内測試奇分支線 133b 内測試偶分支線 134 内測試奇訊號線 135 測試開關 135a 閘極 135b 源極 135c 汲極 136 内測試偶訊號線 14 晝素電極 140 外測試電路 1401 外測試訊號模組 1402 外測試奇訊號墊 1403 外測試偶訊號墊 141 外測試分支線 141a 外測試奇分支線 141b 外測試偶分支線 142 外測試訊號線 143 外測試奇訊號線 144 外測試偶訊號線 15 主動元件 150 導電層 20 201011383 151 絕緣層 152 保護層 20 對向基板 30 液晶層131 Inner test gate line 132 Test signal line 133 Test branch line 133a Test odd branch line 133b Test even branch line 134 Test odd signal line 135 Test switch 135a Gate 135b Source 135c Bungee 136 Test couple Signal line 14 Alizarin electrode 140 External test circuit 1401 External test signal module 1402 External test odd signal pad 1403 External test even signal pad 141 External test branch line 141a External test odd branch line 141b External test even branch line 142 External test signal line 143 External test odd signal line 144 External test even signal line 15 Active element 150 Conductive layer 20 201011383 151 Insulation layer 152 Protective layer 20 Counter substrate 30 Liquid crystal layer

21twenty one

Claims

201011383 十、申請專利範圍： 1. 一種主動陣列基板，包括：一基底； ’該晝素陣列包括複一晝素陣列，設置於該基底上數導線； -内測試電路’與崎數導線巾之―料導線電性連接；以及201011383 X. Patent application scope: 1. An active array substrate comprising: a substrate; 'The halogen array comprises a plurality of halogen arrays, a plurality of wires disposed on the substrate; - an inner test circuit' and a number of wire guides ―Electrical connection of the material wires;

外測試分支線’與該複數導線中之該部分導線直接連接。 2.如申明專利範圍第1項所述之主動陣列基板其中該内測試電料與該相m分支線並聯。如申請專利範圍第1項所述之主動陣列基板，其中該内測試電路包括：一内測試閘極線；内測試閘極訊號模組，與該内測試閘極線連接；複數測試開關，與該内測試閘極線電性連接，該些測試開關係分別與該複數導線中之—部分對應連接；至v —内測試訊號線，與該些測試開關連接；以及内測試訊號模組，與該内測試訊號線電性連接。 .如申凊專利範圍第3項所述之主動陣列基板，其中二導線包括複數掃描線以及複數資料線該内測試 22 以及The outer test branch line ' is directly connected to the portion of the plurality of wires. 2. The active array substrate of claim 1, wherein the inner test material is connected in parallel with the phase m branch line. The active array substrate according to claim 1, wherein the internal test circuit comprises: an inner test gate line; an inner test gate signal module connected to the inner test gate line; a plurality of test switches, and The inner test gate is electrically connected, and the test open relationship is respectively connected to a portion of the plurality of wires; to v, the inner test signal line is connected to the test switches; and the inner test signal module is The inner test signal line is electrically connected. The active array substrate according to claim 3, wherein the two wires comprise a plurality of scan lines and a plurality of data lines, wherein the inner test 22

201011383 電路係與該些掃描線電性連接。專利範圍第4項所述之主動陣列基板，其中二内測“號線包括—内測試奇訊號線以及一内測试偶訊號線，該内測試訊號模組包括：内測試奇訊餘’與勒_奇减線連接； -内測試偶訊’與勒賴偶訊號線連接 ^如申明專利範圍第3項所述之主動陣列基板，其中該些導線包括複數掃贿以及複數資料線，該内測試電路係與該些資料線電性連接。 7.如申請專利範圍第6項所述之主動陣列基板，其中 s亥些内測試訊號線包括一内測試紅色訊號線一内測試綠色訊號線以及一内測試藍色訊號線，該内測試訊號模組包括：一内測試紅色訊號墊，與該内測試紅色訊號線連接；一内測試綠色訊號墊’與該内測試綠色訊號線連接；以及一内測試藍色訊號墊，與該内測試藍色訊號線連接，其中分別與該内測試紅色訊號線、該内測試綠色訊號線以及與該内測試藍色訊號線連接之該些測 23 201011383 試開關係為依序排列。 8. 如申請專利範圍第1項所述之主動陣列基板，更括：另内測试電路，設置於該基底上，與該複數導線中之另一部分導線電性連接；以及一另一外測試分支線，與該複數導線中之該另一部魯分導線直接連接。 9. 如申請專利範圍第8項所述之主動陣列基板，其中該另一内測試電路係與該另一外測試分支線並聯。 10. —種液晶顯示面板，包括：如申請專利範圍第1項至第9項中任一項所述之主動陣列基板； 0 —對向基板；以及 —液晶層’設置於該主動陣列基板以及該對向基板之間。 U.—種製造液晶顯示面板之方法，包括：提供一陣列母板，該陣列母板包括：一基底；一晝素陣列，設置於該基底上，該畫素陣列包括複數導線；以及 24 201011383 一第一測試模組，設置於該基底上，與該畫素陣列電性連接，該第一測試模組包括：一内測試電路，與該複數導線中之一部分電性連接；以及一外測試電路，與該複數導線中之該部分直接連接；藉由該外測試電路傳送至少一外測試訊號給該畫素陣列以執行一第一測試程序； ® 切割該陣列母板以將該外測試電路之至少一部分脫離該晝素陣列以形成一主動陣列基板；形成一液晶層於該主動陣列基板以及一對向基板之間；以及藉由該内測試電路傳送至少一内測試訊號給該晝素陣列以執行一第二測試程序。 12. 如申請專利範圍第11項所述之方法，其中該陣列 Q 母板具有一切割線位於該内測試電路以及該外測試電路之間，其中該切割該陣列母板以將該外測試電路之至少一部分脫離該畫素陣列之步驟係包括沿該切割線切割該陣列母板。 13. 如申請專利範圍第11項所述之方法，其中該内測試電路包括：一内測試閘極線； 25 201011383 一内測試閘極訊號模組，與該内測試閘極線連接；複數測試開關，與該内測試閘極線電性連接，今些測試開關係分別與該複數導線中之一部分對應^ 接，複數内測試訊號線，分別與該些測試開關對應遠接；以及 …咬一内測試訊號模組，與該些内測試訊號線電性拉· 按，該方法更包括藉由該内測試閘極訊號模組傳送至少—關閉訊號給該些測試開關。、 M.如申請專利範圍第13項所述之方法，其中該内測試閘極訊號模組包括一閘極訊號墊以及一關閉訊號墊，該至少一關閉訊號係藉由該關閉訊號墊傳送給該些測試開關’該關閉訊號之電壓約為-5伏至-10伏。 15. 如申請專利範圍第13項所述之方法，其中該内測試閘極訊號模組包括一閘極訊號墊，該方法更包括藉由該閘極訊號墊傳送一開啟訊號給該些測試開關，該開啟訊號之電壓約為20伏至30伏。 16. 如申請專利範圍第13項所述之方法，其中該些導線包括複數掃描線以及複數資料線，該内測試電路係 26 201011383 與，些掃摇線t性連接’該些内測試訊號線包括—内測試奇訊號線以及—㈣試偶訊號線，舶測試模組包括： ~ 一内測試奇訊號墊，與該内測試奇訊號線連接；以及一偶測試奇訊號墊，與該内測試偶訊號線連接；其中該至少一内測試訊號包括至少一内測試奇訊號以及至少一内測試偶訊號，該至少一内測試奇訊號係藉由該内測試奇訊號線傳送至該畫素陣列，該至少一内測試偶訊號係藉由該内測試偶訊號線傳送至該畫素陣列。 17.如申請專利範圍第13項所述之方法，其中該些導線包括複數掃描線以及複數資料線’該内測試電路係與該些資料線電性連接，其中該些内測試訊號線包括一内測試紅色訊號線、一内測試綠色訊號線以及一内測試藍色訊號線，該内測試訊號模組包括：一内測試紅色訊號墊，與該内測試紅色訊號線連接；一内測試綠色訊號墊，與該内測試綠色訊號線連接；以及一内測試藍色訊號蟄，與該内測試藍色訊號線連接；其中該至少一内測試訊號包括至少一内測試紅 27 201011383 色訊號、至少—内測試綠色訊號以及至少一内測試藍色訊號’該至少—内測試紅色訊號係藉由該内測試紅色§fi號線傳送至該畫素陣列，該至少一内測試綠色訊號係藉由該内測試綠色訊號線傳送至該畫素陣列，該至少一内測試藍色訊號係藉由該内測試藍色訊號線傳送至該畫素陣列。 18.如申請專利範圍第n項所述之方法，其中該外測試電路包括：至少一外測試訊號線，與該複數導線中之該部分直接連接；以及一外測試訊號模組，與該至少一外測試訊號線電性連接；其中該些導線包括複數掃描線以及複數資料線’該外測試電路係與該些掃描線電性連接，該至少一外測，訊號線包括一外測試奇訊號線以及一外測試偶訊號線’該外測試訊號模組包括：一外測試奇訊號墊，與該外測試奇訊號線連接；以及一外測試偶訊號墊，與該外測試偶訊號線連接，其中該至少一外測試訊號包括至少一外測試奇訊號二及至少—外測試偶訊號’該至少一外測試奇訊號係藉由該外測試奇訊號線傳送至該畫素陣列，該至夕外測武偶紙號係藉由該外測試偶訊號線傳送至 28 201011383 該畫素陣列。 19.如申請專利範圍第11項所述之方法，其中該外測試電路包括：至少一外測試訊號線，與該些測試開關連接；以及一外測試訊號模組，與該至少一外測試訊號線電性連接；The 201011383 circuit is electrically connected to the scan lines. The active array substrate according to the fourth aspect of the patent, wherein the two internal measurement "number lines include - an inner test odd signal line and an inner test even signal line, and the inner test signal module comprises: an inner test odd signal" _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The test circuit is electrically connected to the data lines. 7. The active array substrate according to claim 6, wherein the inner test signal line includes an inner test red signal line and an inner test green signal line. The inner test signal module includes: an inner test red signal pad connected to the inner test red signal line; an inner test green signal pad 'connected to the inner test green signal line; and one The inner test blue signal pad is connected to the inner test blue signal line, wherein the inner test red signal line, the inner test green signal line and the inner test blue signal line respectively The test is connected to the test 23 201011383 The test open relationship is in order. 8. The active array substrate according to claim 1, further comprising: another test circuit disposed on the substrate, and the plurality of wires The other part of the plurality of wires is electrically connected; and the other outer test branch line is directly connected to the other of the plurality of wires. 9. The active array substrate according to claim 8 of the patent application, The other internal test circuit is connected in parallel with the other external test branch line. 10. A liquid crystal display panel, comprising: the active array substrate according to any one of claims 1 to 9; 0. an opposite substrate; and a liquid crystal layer disposed between the active array substrate and the opposite substrate. U. A method of manufacturing a liquid crystal display panel, comprising: providing an array mother board, the array mother board comprising: a substrate; a pixel array disposed on the substrate, the pixel array includes a plurality of wires; and 24 201011383 a first test module disposed on the substrate, and the pixel matrix The first test module includes: an inner test circuit electrically connected to one of the plurality of wires; and an outer test circuit directly connected to the portion of the plurality of wires; The test circuit transmits at least one external test signal to the pixel array to perform a first test procedure; cutting the array mother board to remove at least a portion of the external test circuit from the pixel array to form an active array substrate; forming a a liquid crystal layer between the active array substrate and the pair of substrates; and transmitting, by the internal test circuit, at least one internal test signal to the pixel array to perform a second test procedure. The method, wherein the array Q motherboard has a dicing line between the inner test circuit and the outer test circuit, wherein the arranging the array mother board to detach at least a portion of the outer test circuit from the pixel array The step includes cutting the array master along the cutting line. 13. The method of claim 11, wherein the internal test circuit comprises: an inner test gate line; 25 201011383 an inner test gate signal module connected to the inner test gate line; The switch is electrically connected to the inner test gate line, and the test open relationship is respectively connected to one of the plurality of wires, and the plurality of test signal lines are respectively connected to the test switches; and the bite is The internal test signal module is electrically connected to the internal test signal lines, and the method further includes transmitting at least the off signal to the test switches by the internal test gate signal module. The method of claim 13, wherein the internal test gate signal module comprises a gate signal pad and a turn-off signal pad, and the at least one off signal is transmitted to the off signal pad The test switches have a voltage of about -5 volts to -10 volts. 15. The method of claim 13, wherein the inner test gate signal module comprises a gate signal pad, the method further comprising transmitting an open signal to the test switches via the gate signal pad The voltage of the turn-on signal is about 20 volts to 30 volts. 16. The method of claim 13, wherein the wires comprise a plurality of scan lines and a plurality of data lines, the inner test circuit is 26 201011383 and the scan lines are t-connected with the inner test signal lines Including - testing the odd signal line and - (4) test signal line, the ship test module includes: ~ an inner test odd signal pad, connected with the inner test odd signal line; and an even test odd signal pad, and the inner test The at least one internal test signal includes at least one inner test odd signal and at least one inner test even signal, and the at least one inner test odd signal is transmitted to the pixel array by the inner test odd signal line. The at least one internal test even signal is transmitted to the pixel array by the internal test even signal line. 17. The method of claim 13, wherein the wires comprise a plurality of scan lines and a plurality of data lines, wherein the inner test circuit is electrically connected to the data lines, wherein the inner test signal lines comprise a The inner test red signal line, the inner test green signal line and the inner test blue signal line, the inner test signal module comprises: an inner test red signal pad connected to the inner test red signal line; an inner test green signal a pad connected to the inner test green signal line; and an inner test blue signal 蛰 connected to the inner test blue signal line; wherein the at least one inner test signal includes at least one inner test red 27 201011383 color signal, at least - The inner test green signal and the at least one inner test blue signal 'the at least one inner test red signal is transmitted to the pixel array by the inner test red §fi line, and the at least one inner test green signal is used by the inner signal Transmitting a green signal line to the pixel array, the at least one inner test blue signal being transmitted to the picture by the inner test blue signal line Prime array. 18. The method of claim n, wherein the external test circuit comprises: at least one external test signal line directly connected to the portion of the plurality of wires; and an external test signal module, and the at least An external test signal line is electrically connected; wherein the wires comprise a plurality of scan lines and a plurality of data lines, wherein the external test circuit is electrically connected to the scan lines, and the at least one external test, the signal line includes an external test odd signal The line and an external test signal line 'the external test signal module include: an external test odd signal pad connected to the external test odd signal line; and an external test even signal pad connected to the external test even signal line, The at least one external test signal includes at least one external test odd signal 2 and at least one outer test even signal number. The at least one external test odd signal is transmitted to the pixel array by the external test odd signal line, and the external signal is transmitted to the pixel array. The numerator paper number is transmitted to the pixel array by 28, 201011383 by the external test even signal line. 19. The method of claim 11, wherein the external test circuit comprises: at least one external test signal line connected to the test switches; and an external test signal module, and the at least one external test signal Wire electrical connection;

其中該些導線包括複數掃描線以及複數資料線’該外測試電路係與該些資料線電性連接，其中該些外測試訊號線包括一外測試紅色訊號線、一外測試綠色訊號線以及一外測試藍色訊號線，該外測試訊號模組包括：一外測試紅色訊號墊，與該外測試紅色訊號線連接，一外測試綠色訊號墊’與該外測試綠色訊號線連接；以及接，外測試藍色訊號墊，與該外測試藍色訊號線連 > f中该至少一外測試訊號包括至少一外測試紅色:1纟）—外測試綠色訊號以及至少-外測試藍 =線:二色訊號係藉由該外測試紅號係藉由該= 該至少—外測試綠色訊卜貝J试綠色矾號線傳送至該晝素陣列，該 29 201011383 至少一外測試藍色訊號係藉由該外測試藍色訊號線傳送至該畫素陣列。The wires include a plurality of scan lines and a plurality of data lines. The external test circuit is electrically connected to the data lines, wherein the external test signal lines comprise an external test red signal line, an external test green signal line, and a The external test signal module includes: an external test red signal pad connected to the external test red signal line, and an external test green signal pad 'connected to the external test green signal line; The external test blue signal pad is connected to the external test blue signal line. The at least one external test signal includes at least one external test red: 1纟) - the outer test green signal and at least the outer test blue = line: The two-color signal is transmitted to the pixel array by the external test red number by the = at least the outer test green signal, the green signal line, the 29 201011383 at least one external test blue signal The external test blue signal line is transmitted to the pixel array.

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