TW201007942A

TW201007942A - Carbon-based interface layer for a memory device and methods of forming the same

Info

Publication number: TW201007942A
Application number: TW98123088A
Authority: TW
Inventors: hui-wen Xu; April D Schricker; Er-Xuan Ping
Original assignee: Sandisk 3D Llc
Priority date: 2008-07-08
Filing date: 2009-07-08
Publication date: 2010-02-16

Abstract

In a first aspect, a memory cell is provided that includes (1) a first conductor; (2) a reversible resistance-switching element formed above the first conductor including (a) a carbon-based resistivity switching material; and (b) a carbon-based interface layer coupled to the carbon-based resistivity switching material; (3) a steering element formed above the first conductor; and (4) a second conductor formed above the reversible resistance-switching element and the steering element. Numerous other aspects are provided.

Description

201007942 六、發明說明：【發明所屬之技術領域】概言之本發明係關於用於半導體裝置中之碳基材料，且更特定而言係關於碳基介面材料及製程。201007942 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to carbon-based materials used in semiconductor devices, and more particularly to carbon-based interface materials and processes.

本申請案主張2009年5月13曰申請且名稱為「CARBON-BASED INTERFACE LAYER FOR A MEMORY DEVICE AND • METHODS OF FORMING THE SAME」之美國非臨時專利申請案第12/465,315號（檔案號為293)之優先權，且主張2008 # 年 7月 8 日申請且名稱為「CARBON-BASED INTERFACE LAYER FOR A MEMORY DEVICE AND METHODS OF FORMING THE SAME」之美國臨時專利申請案第61/078,911號（檔案號為 293P)之優先權，該等申請案中之每一者出於各種目的以全文引用之方式併入本文中。本申請案係關於2008年4月11曰申請且名稱為「DAMASCENE INTEGRATION METHODS FOR GRAPHITIC FILMS IN THREE-DIMENSIONAL MEMORIES AND MEMORIES ® FORMED THEREFROM」之美國臨時專利申請案第61/044,352 號（檔案號為247P)，該案出於各種目的以全文引用之方式 - 併入本文中。本申請案係關於以下2008年7月8曰申請且名稱為「CARBON-BASED RESISTIVITY-SWITCHING MATERIALS AND METHODS OF FORMING THE SAME」之共同讓與美國專利申請案美國臨時專利申請案第61/078,924號（檔案號為 294P)，該案出於各種目的以全文引用之方式併入本文中。 141458.doc 201007942 【先前技術】已知非揮發性記憶體由可逆電阻切換元件形成。舉例而言，以下美國專利申請案闡述一種包含與一可逆電阻率切換材料（例如，一金屬氧化物或金屬氮化物）串聯耦合之一二極體之三維可再寫非揮發性記憶體單元：2005年5月9曰申請且名稱為「REWRITEABLE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL」之美國專利申請案第1 1/125,939號，該案出於各種目的以全文引用之方式併入本文中。亦已知某些碳基膜可展示可逆電阻率切換性質，從而使得此等膜成為一三維記憶體陣列内整合之候選者。然而，在記憶體裝置中整合碳基電阻率切換材料係困難的；且形成採用碳基可逆電阻率切換材料之記憶體裝置之經改良方法係期望的。【發明内容】在本發明之某些實施例中，提供一種記憶體單元，其包含：（1)一第一導體；（2)形成於該第一導體上方之一可逆電阻切換元件，其包含：（a) —碳基電阻率切換材料；及 (b)耦合至該碳基電阻率切換材料之一碳基介面層；（3)形成於該第一導體上方之一引導元件；及（4)形成於該可逆電阻切換元件及該引導元件上方之一第二導體。在本發明之其他實施例中，提供一種設備，其包含： (1)一碳基介面層；及（2)毗鄰該碳基介面層之一碳基電阻率切換材料。該碳基介面層比該碳基電阻率切換材料稠 141458.doc 201007942 密。在本發明之其他實施例中，提供一種設備，其包含： (1)一第一碳基介面層；及毗鄰該第一碳基介面層之一碳基電阻率切換材料。該第一碳基介面層包括經氮化碳基材料。 . 在本發明之又其他實施例中，提供一種形成一記憶體單兀之方法，該方法包含：在一基板上方形成一第一導體，（2)在該第一導體上方形成一碳基介面層；（3)毗鄰該炭基；丨面層形成一碳基電阻率切換材料；且（4)在該碳基介面層及該碳基電阻率切換材料上方形成一第二導體。提供眾多其他態樣。依據以下詳細說明、隨附申請專利範圍及附圖，本發明之其他特徵及態樣將變得更加顯而易見。【實施方式】 *包含（但不限於）含有微晶或其他石墨烯區域之非晶形 • 碳、石墨烯、碳奈米管（CNT)、其他石墨碳膜等等之某些碳基膜可展示可逆電阻率切換性質，從而使得此等膜成為三維記憶體陣列内整合之候選者、然而，將碳基電阻率換（C基切換」）材料成功地用作可逆電阻可切換元件 <-挑戰係在-C基切換材料與__鄰膜(例如通、、 W等等）之間可發生脫層及㈤_。另—困難係1比鄰膜可不期望地滲透一多孔c基切換材料，例如一 cnt層(例如，橫跨C基切換材料形成一短路）。本發明提供改良C基切換材料與可用於一非揮發性記憶 141458.doc 201007942 體陣列中之其他膜之間的黏合之c基介面層。此c基介面層除充當黏合層之外，在某些實施例中可用作密封多孔C 基切換材料（例如，CNT切換材料）之覆蓋層。This application claims the United States non-provisional patent application No. 12/465,315 (file number 293), filed on May 13, 2009, entitled "CARBON-BASED INTERFACE LAYER FOR A MEMORY DEVICE AND • METHODS OF FORMING THE SAME" Priority US Patent Application No. 61/078,911, filed on July 8, 2008, entitled "CARBON-BASED INTERFACE LAYER FOR A MEMORY DEVICE AND METHODS OF FORMING THE SAME" (Archive No. 293P) The priority of each of these applications is hereby incorporated by reference in its entirety for all purposes. This application is related to U.S. Provisional Patent Application No. 61/044,352 (file number 247P) filed on Apr. 11, 2008, entitled "DAMASCENE INTEGRATION METHODS FOR GRAPHITIC FILMS IN THREE-DIMENSIONAL MEMORIES AND MEMORIES ® FORMED THEREFROM" This case is hereby incorporated by reference in its entirety for all purposes. This application is related to the following U.S. Patent Application Serial No. 61/078,924, entitled "CARBON-BASED RESISTIVITY-SWITCHING MATERIALS AND METHODS OF FORMING THE SAME", filed on July 8, 2008. The file number is 294P), which is hereby incorporated by reference in its entirety for all purposes. 141458.doc 201007942 [Prior Art] Non-volatile memory is known to be formed by a reversible resistance-switching element. For example, the following U.S. Patent Application describes a three-dimensional rewritable non-volatile memory cell comprising a diode coupled in series with a reversible resistivity switching material (e.g., a metal oxide or metal nitride): U.S. Patent Application Serial No. 1 1/125,939, filed on May 29, 2005, which is hereby incorporated by reference in its entirety in its entirety in in. It is also known that certain carbon-based films exhibit reversible resistivity switching properties, making these films candidates for integration within a three-dimensional memory array. However, it is difficult to integrate a carbon-based resistivity switching material in a memory device; and an improved method of forming a memory device using a carbon-based reversible resistivity switching material is desired. SUMMARY OF THE INVENTION In some embodiments of the present invention, a memory unit is provided, comprising: (1) a first conductor; (2) a reversible resistance-switching element formed over the first conductor, comprising (a) a carbon-based resistivity switching material; and (b) a carbon-based interface layer coupled to the carbon-based resistivity switching material; (3) a guiding element formed over the first conductor; and (4) a second conductor formed on the reversible resistance-switching element and above the guiding element. In other embodiments of the invention, an apparatus is provided comprising: (1) a carbon-based interface layer; and (2) a carbon-based resistivity switching material adjacent to the carbon-based interface layer. The carbon-based interface layer is denser than the carbon-based resistivity switching material 141458.doc 201007942. In other embodiments of the present invention, an apparatus is provided comprising: (1) a first carbon-based interface layer; and a carbon-based resistivity switching material adjacent to the first carbon-based interface layer. The first carbon-based interface layer comprises a carbon nitride-based material. In still another embodiment of the present invention, a method of forming a memory cell is provided, the method comprising: forming a first conductor over a substrate, and (2) forming a carbon-based interface over the first conductor a layer; (3) adjacent to the carbon base; a tantalum layer forming a carbon-based resistivity switching material; and (4) forming a second conductor over the carbon-based interface layer and the carbon-based resistivity switching material. There are many other aspects to offer. Other features and aspects of the present invention will become more apparent from the detailed description of the appended claims. [Embodiment] * Some carbon-based films including, but not limited to, amorphous carbon, graphene, carbon nanotubes (CNT), other graphite carbon films, etc. containing crystallites or other graphene regions can be exhibited. Reversible resistivity switching properties, making these films a candidate for integration within a three-dimensional memory array, however, a carbon-based resistivity-switched (C-based switching) material has been successfully used as a reversible resistance switchable element<-challenge The delamination and (5) _ may occur between the -C based switching material and the __ adjacent film (eg, pass, W, etc.). Alternatively, the 1 matrix film may undesirably penetrate a porous c-based switching material, such as a cnt layer (e.g., forming a short across the C-based switching material). The present invention provides a c-based interface layer that improves the adhesion of a C-based switching material to other films that can be used in a non-volatile memory 141458.doc 201007942 body array. In addition to acting as an adhesion layer, this c-based interface layer can be used as a cover layer for sealing porous C-based switching materials (e.g., CNT switching materials) in certain embodiments.

例如非晶形碳膜之C基材料主要展示兩種鍵結結構sp2及 sp3。一 sp3鍵結結構具有比一較平坦三角形sp2鍵結結構更有利於與其他材料層鍵結之一四面體形狀。因此，在本發明之某些實施例中，一 C基介面層具有一增加之sp3鍵濃度 (相對於C基介面層充當其一介面層之c基切換材料）。舉例而言’可在一導電層（例如TiN ' TaN、W、WN、Mo等等）與一 C基切換材料之間採用一富含sp3之c基介面層以改良該C基切換材料與該導電層之間的黏合。如下文進-步所闡述，在某些實施例中，可使用電浆增強化學氣相沈積（PECVD)形成c基士刀換材料及C基介面層兩者。為形成-C基介面層，在膜形成期間可降低製程溫度及/或可增加電漿離子化以增加所得膜之sp3濃度。亦可使For example, a C-based material of an amorphous carbon film mainly exhibits two bonding structures sp2 and sp3. A sp3 bond structure has a tetrahedral shape that is more advantageous for bonding with other material layers than a flatter sp2 bond structure. Thus, in certain embodiments of the present invention, a C-based interface layer has an increased sp3 bond concentration (a c-based switching material that acts as an interface layer for the C-based interface layer). For example, an sp3-containing c-based interfacial layer may be employed between a conductive layer (eg, TiN 'TaN, W, WN, Mo, etc.) and a C-based switching material to improve the C-based switching material and Bonding between conductive layers. As explained further below, in some embodiments, plasma enhanced chemical vapor deposition (PECVD) can be used to form both the c-base knife replacement material and the C-based interface layer. To form a -C based interfacial layer, the process temperature can be lowered during film formation and/or plasma ionization can be increased to increase the sp3 concentration of the resulting film. Can also make

用其他C基切換及/或黏合材料形成製程（例如，熱⑽、低壓C VD、低大氣壓C VD，等等）。，、已發現增加—C基膜之密度可改良該膜與其他材料（例. :電層)之黏合。在某些實施財，相對於-C基介面層; :至其之C基切換材料，該C基介面層形成有一增力… 度。如下文進一步闌述’藉由在層形成期間增加表面離: 基層形成期間之沈積速率可增加層密度。一-:::層：沈積速率之減小可因C基介面的則體之稀釋及/或因氦、氬1、氪或另—惰性物= 141458.doc -6 · 201007942 立曰加之離子森擊而發生。舉例而言，可藉由增加載體氣體濃度（例如，氬、氦、氪、氙或另一惰性氣體濃度）以便產生更多離子物質來增加離子轟擊。另外或或者’可採用一基板偏壓及/或低^ 率RF來增加離子轟擊。亦可增加高頻率汉？功率。注意，降低製程溫度來增加sp3濃度可降低膜之密度。因此，可採用減少沈積速率及/或增加表面離子轟擊來增加膜之密度以補償用來增加sp3濃度之減少的製程溫度。Processes are formed using other C-based switching and/or bonding materials (eg, heat (10), low pressure C VD, low atmospheric pressure C VD, etc.). It has been found that increasing the density of the C-based film improves the adhesion of the film to other materials (eg, electrical layers). In some implementations, the C-based interface layer is formed with a boosting force relative to the -C based interface layer; to its C-based switching material. As will be further described below, the layer density can be increased by increasing the surface separation during layer formation: the deposition rate during formation of the base layer. One-::: layer: the decrease in deposition rate may be due to the dilution of the C-based interface and/or due to helium, argon, helium or another inert substance = 141458.doc -6 · 201007942 Hit it. For example, ion bombardment can be increased by increasing the carrier gas concentration (e.g., argon, helium, neon, xenon, or another inert gas concentration) to produce more ionic species. Additionally or alternatively, a substrate bias and/or low RF can be used to increase ion bombardment. Can also increase the high frequency of Han? power. Note that lowering the process temperature to increase the sp3 concentration reduces the density of the film. Thus, reducing the deposition rate and/or increasing surface ion bombardment can be used to increase the density of the film to compensate for the process temperature used to increase the decrease in sp3 concentration.

在本發明之另一實施例中，可藉助一藉由氮化一c基材料層而形成之C基介面層來改良一c基切換層與另一層（例如導電或介電層）之間的黏合。可氮化一 C基切換層自身之一部分以形成該C基介面層，或可氮化毗鄰該C基切換層之一單獨c基材料層以形成該C基介面層。舉例而言，可藉由在一升高之溫度下將C基材料層曝露於沁或任何其他含N氣體（NH3、N2〇或類似氣體），藉由在一PECVD 至中進行電漿氮化或藉由類似方法（下文所述）來氮化一 c 基材料層。類似地，為改良一C基切換層與一下伏金屬層之黏合，可在金屬層上方沈積C基材料之前使用乂或任何其他含N氣體來氮化該下伏金屬層。In another embodiment of the present invention, a C-based switching layer formed by nitriding a c-based material layer can be used to improve between a c-based switching layer and another layer (eg, a conductive or dielectric layer). Bonding. A C-based switching layer may be nitrided to form the C-based interposer layer, or a single c-based material layer adjacent to the C-based switching layer may be nitrided to form the C-based interfacial layer. For example, by exposing the C-based material layer to germanium or any other N-containing gas (NH3, N2, or the like) at an elevated temperature, by plasma nitridation in a PECVD to A layer of c-based material is nitrided by a similar method (described below). Similarly, to improve adhesion of a C-based switching layer to a underlying metal layer, the underlying metal layer can be nitrided using germanium or any other N-containing gas prior to depositing the C-based material over the metal layer.

在本發明之一個或多個實施例中，上述C基介面層亦可充*夕孔C基切換材料之覆蓋層。舉例而言，一所沈積或生長之CNT材料層通常具有一粗糙表面形貌，其具有顯著的厚度變化，例如眾多峰及毂。此一 CNT層亦可係如比多孔以至於在該CNT層上直接沈積一導電層可透過整個CNT 141458.doc 201007942 層形成一短路。h°le在—些實施财，已觀測到金屬直接沈積至CNT孔洞中，此可在CNT膜中形成—小孔。在其他實施例中，可能在用於裝置製造之較高能量或溫度處理期間，金屬可在CNT之間遷移穿過CNT膜。為克服此等潛在問題，在本發明之一個或多個實施例中，可在一多孔C基切換材料上方形成一導電層之前在該 C基切換材料上方形成一介面層（例如非晶形碳）以覆蓋該多孔c基切換材料。此一c基介面（覆蓋）層在後續熱製程中可係稠密且穩定的（例如，由於後續熱處理，碳或其他材料遷移/擴散穿過C基介面/覆蓋層及/或多孔c基切換層係In one or more embodiments of the present invention, the C-based interface layer may also be a capping layer of a C-switching material. For example, a deposited or grown CNT material layer typically has a rough surface topography with significant thickness variations, such as numerous peaks and hubs. The CNT layer may also be such as to be more porous than to deposit a conductive layer directly on the CNT layer to form a short circuit through the entire CNT 141458.doc 201007942 layer. H°le has been observed to deposit directly into the CNT pores, which can form small pores in the CNT film. In other embodiments, metals may migrate through the CNT film between the CNTs during higher energy or temperature processing for device fabrication. To overcome such potential problems, in one or more embodiments of the invention, an interfacial layer (eg, amorphous carbon) may be formed over the C-based switching material prior to forming a conductive layer over a porous C-based switching material. ) to cover the porous c-based switching material. The c-based interface (cover) layer can be dense and stable during subsequent thermal processes (eg, carbon or other material migration/diffusion through the C-based interface/cover layer and/or porous c-based switching layer due to subsequent heat treatment) system

最小）。不同於某些金屬層，C基介面/覆蓋層將不與多孔C 基切換層（例如，一CNT層）進行反應及/或另外負面地影響該多孔c基切換層。此一c基介面/覆蓋層亦可改良c基切換材料與導電層之間的黏合。前述〇基介面層中之任一者可充當此一覆蓋層。實例性裝置結構Minimal). Unlike certain metal layers, the C-based interface/cover layer will not react with the porous C-based switching layer (e.g., a CNT layer) and/or otherwise negatively affect the porous c-based switching layer. This c-based interface/cover layer also improves the adhesion between the c-based switching material and the conductive layer. Any of the aforementioned thiol interface layers can serve as such a cover layer. Example device structure

在本發明之某些實施例中，可將薄C基膜與一引導元件 (例如一（垂直）二極體或一薄膜電晶體（TFT))串聯整合以形成一可再寫記憶體裝置。為達成此，可在一金屬_絕緣體_ 金屬（MIM)平面堆疊中之兩個金屬層或其他導體之間形成一碳基切換材料，例如一含有微晶石墨烯之非晶形碳膜、碳奈米管膜、另一石墨碳膜，或類似膜。可將此一 MIM 堆疊與一（垂直）二極體或其他引導元件串聯放置以形成一可再寫記憶體裝置。 14J458.doc 201007942 圖1係根據本發明所形成之一實例性記憶體單元100之一剖視圖。參考圖1，一第一軌導體102形成於一基板（未顯示）上方。舉例而言，第一導體102可包含具有或不具有一 TiN、TaN、WN或其他黏合/障壁層106之一鎢層或其他導電層104。例如一經沈積多晶矽或其他多晶半導體二極體之一垂直P-I-N或N-I-P二極體108形成於第一軌導體102上方。一TiN、WN、TaN或其他黏合/障壁層110形成於二極體108上方。黏合/障壁層110可充當一金屬-絕緣體-金屬 (MIM)堆疊111之一底部電極。在某些實施例中，與二極體108接觸地形成一矽化物區域（未顯示）。如第7,176,064號美國專利「MEMORY CELL COMPRISING A SEMICONDUCTOR JUNCTION DIODE CRYSTALLIZED ADJACENT TO A SILICIDE」中所闡述，在退火期間矽化物形成材料（例如鈦及鈷）與經沈橫矽反應以形成一矽化物層，該專利出於各種目的以全文引用之方式併入本文中。矽化鈦及矽化鈷之晶格間距接近矽之晶格間距，且此等矽化物層顯示可在經沈積矽結晶時充當用於毗鄰該經沈積矽之「結晶模板」或「晶種」（例如，一矽化物層在退火期間可增強二極體108之晶體結構）。藉此提供較低電阻率之矽。對於矽鍺合金及/或鍺二極體而言，可達成類似結果。In some embodiments of the invention, a thin C base film can be integrated in series with a guiding element (e.g., a (vertical) diode or a thin film transistor (TFT)) to form a rewritable memory device. To achieve this, a carbon-based switching material can be formed between two metal layers or other conductors in a metal-insulator-metal (MIM) planar stack, such as an amorphous carbon film containing microcrystalline graphene, carbon nano Rice tubular membrane, another graphite carbon membrane, or similar membrane. This MIM stack can be placed in series with a (vertical) diode or other guiding element to form a rewritable memory device. 14J458.doc 201007942 Figure 1 is a cross-sectional view of one exemplary memory cell 100 formed in accordance with the present invention. Referring to Figure 1, a first rail conductor 102 is formed over a substrate (not shown). For example, the first conductor 102 can comprise a tungsten layer or other conductive layer 104 with or without a TiN, TaN, WN or other bonding/barrier layer 106. For example, a vertical P-I-N or N-I-P diode 108, one of deposited polysilicon or other polycrystalline semiconductor diodes, is formed over the first rail conductor 102. A TiN, WN, TaN or other bonding/barrier layer 110 is formed over the diode 108. The bond/barrier layer 110 can serve as a bottom electrode of a metal-insulator-metal (MIM) stack 111. In some embodiments, a germanide region (not shown) is formed in contact with the diode 108. As described in U.S. Patent No. 7,176,064, "MEMORY CELL COMPRISING A SEMICONDUCTOR JUNCTION DIODE CRYSTALLIZED ADJACENT TO A SILICIDE", a telluride-forming material (e.g., titanium and cobalt) reacts with a precipitated yttrium to form a vaporized layer during annealing. This patent is hereby incorporated by reference in its entirety for all purposes. The lattice spacing of titanium telluride and cobalt telluride is close to the lattice spacing of germanium, and such germanide layers are shown to act as "crystallization templates" or "seeds" adjacent to the deposited germanium during deposition of germanium crystals (eg, A germanide layer enhances the crystal structure of the diode 108 during annealing. This provides the advantage of lower resistivity. Similar results can be achieved for tantalum alloys and/or tantalum diodes.

在某些實施例中，一金屬硬遮罩（未顯示）形成於二極體 108上方。舉例而言，金屬硬遮罩之使用闡述於2006年5月 13 日申請且名稱為「CONDUCTIVE HARD MASK TO PROTECT 141458.doc -9- 201007942 patterned FEATURES DU職G TRENCH ETCH」之美國專利申請案第ll/444,936號（下文稱為「，936申請案」）中，該案出於各種目的以全文引用之方式併入本文中。在一個實施射，根據本發明之一第一C基介面層112形成於黏合/障壁層110上方以改良黏合/障壁層11〇與—欲形成（下文所述）之C基切換材料之間的黏合。第一c基介面層 112可具有如先前所述之一增加的邛3鍵濃度、一增加的密度、一經氮化區域或類似物中之一者或多者。例如石墨烯、含有微晶石墨烯之非晶形碳、碳奈米管 (CNT)、其他石墨碳等等之一c基切換材料114形成於第— C基介面層H2上方。可藉由任一適合技術沈積及/或生長c 基切換材料114，例如化學氣相沈積（CVD)、高密度電漿 (HDP)沈積、電漿增強CVD、自一非晶形或石墨目標之濺射沈積、一旋塗製程、晶種生長等等❶在某些實施例中，可採用沈積後處理（例如在降低之壓力或氧環境中進行退火）以影響或另外改良C基切換材料114之性質。根據本發明之一第二C基介面層116形成於c基切換材料 114上方。第二c基介面層116可與第一 c基介面層Π2相同或不同。第一C基介面層112、C基切換材料114及第二C基介面層116可充當MIM堆疊111之一絕緣部分。其後’在上部C基介面層116上方形成一頂部導體118。舉例而言，頂部導體11 8可包含具有或不具有一 TiN、 WN、TaN或其他黏合/障壁層122之一鎢層或其他導電層 120。頂部導體11 8之一部分（例如黏合/障壁層丨22)可用作 141458.doc • 10· 201007942 MIM堆疊111之一頂部電極。注意，在某些實施例中，二極體108可定位於C基切換材料114上方。舉例而言，導電層104、120可包括約200至約2500埃之鎢。可使用其他導電層材料及/或厚度。舉例而言，黏合層106、11〇、122可包括約20至約500埃且較佳約1〇〇埃之氮化鈦或另一適合黏合層（例如氮化钽、氮化鎢、一個或多個黏合層之組合，或類似層）。可採用其他黏合層材料及/或厚度。導體102、118之實例性寬度及/或導體之間的間距之範圍係自約200至約2500埃，但可使用其他導體寬度及/或間距。. 在一個或多個實施例中’第一 C基介面層112及/或第二C 基介面層116可具有一約為2至約500埃之厚度，更佳約為2 至約50埃且仍更佳約為10至約20埃。c基切換材料114可具有一約為1至約2000埃且更佳約為2至約1000埃之厚度。其他厚度範圍亦可用於此等層。在某些實施例中，可以一低速率沈積c基切換材料114以使得僅沈積數個原子層（例如，在某些實施例中大約為2〇個層，但可使用較多或較少層）以形成石墨材料中典型之諸多sp2碳-碳兀鍵。在約4〇〇t至約9〇〇tt溫度下，較佳在低於大約55CTC且更佳在低於大約45〇t自氫及一碳源（例如qH2、QH6等等）之一混合物進行一電漿輔助分解及沈積可用來最小化其他裝置層之總曝露溫度及時間。若干實例性PECVD室可從市場上購得，但可使用任一適： PECVD 室。 141458.doc 201007942 可在具有或不具有一稀釋及/或載體氣體（例如氦、氬、氙、氪，相同氣體之組合或類似氣體）之情況下執行此一製程。在某些實施例中，氫之一流動速率可等於或大於烴前鱧源之一（莫耳）流動速率。烴前體氣體源可包含（但不限於）：己烷、環己烷、乙炔、單及雙短鏈烴（例如曱烷）、各種苯基烴、多環芳香族化合物、脂肪族烴、脂環族烴、芳香族烴、短鏈醚、醚及醇或其一組合。在某些實施例中，可在不使用一 PECVD室之情況下，採用此一烴源及H2氣體形成製程來形成一 C基層（例如非晶形碳）。舉例而言，熱能可係在C基層形成製程期間之唯一能量輸入。可在具有或不具有一稀釋及/或載體氣體（例如氦、氬、氙、氪，相同氣體之組合及/或類似氣體）之情形下執行此一製程。在某些實施例中，氫之一流動速率可等於或大於烴源之一（莫耳）流動速率。在一替代製程中，為減小碳層之切換電壓可使用多個碳沈積，每一者沈積約一單層碳。在某些實施例中，可在連續沈積下一個碳（接近）單一層之前在一非氧化氣氛中執行一退火（例如，在小於約600°C下）。舉例而言，在添加C基介面層116之前，C基切換材料114可由至少兩個層及小於大約二十個層形成。（參見，例如，2008年4月11日申請且名稱為「THIN DEPOSITED CARBON SWITCHABLE RESISTOR AND DIODE MATRIX CELL FOR 3D ARRAYS」之美國臨時專利申請案第61/044,399號（檔案號為257P)，該案出於各種目的以全文引用之方式併入本文中。） 141458.doc •12- 201007942 q步驟可形成額外平面内碳鍵（例如，叩2鍵）且限制 ::面外妷鍵之數量。既然sp2比邛3導電性強，目此藉由退火5玄結構增加Sp2之分你丨例’由此降低垂直導電路徑之電阻。在一較佳實施例中， ^ c基切換材料114與選擇裝置電流電壓谷量致。在某些實施例中’。基切換層之總厚度可在大約1埃至大埃之範圍中。然、而，在其他實In some embodiments, a metal hard mask (not shown) is formed over the diode 108. For example, the use of a metal hard mask is described in US Patent Application No. ll., filed on May 13, 2006, entitled " CONDUCTIVE HARD MASK TO PROTECT 141458.doc -9- 201007942 patterned FEATURES DU G TRENCH ETCH. /444,936 (hereinafter referred to as "the 936 application"), which is incorporated herein by reference in its entirety for all purposes. In one embodiment, a first C-based interfacial layer 112 is formed over the bonding/barrier layer 110 to improve the adhesion/barrier layer 11 and the C-based switching material to be formed (described below) in accordance with the present invention. Bonding. The first c-based interface layer 112 can have one or more of a 邛3 bond concentration, an increased density, a nitrided region, or the like, as increased by one of the foregoing. For example, graphene, amorphous carbon containing microcrystalline graphene, carbon nanotubes (CNT), other graphitic carbon, and the like, a c-based switching material 114 is formed over the C-based interface layer H2. The c-based switching material 114 can be deposited and/or grown by any suitable technique, such as chemical vapor deposition (CVD), high density plasma (HDP) deposition, plasma enhanced CVD, sputtering from an amorphous or graphite target. Shot deposition, spin coating process, seed crystal growth, etc. In some embodiments, post deposition processing (eg, annealing in a reduced pressure or oxygen environment) may be employed to affect or otherwise modify the C-based switching material 114. nature. A second C-based interfacial layer 116 is formed over the c-based switching material 114 in accordance with the present invention. The second c-based interface layer 116 can be the same or different than the first c-based interface layer Π2. The first C-based interface layer 112, the C-based switching material 114, and the second C-based interface layer 116 can serve as an insulating portion of the MIM stack 111. Thereafter, a top conductor 118 is formed over the upper C-based interface layer 116. For example, top conductor 187 may comprise a tungsten layer or other conductive layer 120 with or without a TiN, WN, TaN or other bonding/barrier layer 122. A portion of the top conductor 187 (e.g., bond/barrier layer 22) can be used as one of the top electrodes of the 141458.doc • 10·201007942 MIM stack 111. Note that in some embodiments, the diode 108 can be positioned over the C-based switching material 114. For example, conductive layers 104, 120 can comprise from about 200 to about 2500 angstroms of tungsten. Other conductive layer materials and/or thicknesses can be used. For example, the adhesive layers 106, 11A, 122 may comprise about 20 to about 500 angstroms and preferably about 1 angstrom of titanium nitride or another suitable bonding layer (such as tantalum nitride, tungsten nitride, or A combination of multiple adhesive layers, or a similar layer). Other adhesive layer materials and/or thicknesses may be used. Exemplary widths of the conductors 102, 118 and/or spacing between the conductors range from about 200 to about 2500 angstroms, although other conductor widths and/or spacings can be used. In one or more embodiments, the first C-based interfacing layer 112 and/or the second C-based interfacial layer 116 can have a thickness of from about 2 to about 500 angstroms, more preferably from about 2 to about 50 angstroms. Still more preferably about 10 to about 20 angstroms. The c-based switching material 114 can have a thickness of from about 1 to about 2000 angstroms and more preferably from about 2 to about 1000 angstroms. Other thickness ranges are also available for these layers. In some embodiments, the c-based switching material 114 can be deposited at a low rate such that only a few atomic layers are deposited (eg, in some embodiments about 2 layers, but more or fewer layers can be used) ) to form a plurality of sp2 carbon-carbon oxime bonds typical of graphite materials. At a temperature of from about 4 Torr to about 9 Torr, preferably less than about 55 CTC and more preferably less than about 45 Torr from a mixture of hydrogen and a carbon source (e.g., qH2, QH6, etc.) A plasma assisted decomposition and deposition can be used to minimize the total exposure temperature and time of other device layers. Several exemplary PECVD chambers are commercially available, but any suitable: PECVD chamber can be used. 141458.doc 201007942 This process can be carried out with or without a diluent and/or carrier gas (e.g., helium, argon, neon, xenon, a combination of the same gases or the like). In certain embodiments, one of the hydrogen flow rates may be equal to or greater than one of the hydrocarbon precursor sources (mole) flow rate. Hydrocarbon precursor gas sources may include, but are not limited to, hexane, cyclohexane, acetylene, mono- and di-short-chain hydrocarbons (eg, decane), various phenyl hydrocarbons, polycyclic aromatic compounds, aliphatic hydrocarbons, lipids A cyclocarbon, an aromatic hydrocarbon, a short chain ether, an ether, and an alcohol or a combination thereof. In some embodiments, the carbon source and H2 gas formation process can be used to form a C-based layer (e.g., amorphous carbon) without the use of a PECVD chamber. For example, thermal energy can be the only energy input during the C-base formation process. This process can be carried out with or without a diluent and/or carrier gas (e.g., helium, argon, neon, xenon, a combination of the same gases, and/or the like). In certain embodiments, one of the hydrogen flow rates may be equal to or greater than one of the hydrocarbon source (mole) flow rates. In an alternative process, multiple carbon deposits can be used to reduce the switching voltage of the carbon layer, each depositing about a single layer of carbon. In certain embodiments, an anneal may be performed in a non-oxidizing atmosphere (e.g., at less than about 600 °C) prior to successive deposition of the next carbon (near) single layer. For example, prior to the addition of the C-based interface layer 116, the C-based switching material 114 can be formed from at least two layers and less than about twenty layers. (See, for example, U.S. Provisional Patent Application No. 61/044,399, filed on Apr. 11, 2008, entitled "THIN DEPOSITED CARBON SWITCHABLE RESISTOR AND DIODE MATRIX CELL FOR 3D ARRAYS,' It is incorporated herein by reference in its entirety for all purposes.) 141458.doc • 12- 201007942 The q step can form additional in-plane carbon bonds (eg, 叩2 keys) and limits: the number of out-of-plane 妷 bonds. Since sp2 is more conductive than 邛3, it is necessary to increase the resistance of the vertical conductive path by increasing the Sp2 by the annealing structure. In a preferred embodiment, the ^c-based switching material 114 is sized to select the device current voltage. In some embodiments '. The total thickness of the base switching layer can range from about 1 angstrom to about angstrom. However, in other realities

施例中’ C基切換層114之總厚度可在大約細埃與大約8〇〇埃之間。可使用其他厚度範圍。如先前所述，在上述碳膜中主要存在兩種不同的所關注之鍵結構，亦即印2及sp3。該sp3鍵類似於—具有一四面體形狀之類金剛石結構，而該sp2鍵較平坦且呈—三角形形狀。對於一 C基切換材料，sp2(雙（><：鍵）與sp3(單c_c鍵）之期望比率可藉由評估D及G鍵而經由（例如）拉曼光譜學 (Raman spectroscopy)確定。在本發明之一個實施例中，c基介面層112及/或116可具有一增加的sp3濃度（相對於C基切換層114)以改良C基切換層114與導電層110及/或122之間的黏合。如將在下文中更詳細闡述，在採用一 PECVD製程將非晶形碳沈積為c基介面層112、116及/或C基切換層114之一實施例中，可藉由降低製程溫度及/或增加該PECVD製程之一電漿離子化組份來達成C基介面層112、116中一期望（增加的）sp3鍵濃度。舉例而言’可增加載體氣體濃度（例如，氬、氦、氣、氪或另一惰性氣體濃度）以使得產生更多離子物質。另外或或者，可採用一基板偏壓及/或低頻率RF來增加離 141458.doc •13· 201007942 子轟擊。亦可增加高頻率RF功率。一般而言，C基介面層112、116及c基切換層114之沈積方法可包含（但不限於）自一目標之濺射沈積、PECVD、 CVD、弧光放電技術、雷射剝蝕等等。儘管所使用之沈積溫度較佳係低於大约600〇c，但在某些實施例中其可係在自大約300°C至大約9〇(TC之範圍。前體氣體源可包含（但不限於）己烷、環己烷、乙炔、單及雙短鏈烴（例如，甲烷）、各種苯基烴、多環芳香族化合物、脂肪族烴、脂環族烴、芳香族烴、短鏈醚、醚及醇或其一組合。在將碳奈米管用於C基切換元件時，可使用一旋塗製程、晶種生長或類似方法來形成C基切換層114。下文闡述包含（但不限於）應用於經改良之黏合或用作一氆封或覆蓋層之用於形成一 C基介面層之一 pecvd製程之兩個實例。實例性C基介面層形成製程在一第一實例中，可根據本發明藉由一第一PECVD製程產生一非晶形c基介面層。可採用任一適合pECVD室。在一實例性實施例中，藉由使用一約為5〇至約1〇〇 ^⑽之 (：2出或（：出6源氣體流動速率、一約為25〇〇至約5〇〇〇之氦載體/稀釋劑氣體流動速率、一約為15〇至約25〇瓦特之RF功率、一約為5至約7托之室壓、一約為55〇t>c之製程溫度及一約為300至約400密而之電極間隔所形成之_ c基 "面層產生一具有至一導電膜（例如TiN、WN或w)之強介面黏合性質之導電非晶形碳膜。以上膜在此實例中之沈積 I41458.doc 201007942 速率約為1埃/秒。拉曼光譜在碳膜中偵測到大約2奈米晶。 ’、根據本發明之一c基介面層之一實例性製程窗口包含·· (a)載體（稀釋劑）氣體與源氣體比率約為1:1至約100: i，且更佳約為5:1至約5〇: 1 ; , (b)—高頻率RF功率，在一約為135兆赫之頻率下約為 3〇至約1000瓦特，且更佳約為30至約250瓦特；翁、（）汉？功率雄、度，約為0.45至約20瓦特"η2，且更佳約為〇·45至約5瓦特/in2 ; (c)—低頻率RF功率，在—約為9〇千赫之頻率下約為〇至約500瓦特，且更佳約為0至約150瓦特； (c) 一室壓，約為1至約10托，且更佳約為2 5至約7托； (d) 電極間隔，約為200至約looo密而，且更佳約為 200至約500密而；及/或 (e) —製程溫度，約為3〇(rc至約6〇〇β(：，且更佳約為 φ 300 C至約55〇 C。在其他實施例中，可使用一約為4〇(rc 至約900Χ：之製程溫度。 /主思，可使用其他適合載體氣體/源氣體比率、灯功率、至壓、電極間隔及/或製程溫度。任一匕^^前體或其他適〇别體可與任一載體/稀釋氣體（例如出、He、Ar、 Xe Kr等等）一起使用。在膜形成期間，相對於源/前體氣體流動增加載體/稀釋氣體流動降低c基介面層之沈積速率且曰加表面離子轟擊，兩者皆增加c基介面層之密度（例如’相對於一 C基切換層）。目此改良膜黏合。 141458.doc -15· 201007942 實例性c基介面層沈積速率約為㈣秒或以下，更佳約為5埃/秒或以下且更佳約為t至約⑻秒。實例性c基介面層厚度約為1_埃或以下，且更佳約為5⑼埃或以下。在某些實施例中’一C基介面層可具有—約為12克/立方公分至約3·5克/立方公分之密度。可使用其他沈積速率、膜厚度及/或膜密度。 _ 在第一實例中，可根據本發明藉由一氮化製程產生- . 非晶形c基介面層。在某些實施例中，可在— pecvd室中使二電漿氮化形成-具有經改良黏合之碳基介面層。舉W _ 而。可氮化C基切換疋件i 14本身，或可氮化另一 c基材料層以形成一C基介面層。可在以下製程條件下執行一 PECVD製程： (a) —仏流動速率，約為1〇〇〇至約2〇〇〇〇 secm，且更佳約為 12,0〇〇至約 18 〇〇〇 sccm ; (b) —高頻率RF功率，約為4〇瓦特至約ι〇〇〇瓦特且更佳約為40瓦特至約250瓦特； (c) 一室壓，約為1至約10托，且更佳約為3托至約7 〇托； (d) —電極間隔，約為2〇〇至約1〇〇〇密而，且更佳約為 . 250至約6〇〇密而；及/或 (e) 一製程溫度，約為300°C至約6〇〇°c。 ’ 庄意，可使用其他適合氣體流動速率、rf功率、室壓、電極間隔及/或製程溫度。可採用其他氮化製程，例如在一升兩之溫度下將一 c基材料層曝露至]^札、N2〇或類似氣 141458.doc -16- 201007942 體及/或任何其他氮氣體源。儘管圖1圖解說明根據本發明採用C基介面層之一 c基切換設備之一實例，但彼等熟悉此項技術者將瞭解本發明之 C基介面層可實施於各種裝置及應用中’例如用於覆蓋或密封層。舉例而言，一所沈積或生長之CNT材料層通常真有粗心表面形貌’其具有顯著的厚度變化，例如眾多峰及縠。此一 CNT層亦可係如此多孔以至於在該cNT層上直接沈積一導電金屬層可透過整個CNt層形成一短路（例如，由於因在裝置製造期間之熱處理導致金屬原子透過 CNT膜之遷移）。為克服此等潛在問題，在本發明之一個或多個實施例中，可在一多孔C基切換材料上方形成一導電層之前在該多孔C基切換材料上方形成介面層以覆蓋該多孔c基切換材料。此一 c基介面層亦可改良該C基切換材料與該導電層之間的黏合。先前所述C基介面層中之任一者可充當此—覆蓋層。額外實施例圖2係根據本發明之一實例性記憶體單元2〇〇之一示意性圖解說明。記憶體單元2〇〇包含一耦合至一引導元件2〇4之 C基可逆電阻切換元件2〇2。舉例而言，可將一 c基電阻率切換元件202(例如圖1中之MIM堆疊111)與一引導元件 2〇4(例如二極體j 〇8)串聯放置以形成記憶體單元2〇〇。引導元件204可包含一薄膜電晶體、一二極體或藉由選擇性地限制跨越及/或流經可逆電阻切換元件2〇2之電壓及/或電流 141458.doc •17· 201007942 而展示出非歐姆導電之另一適合引導元件。可迚電阻切換元件202包含— , ^ J逆電阻率切換材料（未單獨顯不），該可逆電阻率切換材料具平個狀1、之間進行可逆切換之電阻。舉例而言，元件如之可逆電阻率切換材料在製造後可處於一初始低電阻率狀離 t，在施加一第，及/或電流後，該初始低電阻率：態可切換至一高電阻率狀態。施加一第二電遷及/或電产可使該可逆電阻率切換材料返回至一低電阻率狀態。另；選擇為，可逆電阻切換元件2〇2在製造後可處於—初始高電阻狀態巾’在施加適當電壓及/或電流後，該高電阻狀態可逆地可切換至一低電阻狀態。當用於一記憶體單元中 SU電阻狀態可表示一二進制「〇」而另一電阻狀態可表示一進制1」，但可使用兩個以上的資料/電阻狀態。在某些實施例中，該可逆電阻率切換材料可係一c基切換膜（如先前所闡述）。圖3繪示在多個記憶體層級上具有眾多記憶體單元細之一實例性三維記憶體陣列3〇〇。藉由使用引導元件2〇4選擇性地限制跨越及/或流經可逆電阻切換元件之電壓及/或電流，記憶體單元200可用作一二維或三維記憶體陣列之一郤为。可將資料寫入至一記憶體單元2〇〇及/或自一記憶體單兀200讀取資料，而不影響如在圖3中圖解說明之一陣列中之其他記憶體單元之狀態。互連可經製造以將每一記憶體單元（例如，與一 c基切換材料串聯之一引導元件）連接至R/W電路。 141458.doc -18- 201007942 舉例而言，形成此等記憶體層級之實例性方法闡述於美國專利第 6,952,030 號「High-density three-dimensional memory cell」及/或2〇〇7年3月27日中請且名稱為「LARGe ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT」之美國專利申請案第 1 1/692,151號中，該等專利申請案中之每一者出於各種目的而以全文引用之方式併入本文中。本發明之實施例證明在形成一單片三維記憶體陣列中係 ® 尤其有用。一單片三維記憶體陣列係一種其中多個記憶體層級开> 成於一單個基板（例如一晶圓）上方而不具有中間基板之記憶體陣列。形成一個記憶體層級之層沈積或直接生長在一現有層級或多個現有層級之層上方。相反，已藉由在單獨基板上形成記憶體層級且將該等記憶體層級黏附於彼此頂部上來構造經堆疊之記憶體，如Leedy的第 5,915,167號美國專利中所述。可在結合之前使該等基板變 φ 薄或自記憶體層級移除，但由於該等記憶體層級最初形成於單獨基板上方，因此此等記憶體並非係真正的單片三維記憶體陣列。如上所述，記憶體單元作業係基於在施加高偏壓（>4 之情形下C基材料中之一雙穩態電阻率改變。通過記憶體單元之電流可藉由c基材料之電阻率調變。在一較低電壓下讀取記憶體單元，該較低電壓將不會改變C基材料之電阻率。在某些實施例中’如在美國專利第6,706,4()2號反其他專利中所闡述，兩種狀態之間的電阻率之差別可大於 141458.doc 201007942 1 00x °在對引導元件施加高正向偏壓之情形下，該單元可自一「0」改變至一「1」。在施加一高正向偏壓之情形下，該單元可自一「1」改變回至一「〇」。圖4係根據本發明所形成之複數個實例性記憶體單元4〇〇之一剖視圖。參考圖4，一第一軌導體4〇2形成於一基板 (未顯示）上方。舉例而言’第一導體402可包含具有或不具有一 TiN、TaN、WN、Mo或其他黏合/障壁層406之一鎢層或其他導電層404。一垂直P-I-N(或N-I-P)二極體408(例如一經沈積多晶矽或其他多晶半導體二極體）形成於第一導體402上方，一矽化物區域41〇及一金屬硬遮罩412亦係如此。如先前以全文引用之方式併入本文中之美國專利第 7，176,064號所闡述，矽化物區域41〇係由一矽化物形成金屬形成，例如鈦或鈷。在某些實施例中，在退火期間矽化物層410增強二極體408之晶體結構，從而提供較低電阻率矽。對於矽鍺合金及/或鍺二極體而言，可達成類似結果。舉例而言，金屬硬遮罩闡述於先前以全文引用之方式併入本文中之，936申請案中。金屬硬遮罩412可包含（例如）一障壁層412a(例如TiN、TaN、WN、Mo等等）及/或導電層 412b(例如，W或另一導電層），且可在二極體4〇8之形成期間充當一硬遮罩。一 TiN、TaN、WN、Mo或其他黏合/障壁層414形成於金屬硬遮罩412上方。一 C基切換膜418(具有頂部及/或底部匸基介面層418a、41 8b)形成於黏合/障壁層414上八面層 141458.doc -20- 201007942 418a、418b可包含C基切換膜418或具有增加之sp3鍵密度及/或增加之膜密度之另一 c基材料之區域、c基切換膜418 或另一 C基材料之一氮化區域，或如先前所述之類似物。其後’在C基切換膜418上方形成一頂部導體422。舉例而言，頂部導體422可包含具有或不具有一 TiN、TaN、 WN、Mo或其他黏合/障壁層426之一鎢層或其他導電層 424。在某些實施例中，可將c基切換膜418定位在二極體 4 0 8下方。在某些實施例中，可一起蝕刻障壁層414、硬遮罩412及一極體408以形成柱結構，且可將介電材料42〇沈積在該等柱結構頂部上及其周圍以便使該等柱結構彼此隔離。然後執行一 CMP或電介質回姓步驟以平坦化介電材料42〇並自障壁層414之頂部移除該介電材料。其後，可沈積、圖案化且姓刻C基切換膜418及/或介面層418a、418b。隨後可將絕緣材料420沈積在經餘刻層41 8、41 8a、41 8b周圍並藉由一回蝕製程、化學機械拋光（CMp)或類似方法將其乎坦化。在一替代實施例中，可在圖案化及蝕刻障壁層4丨4、硬遮罩412及二極體408之前沈積c基切換膜418及/或介面層418a、418b。以此方式，層418、418a、418b可與障壁層414、硬遮罩412及二極體408 —起圖案化及蝕刻。然後，可將介電材料420沈積在所得柱結構頂部上及其周圍以便使该等柱結構彼此隔離。然後執行一 CMp或電介質回蝕步驟以平坦化介電材料42〇且自€基切換膜418(及/或介面層41 8b)之頂部移除介電材料。 141458.doc •21- 201007942 在本發明之某些實旛 J中’在_導電層（例如TaN、The total thickness of the 'C-based switching layer 114 in the embodiment can be between about fine and about 8 angstroms. Other thickness ranges are available. As described earlier, there are mainly two different key structures of interest in the above carbon film, i.e., 2 and sp3. The sp3 bond is similar to a diamond structure having a tetrahedral shape, and the sp2 bond is relatively flat and has a triangular shape. For a C-based switching material, the desired ratio of sp2 (double (><: bond) to sp3 (single c_c bond) can be determined by, for example, Raman spectroscopy by evaluating the D and G bonds. In one embodiment of the invention, the c-based interface layer 112 and/or 116 may have an increased sp3 concentration (relative to the C-based switching layer 114) to improve the C-based switching layer 114 and the conductive layer 110 and/or 122. Bonding between. As will be explained in more detail below, in an embodiment in which amorphous carbon is deposited as a c-based interface layer 112, 116 and/or C-based switching layer 114 using a PECVD process, the process can be reduced by Temperature and/or increasing one of the PECVD processes to achieve a desired (increased) sp3 bond concentration in the C-based interface layers 112, 116. For example, 'the carrier gas concentration can be increased (eg, argon, Helium, gas, helium or another inert gas concentration) to produce more ionic species. Alternatively or alternatively, a substrate bias and / or low frequency RF can be used to increase the IA. 141458.doc •13· 201007942 sub-bombardment. High frequency RF power can be added. In general, C-based interface layer 1 The deposition methods of the 12, 116 and c-based switching layers 114 may include, but are not limited to, sputtering deposition from a target, PECVD, CVD, arc discharge techniques, laser ablation, etc., although the deposition temperature used is preferably Below about 600 〇c, but in certain embodiments it can range from about 300 ° C to about 9 〇 (TC range. The precursor gas source can include, but is not limited to, hexane, cyclohexane, Acetylene, mono- and di-short-chain hydrocarbons (eg, methane), various phenyl hydrocarbons, polycyclic aromatic compounds, aliphatic hydrocarbons, alicyclic hydrocarbons, aromatic hydrocarbons, short-chain ethers, ethers, and alcohols, or a combination thereof. When a carbon nanotube is used for the C-based switching element, a spin coating process, seed growth, or the like can be used to form the C-based switching layer 114. The following description includes, but is not limited to, applied to improved bonding or use. Two examples of a pecvd process for forming a C-based interface layer as a capping or capping layer. An exemplary C-based interposer forming process in a first example can be performed by a first PECVD in accordance with the present invention. The process produces an amorphous c-based interface layer. Any suitable p can be used. ECVD chamber. In an exemplary embodiment, by using approximately 5 〇 to about 1 ( (10) (: 2 out or (: 6 source gas flow rate, a range of about 25 〇〇 to about 5 The carrier/diluent gas flow rate, an RF power of from about 15 Torr to about 25 watts, a chamber pressure of from about 5 to about 7 Torr, and a process temperature of about 55 〇t > And a _c-based " surface layer formed by an electrode spacing of about 300 to about 400 mils produces a conductive amorphous carbon film having a strong interfacial adhesion property to a conductive film (e.g., TiN, WN or w). The deposition of the above film in this example was I41458.doc 201007942 at a rate of about 1 angstrom/second. Raman spectroscopy detected approximately 2 nanocrystals in the carbon film. An exemplary process window of a c-based interfacial layer according to the present invention comprises: (a) a carrier (diluent) gas to source gas ratio of from about 1:1 to about 100: i, and more preferably about 5 : 1 to about 5 〇: 1 ; , (b) - high frequency RF power, about 3 〇 to about 1000 watts at a frequency of about 135 MHz, and more preferably about 30 to about 250 watts; ()Chinese? Power male, degree, about 0.45 to about 20 watts " η 2, and more preferably about 〇 · 45 to about 5 watts / in 2 ; (c) - low frequency RF power, at - about 9 kHz Lower is about 500 watts, and more preferably about 0 to about 150 watts; (c) one chamber pressure, about 1 to about 10 Torr, and more preferably about 25 to about 7 Torr; (d) The electrode spacing is about 200 to about looo dense, and more preferably about 200 to about 500 mils; and/or (e) - the process temperature is about 3 〇 (rc to about 6 〇〇 β (:, and More preferably from about φ 300 C to about 55 〇 C. In other embodiments, a process temperature of about 4 〇 (rc to about 900 Χ: can be used. / /, other suitable carrier gas / source gas ratios can be used , lamp power, to pressure, electrode spacing and/or process temperature. Any precursor or other suitable body may be combined with any carrier/dilution gas (eg, He, Ar, Xe Kr, etc.) During film formation, increasing the carrier/dilution gas flow relative to the source/precursor gas flow reduces the deposition rate of the c-based interface layer and adds surface ion bombardment, both of which increase the density of the c-based interface layer (eg, 'Improved film adhesion with respect to a C-based switching layer. 141458.doc -15· 201007942 The exemplary c-based interface layer deposition rate is about (four) seconds or less, more preferably about 5 angstroms/second or less and more. Preferably, the thickness of the c-based interface layer is about 1 angstrom or less, and more preferably about 5 (9) angstroms or less. In some embodiments, the 'c-based interface layer can have about 约. It is a density of from 12 g/cm 3 to about 3.5 g/cm 3 . Other deposition rates, film thicknesses, and/or film densities can be used. _ In the first example, it can be produced by a nitridation process according to the present invention. An amorphous c-based interfacial layer. In some embodiments, the two plasmas can be nitrided in a - pecvd chamber - a carbon-based interfacial layer with improved adhesion. W _ can be nitrided C-based Switching the element i 14 itself, or nitriding another c-based material layer to form a C-based interface layer. A PECVD process can be performed under the following process conditions: (a) - 仏 flow rate, about 1 〇〇〇 Up to about 2 〇〇〇〇sec, and more preferably about 12,0 〇〇 to about 18 〇〇〇sccm; (b) - high frequency RF power, about 4 Watts to about ι watts and more preferably from about 40 watts to about 250 watts; (c) one chamber pressure, from about 1 to about 10 Torr, and more preferably from about 3 Torr to about 7 Torr; ) - the electrode spacing is from about 2 Torr to about 1 mil, and more preferably from about 250 to about 6 mils; and / or (e) a process temperature of about 300 ° C to About 6 〇〇 ° c. 'Zhuang Yi, other suitable gas flow rate, rf power, chamber pressure, electrode spacing and / or process temperature can be used. Other nitridation processes may be employed, such as exposing a c-based material layer to a temperature of one liter and two to a gas source of 141458.doc -16-201007942 and/or any other source of nitrogen gas. Although FIG. 1 illustrates an example of a c-based switching device employing a C-based interface layer in accordance with the present invention, those skilled in the art will appreciate that the C-based interface layer of the present invention can be implemented in a variety of devices and applications, for example. Used to cover or seal the layer. For example, a layer of deposited or grown CNT material typically has a careless surface topography that has significant thickness variations, such as numerous peaks and flaws. The CNT layer may also be so porous that a direct deposition of a conductive metal layer on the cNT layer may form a short circuit through the entire CNt layer (eg, due to migration of metal atoms through the CNT film due to heat treatment during device fabrication) . To overcome such potential problems, in one or more embodiments of the present invention, an interfacial layer may be formed over the porous C-based switching material to form the porous c prior to forming a conductive layer over a porous C-based switching material. Base switching material. The c-based interface layer also improves adhesion between the C-based switching material and the conductive layer. Any of the previously described C-based interface layers may serve as a cover layer. Additional Embodiments Figure 2 is a schematic illustration of one exemplary memory cell 2 in accordance with the present invention. The memory cell 2A includes a C-based reversible resistance-switching element 2〇2 coupled to a guiding element 2〇4. For example, a c-based resistivity switching element 202 (eg, MIM stack 111 in FIG. 1) can be placed in series with a guiding element 2〇4 (eg, diode j 〇 8) to form a memory cell 2〇〇 . The guiding element 204 can comprise a thin film transistor, a diode or by selectively limiting the voltage and/or current across the reversible resistance-switching element 2〇2 and/or current 141458.doc •17·201007942 Another suitable non-ohmic conductive element is the guiding element. The resistive resistance switching element 202 includes -, ^ J reverse resistivity switching material (not separately shown), and the reversible resistivity switching material has a flat shape and a resistance that is reversibly switched between. For example, the component such as the reversible resistivity switching material may be in an initial low resistivity after being manufactured, and after the application of a first and/or current, the initial low resistivity: state may be switched to a high resistance. Rate status. Applying a second electromigration and/or electrical output returns the reversible resistivity switching material to a low resistivity state. Alternatively, the reversible resistance-switching element 2〇2 may be in the initial high-resistance state after manufacture. The high-resistance state is reversibly switchable to a low-resistance state after application of an appropriate voltage and/or current. When used in a memory cell, the SU resistance state can represent a binary "〇" and the other resistance state can represent a binary 1", but more than two data/resistance states can be used. In some embodiments, the reversible resistivity switching material can be a c-based switching film (as previously explained). Figure 3 illustrates an exemplary three dimensional memory array 3 having a plurality of memory cell details at a plurality of memory levels. The memory cell 200 can be used as one of a two-dimensional or three-dimensional memory array by selectively limiting the voltage and/or current flowing across and/or through the reversible resistance-switching element using the guiding elements 2〇4. Data can be written to a memory unit 2 and/or read from a memory unit 200 without affecting the state of other memory cells in an array as illustrated in FIG. The interconnects can be fabricated to connect each of the memory cells (e.g., one of the directing elements in series with a c-based switching material) to the R/W circuit. 141458.doc -18- 201007942 For example, an exemplary method of forming such memory levels is described in U.S. Patent No. 6,952,030, "High-density three-dimensional memory cell" and/or March 27, 2007. In U.S. Patent Application Serial No. 1 1/692,151, the disclosure of which is incorporated herein by reference in its entirety in its entirety in its entirety in the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all all all The manner is incorporated herein. Embodiments of the invention are particularly useful in forming a single piece of three dimensional memory array. A monolithic three dimensional memory array is a memory array in which a plurality of memory levels are layered over a single substrate (e.g., a wafer) without an intermediate substrate. A layer of memory level is deposited or grown directly over a layer of an existing level or a plurality of existing levels. In contrast, the stacked memory has been constructed by forming a memory level on a separate substrate and adhering the memory levels to the top of each other, as described in U.S. Patent No. 5,915,167, issued to hereby. The substrates may be thinned or removed from the memory level prior to bonding, but since the memory levels are initially formed over a separate substrate, such memory is not a true monolithic three dimensional memory array. As described above, the memory cell operation is based on the change of one of the C-based materials in the case of applying a high bias voltage (>4). The current through the memory cell can be made by the resistivity of the c-based material. Modulation. Reading a memory cell at a lower voltage, the lower voltage will not change the resistivity of the C-based material. In some embodiments, as in U.S. Patent No. 6,706, 4() No. 2 As stated in other patents, the difference in resistivity between the two states can be greater than 141458.doc 201007942 1 00x ° In the case of applying a high forward bias to the guiding element, the unit can be changed from a "0" to a "1". In the case of applying a high forward bias, the unit can be changed back from a "1" to a "〇". Figure 4 is a plurality of exemplary memory cells formed according to the present invention. Referring to Figure 4, a first rail conductor 4〇2 is formed over a substrate (not shown). For example, 'the first conductor 402 may or may not have a TiN, TaN, WN, Mo or One of the other bonding/barrier layers 406 is a tungsten layer or other conductive layer 404. A vertical PIN ( A NIP) diode 408 (eg, a deposited polysilicon or other polycrystalline semiconductor diode) is formed over the first conductor 402, as is a germanide region 41 and a metal hard mask 412. In the manner described in U.S. Patent No. 7,176,064, the telluride region 41 is formed from a telluride forming metal, such as titanium or cobalt. In certain embodiments, the vaporized layer 410 during annealing. The crystal structure of the diode 408 is enhanced to provide a lower resistivity. Similar results can be achieved for tantalum alloys and/or tantalum diodes. For example, metal hard masks are described above in full. The manner is incorporated herein, in the '936 application. The metal hard mask 412 can comprise, for example, a barrier layer 412a (eg, TiN, TaN, WN, Mo, etc.) and/or a conductive layer 412b (eg, W or Another conductive layer) can serve as a hard mask during the formation of the diodes 4A. A TiN, TaN, WN, Mo or other bonding/barrier layer 414 is formed over the metal hard mask 412. Base switching film 418 (having a top and/or bottom) The ruthenium-based interface layers 418a, 41 8b) are formed on the affixing/damper layer 414. The octahedron 141458.doc -20-201007942 418a, 418b may comprise a C-based switching film 418 or a film having an increased sp3 bond density and/or increase a region of another c-based material of density, a c-based switching film 418 or a nitrided region of another C-based material, or an analog as previously described. Thereafter, a top conductor is formed over the C-based switching film 418. 422. For example, the top conductor 422 can include a tungsten layer or other conductive layer 424 with or without a TiN, TaN, WN, Mo, or other bonding/barrier layer 426. In some embodiments, the c-based switching film 418 can be positioned below the diodes 48. In some embodiments, the barrier layer 414, the hard mask 412, and the one body 408 may be etched together to form a pillar structure, and a dielectric material 42 may be deposited on top of and around the pillar structure to enable the The column structures are isolated from each other. A CMP or dielectric return step is then performed to planarize the dielectric material 42 and remove the dielectric material from the top of the barrier layer 414. Thereafter, the C-based switching film 418 and/or the interface layers 418a, 418b can be deposited, patterned, and surnamed. The insulating material 420 can then be deposited around the reticle layers 41 8 , 41 8a, 41 8b and etched by an etch back process, chemical mechanical polishing (CMp) or the like. In an alternate embodiment, the c-based switching film 418 and/or the interface layers 418a, 418b may be deposited prior to patterning and etching the barrier layer 4, 4, the hard mask 412, and the diode 408. In this manner, layers 418, 418a, 418b can be patterned and etched with barrier layer 414, hard mask 412, and diode 408. Dielectric material 420 can then be deposited on top of and around the resulting pillar structure to isolate the pillar structures from one another. A CMp or dielectric etch back step is then performed to planarize the dielectric material 42 and remove the dielectric material from the top of the H-switching film 418 (and/or the interface layer 418b). 141458.doc • 21- 201007942 In some implementations of the invention J is in a conductive layer (eg TaN,

TiN?N或類似物)上方形成-C基切換層及/或-C基介面層之刖，可預處理一導·雷思主γThe formation of a -C-based switching layer and/or a -C-based interface layer over TiN?N or the like) can be pretreated with a lead-rear gamma

等電層表面以改良C基切換層（及/或C 基介面層（若使用）)與導電層之間的黏合。舉例而言，可在 c基材料形成之前將該導電層表面曝露至-氣體電漿以處理该導電層表面。在至少-個實施例中，可採用一在用來成基"面及/或切換層（但在沒有碳前體源之情形下）之相同條件下所產生之氣體電漿來預處理一導電層之一表面舉例而s，在C基材料形成期間所使用之相同載體氣體（例如He、Ar、H2、N2、Xe、Kl•等”可用在預處理氣體電漿中(例如，具有相同流動速率、室壓、RF功率、電極間:及7或處理溫度）。在某些實施例中，-預處理可包含將導電層之表面曝露至一氣體電漿達約5至2〇秒，但可使用較長或較短的時間。為避免電漿不穩定，可在預處理 :後立即(例如無需中斷電漿)添加用來形成C基材料之碳前體。在其他實施例中，在C基材料形成期間所使用之處理參數中之一者或多者可在導電表面之預處理期間變化。在一個或多個實施例中，可在一導電層（例如TiN、TaN 等等）卜士屮或下方形成一 C基材料（例如一 c基介面層及/或一 c基切換層）之後執行一熱退火以改良該C基材料與該導之間的黏合。可在一約為3〇〇_6〇〇°C之溫度下在He、The surface of the isoelectric layer is modified to bond the C-based switching layer (and/or the C-based interfacial layer (if used)) to the conductive layer. For example, the surface of the conductive layer can be exposed to a gas plasma to treat the surface of the conductive layer prior to formation of the c-based material. In at least one embodiment, a gas plasma produced under the same conditions used to form a "face and/or switching layer (but without a carbon precursor source) may be used to pretreat a One surface of the conductive layer is exemplified, and the same carrier gas (for example, He, Ar, H2, N2, Xe, Kl, etc.) used during the formation of the C-based material can be used in the pretreatment gas plasma (for example, having the same Flow rate, chamber pressure, RF power, interelectrode: and 7 or processing temperature. In some embodiments, the pretreatment can include exposing the surface of the electrically conductive layer to a gas plasma for about 5 to 2 seconds, However, longer or shorter times may be used. To avoid plasma instability, the carbon precursor used to form the C-based material may be added immediately after the pretreatment: (eg, without interrupting the plasma). In other embodiments One or more of the processing parameters used during the formation of the C-based material may vary during the pre-treatment of the conductive surface. In one or more embodiments, a conductive layer (eg, TiN, TaN, etc.) may be employed. a C-based material (for example, a c-based interface) And / or c perform a thermal anneal after a quiche conversion layer) to the improved adhesion between the conductive material and the substrate C may be at a temperature of from about 3〇〇_6〇〇 [deg.] C in the He,

2 、Xe或另一惰性氣體中執行一實例性熱退火達为20-35分鐘。在某些實施例中，用來在一導電層上方形成一 C基介面層及/或一 C基切換層之相同PECVD室可用 141458.doc •22· 201007942 來執行該退火。在一個特定實例中，可使用約為ι〇〇〇 seem或以上之一退火氣體流動速率，約為2托或以上之一至壓，約為350-600密而之一電極間隔及約為3〇〇_55〇亡之一退火溫度達約30分鐘。亦可使用其他流動速率、室壓、電極間隔及/或溫度。同樣，可在一不同室（例如一退火爐）内執行退火。儘管前述内容針對本發明之實例性實施例，但不背離本發明範疇之其他及進一步之實施例對於熟悉此項技術者而言將係顯而易見。因此，儘管已結合本發明之實例性實施例來揭示本發明，但應理解，其他實施例可歸屬於由以下申請專利範圍所界定之本發明之精神及範疇内。【圖式簡單說明】可藉由參考本發明之所闞述實施例來獲得對本發明之一更明確理解，該等實施例圖解說明於隨附圖式中。該等隨附圖式僅圖解說明本發明之典型實施例，其並非意欲按比例，且其不應視為限定本發明之範疇，因為本發明可容許其他有效實施例。為促進理解，盡可能使用了類似參考編號來指定各圖中共有的類似元件。圖1係根據本發明之一實施例之一裝置之一剖視側立圖2繪示根據本發明之一記憶體單元；圖3繪示根據本發明之一記憶體單元陣列之—實例一透視圖；及 141458.doc -23- 201007942 圖4係根據本發明所形成之複數個實例性記憶體單元之一剖視側立面圖。【主要元件符號說明】 100 記憶體單元 102 第一軌導體 104 導電層 106 黏合/障壁層 108 垂直P-I-N或N-I-P二極體 110 黏合/障壁層 111 金屬-絕緣體-金屬（MIM)堆疊 112 第一 C基介面層 114 C基切換材料 116 第二C基介面層 118 頂部導體 120 導電層 122 黏合/障壁層 200 記憶體單元 202 C基可逆電阻切換元件 204 引導元件 300 三維記憶體陣列 400 記憶體單元 402 第一軌導體 404 導電層 406 黏合/障壁層 141458.doc -24- 201007942 408 垂直P-I-N(或N-I-P)二極體 410 石夕化物區域 412 金屬硬遮罩 412a 障壁層 412b 導電層 414 黏合/障壁層 418 C基切換膜 418a 介面層胃 418b 介面層 422 頂部導體 424 導電層 426 黏合/障壁層 141458.doc -25-An example thermal anneal is performed in X, Xe or another inert gas for 20-35 minutes. In some embodiments, the same PECVD chamber used to form a C-based interface layer and/or a C-based switching layer over a conductive layer can be performed using 141458.doc • 22·201007942. In one particular example, an annealing gas flow rate of about ι〇〇〇seem or more, about 2 Torr or more to pressure, about 350-600 mils and one electrode spacing and about 3 可 can be used. One of the 退火_55 annihilation temperatures is about 30 minutes. Other flow rates, chamber pressures, electrode spacing and/or temperature can also be used. Also, annealing can be performed in a different chamber, such as an annealing furnace. While the foregoing is directed to the exemplary embodiments of the present invention, it will Therefore, while the invention has been described in connection with the exemplary embodiments of the present invention, it should be understood that other embodiments may be in the spirit and scope of the invention as defined by the following claims. BRIEF DESCRIPTION OF THE DRAWINGS A more clear understanding of the present invention may be obtained by reference to the embodiments of the present invention, which are illustrated in the accompanying drawings. The present invention is intended to be illustrative of the preferred embodiments of the invention, and is not intended to To promote understanding, similar reference numbers are used whenever possible to specify similar components that are common to each figure. 1 is a cross-sectional side view of a device according to an embodiment of the present invention. FIG. 2 illustrates a memory cell according to the present invention; FIG. 3 illustrates a memory cell array according to the present invention. Figure; and 141458.doc -23- 201007942 Figure 4 is a cross-sectional side elevational view of one of a plurality of exemplary memory cells formed in accordance with the present invention. [Main component symbol description] 100 Memory unit 102 First rail conductor 104 Conductive layer 106 Bonding/barrier layer 108 Vertical PIN or NIP diode 110 Bonding/barrier layer 111 Metal-insulator-metal (MIM) stack 112 First C Substrate layer 114 C-based switching material 116 second C-based interposer layer 118 top conductor 120 conductive layer 122 bonding/barrier layer 200 memory unit 202 C-based reversible resistance-switching element 204 guiding element 300 three-dimensional memory array 400 memory unit 402 First rail conductor 404 conductive layer 406 adhesive/barrier layer 141458.doc -24- 201007942 408 vertical PIN (or NIP) diode 410 asherm region 412 metal hard mask 412a barrier layer 412b conductive layer 414 bonding/barrier layer 418 C-based switching film 418a interface layer stomach 418b interface layer 422 top conductor 424 conductive layer 426 bonding/barrier layer 141458.doc -25-

Claims

201007942 七、申請專利範圍： 1 · 一種記憶體單元，其包括：一第一導體；一可逆電阻切換元件，其形成於該第—導可逆電阻切換元件包含：以一碳基電阻率切換材料；及 -碳基介面層，其耦合至該碳基電阻率切換称一引導元件，其形成於該第一導體上方·，及一第二導體，其形成於該可逆電阻切換元件及該引導元件上方。 2·如請求心之記憶體單元，其中該介面層具有大於該破基電阻率切換材料之sp3鍵濃度之_sp3鍵濃度。 3.:請求項i之記憶體單元，其中該介面層：有大於該碳基電阻率切換材料之密度之_密度。 4·如請求項1之記憶體單元’其中該碳基介面層包括經氮化碳基材料。 5·=求们之記憶體單元’其中該介面層具有—約為5〇〇埃或較小之一厚度。 I Si項1之記憶體單元，其進-步包括輕合至該碳基切換材料之-第二碳基介面層且其中該碳基電阻旱：換材料係在該第一介面層與該第二介面層之間。 7.如請求項6之記憶體單元，其進一步 -第-導電層及…該第二介面層之第二導電層。 141458.doc 201007942 8.如請求項1之記憶 _ ^ ^ 0 疋，其中該碳基介面層包括非晶 ▲主广碳基電阻率切換材料包括碳奈米管。 9·如π求項丨之記憶體單元，其中該電阻率切換材料中之〜 4 者或夕者包括含有石墨烯之非晶 …石墨烯及碳奈米管中之一者或多者。如π求項1之§己憶體單元，其中該引導元件包括— 二極體。 11. 一種設備，其包括：一碳基介面層；及妷基電阻率切換材料，其毗鄰該碳基介面層；其中該碳基介面層比該碳基電阻率切換材料稠密。 12. 如凊求項丨丨之設備，其中該碳基介面層具有大於該碳基電阻率切換材料之Sp3鍵濃度之一 sp3鍵濃度。 13·如請求項丨丨之設備，其中該碳基介面層包括經氮化碳基材料。 14. 一種設備，其包括：一第一碳基介面層；及一碳基電阻率切換材料，其毗鄰該第一碳基介面層；其中該第一碳基介面層包括經氮化碳基材料。 15. 如請求項14之設備，其中該第一碳基介面層具有大於該碳基電阻率切換材料之Sp3鍵濃度之一 Sp3鍵濃度。 16. 如請求項14之設備，其中該第一碳基介面層具有大於該碳基電阻率切換材料之密度之一密度。 1 7 ·如請求項14之設備，其進一步包括紕鄰該碳基電阻率切 141458.doc -2 - 201007942 且其中該碳基電阻率切換材二介面層之間。換材料之一第二碳基介面層料係在該第一介面層與該第 18. 如吻求項17之設備’其進一步包括毗鄰該第一介面層之一第—導電層及鄰該第二介面層之—第二導電層。 19. 如明求項14之設備，其中該經氮化碳基材料係該碳基電阻率切換材料之一部分。 20. —種用於形成一記憶體單元之方法，其包括：201007942 VII. Patent application scope: 1 . A memory unit, comprising: a first conductor; a reversible resistance switching element formed on the first conductive reversible resistance switching element, comprising: switching a material with a carbon-based resistivity; And a carbon-based interface layer coupled to the carbon-based resistivity switching device, formed on the first conductor, and a second conductor formed over the reversible resistance-switching element and the guiding element . 2. A memory cell of a request heart, wherein the interface layer has a _sp3 bond concentration greater than a sp3 bond concentration of the breakage resistivity switching material. 3. The memory cell of claim i, wherein the interface layer has a density greater than a density of the carbon-based resistivity switching material. 4. The memory unit of claim 1 wherein the carbon based interface layer comprises a carbon nitride based material. 5·= the memory unit of the 'where the interface layer has a thickness of about 5 angstroms or less. The memory unit of I Si item 1 further comprising: a second carbon-based interface layer lightly coupled to the carbon-based switching material and wherein the carbon-based resistor is dry: the replacement material is in the first interface layer and the first Between the two interface layers. 7. The memory unit of claim 6, further comprising a second conductive layer and a second conductive layer of the second interface layer. 141458.doc 201007942 8. The memory of claim 1 _ ^ ^ 0 疋, wherein the carbon-based interface layer comprises an amorphous ▲ main broad carbon-based resistivity switching material comprising a carbon nanotube. 9. A memory cell such as π, wherein the one or more of the resistivity switching materials comprise one or more of graphene-containing graphene and carbon nanotubes. For example, the π reciprocal unit of π, wherein the guiding element comprises a diode. 11. An apparatus comprising: a carbon-based interface layer; and a ruthenium-based resistivity switching material adjacent to the carbon-based interface layer; wherein the carbon-based interface layer is denser than the carbon-based resistivity switching material. 12. The apparatus of claim 1, wherein the carbon-based interface layer has a sp3 bond concentration greater than one of the Sp3 bond concentrations of the carbon-based resistivity switching material. 13. The apparatus of claim 1, wherein the carbon based interface layer comprises a carbon nitride based material. 14. An apparatus comprising: a first carbon-based interface layer; and a carbon-based resistivity switching material adjacent to the first carbon-based interface layer; wherein the first carbon-based interface layer comprises a carbon nitride-based material . 15. The device of claim 14, wherein the first carbon-based interface layer has a Sp3 bond concentration greater than one of the Sp3 bond concentrations of the carbon-based resistivity switching material. 16. The device of claim 14, wherein the first carbon-based interface layer has a density greater than a density of the carbon-based resistivity switching material. 17. The device of claim 14, further comprising a carbon-based resistivity cut 141458.doc -2 - 201007942 and wherein the carbon-based resistivity switch is between the two interface layers. a second carbon-based interface layer of the material in the first interface layer and the apparatus of the 18th item, which further comprises a first conductive layer adjacent to the first interface layer and adjacent to the first The second interface layer of the second interface layer. 19. The apparatus of claim 14, wherein the carbon nitride based material is part of the carbon based resistivity switching material. 20. A method for forming a memory unit, comprising:

在一基板上方形成一第一導體；在该第一導體上方形成一碳基介面層；毗鄰該碳基介面層形成一碳基電阻率切換材料；及在該碳基介面層及該碳基電阻率切換材料上方形成一第二導體。 21. 如請求項20之方法，其中形成該碳基介面層包括相對於该碳基電阻率切換材料之sp3鍵濃度增加該碳基介面層之一 sp3鍵濃度。 22. 如請求項21之方法，其中增加該sp3鍵濃度包括減小用來形成該碳基介面層之一處理溫度及相對於用來形成该碳基電阻率切換材料之PECVD製程增加用來形成該碳基介面層之一 PECVD製程之一電榮離子化組份中之至少一者0 23. 如請求項20之方法，其中形成該碳基介面層包括相纣於該碳基電阻率切換材料之密度增加該碳基介面層之一密度。 24. 如請求項23之方法，其中形成該碳基介面層包括減、一 141458.doc 201007942 沈積速率及相對於用來形成該碳基電阻率切換材料面離子轟擊增加用來形成該碳基介面層之表苗心表面離子蟲擊中之一者或多者。 25. 如請求項20之方法，其中形成該碳基介面層包括氮化該碳基介面層之至少一個表面。 26. 如請求項20之方法，其進一步包括毗鄰該碳基電阻率切換材料形成一第二碳基介面層，其中該碳基電阻率切換材料係在該等介面層之間。 ' 27. 如請求項20之方法，其中該碳基介面層及該碳基電阻率切換材料中之-者或多者包括含有石墨稀之非晶形碳、石墨稀及碳奈米管中之一者或多者。 28. 如請求項2〇之方法，其中在相同室中執行形成該碳基介面層及形成該碳基電阻率切換材料。 29. 如請求項20之方法，其進一步包括在該第一與第二導體之間形成一引導元件。 I41458.docForming a first conductor over a substrate; forming a carbon-based interface layer over the first conductor; forming a carbon-based resistivity switching material adjacent to the carbon-based interface layer; and the carbon-based interface layer and the carbon-based resistor A second conductor is formed over the rate switching material. 21. The method of claim 20, wherein forming the carbon-based interface layer comprises increasing a sp3 bond concentration of the carbon-based interface layer relative to a sp3 bond concentration of the carbon-based resistivity switching material. 22. The method of claim 21, wherein increasing the sp3 bond concentration comprises reducing a processing temperature used to form the carbon-based interface layer and increasing a PECVD process for forming the carbon-based resistivity switching material to form A method of claim 20, wherein the forming of the carbon-based interface layer comprises opposing the carbon-based resistivity switching material, wherein the carbon-based interface layer comprises at least one of the carbon-based ionization components. The density increases the density of one of the carbon-based interface layers. 24. The method of claim 23, wherein forming the carbon-based interface layer comprises subtracting a deposition rate of 141458.doc 201007942 and increasing the surface ion bombardment of the switching material used to form the carbon-based resistivity to form the carbon-based interface One or more of the surface seedlings on the surface of the seedlings. 25. The method of claim 20, wherein forming the carbon-based interface layer comprises nitriding at least one surface of the carbon-based interface layer. 26. The method of claim 20, further comprising forming a second carbon-based interposer adjacent the carbon-based resistivity switching material, wherein the carbon-based resistivity switching material is between the interfacial layers. 27. The method of claim 20, wherein one or more of the carbon-based interface layer and the carbon-based resistivity switching material comprises one of amorphous carbon, graphite thin, and carbon nanotubes containing graphite thin Or more. 28. The method of claim 2, wherein forming the carbon-based interposer and forming the carbon-based resistivity switching material is performed in the same chamber. 29. The method of claim 20, further comprising forming a guiding element between the first and second conductors. I41458.doc