TW201007926A - Semiconductor device for electrostatic discharge protection - Google Patents

Semiconductor device for electrostatic discharge protection Download PDF

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Publication number
TW201007926A
TW201007926A TW097151294A TW97151294A TW201007926A TW 201007926 A TW201007926 A TW 201007926A TW 097151294 A TW097151294 A TW 097151294A TW 97151294 A TW97151294 A TW 97151294A TW 201007926 A TW201007926 A TW 201007926A
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Taiwan
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semiconductor device
type
protection semiconductor
esd protection
well
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TW097151294A
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Chinese (zh)
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TWI440161B (en
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Chiu-Chih Chiang
Han-Chung Tai
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System General Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/7436—Lateral thyristors

Abstract

A semiconductor device for electrostatic discharge protection is disclosed, and at least comprises a high-voltage parasite silicon controlled rectifier (HVSCR) and a diode. The HVSCR has an anode and a cathode, and the cathode of HVSCR is coupled to a ground. The diode, coupled to the HVSCR in series, also has an anode and a cathode. The anode of the diode is coupled to the anode of the HVSCR, and the cathode of the diode is coupled to a terminal applied with a positive voltage. The diode has a second conductivity type zone that could be constructed to form several strips or small blocks spaced apart from each other. Those small blocks could be any shapes and arranged regularly or randomly.

Description

201007926201007926

X WHO/ZrA 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種靜電放電防護半導體裝置，且特 別是有關於一種用以保護於高電壓下操作之電子設備之 積體電路之靜電放電防護半導體裝置。 【先前技術】 一般來說，積體電路（integrated circuits，ICs)非常 _容易受靜 電放電（electrostatic discharge, ESD)之影響而 受損’例如是電子設備中的高壓瞬變。在某些電子設備 中’高壓瞬變可能具有正值及/或負值之尖峰，範圍由數百 伏特至數千伏特（靜電壓），且時間長達數微秒。高電壓 靜電放電瞬變可能由使用者之靜電放電所造成，例如是由 摩擦力或感應並接觸積體電路（例如是設備控制）之端子 或電路之設備機殼所造成。因此，由於疏忽所造成之靜電 電壓可能導致輸入電晶體之毀損。 ® 積體電路通常都需要靜電放電防護設計以保護内部 的電子元件。一種典型的靜電放電防護係將寄生矽控整流 器（silicon controlled rectifier, SCR)連接至輸入電晶體之 閘極。矽控整流器通常係做為高效靜電放電防護箝，且矽 控整流器防護結構已於美國專利字號4,400,711、 4,405,933、4,631，567及4,692,781中所揭露。此些砍控整 流器防護結構主要之優點為具有吸收高能量之能力。 高電壓發控整流器（high-voltage silicon controlled 201007926X WHO/ZrA IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to an electrostatic discharge protection semiconductor device, and more particularly to an integrated circuit for protecting an electronic device operating at a high voltage. Electrostatic discharge protection semiconductor device. [Prior Art] In general, integrated circuits (ICs) are very susceptible to damage due to electrostatic discharge (ESD), such as high voltage transients in electronic equipment. In some electronic devices, high voltage transients may have positive and/or negative spikes ranging from hundreds of volts to thousands of volts (static voltage) for as long as several microseconds. High Voltage Electrostatic discharge transients can be caused by the user's electrostatic discharge, such as by friction or by the device housing that senses and contacts the terminals of the integrated circuit (for example, device control) or the circuit. Therefore, the electrostatic voltage caused by negligence may cause damage to the input transistor. ® integrated circuits typically require an ESD protection design to protect internal electronic components. A typical ESD protection system connects a parasitic silicon-controlled rectifier (SCR) to the gate of an input transistor.矽 整流 整流 通常 通常 通常 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The main advantage of these cut-control rectifier protection structures is their ability to absorb high energy. High voltage control rectifier (high-voltage silicon controlled 201007926

TW4672FA rectifier, HVSCR)係用以保護電子設備之積體電路於高電 壓（例如是30伏特或是更高之電壓）下操作而不受損害。 第1圖繪示高電壓矽控整流器之典型電流一電壓曲線。第 1圖中，點A代表崩潰電麼（breakdown voltage )，點B代 表保持電壓（holding voltage )。然而，在一些特定之應用 中，例如在高電壓下操作之電子設備，需使用具有較高崩 潰電壓及保持電壓之靜電放電防護裝置，方能適當地發揮 其防護效果。 【發明内容】 本發明係有關於一種靜電放電防護半導體裝置，且特 別是有關於一種用以保護於高電壓下操作之電子設備之 積體電路之裝置。 本發明之一實施例係提供一種靜電放電防護裝置。此 裝置至少包括一高電壓寄生矽控整流器（high-voltage parasite silicon controlled rectifier，HVSCR)及一二極體。 高電壓碎控整流器具有陽極及陰極，且高電壓石夕控整流器 之陰極係為接地。以串聯方式耦接至高電壓矽控整流器之 二極體亦具有陽極與陰極。二極體之陽極係耦接至高電壓 矽控整流器之陽極’且二極體之陰極係耦接至一施加有正 電壓之端子。 本發明提供另一種靜電放電防護半導體裝置，包括一 寄生矽控整流器及一二極體’形成於第二導電態基板中， 且二極體以串聯方式耦接至發控整流器。梦控整流器至少 201007926TW4672FA rectifier, HVSCR) is used to protect the integrated circuit of electronic equipment from high voltage (for example, voltage of 30 volts or higher) without damage. Figure 1 shows a typical current-voltage curve for a high voltage voltage controlled rectifier. In Figure 1, point A represents the breakdown voltage and point B represents the holding voltage. However, in some specific applications, such as an electronic device operating at a high voltage, an electrostatic discharge protection device having a high breakdown voltage and a holding voltage is required to properly exert its protective effect. SUMMARY OF THE INVENTION The present invention is directed to an electrostatic discharge protection semiconductor device, and more particularly to an apparatus for protecting an integrated circuit of an electronic device that operates at a high voltage. One embodiment of the present invention provides an electrostatic discharge protection device. The device includes at least a high-voltage parasite silicon controlled rectifier (HVSCR) and a diode. The high voltage shredder rectifier has an anode and a cathode, and the cathode of the high voltage rock-controlled rectifier is grounded. The diode coupled in series to the high voltage step-controlled rectifier also has an anode and a cathode. The anode of the diode is coupled to the anode of the high voltage step-controlled rectifier and the cathode of the diode is coupled to a terminal to which a positive voltage is applied. The present invention provides another ESD protection semiconductor device comprising a parasitic 矽-controlled rectifier and a diode formed in a second conductive substrate, and the diodes are coupled in series to the control rectifier. Dream-controlled rectifier at least 201007926

i w峙o/zrA 包括數個第一及第二導電態摻雜區域’此些第一及第二導 電態摻雜區域係交錯且連續地形成於第一導電態之第一 井中。第二導電態換雜區域係為接地’且配置於兩個第一 導電態摻雜區域之間。三個摻雜區域係與第一井相隔且形 成於第二導電態基板中。二極體包括第二導電態區域及第 一導電態摻雜區域。第二導電態區域係形成於第一導電態 之第二井中，且第二導電態區域係耦接至第一井中之第一 導電態摻雜區域之一。此外，二極體之第一導電態摻雜區 ❹域係形成於第一導電態之第二井中且與第二導電態區域 相隔。第一導電態摻雜區域係連接至一施加有正電壓之端 子。在實施例中，第一及第二導電態可為N型及P型。 此外，在實施例中，二極體之第二導電態區域可建構 成具有彼此相隔之複數個長條或小區塊。此些小區塊可為 任意形狀且規則地或隨機地排列。 為讓本發明之上述内容能更明顯易僅，下文特舉較佳 實施例’並配合所附圖式，作詳細說明如下： ❷ 【實施方式】 本發明提供之靜電放電（electrostatic discharge，ESD) 防護半導體裝置係適合用以保護於高電壓下操作之電子 設備之積體電路。第2圖緣示本發明之靜電放電防護半導 體裝置。靜電放電防護半導體裝置10至少包括一高電壓 寄生石夕控整流器（high-voltage parasite silicon controlled rectifier) 11及一二極體12。二極體12之陰極121係耦接 201007926 TW4672FA 至施加有高電壓之端子Μ ’且二極體12之陽極123係麵 接至高電壓石夕控整流器11之陽極112。高電壓矽控整流器 11之陰極114係耦接至沒有施加電壓之接地端子16。與 使用單獨之高電壓矽控整流器之靜電放電防護裝置相 較’本發明之半導體裝置10 (亦即包括高電壓矽控整流器 及二極體）之崩潰電壓（breakdown voltage)及保持電壓 (holding voltage)有顯著的增加’且半導體裝置可適 當地做為於高電壓（例如是超過30伏特）下操作之電子 設備之防護裝置。 以下提供二實施例以說明本發明之靜電放電防護半 導體裝置。此些實施例說明二極體及高電壓碎控整流器之 間之電子連接。此外’此些實施例亦說明本發明之二極體 結構之不同的可實施設計。然而，此處揭露之實施例係用 以說明本發明，而非用以限制本發明之範圍。 再者，本發明所屬技術領域中具有通常知識者當可明 白本發明之基本的技術，例如是P型井、p型區域、N型 井、N型區域、深N型井及N型埋藏層（buried iayer)等 之形成，因而不詳細敘述。此外，本發明所屬技術領域中 具有通常知識者當可明白此些實施例及圖式中之高電壓 矽控整流器的結構在本發明之精神下可稍做修改。因此， 圖式及說明係視為說明之用’而非限制本發明之範圍。用 以說明本發明之此些實施例及應用之圖式僅緣示主要之 特徵元件，以避免混淆本發明。 201007926i w峙o/zrA includes a plurality of first and second conductive state doped regions. The first and second conductive doped regions are staggered and continuously formed in the first well of the first conductive state. The second conductive state change region is grounded and disposed between the two first conductive state doped regions. The three doped regions are spaced apart from the first well and formed in the second conductive state substrate. The diode includes a second conductive state region and a first conductive state doped region. The second conductive state region is formed in the second well of the first conductive state, and the second conductive state region is coupled to one of the first conductive state doped regions in the first well. In addition, the first conductive state doped region of the diode is formed in the second well of the first conductive state and spaced apart from the second conductive region. The first conductive state doped region is connected to a terminal to which a positive voltage is applied. In an embodiment, the first and second conductive states can be N-type and P-type. Moreover, in an embodiment, the second conductive region of the diode can be constructed to have a plurality of strips or blocks separated from one another. Such blocks may be of any shape and arranged regularly or randomly. In order to make the above description of the present invention more obvious, the following detailed description of the preferred embodiment 'with the accompanying drawings will be described in detail as follows: ❷ Embodiments The present invention provides an electrostatic discharge (ESD). The protective semiconductor device is suitable for an integrated circuit for protecting an electronic device that operates at a high voltage. Fig. 2 shows the electrostatic discharge protection semiconductor device of the present invention. The ESD protection semiconductor device 10 includes at least a high-voltage parasite silicon controlled rectifier 11 and a diode 12. The cathode 121 of the diode 12 is coupled to the 201007926 TW4672FA to the terminal Μ' to which the high voltage is applied, and the anode 123 of the diode 12 is connected to the anode 112 of the high voltage rock-controlled rectifier 11. The cathode 114 of the high voltage step-controlled rectifier 11 is coupled to a ground terminal 16 to which no voltage is applied. The breakdown voltage and holding voltage of the semiconductor device 10 of the present invention (that is, including the high voltage step-controlled rectifier and the diode) compared to the electrostatic discharge protection device using a separate high voltage step-controlled rectifier There is a significant increase' and the semiconductor device can be suitably used as a guard for electronic devices operating at high voltages (eg, over 30 volts). Two embodiments are provided below to illustrate the electrostatic discharge protection semiconductor device of the present invention. These embodiments illustrate the electrical connections between a diode and a high voltage shredder. Further, these embodiments also illustrate different implementable designs of the diode structure of the present invention. However, the embodiments disclosed herein are intended to illustrate the invention and are not intended to limit the scope of the invention. Furthermore, those having ordinary skill in the art to which the present invention pertains can understand the basic techniques of the present invention, such as a P-type well, a p-type region, an N-type well, an N-type region, a deep N-type well, and an N-type buried layer. (buried iayer) and the like are formed, and thus will not be described in detail. In addition, it is obvious to those skilled in the art that the structure of the high voltage step-controlled rectifier in these embodiments and the drawings can be slightly modified in the spirit of the present invention. Accordingly, the drawings and description are to be regarded as illustrative rather The drawings which illustrate the embodiments and applications of the present invention are merely illustrative of the main features in order to avoid obscuring the invention. 201007926

1 WH〇/zrA 第一實施你 l 第3A圖繪示根據本發明之第一實施例之靜電放電防 護半導體裝置之上視圖。第3B圖繪示第3A圖之半導體裝 置沿著剖面線3A-3A之剖面圖。 如第3A圖所示，高電壓矽控整流器31係耦接於二 極體32。一般來說，二極體包括形成於一正N型井中之 一正P型區’且正P型區及正N型井間之介面會發生接面 崩潰（junction breakdown)。此外，接面崩潰首先發生於 ❷正P型區及正N型井間之介面之邊緣（由於尖端放電效 應）。因此，為了增加邊緣數目，本發明之第一實施例之 二極體32之正p型區係設計為數個正p型條323,且此些 正P型條係彼此相隔並實質上平行設置。對每一個正p型 條323而言，接面崩潰首先發生在靠近區域323a之邊緣， 區域323a係圍繞正P型條323之兩端。 第3B圖繪示第3A圖之半導體裝置沿著剖面線 3A-3A之剖面圖。如第3B圖所示，靜電放電防護半導體 ®裝置至少包括形成於基板30中之高電壓矽控整流器31及 二極體32 〇 高電壓矽控整流器31至少包括數個第一導電態摻雜 區域（first conductivity type doping region ) (312a/312b/312c)及第二導電態摻雜區域（second conductivity type doping region) ( 313a/313b)’ 第一導電態 摻雜區域及第二導電態摻雜區域係交錯且連續地形成於 第一導電態之第一井311中。另外，高電壓矽控整流器之 9 2010079261 WH〇/zrA First Embodiment You Fig. 3A is a top view showing an electrostatic discharge protection semiconductor device according to a first embodiment of the present invention. Figure 3B is a cross-sectional view of the semiconductor device of Figure 3A taken along section line 3A-3A. As shown in Fig. 3A, the high voltage step-controlled rectifier 31 is coupled to the diode 32. Generally, the diode includes a positive P-type region formed in a positive N-type well and a junction breakdown occurs between the interface between the positive P-type region and the positive N-type well. In addition, the junction collapse first occurred at the edge of the interface between the positive P-type zone and the positive N-type well (due to the tip discharge effect). Therefore, in order to increase the number of edges, the positive p-type region of the diode 32 of the first embodiment of the present invention is designed as a plurality of positive p-type strips 323, and the positive P-type strips are spaced apart from each other and disposed substantially in parallel. For each positive p-strip 323, junction collapse occurs first near the edge of region 323a, which surrounds both ends of positive P-strip 323. Figure 3B is a cross-sectional view of the semiconductor device of Figure 3A taken along section line 3A-3A. As shown in FIG. 3B, the ESD protection semiconductor device includes at least a high voltage step-controlled rectifier 31 and a diode 32 formed in the substrate 30. The high voltage step-controlled rectifier 31 includes at least a plurality of first conductive state doped regions. (first conductivity type doping region ) (312a/312b/312c) and a second conductivity type doping region (313a/313b)' first conductive state doped region and second conductive state doped region The first well 311 is formed in a first conductive state in a staggered and continuous manner. In addition, the high voltage voltage controlled rectifier 9 201007926

1W4672FA 第一井311中之第二導電態摻雜區域（313a/313b)係彼此 耦接。高電壓矽控整流器31更包括第二導電態摻雜區域 315，且第二導電態摻雜區域315係連接至接地端子及兩 個第一導電態摻雜區域（317a/317b)。其中第二導電態摻 雜區域315係配置於第一導電態摻雜區域317&及317b之 間。高電壓矽控整流器31之第一導電態摻雜區域317a及 317b係與第一井311相隔，且第一導電態摻雜區域317a 及317b係彼此柄接。形成於基板3〇中之摻雜區域315、 317a及317b係相隔於第一井311，並位於第一井311之外。 本發明之第一導電態及第二導電態分別為N型及p 型。因此’第一井311係為N型井，摻雜區域312a、312b、 312c、317a及317b為正N型區域，且摻雜區域313a、313b 及315為正P型區域。本實施例之基板3〇係為第二導電 態，也就是P型（以下稱P型基板）。 二極體32係形成於P型基板30中且以串聯方式輪接 於高電壓矽控整流器31。二極鱧32具有形成於第一導電 態（亦即N型）之第二井321中之第二導電態區域（亦即 P型），且第二導電態區域係耦接至第一井311中之第一導 電態摻雜區域（312a/312b/312c)之一。根據第一實施例， -—極體32之第二導電態區域包括數個正p型條323以產 生更多接面崩潰邊緣，且此些正P型條323並非連續形 成。每一個正P型條323係電性連接至一端子τ，且端子 T係耦接至第一井311中之第一導電態摻雜區域312b。 第4圖緣示根據本發明之第一實施例之靜電放電防 201007926 護半導體裝置之特性曲線，此裝置包括高電壓矽控整流器 及二極體，且二極體包括數個正Ρ型條。第4圖中，點C 代表崩潰電壓，點D代表保持電壓。此外，半導體裝置之 保持電流（holding current)係根據L1線之斜率所決定的。 與僅使用高電壓矽控整流器做為防護之靜電放電裝置相 較’第二實施例之半導體裝置（亦即高電壓矽控整流器及 二極體）之崩潰電壓及保持電壓較高，使得此裝置適合做 為於高電壓下操作之電子設備之防護裝置。 -第二實施例 第5圖繪示本發明之第二實施例之靜電放電防護半 導體裝置之上視圖。第5圖之半導體裝置沿著剖面線5_5 之剖面圖係與第3B圖相同。第二實施例之半導體裝置係 相似於第一實施例之半導體裝置。請同時參照第3B圖及 相關圖式以了解裝置結構之詳細說明。第一實施例及第二 _實施例之結構差異在於二極體之第二導電態區域之設計。 第一實施例中，半導體32之第二導電態區域係形成 為數個長條，例如是如第3A圖所示之正ρ型條323。第 一實施例中，半導體52之第二導電態區域可形成數個彼 此相隔之小區塊（例如是具有正方形剖面之區塊521 )。其 中T區塊共同耦接至第一井中之第一導電態摻雜區域（例 如疋第一井311中之區域312b)。第二實施例中，此些小 區塊可為任何形狀且為規則或隨機地排列。可了解的是’ 其形狀及排列方式可依照實施之應用及製程能力而修改。 11 201007926 右圖所示’每—個小區塊521 (jEp型區塊）具 i實質上為正方形剖面。此外，小區塊521 係排列為矩陣。 數偭根3二實施例’二極體52之第二導電態區域包括 用以形成更多數量的接㈣潰邊緣。 之二二=潰邊緣的數量，本發明《第二實施例 ❹ 此此正ΡΦΙ丨似計為數個正Pl!小區塊521。 靠^域5^521係彼此相隔。接面崩潰首先發生於 5== I緣，且區域灿係包圍正Ρ型小區塊 型小£塊521 Μ圖）之設計相較，正Ρ 四個邊都可迅訴產生接面崩潰)，：::(即小區㈣ 具有低阻抗之靜電放電㈣半導 ^—_之阻抗。 爭力。 置可具有相當之競 第6圖繪示第5圖中之本發 電防護半導體裝置之特性曲線。此—實施例之靜電放 流器及二極體，且二極體包括數個具置包括高電壓矽控整 型小區塊。第6圖中，點Ε代表泉有正方形剖面之正ρ 電堡。此外，半導體裝置之保持電;^ = 表保持 所決定的。L2線之斜率代表二極 很據L2線之斜率 總阻抗。 尚電壓矽控整流器之 電堡。此外，半導體裝置之保持電 所決定的。L2德之斜鱼你主______及係、根據 總阻抗 請參照第4圖及第6圖。與第_ 之正Ρ型條323)之靜電放電裝置相實施例（二極體32 極體52之正Ρ型小區塊521) 二較’第二實施例（二 靜電玫電裝置之崩潰電麗 12 201007926The second conductive state doped regions (313a/313b) of the 1W4672FA first well 311 are coupled to each other. The high voltage step-controlled rectifier 31 further includes a second conductive state doped region 315, and the second conductive state doped region 315 is connected to the ground terminal and the two first conductive state doped regions (317a/317b). The second conductive state doped region 315 is disposed between the first conductive doped regions 317 & and 317b. The first conductive state doped regions 317a and 317b of the high voltage step-controlled rectifier 31 are spaced apart from the first well 311, and the first conductive state doped regions 317a and 317b are stalked to each other. The doped regions 315, 317a, and 317b formed in the substrate 3 are spaced apart from the first well 311 and are located outside the first well 311. The first conductive state and the second conductive state of the present invention are N-type and p-type, respectively. Therefore, the first well 311 is an N-type well, the doped regions 312a, 312b, 312c, 317a, and 317b are positive N-type regions, and the doped regions 313a, 313b, and 315 are positive P-type regions. The substrate 3 of the present embodiment is in a second conductive state, that is, a P-type (hereinafter referred to as a P-type substrate). The diode 32 is formed in the P-type substrate 30 and is connected in series to the high voltage step-controlled rectifier 31. The diode 52 has a second conductive region (ie, P-type) formed in the second well 321 of the first conductive state (ie, N-type), and the second conductive region is coupled to the first well 311. One of the first conductive state doped regions (312a/312b/312c). According to the first embodiment, the second conductive state region of the - body 32 includes a plurality of positive p-type strips 323 to create more junction collapse edges, and such positive P-type strips 323 are not continuously formed. Each positive P-type strip 323 is electrically connected to a terminal τ, and the terminal T is coupled to the first conductive state doped region 312b in the first well 311. Fig. 4 is a view showing the characteristic curve of the electrostatic discharge prevention 201007926 semiconductor device according to the first embodiment of the present invention. The device includes a high voltage step-controlled rectifier and a diode, and the diode includes a plurality of positive strips. In Figure 4, point C represents the breakdown voltage and point D represents the hold voltage. Further, the holding current of the semiconductor device is determined based on the slope of the L1 line. Compared with the electrostatic discharge device using only the high voltage voltage-controlled rectifier as the protection, the breakdown voltage and the holding voltage of the semiconductor device of the second embodiment (that is, the high voltage voltage-controlled rectifier and the diode) are higher, so that the device Suitable as a protective device for electronic equipment operating at high voltages. - Second Embodiment Fig. 5 is a top view showing an electrostatic discharge protection semiconductor device of a second embodiment of the present invention. The cross-sectional view of the semiconductor device of Fig. 5 along the section line 5_5 is the same as that of Fig. 3B. The semiconductor device of the second embodiment is similar to the semiconductor device of the first embodiment. Please refer to Figure 3B and related diagrams for a detailed description of the structure of the unit. The structural difference between the first embodiment and the second embodiment is the design of the second conductive region of the diode. In the first embodiment, the second conductive region of the semiconductor 32 is formed as a plurality of strips, such as a positive p-type strip 323 as shown in Fig. 3A. In the first embodiment, the second conductive region of the semiconductor 52 can form a plurality of blocks that are spaced apart from each other (e.g., block 521 having a square cross-section). The T block is commonly coupled to the first conductive state doped region in the first well (e.g., the region 312b in the first well 311). In the second embodiment, such small blocks may be of any shape and arranged regularly or randomly. It will be appreciated that the shape and arrangement may be modified in accordance with the application and process capabilities of the application. 11 201007926 The right block 521 (jEp type block) shown in the right figure has a substantially square cross section. Further, the cell blocks 521 are arranged in a matrix. The second conductive region of the diode 52 includes a plurality of junctions for forming a plurality of junctions. Twenty-two = the number of broken edges, the second embodiment of the present invention ❹ This is exactly Φ Ι丨 is counted as a number of positive Pl! cell blocks 521. The domain 5^521 is separated from each other. The junction collapse occurs first in the 5== I edge, and the design of the area can surround the positive block type block type small block 521 Μ ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ::: (ie, the cell (4) has a low-impedance electrostatic discharge (four) semi-conductance ^ - _ impedance. The competing force can be compared with the characteristic curve of the power generation protection semiconductor device in FIG. The electrostatic discharge device and the diode of the embodiment, and the diode includes a plurality of blocks including a high voltage 矽 control unit. In Fig. 6, the point Ε represents a positive ρ electric castle with a square profile. In addition, the semiconductor device maintains electricity; ^ = the table is determined by the hold. The slope of the L2 line represents the total impedance of the slope of the two poles according to the L2 line. The voltage is also controlled by the electric rectifier of the rectifier. In addition, the holding capacity of the semiconductor device is determined. L2 De slanted fish your main ______ and system, according to the total impedance, please refer to Figure 4 and Figure 6. The electrostatic discharge device phase of the _ _ _ _ _ _ _ _ _ _ _ The positive body type block 521 of the polar body 52 is the second embodiment (the collapse of the second electrostatic rose device) Li 12,201,007,926

i W40 /2FA 及保持電壓之值較高，因此第二實施例之裝置適合做為於 局電壓下操作之電子設備之防護裝置。由於第二實施例之 裝置具有較大之接面崩潰面積（亦即具有更多接近區域 521R之邊緣）’因而降低了二極體之阻抗，使得L2線之 斜率大於U線之斜率。因此，第二實施例之半導體裝置 之保持電流南於第-實施例之半導體裝置之保持電流。在 實際應用時’如此具有高保持電流之靜電放電防護半導體 裝置，其保持電流係較佳地超過内部/外部電流能力 ❹（晴ent source capability) ’以達到優良的靜電”二防護效 果。 一極體52之做為第二導電態區域之正p型小區塊之 其他種可實施之形狀及排列方式係繪示於第7圖至第1〇 圖。然而，本發明並不以此為限。本發明所屬技術領域中 具有通常知識者當可更動本發明所揭露之小區塊之形狀 或排列方式。 第7圖繪示依照本發明之第二實施例之靜電放電防 ❹護半導體裝置之上視圖。如第7圖所示，二極體包括數個 具有實質上為正方形剖面形狀之第二導電態（例如是正p 型）小區塊621 (形成於第二井321中），且小區塊621係 排列為平行之數行。每一行/列之正P型小區塊621係彼此 相隔’且相鄰行/列之正p塑小區塊621亦彼此相隔。每一 個正P型小區塊621係類似島狀，不與其他區塊相連。 第8圖繪示依照本發明之第二實施例之另一種靜電 放電防護半導體裝置之上視圖。如第8圖所示，二極體包 13 201007926 括具有實質上為正方形之剖面形狀之正卩型小區塊Mi (形成於第二井321中），且正Ρ型小區塊721係排列為 平订之數行。每-行之正ρ型小區塊721彼此相隔，且相 鄰行之正Ρ型小區塊721係彼此相隔。此外，每一行之正 ρ型小區塊721與相鄰行之正Ρ型小區塊係實質上交錯排 列，且正Ρ型小區塊721之角落可與其他區塊相接。如第 8圖所不，此些小區塊係排列為棋盤狀圖案。 第9圖繪示依照本發明之第二實施例之另一種 放電防護半導體裝置之上視圖。如第9圖所示，二極體包 括具有實質上為正方形之剖面形狀之正Ρ型小區塊821 第二：321中)，且正ρ型小區塊821係排列為 十二之數订。每-行之正ρ型小區塊821彼此鄰接且相 鄰行之正Ρ型小區塊821係彼此相隔。此外，每一行之正 Ρ型小區塊821與相鄰行之正ρ型小區塊係實質上交錯 列。 第10圖繪示依照本發明之第二實施例之另一種靜電 放電防護半導體裝置之上視圖。如第1G圖所示，二極體 包括具有數個剖面形狀實質上為菱形之正Ρ型小區塊921 j形成於第二井321中）。正Ρ型小區塊921係排列為平 订^數行。每一行之正P型小區塊921係彼此相隔，且相 鄰行之正ρ型小區塊921亦彼此相隔。此外，每一行之正 P型小區塊921與相鄰行之正p型小區塊係實質上交錯排 列0 除了第3A圖、第5圖及第7圖至第10圖之圖案之 201007926The value of i W40 /2FA and the holding voltage is high, so the apparatus of the second embodiment is suitable as a guard for electronic equipment operating at a local voltage. Since the apparatus of the second embodiment has a large junction collapse area (i.e., has more edges near the region 521R), the impedance of the diode is lowered, so that the slope of the L2 line is larger than the slope of the U line. Therefore, the holding current of the semiconductor device of the second embodiment is higher than the holding current of the semiconductor device of the first embodiment. In practical applications, the electrostatic discharge protection semiconductor device having such a high holding current maintains a current system that preferably exceeds the internal/external current capability to achieve excellent electrostatic protection. Other shapes and arrangements of the positive p-type block of the body 52 as the second conductive state region are shown in Figures 7 to 1 . However, the present invention is not limited thereto. The shape or arrangement of the cell block disclosed in the present invention can be modified by those skilled in the art. FIG. 7 is a top view of the electrostatic discharge protection semiconductor device according to the second embodiment of the present invention. As shown in FIG. 7, the diode includes a plurality of second conductive state (for example, positive p-type) cell block 621 (formed in the second well 321) having a substantially square cross-sectional shape, and the cell block 621 is The rows are arranged in parallel. The positive P-type cell blocks 621 of each row/column are separated from each other and the adjacent rows/columns of positive p-plastic cells 621 are also separated from each other. Each positive P-type cell block 621 is similar to an island. shape Figure 8 is a top view of another electrostatic discharge protection semiconductor device in accordance with a second embodiment of the present invention. As shown in Figure 8, the diode package 13 201007926 includes substantially A square-shaped block Mi (formed in the second well 321) having a square cross-sectional shape, and the positive-type block 721 is arranged in a number of rows. The positive-p-cell blocks 721 of each row are separated from each other. And the positive-row type cell blocks 721 of the adjacent rows are separated from each other. In addition, the positive p-type cell block 721 of each row and the positive-row type cell block of the adjacent row are substantially staggered, and the positive-type cell block 721 The corners may be connected to other blocks. As shown in Fig. 8, the cell blocks are arranged in a checkerboard pattern. Fig. 9 is a view showing another discharge protection semiconductor device according to the second embodiment of the present invention. As shown in Fig. 9, the diode includes a positive-shaped cell block 821 having a substantially square cross-sectional shape (second: 321), and the positive p-type cell block 821 is arranged in a number of twelve Each positive ρ-type cell block 821 is adjacent to each other and adjacent to each other The type cell blocks 821 are spaced apart from each other. In addition, each row of the positive cell block 821 and the adjacent row of positive p type cell blocks are substantially staggered. FIG. 10 is a diagram showing another embodiment according to the second embodiment of the present invention. A top view of an ESD protection semiconductor device. As shown in FIG. 1G, the diode includes a positive-type cell block 921 j having a plurality of cross-sectional shapes substantially in a diamond shape formed in the second well 321). The cell block 921 is arranged in a flat order row. The positive P-type cell blocks 921 of each row are separated from each other, and the positive p-type cell blocks 921 of adjacent rows are also separated from each other. In addition, each row of positive P-type cell blocks 921 and adjacent rows of positive p-type cell blocks are substantially staggered 0 except for the patterns of 3A, 5, and 7 to 10; 201007926

i ww/^rA 外’第二實施例之小區塊亦可 他可實施之圖案。再者，小c狀、細胞狀或其 例如是圓形剖面、蜂巢狀剖面妹2不同之剖面形狀， 此些實施例與此處揭露之内容僅，幾何形狀之剖面。 制本發明之範圍。 之用’而非用以限 之敘述，本發明之靜電放電i ww / ^ rA outside the cell block of the second embodiment may also be a pattern that can be implemented by him. Further, the small c shape, the cell shape or the cross-sectional shape of the circular cross-section and the honeycomb cross-section 2, for example, are only a cross-section of the geometry disclosed herein. The scope of the invention is made. The electrostatic discharge of the present invention is used instead of the limitation.

至少包括一尚電壓寄生矽控整流器及牛導體裝置 玫電防護半導體I置具有高崩潰電壓及高保持=此= 此裝置適合用以保護於高電壓下操作之電子設備之積體 電路。此外，本發明之裝置之二極體之正p型區可較佳地 為形成於N型井中之數個正P型條或正？型小區塊用以 大幅增加接面崩潰邊緣之數量。當接面崩潰邊緣之數量越 多時，靜電放電防護半導體裝置之阻抗越低。 綜上所述，雖然本發明已以較佳實施例揭露如上，然 其並非用以限定本發明。本發明所屬技術領域中具有通常 知識者’在不脫離本發明之精神和範圍内，當可作各種之 更動與潤飾。因此，本發明之保護範圍當視後附之申請專 利範園所界定者為準。 15 201007926 A. T? —r\J I ΓΛ. 【圖式簡單說明】 第1圖繪示高電壓矽控整流器之典型電流一電壓曲 線； 第2圖繪示本發明之靜電放電防護半導體裝置； 第3A圖繪示根據本發明之第一實施例之靜電放電防 護半導體裝置之上視圖； 第3B圖繪示第3A圖之半導體裝置沿著剖面線 3A-3A之剖面圖； 第4圖繪示根據本發明之第一實施例之靜電放電防 護半導體裝置之特性曲線，此裝置包括高電壓矽控整流器 及二極體，且二極體包括數個正P型條； 第5圖繪示本發明之第二實施例之靜電放電防護半 導體裝置之上視圖； 第6圖繪示第5圖中之本發明之第二實施例之靜電放 電防護半導體裝置之特性曲線，此裝置包括高電壓矽控整 流器及二極體，且二極體包括數個具有矩形剖面之正P型 小區塊； 第7圖繪示依照本發明之第二實施例之另一種靜電 放電防護半導體裝置之上視圖； 第8圖繪示依照本發明之第二實施例之另一種靜電 放電防護半導體裝置之上視圖； 第9圖繪示依照本發明之第二實施例之另一種靜電 放電防護半導體裝置之上視圖；以及 第10圖繪示依照本發明之第二實施例之另一種靜電 201007926 1 ννΗ·〇/Ζ.Γ/\ 放電防護半導體裝置之上視圖。 【主要元件符號說明】 11 :高電壓寄生矽控整流器 12 :二極體 14:端子 16 :接地端子 112:高電壓寄生矽控整流器之陽極 〇 114 :高電壓寄生矽控整流器之陰極 121 :二極體之陰極 123 :二極體之陽極 30 :基板 31 :高電壓寄生矽控整流器 32 :二極體 52 :半導體 311 :第一井 ❿ 312a、312b、312c、317a 及 317b :正 Ν 型區域 313a、313b及135 :正P型區域 321 :第二井 323 :正P型條 323a :區域 521、621、721、821、921 :小區塊 521R :區域 17At least one voltage parasitic sigma-controlled rectifier and a bull-conductor device are provided. The galvanic protection semiconductor I has a high breakdown voltage and a high hold = this = This device is suitable for protecting integrated circuits of electronic devices operating at high voltages. Furthermore, the positive p-type region of the diode of the device of the present invention may preferably be a plurality of positive P-type strips or positively formed in the N-type well. The type of block is used to greatly increase the number of junction collapse edges. The greater the number of junction collapse edges, the lower the impedance of the ESD protection semiconductor device. In the above, the present invention has been disclosed in the above preferred embodiments, but it is not intended to limit the present invention. It will be apparent to those skilled in the art that the present invention can be modified and modified without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention is subject to the definition of the application patent specification. 15 201007926 A. T? —r\JI ΓΛ. [Simple description of the diagram] Figure 1 shows a typical current-voltage curve of a high voltage voltage-controlled rectifier; Figure 2 shows an electrostatic discharge protection semiconductor device of the present invention; 3A is a top view of the ESD protection semiconductor device according to the first embodiment of the present invention; FIG. 3B is a cross-sectional view of the semiconductor device of FIG. 3A along the section line 3A-3A; FIG. 4 is a view A characteristic curve of an ESD protection semiconductor device according to a first embodiment of the present invention, the device comprising a high voltage step-controlled rectifier and a diode, and the diode comprises a plurality of positive P-type strips; and FIG. 5 illustrates the present invention 2 is a top view of the ESD protection semiconductor device of the second embodiment; FIG. 6 is a view showing a characteristic curve of the ESD protection semiconductor device of the second embodiment of the present invention in FIG. 5, the device comprising a high voltage step-controlled rectifier and a diode, and the diode includes a plurality of positive P-type cell blocks having a rectangular cross section; FIG. 7 is a top view of another electrostatic discharge protection semiconductor device according to a second embodiment of the present invention; FIG. 9 is a top view showing another electrostatic discharge protection semiconductor device according to a second embodiment of the present invention; and FIG. 10 is a top view; The figure shows a top view of another electrostatic 201007926 1 ννΗ·〇/Ζ.Γ/\ discharge protection semiconductor device in accordance with a second embodiment of the present invention. [Main component symbol description] 11: High voltage parasitic 矽 control rectifier 12: diode 14: terminal 16: ground terminal 112: high voltage parasitic 矽 controlled rectifier anode 〇 114: high voltage parasitic 矽 controlled rectifier cathode 121: two Cathode 123 of the polar body: anode 30 of the diode: substrate 31: high voltage parasitic controlled rectifier 32: diode 52: semiconductor 311: first well 312a, 312b, 312c, 317a and 317b: positively-shaped region 313a, 313b, and 135: positive P-type region 321: second well 323: positive P-type strip 323a: region 521, 621, 721, 821, 921: cell block 521R: region 17

Claims (1)

201007926 Λ. VT ~rvr / SmA. Λ. λ 十、申請專利範圍： 1. 一種靜電放電防護半導體裝置，包括·· 一寄生矽控整流器，至少包括： 複數個第一及第二導電態摻雜區域，交錯且連 續地形成於第一導電態之一第一井中；及 一第二導電態摻雜區域，係為接地並配置於兩 個第一導電態摻雜區域之間，該三個掺雜區域係與該第一 井相隔並形成於第二導電態之一基板中；以及 一二極體，形成於第二導電態之該基板中並以串聯方 _ 式耦接至該矽控整流器，該二極體包括： 一第二導電態區，形成於第一導電態之一第二 井中且耦接至該第一井中之該些第一導電態摻雜區域之 一；及 一第一導電態摻雜區域，形成於第一導電態之 該第二井中且與該第二導電態區域相隔，其中該第一導電 態推雜區係連接至施加有一正電壓之一端子。 2. 如申請專利範圍第1項所述之靜電放電防護半導 〇 體裝置，其中該二極體之該第二導電態區域包括彼此相隔 之複數個長條，該些長條係共同耦接至該第一井中之該些 第一導電態摻雜區域之一。 3. 如申請專利範圍第1項所述之靜電放電防護半導 體裝置，其中該二極體之該第二導電態區域包括彼此相隔 之複數個小區塊，且該些小區塊係共同耦接至該第一井中 之該些第一導電態摻雜區域之一。 18 201007926 1 W4072^A 4. 如申請專利範圍第3項所述之靜電放電防護半導 體裝置，其中每一該些小區塊具有一矩形剖面。 5. 如申請專利範圍第3項所述之靜電放電防護半導 體裝置，其中每一該些小區塊具有一菱形剖面。 6. 如申請專利範圍第3項所述之靜電放電防護半導 體裝置，其中每一該些小區塊具有一圓形剖面。 7. 如申請專利範圍第3項所述之靜電放電防護半導 體裝置，其中該些小區塊係排列為一矩陣。 ❿ 8.如申請專利範圍第3項所述之靜電放電防護半導 體裝置，其中該些小區塊係排列為一棋盤狀圖案。 9. 如申請專利範圍第3項所述之靜電放電防護半導 體裝置，其中該些小區塊係排列為一蜂巢狀圖案。 10. 如申請專利範圍第3項所述之靜電放電防護半導 體裝置，其中該些小區塊係分佈為一細胞狀圖案。 11. 如申請專利範圍第3項所述之靜電放電防護半導 體裝置，其中該些小區塊係排列為平行之複數行。 ® 12.如申請專利範圍第11項所述之靜電放電防護半 導體裝置，其中該些行中每一行之該些小區塊係與相鄰該 行之該些區塊係交錯配置。 13. 如申請專利範圍第11項所述之靜電放電防護半 導體裝置，其中該些行中每一行之該些小區塊係彼此鄰 接。 14. 如申請專利範圍第11項所述之靜電放電防護半 導體裝置，其中該些行中每一行之該些小區塊係彼此分 201007926 , 1 yr*rw /^rrrv 隔。 15. 如申請專利範圍第11項所述之靜電放電防護半 導體裝置，其中該第一及該第二導電態係分別為Ν型導電 態及Ρ型導電態。 16. 如申請專利範圍第1項所述之靜電放電防護半導 體裝置，其中該矽控整流器之該第一井中之該些第二導電 態摻雜區域係彼此耦接。 17. 如申請專利範圍第1項所述之靜電放電防護半導 體裝置，其中與該第一井相隔之該矽控整流器之該些第一 導電態摻雜區域係彼此耦接。 18. —種靜電放電防護半導體靜電放電防護半導體 裝置，包括·· 一高電壓寄生碎控整流器，包括一陽極與一陰極，該 高電壓矽控整流器之該陰極係為接地，·以及 一二極體’以串聯方式搞接至該高電壓石夕控整流器， 且該二極體包括一陽極與一陰極’該二極體之該陽極係麵 接至該高電壓矽控整流器之該陽極，且該二極體之該陰極 ❹ 係輕接至施加.有一正電壓之一端子。 19. 如申請專利範圍第18項所述之靜電放電防護半 導體裝置，其中該高電壓矽控整流器包括： 複數個Ν型及Ρ型摻雜區域，交錯且連續地形成於 一第一 Ν型井中。 20. 如申請專利範圍第19項所述之靜電放電防護半 導體裝置，其中該高電壓矽控整流器更包括： 20 201007926 1 ww/zr/\ 一 p型摻雜區域，配置於二個N型摻雜區域之間， 且該二個摻雜區域係與該第一井相隔且形成於一 p型美板 中，該P型摻雜區域係耦接至接地端。 21. 如申請專利範圍第2〇項所述之靜電放電防護 導體裝置’其中該二極體包括形成於一第型井中°之一 Ρ型區及一 Ν型摻雜區域。 22. 如申請專利範圍第21項所述之靜電放電防護半 導體裝置，其中該二極體之該ρ型區係耦接至該高電壓矽 ❹控整流器之該第一井中之該些Ν型掺雜區域之一。 23. 如申請專利範圍第21項所述之靜電放電防護半 導體裝置，其中一 Ν型摻雜區域係形成於該第二Ν型井中 且與該Ρ型區相隔。 24·如申請專利範圍第23項所述之靜電放電防護半 導體裝置’其中形成於該第型井中之該Ν型摻雜區域 係連接至施加有該正電壓之該端子。 25·如申請專利範圍第21項所述之靜電放電防護半 ❿導體裝置，其中該Ρ型區包括彼此相隔之複數個ρ型條， 且該些Ρ型條係共同耦接至該第一 Ν型井中之該些 換雜區域之一。 26·如申請專利範圍第21項所述之靜電放電防護半 導體裝置，其中該二極體之該ρ型區包括複數個彼此相隔 之Ρ型小區塊’且該些ρ型小區塊係共同耦接至該第一 Ν 型井中之該些Ν型摻雜區域之一。 27.如申請專利範圍第26項所述之靜電放電防護半 21 導體裝置，其中每一該些P型小區塊具有一矩形剖面。 28. 如申請專利範圍第26項所述之靜電放電防護半 導體裝置，其中每一該些P型小區塊具有一菱形剖面。 29. 如申請專利範圍第26項所述之靜電放電防護半 導體裝置，其中每一該些P型小區塊具有一圓形剖面。 30. 如申請專利範圍第26項所述之靜電放電防護半 導體裝置，其中該些P型小區塊係排列為一矩形。 31. 如申請專利範圍第26項所述之靜電放電防護半 導體裝置，其中該些P型小區塊係排列為一棋盤狀圖案。 β 32. 如申請專利範園第26項所述之靜電放電防護半 導體裝置，其中該些P型小區塊係排列為一蜂巢狀圖案。 33. 如申請專利範圍第26項所述之靜電放電防護半 導體裝置，其中該些P型小區塊係分佈為一細胞狀圖案。 34. 如申請專利範圍第26項所述之靜電放電防護半 導體裝置，其中該些P型小區塊係排列為平行之複數行。 35. 如申請專利範圍第34項所述之靜電放電防護半 導體裝置，其中該些行中每一行之該些P型小區塊係與相 ❹ 鄰該行之該些區塊交錯配置。 36. 如申請專利範圍第34項所述之靜電放電防護半 導體裝置，其中該些行中每一行之該些P型小區塊係彼此 鄰接。 37. 如申請專利範圍第34項所述之靜電放電防護半 導體裝置，其中該些行中每一行之該些P型小區塊係彼此 相隔。 22 201007926 X Tf TV» / ΛλΜ. 38. 如申請專利範圍第19項所述之靜電放電防護半 導體裝置，其中該矽控整流器之該第一 N型井中之該些P 型摻雜區域係彼此耦接。 39. 如申請專利範圍第20項所述之靜電放電防護半 導體裝置，其中該第一 N型井外之該矽控整流器之該些N 型摻雜區域係彼此耦接。201007926 Λ. VT ~rvr / SmA. Λ. λ X. Patent application scope: 1. An electrostatic discharge protection semiconductor device comprising: a parasitic 矽-controlled rectifier comprising at least: a plurality of first and second conductive state doping a region, staggered and continuously formed in the first well of the first conductive state; and a second conductive state doped region, which is grounded and disposed between the two first conductive doped regions, the three doping The impurity region is spaced apart from the first well and formed in one of the second conductive states; and a diode is formed in the substrate in the second conductive state and coupled to the controlled rectifier in a series mode The diode includes: a second conductive region formed in the second well of the first conductive state and coupled to one of the first conductive doped regions in the first well; and a first A conductive doped region is formed in the second well of the first conductive state and spaced apart from the second conductive state region, wherein the first conductive state doped region is connected to a terminal to which one positive voltage is applied. 2. The electrostatic discharge protection semiconductor device of claim 1, wherein the second conductive region of the diode comprises a plurality of strips spaced apart from each other, the strips being coupled together One of the first conductive state doped regions in the first well. 3. The ESD protection semiconductor device of claim 1, wherein the second conductive state region of the diode comprises a plurality of cell blocks spaced apart from each other, and the plurality of cell blocks are commonly coupled to the One of the first conductive state doped regions in the first well. The electrostatic discharge protection semiconductor device of claim 3, wherein each of the plurality of blocks has a rectangular cross section. 5. The ESD protection semiconductor device of claim 3, wherein each of the plurality of blocks has a diamond-shaped cross section. 6. The ESD protection semiconductor device of claim 3, wherein each of the plurality of blocks has a circular cross section. 7. The ESD protection semiconductor device of claim 3, wherein the plurality of cell blocks are arranged in a matrix. 8. The electrostatic discharge protection semiconductor device of claim 3, wherein the plurality of cell blocks are arranged in a checkerboard pattern. 9. The ESD protection semiconductor device of claim 3, wherein the plurality of cell blocks are arranged in a honeycomb pattern. 10. The ESD protection semiconductor device of claim 3, wherein the cell blocks are distributed in a cell pattern. 11. The ESD protection semiconductor device of claim 3, wherein the plurality of cell blocks are arranged in parallel rows. The electrostatic discharge protection semiconductor device of claim 11, wherein the plurality of blocks of each of the rows are staggered with the blocks of the adjacent row. 13. The ESD protection semiconductor device of claim 11, wherein the plurality of cells of each of the rows are adjacent to each other. 14. The ESD protection semiconductor device of claim 11, wherein the blocks of each of the rows are separated from each other by 201007926, 1 yr*rw /^rrrv. 15. The ESD protection semiconductor device of claim 11, wherein the first and second conductive states are respectively a Ν-type conductive state and a Ρ-type conductive state. 16. The ESD protection semiconductor device of claim 1, wherein the second conductive doped regions of the first well of the step-controlled rectifier are coupled to each other. 17. The ESD protection semiconductor device of claim 1, wherein the first conductive state doped regions of the step-controlled rectifier spaced apart from the first well are coupled to each other. 18. An electrostatic discharge protection semiconductor electrostatic discharge protection semiconductor device comprising: a high voltage parasitic shunt rectifier comprising an anode and a cathode, the cathode of the high voltage step-controlled rectifier being grounded, and a diode The body is connected in series to the high voltage rock-controlled rectifier, and the diode includes an anode and a cathode. The anode of the diode is connected to the anode of the high voltage step-controlled rectifier, and The cathode of the diode is lightly coupled to a terminal having a positive voltage. 19. The ESD protection semiconductor device of claim 18, wherein the high voltage step-controlled rectifier comprises: a plurality of Ν-type and Ρ-type doped regions interleaved and continuously formed in a first Ν type well . 20. The ESD protection semiconductor device of claim 19, wherein the high voltage step-controlled rectifier further comprises: 20 201007926 1 ww/zr/\ a p-type doped region, disposed in two N-type doping Between the impurity regions, the two doped regions are separated from the first well and formed in a p-type doping region coupled to the ground. 21. The ESD protection conductor device of claim 2, wherein the diode comprises a Ρ-type region and a 掺杂-type doped region formed in a first well. 22. The ESD protection semiconductor device of claim 21, wherein the p-type region of the diode is coupled to the Ν-type doping in the first well of the high voltage 矽❹-controlled rectifier One of the miscellaneous areas. 23. The ESD protection semiconductor device of claim 21, wherein a Ν-type doped region is formed in the second Ν-type well and spaced apart from the Ρ-type region. 24. The electrostatic discharge protection semiconductor device of claim 23, wherein the 掺杂-type doped region formed in the first well is connected to the terminal to which the positive voltage is applied. The electrostatic discharge protection semiconductor device of claim 21, wherein the Ρ-shaped region comprises a plurality of p-type strips spaced apart from each other, and the Ρ-type strips are coupled to the first Ν One of the modified areas in the well. The electrostatic discharge protection semiconductor device according to claim 21, wherein the p-type region of the diode includes a plurality of 小区-type cell blocks separated from each other and the p-type cell blocks are coupled together To one of the doped regions of the first doped well. 27. The ESD protection half 21 conductor assembly of claim 26, wherein each of the P-type blocks has a rectangular cross section. 28. The ESD protection semiconductor device of claim 26, wherein each of the P-type blocks has a diamond profile. 29. The ESD protection semiconductor device of claim 26, wherein each of the P-type blocks has a circular cross section. 30. The ESD protection semiconductor device of claim 26, wherein the P-type cell blocks are arranged in a rectangular shape. The electrostatic discharge protection semiconductor device of claim 26, wherein the P-type cell blocks are arranged in a checkerboard pattern. The electrostatic discharge protection semiconductor device of claim 26, wherein the P-type cell blocks are arranged in a honeycomb pattern. 33. The ESD protection semiconductor device of claim 26, wherein the P-type cell blocks are distributed in a cell pattern. 34. The ESD protection semiconductor device of claim 26, wherein the P-type cell blocks are arranged in parallel multiple rows. 35. The ESD protection semiconductor device of claim 34, wherein the P-type cell blocks of each of the rows are staggered with the blocks adjacent to the row. 36. The ESD protection semiconductor device of claim 34, wherein the P-type cell blocks of each of the rows are adjacent to each other. 37. The ESD protection semiconductor device of claim 34, wherein the P-type blocks of each of the rows are spaced apart from each other. The electrostatic discharge protection semiconductor device of claim 19, wherein the P-type doped regions of the first N-type well of the step-controlled rectifier are coupled to each other. Pick up. 39. The ESD protection semiconductor device of claim 20, wherein the N-type doped regions of the step-controlled rectifier outside the first N-type well are coupled to each other. 參 23Reference 23
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US10811497B2 (en) 2018-04-17 2020-10-20 Silanna Asia Pte Ltd Tiled lateral BJT
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