201007458 九、發明說明： 【發明所屬之技術領域】 本發明有關於一種整合傳輸介面之資料處理系統H方 法，特別是有關於讓一嵌入式系統可藉由串列週邊介面 (Serial Peripheral Interface Bus，SPI)傳輸介面來執行門 機、儲存及其相關應用之技術領域。 ©【先前技術】 由於生產晶片的製程被改善，微處理II (Microcontroller)功能越來越強大，在裝置中嵌入功能強大 的微處理器曰益普及的情況下，建立一即時作業系統以供 給這些内嵌於設備之中的微處理器使用，已是一個必然的 趨勢了。 然而内嵌於微處理器的即時系統（以下簡稱嵌入式系 統(Embedded System))，會因為各個不同的系統需求考量而 有不同的設計。所以程式設計者可在使用者模式（User ^ Mode)設計各種可滿足作業系統所提供之行程的需求服 務，其經由嵌入式系統呼叫的方式來服務每一行程。如第1 圖所示，此圖為於嵌入式系統内的一微處理器之各需求服 務說明之示意圖。 嵌入式系統之構造精簡且資源有限，並無個人電腦中 像基本輸入輸出系統(BIOS)這樣的架構，因此在研發此類 嵌入式系統時，需有一小段程式，負責將系統核心(Kemel) 載入記憶體内並執行啟動程式，也就是就是當嵌入式系統 硬體開機或是重設(Reset)之後所要執行的第一段軟體的程 201007458 式碼，此段程式通稱為開機管理程式。 於習知技術中，當嵌入式系統藉由使用多種介面以進 行相應的功能時，例如串列週邊介面（Serial Peripheral Interface Bus，SPI)，裝置及/或嵌入式系統内的微處理器之 間係使用串列週邊介面（S PI)匯流排來進行串列資料同步傳 輸。舉例來說’於第1圖中，主機端之中央處理器11係透過 串列週邊介面（SPI)匯流排而電性連接於一具有如電子抹 ❹ 除式唯讀記憶體 12 (Electronically Erasable Programmable Read-Only Memory，EEPROM)此類的非揮發性記憶體 (non-volatile memory，NVM) ’而開機管理程式係儲存在電 子抹除式唯讀記憶體11。所以，中央處理器U藉由此串列 週邊介面（SPI)匯流排而自電子抹除式唯讀記憶體12載入開 機管理程式。 仍請參閱第1圖，於圖中可知’中央處理器"亦透過一 種集成驅動電子設備（Integrated Drive Electronics，IDE)/通 用串列匯流排(universal serial bus，USB)介面將一巨量儲 ❹ 存(mass storage)裝置13所儲存之核心映象(kernel image)、 應用程式(application)及内容(content)載入，以執行相關的 功能。 接續’於第1圖中，欲入式系統如要執行身份辨識（進 行數學運算’確認其唯一性）或點數計算時（替代成貨幣等 數字型的資料）’使用者需將具一接觸面之智慧卡 14(Smartcard)***嵌入式系統之一相應埠（如201007458 IX. Description of the Invention: [Technical Field] The present invention relates to a data processing system H method for integrating a transmission interface, and more particularly to allowing an embedded system to be connected by a Serial Peripheral Interface Bus (Serial Peripheral Interface Bus, SPI) transmission interface to implement the technical field of door machines, storage and related applications. © [Prior Art] As the process of producing wafers is improved, the Microcontroller II function is becoming more and more powerful. When a powerful microprocessor is embedded in the device, a real-time operating system is built to supply these. The use of microprocessors embedded in devices is an inevitable trend. However, an instant system embedded in a microprocessor (hereinafter referred to as an Embedded System) has different designs depending on various system requirements. Therefore, the programmer can design various service requirements in the user mode to satisfy the travel provided by the operating system, and to service each trip via an embedded system call. As shown in Figure 1, this figure is a schematic diagram of the various service requirements for a microprocessor in an embedded system. The embedded system is compact in structure and limited in resources. There is no architecture like a basic input/output system (BIOS) in a personal computer. Therefore, when developing such an embedded system, a small program is required to be responsible for the system core (Kemel). Into the memory and execute the startup program, that is, the program 201007458 code of the first software to be executed after the embedded system hardware is booted or reset (Reset), this program is generally called the boot management program. In the prior art, when an embedded system uses a plurality of interfaces to perform corresponding functions, such as a Serial Peripheral Interface Bus (SPI), between devices and/or microprocessors in an embedded system. The serial peripheral interface (S PI) bus is used for synchronous transmission of serial data. For example, in FIG. 1 , the central processing unit 11 of the host side is electrically connected to an electronically erased read-only memory 12 (Electronically Erasable Programmable) through a serial peripheral interface (SPI) bus. Read-Only Memory (EEPROM) is a non-volatile memory (NVM) and the boot management program is stored in the electronic erasable read-only memory 11. Therefore, the central processing unit U loads the startup management program from the electronic erasable read-only memory 12 by means of the serial peripheral interface (SPI) bus. Still referring to Figure 1, it can be seen that the 'Central Processing Unit' also has a huge amount of storage through an integrated drive electronics (IDE)/universal serial bus (USB) interface. The kernel image, application, and content stored in the mass storage device 13 are loaded to perform related functions. In the first picture, if the user wants to perform identity recognition (for mathematical operations to confirm its uniqueness) or when calculating points (replaces digital data such as currency), the user needs to have a contact. The smart card 14 (Smartcard) is inserted into one of the embedded systems (such as
Digital，SD介面）’以接觸讀寫輸入/輸出（1/〇)線路，使得 欲入式系統得以執行記憶、識別、加/解密及傳輸等功能。 201007458 依上述所言’嵌入式系統分別以SPI、IDE/USB及SD 卡界面執行不同功能，而此一運作模式已在業界行之多年。 然而，已現有的技術而言，儲存開機管理程式之電子 抹除式唯讀記憶體仍被固定至印刷電路板(pCB board)上， 無法拆離地裝設在此嵌入式系統上，此舉大大地降低巍入 式系統在初期設計時的便利性。 【發明内容】 本發明提供一種整合傳輸介面之資料處理系統與方 法，以提高嵌入式系統執行開機、儲存或執行應用程式之 便利性。而本實施中以串列週邊介面（spi)作為一整合傳輪 介面之傳輸協定。而儲存媒體（如SD卡），也内建相應此^ 列週邊介面（SPI)傳輸協定，且此儲存媒體儲存至少一開 管理程式及-應用資料’至此，喪人式系統可藉由串 邊介面(SPI)傳輸協定自儲存媒體上依序載人開機管理 及應甩資料’以執行開機、儲存及其相關應用之技術領域x。 _根據上述之目的，本發明係揭露一種整合傳輸介面 資料處理系統及其方法，此系統包含—微處理器、 傳輸單兀及一儲存媒體。微處理器内建有一協 資料傳輸單元係、與微處理器連接，且具有相應此傳輪協= 之-傳輸介面。儲存媒體係連接f料傳輸單元，且上 媒體亦内建前述之傳輸協定，且儲存至少—義管理程^ 及-應用資料。其中，微處理器係使用傳輸協定，二 料傳輸單元而自儲存媒體載人及執行開機管理程式，且二 開機管理程魏行完成後，微處理^再使祕輸協定，二 201007458 過資料傳輸單元而自儲存媒體載入及執行應用資料。 【實施方式】The Digital, SD interface) is used to access the read/write input/output (1/〇) line, enabling the on-demand system to perform functions such as memory, recognition, encryption/decryption, and transmission. 201007458 According to the above statement, the embedded system performs different functions with SPI, IDE/USB and SD card interfaces respectively, and this mode of operation has been in the industry for many years. However, in the prior art, the electronic erasing read-only memory storing the boot management program is still fixed to the printed circuit board (pCB board) and cannot be detachably mounted on the embedded system. Greatly reduce the convenience of the intrusion system in the initial design. SUMMARY OF THE INVENTION The present invention provides a data processing system and method for integrating a transmission interface to improve the convenience of an embedded system to perform booting, storing, or executing an application. In this implementation, the serial peripheral interface (spi) is used as a transport protocol for an integrated transport interface. The storage medium (such as the SD card) also has a corresponding peripheral interface (SPI) transmission protocol built therein, and the storage medium stores at least one management program and application data. At this point, the mourning system can be used by the string side. The interface (SPI) transport protocol automatically carries the power-on management and response data from the storage medium to perform the technical field of booting, storage and related applications. In accordance with the above objects, the present invention is directed to an integrated transmission interface data processing system and method thereof, the system comprising a microprocessor, a transmission unit and a storage medium. The microprocessor has a built-in data transmission unit, is connected to the microprocessor, and has a corresponding transmission interface. The storage medium is connected to the f-material transmission unit, and the above media also has the aforementioned transmission protocol built therein, and stores at least the management program and the application data. Among them, the microprocessor uses the transmission protocol, the two-material transmission unit and the self-storage media manned and executes the boot management program, and after the completion of the second boot management process, the micro-processing ^ then makes the secret transfer agreement, the second 201007458 through the data transmission unit Load and execute application data from the storage media. [Embodiment]
在本揭露書中，號碼的標示說明被提供，多個装置、 電路、組件及其方法，用以提供本發明的實施例之構思能 夠讓人充分了解。熟知此技藝者能清楚的明暸，然而，在 沒有一個或多個實施詳細說明下，本發明能被具體之實 施。在其它的範例中，為人所熟知細節說明不會出現或描 述，以避免會混淆本發明構思。 於習知技術中，開機管理程式之電子抹除式唯讀記憶 體被固定至印刷電路板上，無法拆離地裝設在嵌入式系統 上，本發明亦提供一種整合傳輸介面之資料處理系統，亦 解決此一問題。而此資料處理系統亦為是嵌入式系 請參閱第2圖所示’此圖為資料處理系統之方塊示意 圖’於圖中可知’此整合傳輸介面之資料處理系統2包含一 微處理器2!、-資料傳輪單元22及—儲存媒體23。此微處 理器2卜内建有-傳輪協定。資料傳輪單元22，係與微處 理器21連接，且具有相應傳輸協定之—傳輸介面及儲存 媒體23，係可連接資料傳輸單仙，且在儲存媒體23内建 與資料傳輸單元22之相應之傳輸協定，及綠儲存至少一 開機管理程式及-應用資料。特別地，微處理器21係為观 中央處理H(CTU)或觀單晶聽理器之其中—者，而儲存 媒體23為反及⑽剛㈣閃域體、反或(ngr)型快閃記 憶體或具朗資訊之記憶卡其巾之—者。前述儲存媒體所 包含的應用資料包含有-核心映象、―應用程式及一内容。 201007458 而針對習知儲存開機管理程式之電子抹除式唯讀記憶 體無法拆離地裝設在嵌人式祕上，由上述資料傳輸單元 與儲存媒體之間的連接模式，儲存關管理程式及應用資 料之儲存媒體係可拆離地裝設在資料傳輸單元。需注意 地:於微處理器、資料傳輸單元及儲存媒體之傳輸協定皆 係採用串列週邊介面（spi)。 為人所熟知的’串列週邊介面(SPI)是—種四線式的通 面’其使用一主出從入（Master 〇ut Slave In，M〇SI)、 二 =tM:ter In Slave 〇Ut，_)、一串列時脈(S—1 )等二線路進行資料傳輸，而從屬選擇線(Slave SS)則控制裝置的選擇。更詳細地說明，主裝置為 時脈提供者，可發起讀取從屬裝置 私 2田介面上存在多個從屬裝置時，若要發起 裝置將把從屬裝置之選擇線電位降低，編過 :MM〇SI)和主入從出_〇)線路啟動數據4= 發明介：)之傳輸特性，作為本 包含下列步驟： 貝枓處理方法 步驟(300):提供内建一傳輸協定之 一傳輸狀之-儲存媒體’且此儲存媒體及内建 管理程式及-應用資料之儲存媒體，==一開機 列週邊介面（SPI)傳輸協定； 51協疋係採用串 步驟(301):於微處理器與儲存媒體間，配置具串列週 201007458 邊介面（SPI)傳輸協定之一資料傳輪單元； 步驟(302):於微處理器、資料傳輸單元及儲存 者間形成一串列週邊介面(SPI)傳輪橋樑，透過以串列= 介面(SPI)傳輸協定使得微處理器經資料傳輸單元 β 存媒體之開機管理程式’此微處理器透過資料傳輪單元之 串列週邊介面（SPI)傳輸介面載入開機管理程式^部 ΟIn the present disclosure, the description of the number is provided, and the various means, circuits, components, and methods thereof are provided to provide a full understanding of the concept of the embodiments of the present invention. It will be apparent to those skilled in the art that the present invention may be embodied in a particular embodiment. In other instances, well-known details are not described or described in order to avoid obscuring the inventive concept. In the prior art, the electronic erasing read-only memory of the boot management program is fixed to the printed circuit board and can not be detached and mounted on the embedded system. The present invention also provides a data processing system with integrated transmission interface. Also solve this problem. The data processing system is also embedded. Please refer to FIG. 2, which is a block diagram of the data processing system. It can be seen from the figure that the data processing system 2 of the integrated transmission interface includes a microprocessor 2! - data transfer unit 22 and storage medium 23. This microprocessor 2 has a built-in-pass agreement. The data transmission unit 22 is connected to the microprocessor 21 and has a corresponding transmission protocol, a transmission interface and a storage medium 23, which can be connected to the data transmission unit, and is constructed in the storage medium 23 corresponding to the data transmission unit 22. The transmission agreement, and the green storage at least one boot management program and application data. In particular, the microprocessor 21 is one of the central processing H (CTU) or viewing single crystal listeners, while the storage medium 23 is reversed (10) just (four) flash domain, inverse or (ngr) type flash The memory or the memory of the lang information is the towel. The application data contained in the foregoing storage medium includes a - core image, an application, and a content. 201007458 The electronic erasing read-only memory for the conventional storage boot management program can not be detached and installed on the embedded secret. The connection mode between the data transmission unit and the storage medium is stored and the management program is The storage medium of the application data is detachably mounted on the data transmission unit. It should be noted that the transmission protocol for microprocessors, data transmission units and storage media uses a serial peripheral interface (spi). The well-known 'Serial Peripheral Interface (SPI) is a four-wire type of pass surface' that uses a master 〇 ut Slave In (M〇SI), two = tM:ter In Slave 〇 Ut, _), a series of clocks (S-1) and other two lines for data transmission, while the slave selection line (Slave SS) controls the selection of the device. In more detail, the master device is a clock provider, and when the slave slave device can initiate the reading of the slave device, when there are multiple slave devices, if the initiator device is to lower the selection line potential of the slave device, the code is: MM〇 SI) and the master-in-out-out_line line start data 4= invention transmission:) The transmission characteristics, as this includes the following steps: Bellow processing method step (300): providing one of the built-in transmission protocols - Storage medium' and this storage medium and built-in management program and storage medium for application data, == a boot-in peripheral interface (SPI) transfer protocol; 51 protocol uses string step (301): in microprocessor and storage Between the media, one of the data transmission units of the serial interface 201007458 side interface (SPI) transmission protocol is configured; step (302): forming a serial peripheral interface (SPI) transmission between the microprocessor, the data transmission unit and the storage The wheel bridge, through the serial-interface (SPI) transmission protocol, causes the microprocessor to transmit the media through the data transfer unit β. The microprocessor transmits the interface through the serial peripheral interface (SPI) of the data transfer unit. Open ^ Ο program management unit
步驟：（303)將微處理器決定為一主工作模式及資 輸單元決定為-僕X作模式。作為主裝置之微處理器為時 脈提供者，可發起讀取從屬裝置或寫入從屬裝置之斜 輪單元之動作；最後 ’ 步驟：（304)微處理器再次使用串列週邊介面(spi)傳輸 協定，經過資料傳輸單元而自儲存媒體载入及執行包含核 心映象、應用程式及内容之一應用資料。 而步驟（302)與步驟（303)間如以具識別資訊之記憶卡 (如智慧卡Smartcard)而言，此載入開機管理程式之部分資 料包含識別記憶卡編號、加/解密或輸入/輪出（1/〇)等功能， 同時，此資料傳輸單元支援識別記憶卡功能，亦是一種驗 證程序，亦包含下列步驟，如第3B圖所示： 步驟(305) ·提供内建—傳輸協定之—微處理器及内建 -傳輸協定之-儲存媒體，且此儲存媒體儲存至少一開機 管理程式及-㈣資料之儲存雜，此傳輪協定係採用串 列週邊介面（SPI)傳輸協定； 步驟(306).於微處理器與儲存媒體間，配置具串列週 邊介面(SPI)傳輸協定之1料傳輸單元； 201007458 步驟：（307)於微處理器、資料傳輪單元及儲存媒體三 者間形成一串列週邊介面（SH)傳輸橋樑，透過以串列週邊 介面（SPI)傳輸協定使得微處理器經資料傳輸單元而載入儲 存媒體之開機管理程式’其中此在資料傳輸單元傳輸過程 中處於加密（encrypt)狀態，而當微處理器載入儲存媒體之 開機管理程式之一第一部分，且前述第一部分包含驗證 (authentication)及解密（decryption)的功能； φ 步驟：（308)對開機管理程式進行解密以產生一驗證密 - 碼； 步驟：（309)藉由微處理器比對驗證密碼，以決定是否 開放存取權，如驗證成功後，再進行繼續載入儲存媒體之 開機管理程式之一第二部分，以完載入開機管理程式之程 序； 。步驟(310):將微處理器決定為一主工作模式及資料傳 輸f元決定為一僕工作模式。作為主裝置之微處理器為時 ❹脈提供者，可發起讀取從屬裝置或寫入從屬裝置之資料傳 輸單元之動作；最後 a步驟(311):微處理器再次使用串列週邊介面（spi)傳輸 協疋，經過資料傳輸單元而自儲存媒體載入及執行包含核 ""映象、應用程式及内容之一應用資料。 而以如第2圖之資料處理系統之資料傳輸單元為一種 擬器，如儲存媒體為不同串列週邊介面（sn)傳輸協定之 :種傳輸協定，本發明亦提供另一種實施方式，如 所示。 第圖所不，此圖為為根據第2圖係緣示整合傳輸介 201007458 面之資料處理系統4之另一實施例之示意圖。依然地，微處 理器41及資料傳輸單元42皆採用串列週邊介面（sn)傳輸協 定作為一第一傳輸協定，儲存媒體43内建内部整合電路 (Ir^r-Integrated Circuit ’此)傳輸協定、兩蕊介面（2_⑺叫、 四蕊介面（4-Wire)的群組組合中任意選擇其中之一作為一 第二傳輸協定之用，*儲存媒體43賴存至少—開機管理 Ο ⑩ 程式及-應用資料與資料傳輸單元42之連接方式皆與 相同，故在此不在撰述。 於開機時’資料傳輸單元娜此傳輸協定、兩姑介 面、四蕊介面的群組組合中任意選擇其中之-模擬為i列 週邊介面(SPI)傳輸協定，於微處理器41、資料傳輸單元仏 及儲存媒體43三者間共同形成—串列週邊介面(spi)傳輸橋 樑’接著’微處理器41係使用串列週邊介面(spi)傳輸協定， 經過資料傳輸單純而自儲存媒體43載人及執行開機管理 程式且當開機管_•行完成後 ，微處理器41再使用 串列=邊介面（SPI)傳輪以，經過資料傳輸單元42而自儲 存媒體43載入及執行應用資料。 容可^ m式系統採料列週邊介面 (㈣搜」協疋有多種好處’除了比起l2C、兩蕊介面、四蜂 介面傳輸蚊可達㈣㈣ ^ 統A内的微處理器以串列 篏入式糸 I入式系面（SPI)傳輸協定而與另一 示，此圖為兩㈣理接^SCade)。如第5圖所 明顯地，具識別瞀却 》 (se眞digital card，SD = ^卡53如安全數位記憶卡 )、一多媒體記憶卡(multimedia 12 201007458 card ’ MMC card)、一聰明媒體卡（snjart media card，SM card) 至少儲存嵌入式系統A之一開機管理程式及一應用資料與 嵌入式系統B之一開機管理程式及一應用資料，且此記憶卡 53内建串列週邊介面（SPI)傳輸協定。 於兩嵌入式系統開機時，於嵌入式系統A之微處理器 51透過資料傳輸單元52自記憶扣載人相應之開機管理程 式及其應用資料後，嵌入式系統A之微處理器51可作為散 :式系統B之-資料傳輸單元(亦是模擬器)，接著’嵌入弋 tit㈣理以4魏#料傳輸單元之_列週邊/面 機典理」f疋（嵌入式系統A之微處理器51)載入相應之開 機管理程式及其應用資料。 K開 限定2本發明已叫佳實施觸露如上，然其並非用以 和範圍内明二習此技藝者’在不脫離本發明之精神 ❹ 範圍田硯後附之申請專利範圍所界定者為準。之⑽ 【圖式簡單說明】 妒本發明之上述和其他目的、特徵、優點盘實如 第1圖係為嵌入式系統内 之示意圖； 處理器之各需求服務說明 圖為本發明之整合傳輸介面之資料處理系統之示意 第从圖及第糊=本發明之整合傳輸介面之資料處理 糸統之方法流程圖； 13 201007458 第4圖係為根據第2圖係繪示整合傳輸介面之資料處理系統 之另一實施例之示意圖；以及 第5圖係為微處理器係透過序列週邊介面而與另一微處理 器串接(cascade)之示意圖。 【主要元件符號說明】 11 :中央處理器； 12 :電子抹除式唯讀記憶體； 13 :巨量儲存裝置； 14 :智慧卡； 2:資料處理系統； 21 :微處理器； 22 :資料傳輸單元； 23 :儲存媒體； 4:資料處理系統； 41 :微處理器； 42:資料傳輸單元； 43 :儲存媒體； 51 :微處理器； 52 :資料傳輸單元； 53 :記憶卡； 54 :微處理器； A、B :嵌入式系統；以及 步驟：300〜311。 14Step: (303) The microprocessor is determined to be a primary operating mode and the transmission unit is determined to be a servant X mode. The microprocessor as the master device is the clock provider, and can initiate the action of reading the slave device or writing the slave device's skew wheel unit; finally 'step: (304) the microprocessor uses the serial peripheral interface (spi) again. The transport protocol loads and executes one of the application files including the core image, the application and the content from the storage medium through the data transfer unit. And in the case of the memory card with identification information (such as smart card) between step (302) and step (303), part of the data loaded into the boot management program includes identification memory card number, encryption/decryption or input/round At the same time, the data transmission unit supports the identification of the memory card function, and is also a verification program, which also includes the following steps, as shown in FIG. 3B: Step (305) • Providing a built-in transmission protocol a microprocessor and a built-in-transfer protocol-storage medium, and the storage medium stores at least one boot management program and - (4) storage of data, the transport protocol uses a Serial Peripheral Interface (SPI) transport protocol; Step (306). Configuring a serial transmission unit with a serial peripheral interface (SPI) transmission protocol between the microprocessor and the storage medium; 201007458 Step: (307) in the microprocessor, the data transfer unit, and the storage medium Forming a series of peripheral interface (SH) transmission bridges, which are loaded into the storage medium by the data transmission unit through a serial peripheral interface (SPI) transmission protocol. The transmission unit is in an encrypted state during transmission, and when the microprocessor loads the first part of the boot management program of the storage medium, and the first part includes the functions of authentication and decryption; φ step (308) decrypting the boot management program to generate a verification secret code; step: (309) verifying the password by the microprocessor to determine whether to open the access right, if the verification is successful, then continue to carry Enter the second part of the boot media management program to complete the program to load the boot manager; Step (310): determining the microprocessor to be a main working mode and the data transmission f element is determined to be a servant working mode. The microprocessor as the master device can initiate the action of reading the slave device or the data transfer unit of the slave device; finally a step (311): the microprocessor uses the serial peripheral interface again (spi The transmission protocol loads and executes one of the application files including the core "" image, application and content from the storage medium through the data transmission unit. The data transmission unit of the data processing system of FIG. 2 is an abbreviated device. For example, the storage medium is a different serial peripheral interface (sn) transmission protocol: the transmission protocol, and the present invention also provides another implementation manner, such as Show. The figure is not shown. This figure is a schematic diagram of another embodiment of the data processing system 4 for integrating the transmission medium 201007458 according to the second figure. Still, the microprocessor 41 and the data transmission unit 42 both use a serial peripheral interface (sn) transmission protocol as a first transmission protocol, and the storage medium 43 has an internal integrated circuit (Ir^r-Integrated Circuit ') transmission protocol. </ br> </ br> </ br> </ br> </ br> </ br> </ br> </ br> </ br> </ br> <br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br> The connection between the application data and the data transmission unit 42 is the same, so it is not written here. At the time of power-on, the data transmission unit can choose any combination of the transmission protocol, the two-guest interface, and the four core interface-simulation For the i-column peripheral interface (SPI) transport protocol, the microprocessor 41, the data transfer unit, and the storage medium 43 are formed together - a serial peripheral interface (spi) transmission bridge 'and then' the microprocessor 41 uses a string The column peripheral interface (spi) transmission protocol, the data transmission is purely from the storage medium 43 and the boot management program is executed, and when the boot pipe_• line is completed, the microprocessor 41 uses the serial=edge The surface (SPI) transfer wheel loads and executes the application data from the storage medium 43 via the data transfer unit 42. The peripheral interface of the (M) system search column has a plurality of benefits 'except for the l2C The two core interface and the four-bee interface can transmit mosquitoes up to (4) (4) ^ The microprocessor in the system A is in series with the 篏I input system (SPI) transmission protocol and the other shows that the figure is two (four) Connect to ^SCade). As clearly shown in Figure 5, there is a recognition card (se眞 digital card, SD = ^ card 53 such as a secure digital memory card), a multimedia memory card (multimedia 12 201007458 card 'MMC card), A smart media card (SM card) stores at least one of the embedded system A boot management program and one application data and one of the embedded system B boot management program and an application data, and the memory card 53 has a built-in string. Column Peripheral Interface (SPI) Transfer Protocol. When the two embedded systems are powered on, the microprocessor 51 of the embedded system A self-memorizes the corresponding boot management program and its application data through the data transfer unit 52, and then embeds The microprocessor 51 of system A can For the dispersion: type system B - data transmission unit (also simulator), then 'embedded 弋tit (four) to 4 Wei # material transmission unit _ column peripheral / face machine theory" f疋 (embedded system A micro The processor 51) loads the corresponding boot management program and its application materials. K Open Limit 2 The present invention has been described as being implemented as above, but it is not intended to be used by those skilled in the art. The spirit of the scope is defined by the scope of the patent application attached to the field. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention are set forth in Figure 1 as a schematic diagram in an embedded system. The various service descriptions of the processor are the integrated transmission interface of the present invention. A schematic diagram of the data processing system and a method flow diagram of the data processing system of the integrated transmission interface of the present invention; 13 201007458 Fig. 4 is a data processing system for integrating the transmission interface according to the second figure A schematic diagram of another embodiment; and FIG. 5 is a schematic diagram of a microprocessor being cascaded with another microprocessor through a sequence peripheral interface. [Main component symbol description] 11: central processing unit; 12: electronic erasing type read only memory; 13: huge storage device; 14: smart card; 2: data processing system; 21: microprocessor; Transmission unit; 23: storage medium; 4: data processing system; 41: microprocessor; 42: data transmission unit; 43: storage medium; 51: microprocessor; 52: data transmission unit; 53: memory card; 54: Microprocessor; A, B: embedded system; and steps: 300~311. 14