TW201003839A - Shallow trench isolation structure and method for formation thereof - Google Patents

Shallow trench isolation structure and method for formation thereof Download PDF

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Publication number
TW201003839A
TW201003839A TW098120811A TW98120811A TW201003839A TW 201003839 A TW201003839 A TW 201003839A TW 098120811 A TW098120811 A TW 098120811A TW 98120811 A TW98120811 A TW 98120811A TW 201003839 A TW201003839 A TW 201003839A
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film
isolation structure
trench isolation
shallow trench
coating
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TW098120811A
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Chinese (zh)
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TWI436450B (en
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Tatsuro Nagahara
Masanobu Hayashi
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Az Electronic Materials Japan
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/764Air gaps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02219Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
    • H01L21/02222Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen the compound being a silazane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Abstract

The present invention is provided a shallow trench isolation structure with great characteristic of insulation and a method for forming the shallow trench isolation structure simply and low-costly. The shallow trench isolation structure is planted a trench structure on the surface by silica films. The silica films are limited at one side of the substrate surface and the bottom of the trench is provided with a vacancy. The said shallow trench isolation structure is formed by coating silazane polymers composition on the substrate surface, irradiating ultraviolet on the coating films to indurate a part of the silazane polymers around the surface of the coating films, and then sintering the coating films.

Description

201003839 六、發明說明: 【發明所屬之技術領域】 本發明係一種關於霄 法。更詳細地說明,本發 等電子裝置時,用於形成 如淺溝槽隔離構造的二氧 【先前技術】 一般於半導體裝置之 f 配置有例如電晶體、電阻 需爲電氣絕緣。因此,該 區域,其係稱爲隔離區域 板之表面選擇性地形成絕 另一方面,於電子裝 且高積集化係不斷演進。 的演進,要形成能配合該 變得困難,需要一種能符 ί 舉出溝槽隔離構造來作爲 基板之表面形成微細的溝 形成使得該溝槽兩側的元 種用以分離元件的構造, 造的區域,所以係爲一種 之有效的元件分離構造。 作爲一種用以形成如前述 種塗布聚矽氮烷組成物, (例如專利文獻1及2 )。 :子裝置中二氧化矽膜的製造方 明係關於一種在製造半導體元件 電子裝置之絕緣膜,用於形成例 化矽形成方法。 各種電子裝置中,雖然於基板上 及其他半導體元件,但該等間必 寺之間必需要有用以分離元件的 。過去’一般係藉由於半導體基 緣膜而作爲該隔離區域。 置之領域中,近年來,高密度化 隨著前述高密度化且高積集度化 必要之積集度的微細隔離構造係 合該等需求之新型隔離構造。可 前述之技術。該構造係於半導體 槽,於該溝槽內部塡充絕緣物而 件之間電性分離的構造。由於此 相較於習知方法係可窄化隔離構 用以達成現今所要求的高積集度 溝槽隔離構造的方法,係考慮一 再將其轉化爲二氧化矽膜的方法 一般於此種方法中,係將聚矽氮 201003839 烷組成物塗布於形成有溝槽構造的基板表面而於溝槽內塡 充聚矽氮烷組成物,其次藉由燒結等使聚矽氮烷組成物硬 化而轉化爲二氧化矽,再藉由化學機械硏磨方法(Chemical Mechanical Polishing··以下稱爲CMP)去除形成於基板表 面之多餘的二氧化政。 以前述方法形成溝槽隔離構造時,如考慮製程之效 率,爲了縮短CMP步驟則以剩餘二氧化矽較少者爲佳。因 此,係考量塗布濃度相對較低的聚矽氮烷組成物。但是, 當降低聚矽氮烷組成物濃度時,塡充於溝槽內之聚矽氮烷 組成物的固體量亦相對地減少。其結果使得燒結後形成於 溝槽內之二氧化矽不足,無法充份地塡充溝槽內抑或使溝 槽內產生強大的拉應力,對最終形成之電子裝置的特性產 生不良影響。最糟的情況’甚至會因形成於溝槽內之二氧 化矽與溝槽內面未緊密接合並自溝槽內脫落’讓溝槽內未 殘留有二氧化矽。其結果係成爲一絕緣特性不充份的溝槽 隔離構造。 爲了解決如前述降低聚矽氮烷組成物濃度所產生的問 題,亦已知有一種分複數次塗布聚矽氮烷組成物的方法(專 利文獻3 )。但該方法就處理成本之觀點來看係非較佳。 爲了回避該等問題,係與前述方法相反而考量相對地 提高聚矽氮烷組成物的濃度。但是’此時因爲形成於基板 表面之多餘二氧化矽增加’於CMP步驟中必需硏磨之二氧 化矽的量亦增加而使處理成本大增。再者,由於該藉由塗 布所形成之聚矽氮烷組成物的塗膜變厚’而發生自環境氣 體中所獲得的水份或氧未能充份地供給至溝槽內部,導致 201003839 於溝槽內部自聚矽氮烷變爲二氧化矽的轉化反應未能 地進行的問題。又,形成較厚之二氧化矽膜時,亦會 內之殘留應力使得膜產生龜裂。 誠如前述,當使用一種塗布聚矽氮烷組成物再轉 二氧化矽的方法時,係因濃度不同而有產生不同問題 向’而爲了調整至其最適當之條件係必需花費莫大心 【專利文獻1】日本專利第3178412號公報(段落 〜0016 ) 【專利文獻2】日本特開第2001-308090號公報 【專利文獻3】日本特開第20 07-036267號公報 【專利文獻4】日本特開第平08-125021號公報 【專利文獻5】日本特開第平01-24.8528號公報 【發明内容】 有鑑於前述問題點,本發明係提供一種塗布相對 之聚矽氮烷組成物,且具有充份之絕緣特性的淺溝槽 構造及其製造方法。 本發明所提供之淺溝槽隔離構造的特徵係具備: 面處具有溝槽構造的基板;以及用以埋設該溝槽的二 砍膜’其中該二氧化矽膜局限於該基板之表面側,且 溝槽之底部具備空孔。 又’本發明所提供之淺溝槽隔離構造之製造方法 特徵係包含有:(A)於具有溝槽構造的基板表面塗布 氮烷組成物而形成塗布膜的塗布步驟;(B )於該塗布 表面照射紫外線來使得該塗布膜之表面附近的聚矽氮 一部份硬化’而於溝槽部份之底部形成空孔的紫外線 充份 因膜 化爲 的傾 力。 0005 較薄 隔離 於表 氧化 於該 ,其 聚矽 膜之 烷之 照射 201003839 步驟;以及(c)藉由燒結該塗布膜,使得 化而形成二氧化矽膜的燒結步驟。 依本發明係提供一種與習知之淺溝槽 具有空孔且絕緣特性優異的淺溝槽隔離構 明之方法係可簡便且低成本地形成淺溝槽 【實施方式】 淺溝槽隔離構造 本發明之淺溝槽隔離構造係具備有於 造的基板以及用以埋設該溝槽的二氧化矽 明之淺溝槽隔離構造之特徵爲用以埋設溝 並未完全地塡充溝槽內部,而係局限於該 該溝槽底部存在有空孔。該構造係如第1 亦即,於基板1之溝槽部表面附近形 (絕緣膜)2,而於溝槽部之底部形成有3 圖可知,本發明中空孔3並非是由相對較 體’而是實質上一連續形成之空孔。亦即 係具有沿溝槽形狀所形成之帶狀或繩狀的 以埋設溝槽的二氧化矽膜2雖係存在於溝 於基板之表面側。亦即,可說是用二氧化 埋入溝槽內。然後,空孔3與溝槽內面之 觸,而溝槽之內側表面處並不存在二氧化 中,於形成淺溝槽隔離構造時,認爲以絕 勻地塡充於溝槽內部者爲佳。的確,藉由 充溝槽內係可提高隔離構造之絕緣性。但 硏討後得知,實際上於基板表面上裝載有 該塗布膜整體硬 隔離構造相異, 造。又,依本發 隔離構造。 表面具有溝槽構 膜。然後,本發 槽的二氧化矽膜 基板之表面側且 圖所示。 成有二氧化矽膜 ?孔3。參照第1 小之空孔的集合 ’本發明之空孔 形狀。然後,用 槽內側,但局限 矽膜2將空孔3 分界面係直接接 矽膜。習知技術 緣膜來緻密且均 緻密且均勻地塡 是,本發明人經 元件時,由於溝 201003839 槽內底部處相對地較難以施加電場,故不需要求太高之絕 緣性。而且,形成於溝槽內的空孔,其本身之絕緣性亦相 對較高。亦即,特別需要高絕緣性者係爲接近元件的表面 附近處,而僅需於該表面附近形成緻密之絕緣膜,即使溝 槽底部係爲空孔,亦可達到作爲隔離構造所需的絕緣性。 然後,因爲溝槽底部形成有空孔,據信該位於其正上方之 二氧化矽膜係被壓迫而形成更緻密之二氧化矽膜。 此處,雖然爲了使該等隔離構造達到較佳之絕緣特性 f 而推薦使用特定之尺寸,但本發明之溝槽隔離構造於溝槽 寬度更窄、抑或於縱橫比更高之情況亦表現出優異之特 性。亦即,溝槽之寬度a爲5〜50nm者較佳,寬度a爲5 〜40nm者更佳。又,溝槽之深度b除以溝槽之寬度a的比 例,亦即縱橫比b/a爲10〜100者較佳,1〇〜50更佳。 又’以空孔於溝槽深度方向之長度爲c時,則c爲5 〜100nm者較佳’長度c爲5〜50nm者更佳。又,觀察與 溝槽之長度方向垂直的剖面時,空孔之剖面積相對於溝槽 ί 構造之剖面積的比例爲5〜20%者較佳,8〜15%者更佳。 該空孔於溝槽深度方向之長度、抑或空孔之剖面積的比例 爲特定値以上時係可獲得緻密之二氧化矽膜,充分地發揮 隔離構造之絕緣特性。又,隨著空孔加大,二氧化矽膜係 因受壓迫而更加緻密,降低拉應力的同時係使其物理強度 變的更充足。 又,本發明中雖於溝槽底部存在有空孔,但該部分幾乎 不存在二氧化矽膜。亦即,空孔部分內,溝槽內壁幾乎未 附著有二氧化矽。因此,由於空孔之剖面積相對於溝槽構 201003839 造之剖面積的比例約與c/b相當,比例c/b爲0.05〜0.2者 較佳,0.08〜0.15爲更佳。 再者,本發明之淺溝槽隔離構造,如此處所記載的溝 槽之寬度與縱橫比、以及空孔之大小時,該效果較強地表 現’但並非特別限定於該等尺寸,僅需具有藉由二氧化矽 膜來埋設基板上之溝槽’且該二氧化矽膜係局限於基板之 表面側,並於該溝槽底部處具備有空孔而形成之構造者, 即可獲得本發明之效果。 f 淺溝槽隔離構造之形成方法 如前述之淺溝槽隔離構造係可由任何方法所形成。該 形成方法之一例係包含有: (A) 於具有溝槽構造的基板表面塗布聚矽氮烷組成物 而形成塗布膜的塗布步驟; (B) 於該塗布膜之表面照射紫外線來使得該塗布膜之 表面附近的聚矽氮烷之一部份硬化,而於溝槽部份之底部 形成空孔的紫外線照射步驟;以及 ί (C)藉由燒結該塗布膜,使得該塗布膜整體硬化而形 成二氧化矽膜的燒結步驟。 本發明之淺溝槽隔離構造之形成方法的特徵在於,於 塗布聚矽氮烷組成物後,首先於塗布膜之表面照射紫外線 來使得表面附近暫時硬化後進行燒結,而使得塗布膜整體 轉化爲二氧化矽膜。首先,藉由於基板表面照射紫外線來 引發聚矽氮烷組成物之氧化及聚合反應,並因此造成體積 之收縮。其結果係針對溝槽內之聚矽氮烷組成物或由其轉 化而形成之二氧化矽膜產生向上拉高之力量。然後,於表201003839 VI. Description of the Invention: [Technical Field to Which the Invention Is Ascribed] The present invention relates to a method. More specifically, in the case of an electronic device such as the present invention, it is used to form a dioxygen such as a shallow trench isolation structure. [Prior Art] Generally, a semiconductor device is provided with, for example, a transistor, and the resistor needs to be electrically insulated. Therefore, in this region, the surface of the plate, which is called the isolation region plate, is selectively formed on the other hand, and the electronic assembly and the high accumulation system are constantly evolving. The evolution of the formation to be able to match this becomes difficult, and a configuration in which a trench isolation structure is used as a surface of the substrate to form a fine groove so that the elements on both sides of the groove are used to separate the elements is required. The area is therefore an effective component separation structure. It is used as a composition for coating a polyazide as described above (for example, Patent Documents 1 and 2). : Manufacture of a ruthenium dioxide film in a sub-device relates to an insulating film for fabricating a semiconductor device electronic device for forming an exemplary ruthenium formation method. In various electronic devices, although on the substrate and other semiconductor components, it is necessary to separate the components between the devices. In the past, it was generally used as the isolation region by the semiconductor base film. In the field of the field, in recent years, the density of the micro-isolation structure with the above-mentioned high density and high integration is required to be compatible with the new isolation structure of such a demand. The aforementioned technology can be used. The structure is a structure in which a semiconductor trench is filled with an insulator and electrically separated between the trenches. Since this method can narrow the isolation structure to achieve the high-accumulation trench isolation structure required today, it is generally considered that this method is generally used to convert it into a hafnium oxide film. In the present invention, a polyfluorene nitrogen 201003839 alkane composition is applied to a surface of a substrate having a grooved structure to form a polyazane composition in a trench, and then a polyazide composition is hardened by sintering or the like. It is cerium oxide, and the excess oxidization formed on the surface of the substrate is removed by a chemical mechanical polishing method (hereinafter referred to as CMP). When the trench isolation structure is formed by the above method, the efficiency of the process is considered, and in order to shorten the CMP step, it is preferable to use less ruthenium dioxide. Therefore, a polyazirane composition having a relatively low coating concentration is considered. However, when the concentration of the polyazane component is lowered, the solid amount of the polyazane composition which is filled in the grooves is also relatively reduced. As a result, the cerium oxide formed in the trench after sintering is insufficient, and it is not possible to sufficiently fill the trench or generate a strong tensile stress in the trench, which adversely affects the characteristics of the finally formed electronic device. In the worst case, the ruthenium dioxide formed in the trench is not tightly bonded to the inner surface of the trench and is detached from the trench, so that no ruthenium dioxide remains in the trench. As a result, it is a trench isolation structure in which the insulating properties are insufficient. In order to solve the problem caused by lowering the concentration of the polyazane component as described above, a method of coating the polyazoxide composition in several times is also known (Patent Document 3). However, this method is not preferable from the viewpoint of cost. In order to circumvent these problems, the concentration of the polyazane component is relatively increased as opposed to the foregoing method. However, at this time, since the amount of excess cerium oxide formed on the surface of the substrate is increased, the amount of cerium oxide which must be honed in the CMP step is also increased to increase the processing cost. Further, since the coating film of the polyazane composition formed by coating is thickened, water or oxygen obtained from the ambient gas is not sufficiently supplied to the inside of the groove, resulting in 201003839 The problem that the conversion reaction from the polyazide to the cerium oxide inside the trench failed to proceed. Further, when a thick ruthenium dioxide film is formed, the residual stress in the film causes cracking of the film. As mentioned above, when a method of coating a polyazide composition and then converting ruthenium dioxide is used, it has different problems due to different concentrations, and it is necessary to spend a lot of money in order to adjust to its most appropriate conditions. Japanese Patent Laid-Open Publication No. 2001-308090 (Patent Document 3) Japanese Laid-Open Patent Publication No. 2001-308090 (Patent Document 3) [Patent Document 5] Japanese Laid-Open Patent Publication No. Hei 01-24.8528. SUMMARY OF THE INVENTION In view of the foregoing, the present invention provides a coated polyazoxide composition having A shallow trench structure with sufficient insulating properties and a method of manufacturing the same. The shallow trench isolation structure provided by the present invention is characterized in that: a substrate having a trench structure at a surface; and a second dicing film for embedding the trench, wherein the cerium oxide film is limited to a surface side of the substrate, And the bottom of the groove is provided with a hole. Further, the manufacturing method of the shallow trench isolation structure provided by the present invention includes: (A) a coating step of forming a coating film by coating a surface of a substrate having a grooved structure with a nitroxane composition; (B) applying the coating The surface is irradiated with ultraviolet rays to harden a part of the polyfluorene nitrogen near the surface of the coating film, and the ultraviolet rays which form voids at the bottom of the groove portion are sufficiently tempered by the filming. 0005 is thinned to be oxidized to the surface of the polyfluorene film by irradiating the alkane 201003839; and (c) a sintering step of forming the ceria film by sintering the coating film. According to the present invention, a shallow trench isolation structure having a hole with a shallow hole and excellent insulation properties is provided, and a shallow trench can be formed simply and at low cost. [Embodiment] Shallow trench isolation structure The present invention The shallow trench isolation structure is provided with a substrate and a shallow trench isolation structure for embedding the trench, and the shallow trench isolation structure is characterized in that the buried trench does not completely fill the trench interior, but is limited to There are voids at the bottom of the trench. In the first embodiment, the shape (insulation film) 2 is formed in the vicinity of the surface of the groove portion of the substrate 1, and the bottom portion is formed in the bottom portion of the groove portion. The hollow hole 3 of the present invention is not relatively relatively ' Rather, it is essentially a continuous formation of voids. That is, the ruthenium dioxide film 2 having a strip shape or a rope shape formed in a groove shape to embed the groove is present on the surface side of the groove. That is, it can be said that it is buried in the trench by using dioxide. Then, the hole 3 is in contact with the inner surface of the groove, and there is no oxidation in the inner surface of the groove. When the shallow groove isolation structure is formed, it is considered that the hole is uniformly filled in the groove. good. Indeed, the insulation of the isolation structure can be improved by filling the trench internals. However, it was found after begging that the coating film was actually loaded on the surface of the substrate, and the overall hard isolation structure was different. Also, according to the present invention, the isolation structure. The surface has a grooved film. Then, the surface side of the germanium dioxide film substrate of the present invention is shown in the figure. It has a ruthenium dioxide film and a hole 3. Referring to the collection of the first small holes, the shape of the hole of the present invention. Then, the inside of the groove is used, but the confining film 2 is used to directly connect the hole 3 interface to the film. Conventional technology The film is dense and dense and uniform. When the inventors passed the element, it is relatively difficult to apply an electric field at the bottom of the groove 201003839, so that it is not required to be too high. Moreover, the voids formed in the trenches are inherently relatively high in insulation. That is, it is particularly necessary to have a high insulation property in the vicinity of the surface of the proximity element, and it is only necessary to form a dense insulating film near the surface, and even if the bottom of the groove is a void, the insulation required as the isolation structure can be achieved. Sex. Then, since voids are formed at the bottom of the trench, it is believed that the ruthenium dioxide film located directly above it is pressed to form a denser ruthenium dioxide film. Here, although a specific size is recommended for the isolation structure to achieve a better insulating property f, the trench isolation structure of the present invention is excellent in the case where the groove width is narrower or the aspect ratio is higher. Characteristics. That is, the width a of the groove is preferably 5 to 50 nm, and the width a is preferably 5 to 40 nm. Further, the ratio of the depth b of the groove divided by the width a of the groove, that is, the aspect ratio b/a is preferably 10 to 100, more preferably 1 to 50. Further, when the length of the hole in the depth direction of the groove is c, it is more preferable that c is 5 to 100 nm, and the length c is preferably 5 to 50 nm. Further, when observing the cross section perpendicular to the longitudinal direction of the groove, the ratio of the sectional area of the void to the sectional area of the groove ί structure is preferably 5 to 20%, more preferably 8 to 15%. When the ratio of the length of the void in the depth direction of the trench or the cross-sectional area of the void is a specific enthalpy or more, a dense ruthenium dioxide film can be obtained, and the insulating property of the isolation structure can be sufficiently exhibited. Further, as the pores increase, the ruthenium dioxide film is more dense due to the compression, and the tensile stress is reduced while the physical strength is more sufficient. Further, in the present invention, although voids are present at the bottom of the trench, there is almost no ruthenium dioxide film in this portion. That is, in the pore portion, the inner wall of the groove is hardly adhered with cerium oxide. Therefore, since the ratio of the sectional area of the void to the sectional area of the groove structure 201003839 is approximately equal to c/b, the ratio c/b is preferably 0.05 to 0.2, more preferably 0.08 to 0.15. Further, in the shallow trench isolation structure of the present invention, when the width and aspect ratio of the trench and the size of the void are as described herein, the effect is strongly expressed 'but is not particularly limited to the size, and only needs to have The present invention can be obtained by embedding a trench on a substrate by a ruthenium dioxide film, and the ruthenium dioxide film is limited to the surface side of the substrate, and a structure having pores formed at the bottom of the trench is formed. The effect. f Method of Forming Shallow Trench Isolation Structure The shallow trench isolation structure as described above can be formed by any method. An example of the formation method includes: (A) a coating step of forming a coating film by coating a polyazide composition on a surface of a substrate having a groove structure; (B) irradiating ultraviolet rays on a surface of the coating film to cause the coating a portion of the polyazide adjacent to the surface of the film is hardened, and a step of forming an ultraviolet ray at the bottom of the groove portion; and ί (C) hardening the coating film by sintering the coating film A sintering step of forming a hafnium oxide film. The method for forming the shallow trench isolation structure of the present invention is characterized in that after coating the polyazide composition, first, the surface of the coating film is irradiated with ultraviolet rays to temporarily harden the vicinity of the surface and then sintered, so that the entire coating film is converted into Ceria film. First, the oxidation and polymerization of the polyazane composition are initiated by the irradiation of ultraviolet rays on the surface of the substrate, and thus the shrinkage of the volume is caused. As a result, the force of the upward pulling up is generated for the polyazide composition in the trench or the cerium oxide film formed by the conversion. Then, in the table

201003839 面附近之二氧化矽膜的密度提高且更加緻密, 部產生空孔。隨後之燒結步驟中,雖然二氧化 加收縮的傾向,但由於其未接觸溝槽內底部, 向不產生拉力而使得二氧化矽膜可達成更高之 亦即,習知技術中爲了均句地塡充溝槽內 相對較低的二氧化矽膜來塡充溝槽內,相對地 請案發明之方法所形成的淺溝槽隔離構造則僅 形成密度較高的二氧化矽膜(絕緣膜)。 關於本發明之淺溝槽隔離構造之形成方法 明係記載如下。 (A)塗布步驟 首先,準備具有用以形成淺溝槽隔離構 造’亦即具有凹凸之基板。基板之材質並無特 使用例如矽基板等習知之任何基板。又,可使 文獻1或2所記載之任何方法來於基板表面形 體方法係記載如下。 首先,藉由例如熱氧化法而於矽基板表面 矽膜。此處所形成的二氧化矽膜厚度一般係爲 依需求可於所形成之二氧化矽膜上藉由例 法來形成氮化矽膜。該氮化矽膜係可於後續之 作爲遮罩、抑或於後述硏磨步驟中作爲停止層 矽膜之情況,一般形成100〜400nm的厚度。 於前述所形成之二氧化矽膜或氮化矽膜 阻。依需求將光阻膜乾燥或硬化後,以所期望 光及顯影而形成圖案。曝光方法係可使用遮澤 而於溝槽底 矽膜係有更 故於底面方 密度。 而使用密度 ,藉由本申 於表面附近 的更詳細說 造的溝槽構 別限定,可 用例如專利 成溝槽。具 形成二氧化 5 〜3 0 n m。 如減壓CVD 蝕刻步驟中 。形成氮化 上再塗布光 之圖案來曝 曝光、掃描 -10-201003839 The density of the cerium oxide film near the surface is increased and more dense, and voids are formed in the part. In the subsequent sintering step, although the tendency of the oxidizing and shrinking is not caused, the cerium oxide film can be made higher even if it does not contact the inner bottom of the groove, that is, in the prior art, The relatively low ceria film in the trench is filled to fill the trench, and the shallow trench isolation structure formed by the method of the present invention relatively forms only a high-density ceria film (insulating film). . A method of forming the shallow trench isolation structure of the present invention is described below. (A) Coating step First, a substrate having a shallow trench isolation structure, i.e., having irregularities, is prepared. The substrate material is not particularly limited to any conventional substrate such as a germanium substrate. Further, any of the methods described in Document 1 or 2 can be described as follows. First, the film is deposited on the surface of the substrate by, for example, thermal oxidation. The thickness of the cerium oxide film formed here is generally such that a cerium nitride film can be formed by an example on the formed cerium oxide film as needed. The tantalum nitride film can be formed as a mask or a ruthenium film as a stop layer in a honing step to be described later, and generally has a thickness of 100 to 400 nm. The ruthenium dioxide film or the tantalum nitride film formed as described above. After the photoresist film is dried or hardened as required, a pattern is formed with desired light and development. In the exposure method, the mask can be used to make the film at the bottom of the groove more dense than the bottom surface. The use density, as defined by the more detailed description of the groove configuration near the surface, can be used, for example, as a patent groove. With the formation of dioxide 5 ~ 3 0 n m. Such as a vacuum CVD etching step. Forming a pattern of light on the nitride to expose the exposure and scanning -10-

201003839 曝光等任何方法來進行。又,亦可就解 任何光阻。 以所形成之光阻膜作爲遮罩,依序 位於其下方之二氧化矽膜。藉由此作業 二氧化矽膜形成所期望的圖案。 以形成有圖案之氮化矽膜及二氧化 矽基板乾蝕刻而形成溝槽隔離溝槽。 該形成之溝槽隔離溝槽之寬度係由 案所決定的。雖然半導體元件中溝槽隔 據最終目的之半導體元件而作適當的設 選自於前述淺溝槽隔離構造項目中所述 發明之淺溝槽構造之形成方法係與習知 均勻地塡充溝槽內。因此,基板表面所 爲更窄、更深之結構。 其次,於前述準備之矽基板上塗布 材料的聚矽氮烷組成物而形成塗布膜。 係可使用將習知的任何聚矽氮烷組成物 本發明所使用之聚矽氮烷組成物並 不損害本發明效果係可隨意選用。其亦 有機化合物中任一者。該等聚砍氮院中 式(la)〜(Ic)表示之單位所組合而成者較 析度等觀點來選用 地蝕刻氮化矽膜及 ,而於氮化矽膜及 矽膜作爲遮罩,將 使光阻膜曝光的圖 離溝槽之寬度係根 定,但本發明中, 範圍者較佳。依本 方法不同,並非是 形成之溝槽構造可 用作二氧化矽膜之 該聚矽氮烷組成物 溶解於溶媒者。 無特別限定,只要 可爲無機化合物或 ,可舉出由下述通 佳:201003839 Exposure and any other method to carry out. Also, any photoresist can be solved. The formed photoresist film is used as a mask, and the ceria film is located underneath. By this operation, the hafnium oxide film forms a desired pattern. The trench isolation trench is formed by dry etching of the patterned tantalum nitride film and the hafnium oxide substrate. The width of the trench isolation trenches formed is determined by the case. The method for forming the shallow trench structure of the invention described in the above-mentioned shallow trench isolation structure item is suitably formed in the trench of the semiconductor device in accordance with the final purpose of the semiconductor device. . Therefore, the surface of the substrate is a narrower, deeper structure. Next, a polyazoxide composition of the material was applied onto the prepared substrate to form a coating film. Any polyazane composition which is conventionally used may be used. The polyazane composition used in the present invention is optional and can be optionally used without impairing the effects of the present invention. It is also an organic compound. The combination of the units represented by the formulas (la) to (Ic) in the polynitrazole chambers selectively etches the tantalum nitride film and the tantalum nitride film and the tantalum film as masks. The pattern in which the photoresist film is exposed is rooted from the width of the groove, but in the present invention, the range is preferred. Depending on the method, it is not the formed trench structure that can be used as the cerium oxide film in which the polyazane composition is dissolved in the solvent. It is not particularly limited as long as it can be an inorganic compound or, and it can be exemplified by the following:

-11 - 201003839 (式中,ml〜m3係表示聚合度) 其中更佳地’苯乙烯(styrene)換算重量平均分子量爲 700〜30,000者爲佳。 又’作爲其他之聚矽氮烷之例,例如,可列舉主要爲 具有由通式(11)所代表的構造單位所組成之骨格且數量平 均分子量爲約100〜50,000之聚砂氮院或其變性物: (Π) R2 R3 (式中,R1、R2及R3,各別獨立表示爲氫原子、烷基、 烯基、環烷基、芳香基抑或除前述以外之其他如氟烷基等 碳與矽直接鍵結的基、烷基矽烷基、烷胺基或烷氧基。但 是,R1、R2及R3中至少任一者係爲氫,η表示聚合度)。該 等聚矽氮烷化合物亦可使用由2種類以上所組合而成者。 本發明所使用之聚矽氮烷組成物係含有可溶解前述聚 矽氮烷化合物的熔媒。此處所使用之溶媒與前述用於浸潤 用溶液的溶媒不同。作爲此種溶媒,雖然僅需爲可溶解前 述各成分者即可而未特別限定,作爲較佳之熔媒的具體 例,係列舉如下: (a)芳香族化合物,例如苯、甲苯、二甲苯、乙苯、二 乙苯、三甲苯、三乙苯等;(b)飽和烴化合物,例如n-戊烷、 i·戊烷、η-己烷、i-己烷、η-庚烷、1-庚烷、η-辛烷、:i-辛烷、 η-壬烷、i-壬烷、η-癸烷、i-癸烷等;(c)脂環式烴化合物, 例如乙環己烷、甲環己烷、環己烷、環己烯、P-薄荷烷 (p-menthane)、十氫化荼、雙戊嫌、檸檬稀(limonene) -12- 201003839 等;(d)醚類,例如二異丙醚、二丁醚、二***、甲基第三 丁基醚(以下稱作MTBE)、苯甲醚等;以及(e)酮類,例如甲 異丁酮(以下稱作MIBK)等。其中,較佳者係爲(b)飽和烴化 合物、(c)脂環式烴化合物、(d)醚類以及(e)酮類。 該等溶劑,爲了調整溶劑之蒸發速度、爲了降低對人 體之有害性、抑或爲了調製各成分之溶解性,亦可適當地 使用混合有2種以上者。 本發明所使用之聚矽氮烷組成物中,依需求亦可含有 f 其他的添加劑成分。作爲該等成分,係可舉出例如用作促 進聚矽氮烷之交聯反應的交聯促進劑、用作二氧化矽之轉 化反應的觸媒、爲了調製組成物之黏度的黏度調整劑等。 又,亦可含有以使用於半導體裝置時的鈉吸氣效果爲目的 之磷化合物,例如Tris(三甲基矽烷基(trimethylsilyl))磷酸 鹽等。 又,前述各成分之含有量係依據塗布條件或燒結條件 等而變化。但是,聚矽氮烷化合物之含有率係爲以聚矽氮 ί 烷組成物之總重量爲基準的1〜30重量%者爲佳,2〜20 重量%爲更佳。但其並非用以限定聚矽氮烷組成物含有之 聚矽氮烷的濃度,只要可形成本發明特定之淺溝槽隔離構 造即可,可使用任何濃度之聚矽氮烷組成物。又,雖然聚 矽氮烷以外之各種添加劑含量係依添加劑之種類而變化, 但其相對聚矽氮烷化合物之添加量宜爲0.001〜40重量 %,較佳地係爲0.005〜30重量%,更佳地係爲〇.〇1〜20 重量%。 前述之聚矽氮烷組成物能以任何方法而塗布於基板 -13- 201003839 上。具體地係可舉出旋轉塗布、簾幕塗布、浸漬塗布或其 他。其中,就塗布膜之均勻性等觀點來看,特別建議旋轉 塗布。塗布之塗布膜的厚度、亦即基板表面非溝槽部分之 塗布膜厚度爲20〜150nm者較佳,更佳地係爲30〜100nm。 需注意的是,當塗布膜厚度太厚時,後述之紫外線可能無 法到達溝槽內的表面附近處,另一方面當塗布膜太薄時塡 充於溝槽內之聚矽氮烷組成物不足,可能導致溝槽之側壁 傾倒或無法形成足夠膜厚之二氧化矽膜。 f (B)紫外線照射步驟 其次,以紫外線照射聚矽氮烷組成物塗布膜的表面。 該紫外線係爲了讓塗布步驟時形成之聚矽氮烷塗布膜之表 面附近發生氧化或聚合反應爲目的。因此,紫外線需能到 達溝槽內。 雖然所使用之紫外線的波長亦與聚矽氮烷組成物之種 類有關,但以150〜200nm者較佳。更佳地係爲170〜 190nm。照射之光能量以〇.〇5〜l〇〇mj/cm2者較佳,更佳地 係爲 0.1 〜50mJ/cm2。 照射步驟一般可於空氣中進行。但是,由於氧會吸收 例如20〇nm以下波長之光線,故依環境氣體之氧濃度或光 源與基板之間的距離’光線係有可能在到達基板表面之前 即被環境氣體中的氧所吸收’而未能有充份的光線到達溝 槽內。因此,較佳地,依需求而在氮等不會吸收紫外線之 非活性氣體與空氣或氧混合的環境氣體下、抑或在不會吸 收紫外線之非活性氣體的環境氣體下來進行紫外線照射。 藉由前述之紫外線照射’而使得塡充於溝槽內的聚矽 -14- 201003839 氮烷中,存在於基板表面附近者係引發氧化或聚合反應, 將聚矽氮烷組成物自溝槽內底部拉高,進而形成緻密之二 氧化矽與溝槽內底部之空孔的雛型。 再者,專利文獻4及5係揭露一種包含有紫外線照射 步驟的SOG膜之形成方法。但是,該等方法係讓溝槽內均 勻地塡充絕緣膜,其欲達成之構造係與本發明相異。 (C)燒結步驟 接續該紫外線照射步驟,係將聚矽氮烷塗布膜燒結而 使塗布膜整體轉化爲二氧化矽膜。藉由該燒結,使紫外線 照射步驟中所形成之二氧化矽膜之原型完全地變爲二氧化 矽膜,亦即轉化爲絕緣膜,該燒結係使用硬化爐或加熱板, 含有水蒸氣,並於非活性氣體或氧之環境氣體下進行爲較 佳。欲充份地使聚矽氮烷化合物轉化爲二氧化矽膜時,水 蒸氣與含有矽之化合物或含有矽之聚合物同時存在係爲重 要,宜爲1%以上,較佳者係爲10%以上,最佳者係爲20 %以上。特別於水蒸氣濃度爲20%以上時,係使聚矽氮烷 化合物轉化爲二氧化矽膜之反應變的更爲容易,使空孔等 缺陷之發生變少,並可改良二氧化矽膜之特性故係爲較 佳。使用非活性氣體作爲環境氣體時,係使用氮、氬或氦。 用以使其硬化之溫度條件,係根據所使用之聚矽氮烷 組成物的種類或步驟之組合方式而改變。但是,溫度較高 時,含有矽之化合物、含有矽之聚合物以及聚矽氮烷化合 物轉化爲二氧化矽之速度係有加速之傾向,又,當溫度較 低時,因矽基板之氧化或結晶構造之變化而對裝置特性之 不良影響係有變小之傾向。基於前述觀點,本發明方法通 -15- 201003839 常係於1 000°C以下,較佳於400〜900 °C以下來進行加熱。 此處,升溫至目標溫度之時間一般係爲1〜1 〇〇°c /分,而到 達目標溫度後之硬化時間一般係爲1分鐘〜1 〇小時’較佳 爲15分鐘〜3小時。亦可依需求而階段性地改變硬化溫度 或硬化環境氣體之組成。 藉由該加熱係使得存在於塗布膜中的聚矽氮烷化合物 轉化爲二氧化矽而獲得最終之淺溝槽隔離構造。依照前述 所獲得之本發明的淺溝槽隔離構造中,溝槽部附近之拉應 ( 力減低且物理性強度亦較高。其係因爲於燒結前預先進行 之紫外線照射而於溝槽底部形成空孔,進而增加存在於空 孔正上方部分之聚矽氮烷組成物或由其轉化而成之二氧化 砍膜之先趨物(precursor)的密度,並提高燒結所形成之二氧 化矽膜的密度。 本發明之淺溝槽隔離構造之形成方法中,前述(A)〜(C) 步驟係爲必要,但亦可依需求而增加下列之輔助步驟。 (a)溶媒去除步驟 L 於塗布步驟後,係於燒結步驟前預先對塗布有聚矽氮 烷組成物之基板進行預烘烤(pre-bake)處理。該步驟係將塗 布膜中所含有之溶媒的至少一部份去除爲其目的。 通常於溶媒去除步驟中,係採用實質地加熱至一特定 溫度的方法。此時,應於不讓聚矽氮烷實質地產生氧化或 聚合反應之條件下來進行該溶媒去除。因此,溶媒去除步 驟之溫度通常爲50〜250 °C,較佳爲80〜200 °C範圍內。溶 媒去除步驟所需時間一般係爲0.5〜10分鐘,較佳爲1〜5 分鐘。 -16- 201003839 (b) 硏磨步驟 於硬化後,宜將硬化後之二氧化矽膜中不需要的部分 去除。爲此,首先藉由硏磨步驟,留下形成於基板上之溝 槽部內側的二氧化矽膜,並藉由硏磨來去除形成於基板表 面之平坦部上的二氧化矽膜。該步驟係爲硏磨步驟。該硏 磨步驟除了可在硬化處理後進行,亦可與預烘烤步驟組 合,並於預烘烤後隨即進行。 硏磨一般係藉由CMP來進行的。該CMP硏磨,係可藉 , 由一般之硏磨劑及硏磨裝置來進行。具體而言,該硏磨劑 V . 係可使用一種將氧化砂(silica)、氧化錫或氧化飾等的硏磨 材料與其他依需求之添加劑分散的水溶液等,該硏磨裝置 係可使用市售一般之CMP裝置。 (c) 蝕刻步驟 前述之硏磨步驟中,雖然幾乎已將由形成於基板表面 之平坦部上的聚矽氮烷組成物所習成的二氧化矽膜去除’ 但爲了去除殘留在基板表面之平坦部的二氧化砂膜’宜更 進一步進行蝕刻處理。一般蝕刻處理係使用鈾刻液’該蝕 刻液僅需能將二氧化矽膜去除即可,並未有特殊限制’但 通常係使用含有氟化銨的氫氟酸水溶液。該水溶液之氟化 銨濃度宜爲5%以上,較佳者係爲30%以上。 本發明之各實施例係如下所述。 實施例1 首先,準備於表面具有溝槽構造的矽基板。該溝槽之 寬度爲40nm’深度爲600nm(縱橫比爲15)。 以聚矽氮烷之二丁醚溶液(以組成物組重量爲基準之 -17- 201003839 固體量濃度爲12重量%)針對前述基板於迴轉速度lOOOrpm 之條件下進行旋轉塗布,並於1 5 0 °C、1分鐘之條件下將溶 媒之一部分去除。此時,基板表面之溝槽構造以外的部分 處聚矽氮烷組成物塗布膜之膜厚爲8 0 nm。又,將該基板於 垂直表面之方向切斷,並使用掃描式電子顯微鏡(日立製作 所股份有限公司製S-4700型(商品名))觀察溝槽構造的剖面 時,溝槽內並未檢測到空孔。 於該基板表面,使用準分子UV照射裝置(USHIO電機 股份有限公司製),以波長172nm之紫外線於10mW/cm2條 件下照射3分鐘。 使用掃描式電子顯微鏡來觀察此時之溝槽構造的剖面 時,可確認於溝槽構造之底部係形成有空孔。 再將該基板使用水蒸氣氧化爐VF- 1 000(商品名:光洋 Thermo System股份有限公司製),並以氧/水蒸氣混合氣體 (H2〇/(〇2 + H2〇) = 80mol%)於8公升/分之速度流通的環境氣 體下’在400 °C燒結1小時。接著再於N2環境氣體下以700 °C進行退火處理1小時。所獲得之樣本進行拉應力測試 時,係爲lOMpa。 又,以掃描式電子顯微鏡來觀察其剖面時,係維持有 燒結前之空孔,而形成於溝槽底部具有空孔之淺溝槽隔離 構造。 此處,使用含有0.5重量%之氫氟酸、20重量%濃度 之氟化銨水溶液作爲緩衝劑,來檢測形成於空孔正上方之 二氧化矽膜的溼蝕刻率。實施例1之二氧化矽膜的溼蝕刻 率係爲以熱氧化膜作爲基準的1. 8〇倍。 比較例1 -18- 201003839 相較於實施例1’除不照射紫外線之外,其餘步驟皆 相同地於具有溝槽構造之基板上形成聚矽氮烷塗布膜。觀 察該塗布膜之剖面時,溝槽內部幾乎被均勻地塡充,而並 未檢測到空隙。 再與實施例1相同地進行燒結與退火處理,將所獲得 之樣本進行拉應力測試時,係爲1 20Mpa。已知該結果係較 實施例1高出許多,且溝槽內部容易發生龜裂或脫落等缺 陷。 „ 又,以掃描式電子顯微鏡來觀察其剖面時,係形成於 溝槽內無空孔之淺溝槽隔離構造。 關於所獲得之二氧化矽膜,係與實施例1相同地檢測 其溼蝕刻率。比較例1之二氧化矽膜的溼蝕刻率係爲以熱 氧化膜作爲基準的4.10倍。此處,已知溼蝕刻率與膜應力 (拉應力)係呈正比,亦即,實施例1之二氧化矽膜的溼蝕 刻率較低且較佳。再者,一般當其溼蝕刻率超過3時,就 實用性之觀點其用途係受限制。 【圖式簡單說明】 第1圖係爲本發明之淺溝槽隔離構造的剖面示意圖。 【主要元件符號說明】 1 基板 2 絕緣膜 3 空孔 a 溝槽寬度 b 溝槽深度 c 空孔於溝槽深度方向之長度 -19--11 - 201003839 (wherein ml~m3 represents a degree of polymerization). More preferably, the styrene-based weight average molecular weight is preferably from 700 to 30,000. Further, as an example of the other polyazane, for example, a polysalt nitrogen or the like having a structural unit composed of the structural unit represented by the general formula (11) and having a number average molecular weight of about 100 to 50,000 or Denature: (Π) R2 R3 (wherein R1, R2 and R3 are each independently represented by a hydrogen atom, an alkyl group, an alkenyl group, a cycloalkyl group, an aromatic group or other carbons such as a fluoroalkyl group other than the above. A group directly bonded to an anthracene, an alkylalkylene group, an alkylamino group or an alkoxy group. However, at least one of R1, R2 and R3 is hydrogen, and η represents a degree of polymerization). These polyazide compounds may be used in combination of two or more types. The polyazane composition used in the present invention contains a solvent which can dissolve the above polyazide compound. The solvent used herein is different from the aforementioned solvent for the solution for infiltration. The solvent is not particularly limited as long as it can dissolve the above components. Specific examples of the preferred solvent are as follows: (a) an aromatic compound such as benzene, toluene or xylene. Ethylbenzene, diethylbenzene, trimethylbenzene, triethylbenzene, etc.; (b) saturated hydrocarbon compounds such as n-pentane, i.pentane, η-hexane, i-hexane, η-heptane, 1- Heptane, η-octane, i-octane, η-decane, i-decane, η-decane, i-decane, etc.; (c) an alicyclic hydrocarbon compound such as ethylcyclohexane, Methane, cyclohexane, cyclohexene, p-menthane, decahydroquinone, diammonium, limonene -12-201003839, etc.; (d) ethers, such as two Isopropyl ether, dibutyl ether, diethyl ether, methyl tertiary butyl ether (hereinafter referred to as MTBE), anisole, etc.; and (e) ketones such as methyl isobutyl ketone (hereinafter referred to as MIBK). Among them, preferred are (b) a saturated hydrocarbon compound, (c) an alicyclic hydrocarbon compound, (d) an ether, and (e) a ketone. These solvents may be used in an appropriate manner in order to adjust the evaporation rate of the solvent, to reduce the harmfulness to the human body, or to prepare the solubility of each component. The polyazane composition used in the present invention may contain other additive components as needed. Examples of the components include a crosslinking accelerator for promoting a crosslinking reaction of polyazane, a catalyst for a conversion reaction of cerium oxide, and a viscosity modifier for modulating the viscosity of the composition. . Further, it may contain a phosphorus compound for the purpose of utilizing a sodium gettering effect in a semiconductor device, for example, Tris (trimethylsilyl) phosphate. Further, the content of each of the above components varies depending on coating conditions, sintering conditions, and the like. However, the content of the polyazide compound is preferably from 1 to 30% by weight based on the total weight of the polyazinane composition, and more preferably from 2 to 20% by weight. However, it is not intended to limit the concentration of polyazane contained in the polyazane composition, and any concentration of the polyazane composition may be used as long as the specific shallow trench isolation structure of the present invention can be formed. Further, although the content of each additive other than polyazane varies depending on the kind of the additive, the amount of the polyazane compound added is preferably 0.001 to 40% by weight, preferably 0.005 to 30% by weight, More preferably, it is 〜.〇1 to 20% by weight. The aforementioned polyazane composition can be applied to the substrate -13-201003839 by any method. Specifically, spin coating, curtain coating, dip coating, or the like can be mentioned. Among them, spin coating is particularly recommended from the viewpoint of uniformity of the coating film and the like. The thickness of the applied coating film, that is, the thickness of the coating film on the non-grooved portion of the substrate surface is preferably from 20 to 150 nm, more preferably from 30 to 100 nm. It should be noted that when the thickness of the coating film is too thick, the ultraviolet rays described later may not reach the vicinity of the surface in the groove, and on the other hand, when the coating film is too thin, the composition of the polyazane filling in the groove is insufficient. It may cause the sidewall of the trench to pour or fail to form a cerium oxide film of sufficient film thickness. f (B) Ultraviolet irradiation step Next, the surface of the coating film of the polyazirane composition is irradiated with ultraviolet rays. This ultraviolet ray is intended to cause oxidation or polymerization reaction in the vicinity of the surface of the polyazirane-coated film formed at the coating step. Therefore, the UV light needs to reach the trench. Although the wavelength of the ultraviolet light to be used is also related to the type of the polyoxazane composition, it is preferably 150 to 200 nm. More preferably, it is 170 to 190 nm. The light energy to be irradiated is preferably 〇5 〇〇 l 〇〇 mj/cm 2 , more preferably 0.1 〜 50 mJ/cm 2 . The irradiation step can generally be carried out in air. However, since oxygen absorbs light having a wavelength of, for example, 20 〇 nm or less, depending on the oxygen concentration of the ambient gas or the distance between the light source and the substrate, the light ray may be absorbed by oxygen in the ambient gas before reaching the surface of the substrate. There is not enough light to reach the trench. Therefore, it is preferred to carry out ultraviolet irradiation under an environmental gas in which an inert gas which does not absorb ultraviolet rays is mixed with air or oxygen or an inert gas which does not absorb ultraviolet rays, as required. In the polyfluorene-14-201003839 azane which is filled in the trench by the aforementioned ultraviolet irradiation, the presence of the polyoxazane composition in the trench is initiated in the vicinity of the surface of the substrate. The bottom is pulled up to form a compact shape of the dense cerium oxide and the pores in the bottom of the trench. Further, Patent Documents 4 and 5 disclose a method of forming an SOG film including a step of irradiating ultraviolet rays. However, these methods allow the trench to uniformly fill the insulating film, and the desired structure is different from the present invention. (C) Sintering step Following the ultraviolet irradiation step, the polyazirane coating film is sintered to convert the entire coating film into a cerium oxide film. By the sintering, the prototype of the cerium oxide film formed in the ultraviolet ray irradiation step is completely changed into a cerium oxide film, that is, converted into an insulating film which uses a hardening furnace or a heating plate and contains water vapor, and It is preferably carried out under an ambient gas of an inert gas or oxygen. In order to sufficiently convert the polyazide compound into a cerium oxide film, it is important that the water vapor is present at the same time as the cerium-containing compound or the cerium-containing polymer, and is preferably 1% or more, preferably 10%. Above, the best is 20% or more. In particular, when the water vapor concentration is 20% or more, the reaction of converting the polyazide gas compound into the ruthenium dioxide film is easier, the occurrence of defects such as voids is reduced, and the ruthenium dioxide film can be improved. The characteristics are preferred. When an inert gas is used as the ambient gas, nitrogen, argon or helium is used. The temperature conditions for hardening are varied depending on the type or combination of steps of the polyazane composition used. However, at higher temperatures, the rate at which the ruthenium-containing compound, the ruthenium-containing polymer, and the polyazide compound are converted to ruthenium dioxide tends to accelerate, and when the temperature is low, the ruthenium substrate is oxidized or The adverse effect on the device characteristics due to the change in the crystal structure tends to be small. Based on the foregoing, the method of the present invention is usually carried out at a temperature below 1 000 ° C, preferably below 400 ° 900 ° C. Here, the time for raising the temperature to the target temperature is generally 1 to 1 〇〇 ° c / min, and the hardening time after reaching the target temperature is generally 1 minute to 1 〇 hour', preferably 15 minutes to 3 hours. The hardening temperature or the composition of the hardening ambient gas can also be changed stepwise according to requirements. The final shallow trench isolation structure is obtained by converting the polyazide compound present in the coating film to cerium oxide by the heating system. According to the shallow trench isolation structure of the present invention obtained as described above, the tension in the vicinity of the groove portion is reduced (the force is reduced and the physical strength is also high. This is formed at the bottom of the groove due to the ultraviolet irradiation previously performed before sintering. The pores, thereby increasing the density of the polyazide composition present in the portion directly above the pore or the precursor of the dioxide etched film formed therefrom, and increasing the cerium oxide film formed by sintering Density. In the method for forming the shallow trench isolation structure of the present invention, the above steps (A) to (C) are necessary, but the following auxiliary steps may be added as needed. (a) Solvent removal step L for coating After the step, the substrate coated with the polyazide composition is pre-baked before the sintering step. This step removes at least a portion of the solvent contained in the coating film. Purpose Generally, in the solvent removal step, a method of substantially heating to a specific temperature is employed. At this time, the solvent removal should be carried out under conditions in which the polyazane is not substantially oxidized or polymerized. Therefore, the temperature of the solvent removal step is usually in the range of 50 to 250 ° C, preferably 80 to 200 ° C. The time required for the solvent removal step is generally 0.5 to 10 minutes, preferably 1 to 5 minutes. - 201003839 (b) After the hardening step, it is preferable to remove the unnecessary portion of the hardened cerium oxide film. For this purpose, first, by the honing step, the inside of the groove portion formed on the substrate is left. a ruthenium dioxide film, and ruthenium is used to remove the ruthenium dioxide film formed on the flat portion of the surface of the substrate. This step is a honing step. The honing step can be performed after the hardening treatment, or The baking step is combined and immediately after prebaking. The honing is generally carried out by CMP. The CMP honing can be carried out by a general honing agent and a honing device. The honing agent V can be an aqueous solution obtained by dispersing a honing material such as silica, tin oxide or oxidized oxide with other additives according to requirements, and the honing device can be used in a commercially available manner. CMP device (c) etching step aforementioned honing step In the case, the cerium oxide film which is conventionally formed from the polyazide composition formed on the flat portion of the surface of the substrate is removed, but it is preferable to remove the sulphur dioxide film remaining in the flat portion of the surface of the substrate. The etching treatment is carried out. Generally, the etching treatment uses an uranium engraving liquid. The etching liquid only needs to be able to remove the hafnium oxide film, and there is no particular limitation. However, an aqueous solution containing hydrofluoric acid containing ammonium fluoride is usually used. The ammonium fluoride concentration is preferably 5% or more, preferably 30% or more. Embodiments of the present invention are as follows. Embodiment 1 First, a ruthenium substrate having a grooved structure on the surface is prepared. The width is 40 nm' the depth is 600 nm (the aspect ratio is 15). The dibutyl ether solution of polyazane (-17-201003839 based on the weight of the composition group) has a solid concentration of 12% by weight for the aforementioned substrate. Spin coating was carried out under a rotation speed of 1000 rpm, and one part of the solvent was partially removed at 150 ° C for 1 minute. At this time, the film thickness of the polyazoxide composition coating film at a portion other than the groove structure on the surface of the substrate was 80 nm. In addition, when the substrate was cut in the direction of the vertical surface and the cross section of the groove structure was observed using a scanning electron microscope (S-4700 (trade name) manufactured by Hitachi, Ltd.), the groove was not detected. Empty hole. The surface of the substrate was irradiated with an ultraviolet light having a wavelength of 172 nm at a temperature of 10 mW/cm 2 for 3 minutes using an excimer UV irradiation device (manufactured by USHIO Electric Co., Ltd.). When the cross section of the trench structure at this time was observed using a scanning electron microscope, it was confirmed that voids were formed in the bottom of the trench structure. Further, the substrate was subjected to a steam oxidation furnace VF-1 000 (trade name: manufactured by Koyo Thermo Systems Co., Ltd.), and an oxygen/water vapor mixed gas (H2〇/(〇2 + H2〇) = 80 mol%) was used. Sintering at 400 °C for 1 hour under ambient gas flow at a speed of 8 liters/min. Annealing was then carried out at 700 ° C for 1 hour under N 2 ambient gas. When the obtained sample was subjected to tensile stress test, it was lOMpa. Further, when the cross section was observed by a scanning electron microscope, the pores before sintering were maintained, and a shallow trench isolation structure having pores at the bottom of the trench was formed. Here, the wet etching rate of the cerium oxide film formed directly above the pores was measured using an aqueous solution of ammonium fluoride containing 0.5% by weight of hydrofluoric acid and 20% by weight as a buffer. 8倍倍。 The wet etching rate of the cerium oxide film of the first embodiment is 1. 8 〇 times. Comparative Example 1 -18-201003839 The polypyrazine coating film was formed on the substrate having the groove structure in the same manner as in Example 1 except that the ultraviolet ray was not irradiated. When the cross section of the coating film was observed, the inside of the groove was almost uniformly filled, and no void was detected. Further, sintering and annealing treatment were carried out in the same manner as in Example 1, and when the obtained sample was subjected to a tensile stress test, it was 1 20 MPa. This result is known to be much higher than that of the first embodiment, and the inside of the groove is liable to be cracked or peeled off. „ Further, when the cross section is observed by a scanning electron microscope, it is formed in a shallow trench isolation structure having no voids in the trench. The obtained ruthenium dioxide film is wet-etched in the same manner as in the first embodiment. The wet etching rate of the cerium oxide film of Comparative Example 1 is 4.10 times as a reference based on the thermal oxide film. Here, it is known that the wet etching rate is proportional to the film stress (tensile stress), that is, the embodiment The wet etching rate of the cerium oxide film of 1 is lower and more preferable. Further, when the wet etching rate exceeds 3, the use is limited in view of practicality. [Simplified illustration] Fig. 1 A schematic cross-sectional view of the shallow trench isolation structure of the present invention. [Main component symbol description] 1 substrate 2 insulating film 3 void a groove width b trench depth c length of the hole in the depth direction of the trench -19-

Claims (1)

201003839 七、申請專利範圍: 1. 一種淺溝槽隔離構造,其特徵係具備: 於表面處具有溝槽構造的基板;以及 用以埋設該溝槽的二氧化矽膜’ 其中該二氧化砂膜局限於該基板之表面側,且於該溝槽 之底部具備空孔。 2. 如申請專利範圍第1項之淺溝槽隔離構造,其中該溝槽 之寬度係爲5〜50nm。 f 3.如申請專利範圍第1或2項之淺溝槽隔離構造,其中該 溝槽之縱橫比係爲10〜100。 4. 如申請專利範圍第1至3項中任一項之淺溝槽隔離構 造,其中該空孔中沿溝槽深度方向的長度係爲5〜100nm。 5. —種淺溝槽隔離構造之形成方法,其特徵係包含有: (A) 於具有溝槽構造的基板表面塗布聚矽氮烷組成物而 形成塗布膜的塗布步驟; (B) 於該塗布膜之表面照射紫外線來使得該塗布膜之表 1, 面附近的聚矽氮烷之一部份硬化,而於溝槽部份之底部 形成空孔的紫外線照射步驟;以及 (c)藉由燒結該塗布膜’使得該塗布膜整體硬化而形成 二氧化矽膜的燒結步驟。 6·如申請專利範圍第5項之淺溝槽隔離構造之形成方法, 其中於塗布步驟(A)與紫外線照射步驟(b)之間,更 進一步地包含使得含於該聚矽氮烷組成物之溶劑的至少 一部份蒸發而去除的溶媒去除步驟。 7.如申請專利範圍第5或6項之淺溝槽隔離構造之形成方 -20- 201003839 法,其中係殘留形成於該溝槽內部的二氧化矽膜’並藉 由硏磨來去除形成於該基板表面之多餘的二氧化矽膜。 8. 如申請專利範圍第5至7項中任一項之淺溝槽隔離構造 之形成方法,其中該聚矽氮烷組成物之固體含量係爲以 組成物之總重量爲基準的1〜30重量%。 9. 如申請專利範圍第5至8項中任一項之淺溝槽隔離構造 之形成方法,其中於該基板上不具備該溝槽構造之部 份,於塗布步驟(A)所形成之塗布膜的厚度係爲150nm 以下。 1 0.如申請專利範圍第5至9項中任一項之淺溝槽隔離構造 之形成方法,其中於燒結步驟中的燒結溫度係爲400〜 110CTC 。 -21 -201003839 VII. Patent application scope: 1. A shallow trench isolation structure, characterized in that: a substrate having a groove structure at a surface; and a ruthenium dioxide film for embedding the groove, wherein the SiO 2 film It is limited to the surface side of the substrate, and is provided with a hole at the bottom of the groove. 2. The shallow trench isolation structure of claim 1, wherein the trench has a width of 5 to 50 nm. f. The shallow trench isolation structure of claim 1 or 2, wherein the groove has an aspect ratio of 10 to 100. 4. The shallow trench isolation structure of any one of claims 1 to 3, wherein the length of the void in the depth direction of the trench is 5 to 100 nm. 5. A method for forming a shallow trench isolation structure, comprising: (A) a coating step of forming a coating film by coating a polyazoxide composition on a surface of a substrate having a groove structure; (B) The surface of the coating film is irradiated with ultraviolet rays to harden one of the polyazide in the vicinity of the surface of the coating film, and the ultraviolet irradiation step of forming a void at the bottom of the groove portion; and (c) The sintering step of sintering the coating film to cause the coating film to be entirely cured to form a ceria film. 6) The method for forming a shallow trench isolation structure according to claim 5, wherein between the coating step (A) and the ultraviolet irradiation step (b), the inclusion further comprises the polyazide composition A solvent removal step in which at least a portion of the solvent is evaporated to remove. 7. The method of forming a shallow trench isolation structure according to claim 5 or 6, wherein the ruthenium dioxide film formed inside the trench is left and removed by honing An excess of ruthenium dioxide film on the surface of the substrate. 8. The method for forming a shallow trench isolation structure according to any one of claims 5 to 7, wherein the solid content of the polyazane component is 1 to 30 based on the total weight of the composition. weight%. 9. The method for forming a shallow trench isolation structure according to any one of claims 5 to 8, wherein the portion of the trench structure is not provided on the substrate, and the coating formed in the coating step (A) The thickness of the film is 150 nm or less. A method of forming a shallow trench isolation structure according to any one of claims 5 to 9, wherein the sintering temperature in the sintering step is 400 to 110 CTC. -twenty one -
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