TW201003263A - Pixel array substrate - Google Patents

Abstract

A pixel array substrate including a substrate, a plurality of scan lines, a plurality of data lines, and a plurality of pixel structures is provided. The substrate includes a display area and an input area of the scan lines. The scan lines, the data lines, and the pixel structures are disposed in the display area, and wherein the scan lines are extended into the input area of the scan lines. The pixel structure is electrically connected to a corresponding scan line and a corresponding data line, and the pixel structure includes a thin film transistor and a pixel electrode. The pixel electrode is disposed above the scan line to form a compensation capacitor within an overlapping region between them. The overlapping region between the pixel electrode and the scan line of each pixel structure has a variably vertical distance, the variably vertical distances of the pixel structures are reduced from the input area of the scan lines to the direction far away the input area of the scan lines, and the compensation capacitors are increased from the input area of the scan lines to the direction far away the input area of the scan lines.

Description

201003263 26188twf.doc/d 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種晝素陣列基板，且特別是有關於 一種防止液晶顯示态之畫面發生閃爍(flicker)的晝素陣 基板。 —μ 【先前技術】 多媒體社會之急速進步多半受惠於半導體元件及顯示 裝置的飛躍性進步。就顯示器而言，具有高晝質、空間利 用效率佳、低/肖耗功率、無輕射等優越特性之液晶顯示器 (Liquid Crystal Display，LCD)已逐漸成為市場之主流。二 般而言，液晶顯示器包括液晶顯示面板（LCDpand)與用 以提供面光源的背光模組，其中，液晶顯示面板通常包括 薄膜電晶體陣列基板（Thin Film Transistor Array Substrate， TFT array substrate )、彩色濾光基板（c〇1〇r Filter _蚶伽， CF substrate)以及位於兩基板之間的液晶層〇iquid町咖 layer)。 圖1繪示為習知一種晝素陣列基板的電路示意圖。請 參照圖1，一般而言，晝素陣列基板1〇位於同一列上的晝 素結構 ρ·、ρ·、ρ1(Κ>·.之薄膜電晶體 TFTi()a、TFTi〇b、 TFT10(:…皆由同一條掃描配線(scan iine)sl〇進行驅動。當 掃描配線S10提供足夠的開啟電壓時，連接至掃描配線s 1 〇 的薄膜電晶體TFT10A、TFTiqb、TFTi〇c…就會被打開，以 使各條資料配線D10所搭載的資料(電壓位準）能夠寫入晝 素結構P10A、P1()B、。當上述寫入動作完成後，薄膜 201003263 2618Stwf.doc/d ，晶體tft10A、tft10B、TFT10C...就會被關閉，並藉由液 晶電容CLC與畫素儲存電容CsT等保持各畫素結構Ρι从/、 P_、Pi〇c…内晝素電極(pixei eiectr〇de)的電壓位準。 然而，當薄膜電晶體TFTi〇a、TFT·、TFTi〇c.. 閉日守’各晝素結構卩财义⑽^此…内之晝素電極的電壓 位準(level)很容易受到其他周圍電壓改變的影響而變動， 此電壓全動量稱為饋通電壓(Feed thiOugh v秦㈣，以下以 表示之。饋通電壓可表示為：201003263 26188twf.doc/d IX. Description of the Invention: [Technical Field] The present invention relates to a halogen substrate array, and more particularly to a halogen preventing flicker in a liquid crystal display state Array substrate. —μ [Prior Art] The rapid advancement of the multimedia society has largely benefited from the dramatic advances in semiconductor components and display devices. In terms of displays, liquid crystal displays (LCDs) with superior properties such as high quality, good space efficiency, low/short power consumption, and no light radiation have gradually become the mainstream of the market. In general, a liquid crystal display includes a liquid crystal display panel (LCDpand) and a backlight module for providing a surface light source, wherein the liquid crystal display panel usually includes a thin film transistor array (TFT) substrate, and a color A filter substrate (c〇1〇r Filter _ 蚶 ,, CF substrate) and a liquid crystal layer between the two substrates 〇iquid town cafe layer). FIG. 1 is a schematic circuit diagram of a conventional halogen matrix substrate. Referring to FIG. 1, in general, the pixel substrate 〇, ρ·, ρ1 of the halogen array substrate 1 〇 are located on the same column, and the thin film transistors TFTi()a, TFTi〇b, and TFT10 of the Κ> :... are all driven by the same scanning wiring (scan iine) sl. When the scanning wiring S10 provides a sufficient turn-on voltage, the thin film transistors TFT10A, TFTiqb, TFTi〇c... connected to the scanning wiring s 1 就会 are Turn on so that the data (voltage level) mounted on each data line D10 can be written to the pixel structure P10A, P1()B. When the above writing operation is completed, the film 201003263 2618Stwf.doc/d, the crystal tft10A , tft10B, TFT10C... will be turned off, and the pixel structure is maintained by the liquid crystal capacitor CLC and the pixel storage capacitor CsT, etc. 从ι from /, P_, Pi〇c... pixei eiectr〇de The voltage level. However, when the thin film transistor TFTi〇a, TFT·, TFTi〇c.. is closed, the voltage level of the elemental electrode in the 昼 卩 昼 昼 昼 昼 10 10 10 10 It is easily changed by the influence of other surrounding voltage changes. This voltage full momentum is called the feedthrough voltage (Feed thiOug). h v Qin (4), denoted below. The feedthrough voltage can be expressed as:

Vfd-[CGd/(Clc+Cst+Cgd)]xAVg ⑴ f中，方程式⑴内的Cu：為液晶電容，&為畫素儲 存電容’ CGD為薄膜電晶體之閘極與汲極間之電容，^ 則為掃描配線在開啟與關閉薄膜f晶體時的電驗。在^ =曰顯示器之躺原理巾，主要就是#由施加Vfd-[CGd/(Clc+Cst+Cgd)]xAVg (1) f, Cu in equation (1) is a liquid crystal capacitor, & is a pixel storage capacitor 'CGD is the capacitance between the gate and the drain of the thin film transistor , ^ is the scan of the wiring when turning on and off the film f crystal. In the ^ = 曰 display lying principle towel, mainly is # by application

At小=晶分子的旋轉角度，進而表現出各種： 的電場A小是由各晝素結構 ’、’、 電極(common electrode)的電虔差戶斤 :=因:匕!巧極的電屋位準受軸壓〜影響而 交寺，就曰衫響液晶顯示器的顯示效果。 -般而言’經由調整共用電極之 所造成之影響。然而，由於掃=二= 己響’使得Vfd會隨著畫素結構距離掃描 所(rreaofthescanlines)越遠而越小，亦 /不之旦素結構Pl〇A、Pl0B、P】〇c的VFD會呈現 (VFD)A>( vfd)b>( VFD)C^,^ , 201003263 2618 8twf.doc/d 發生閃爍的情形。 【發明内容】 本發明提供一種晝素陣列基板，其各個晝素鈐 濟 可調變的補償電容，使各織素結·有相近 值。 本發明另提供一種晝素陣列基板，其各個晝素結搆具 調變的齡電容’使各個晝素結構具有相近的饋通银 本發明提出一種晝素陣列基板，包括一基板、多條掃 描配線、多條資料配線以及多個晝素結構。其中，基板包 括顯示區以及掃描配線輸入端區。多條掃描配線鱼^條資 料配線配置於齡W，其巾_配線延伸至掃描配線輸 入端區内。多個晝素結構配置於顯示區内，每一晝素結構 與對應的掃描配線與資料配線電性連接，每一晝^結^包 括薄膜電晶體與晝素電極’其巾’晝素電極覆蓋於掃描配 線上，以在晝素電極與掃描配線的重疊處產生一補償電 容。其中’在每-晝素結構的晝素電極與掃滅線的重最 處有一變動垂直距離，這些晝素結構中的這些變動垂直ς 離是從掃描配線輸入端區往遠離掃描配線輸入端區的方 逐，減少，以使這些補償電容的大小自掃描配線輸入端‘ 往遠離掃描配線輸入端區的方向逐漸增加。 在本發明之一實施例中，在這些^素結構中，這些查 素電極與其所對應的掃描配線的重疊面積皆相同。 在本發明之-實施例中，上述之每—晝素結構更包括 7 201003263 26188twf.(i〇c/d 一共用配線，設置於晝素電極下方。At small = the rotation angle of the crystal molecules, which in turn exhibits various types: The electric field A is small by the electric structure of each elemental structure ', ', and the common electrode is: 因: 匕! Qiaoji's electric house The position is affected by the axial pressure ~ and the temple is given, and the display effect of the liquid crystal display is smashed. - Generally speaking, the effect of adjusting the common electrode. However, since the sweep = two = already sounded, the Vfd will be smaller as the distance from the rreaofthescanlines, and the VFD of the P/A structure, Pl〇A, P10B, P, 〇c Presentation (VFD) A>(vfd)b>(VFD)C^,^ , 201003263 2618 8twf.doc/d A flicker occurs. SUMMARY OF THE INVENTION The present invention provides a halogen array substrate in which the compensation capacitances of the individual elements are adjusted so that the respective textures have similar values. The present invention further provides a halogen matrix substrate, wherein each of the halogen structures has a modulated age capacitance, such that each of the halogen structures has a similar feedthrough silver. The present invention provides a halogen array substrate comprising a substrate and a plurality of scan lines. , multiple data wiring and multiple halogen structures. Wherein, the substrate comprises a display area and a scanning wiring input end area. A plurality of scanning wiring wires are arranged at the age W, and the towel wiring extends to the scanning wiring input end region. A plurality of pixel structures are disposed in the display area, and each of the pixel structures is electrically connected to the corresponding scan wires and the data wires, and each of the wires includes a thin film transistor and a halogen electrode. On the scan wiring, a compensation capacitor is generated at the overlap of the pixel electrode and the scan wiring. Wherein 'the vertical distance between the ruthenium electrode and the wiper line of each-halogen structure is changed. The vertical deviation of these variations in the structure of the halogen is from the input end of the scan line to the input end of the scan line. The divergence is reduced so that the size of these compensation capacitors gradually increases from the scanning wiring input end toward the scanning wiring input end region. In an embodiment of the invention, in these structures, the overlapping areas of the pixel electrodes and their corresponding scan lines are the same. In the embodiment of the present invention, each of the above-described halogen structure further includes 7 201003263 26188 twf. (i〇c/d a common wiring disposed under the halogen electrode.

本^另提出—種晝素陣列基板，包括—基板、多停 #描配線、多條資料配線以及多個晝素結構。其中，基板 包括顯示區以及掃描配線輸入端區。多條掃描配線與^ 資料配線配置於顯示區内，其中掃描配線延伸至掃描配線 輸入端區内。多個晝素結構配置於顯示區内，每一晝素鈐 構與對應的掃描配線與資料配線電性連接，每一晝^結才^ 包括薄膜電晶體與晝素電極。其中，晝素電極覆蓋於掃描The present invention further proposes a halogen matrix substrate, which comprises a substrate, a multi-stop wiring, a plurality of data wirings, and a plurality of halogen structures. Wherein, the substrate comprises a display area and a scanning wiring input end area. A plurality of scanning wirings and a plurality of wirings are disposed in the display area, wherein the scanning wiring extends into the scanning wiring input end region. A plurality of halogen structures are disposed in the display area, and each of the pixel structures is electrically connected to the corresponding scan wires and the data wires, and each of the wires includes a thin film transistor and a halogen electrode. Wherein, the halogen electrode is covered by the scan

辛電^=狀—實施财，上述之每—晝素結構中的書 素電極與知描配線之間夾有一閘絕緣層以及一保護層。- 明之—實施例中，上述之每—晝素結構;晝 素电極與掃描配線之間僅夾有一閘絕緣層。 配線上，以在晝素電極與掃描配線的重疊處產生一補償電 容。其中，在每一晝素結構的晝素電極與掃描配線的重疊 處有一第一垂直距離與小於第一垂直距離的一第二垂直距 離’且在這些晝素結構中的重疊處，第二垂直距離所在的 區域的面積是從掃描配線輸入端區往遠離掃描配線輸入端 區的方向逐漸増加，以使這些補償電容的大小自掃描配線 輸入端區往送離掃描配線輸入端區的方向逐漸增加。 在本發明之〜實施例中，上述之每一晝素結構中的第 二垂直距離為—變動垂直距離’這些變動垂直距離是從掃 描配線輸入端區往遠離掃描配線輸入端區的方向逐漸減 少〇 在本發明之一實施例中，在這些晝素結構中，這些晝 8 201003263 .26188twf.doc/d 素电極與其所對應的掃描配線的重疊面積皆相同。 在本發明之—實施例中，上述之每—晝素結構更包括 用配線’設置於晝素電極下方。 在本發明之—實施例中’上述之每—晝素結構中的晝 素電極與掃描配線之間夾有一閘絕緣層以及—保護層。 在本發明之一實施例中，上述之每一晝素結構Ϊ的晝 素電極與掃描配線之間僅夾有一閘絕緣層。 * +本發明再提出一種畫素陣列基板，包括一基板、多條 掃描配線、多條資料配線以及多個晝素結構。其中，基板 ^括顯示區以及掃描配線輸入端區。多條掃描配線與多條 二料^線配置於顯示區内，其中掃描配線延伸至掃描配線 輸入端區内。多個畫素結構配置於顯示區内，每—書素結 構與對應的掃描配線與資料配線電性連接，每一晝素結構 匕括✓專膜笔晶體、共用配線以及晝素電極。其中用配 線平行於掃描配線，晝素電極覆蓋於共用配線上，以在晝 素電極與共用配線的重疊處產生一儲存電容。其中，在每 一晝素結構的畫素電極與共用配線的重疊處有—變動垂直 距離’這些晝素結構中的這些變動垂直距離會從掃描配線 輸入端區往遠離掃描配線輸入端區的方向逐漸增加，以使 這些儲存電容的大小自掃描配線輸入端區往遠離掃描配線 輸入端區的方向逐漸減少。 在本發明之一實施例中’在上述晝素結構中，這些書 素電極與其所對應的共用配線的重疊面積皆相同。 在本發明之一實施例中，上述之每一晝素結構中的晝 26188twf.doc/d 201003263 素電極與共用配線之間夾有一閘絕緣層以及—保護声。 去带，，，明之—實闕巾，上述之每—畫素結構中的晝 ”電極/、掃描配線之間僅夾有一閘絕緣層。 本發明又提出-種畫素陣列基板^括—基板、多條 知描配線、㈣資料配線以及多個畫素結構。其中，某板 =顯示區以及掃描配線輸人端區。多條掃描配線^條 二枓配線配置於顯示區内’其中掃描配線延伸至掃描配線 輸入端區内。多個晝素結構配置於顯示區内，每—晝素結 構與對應的掃描配線與資料配線電性連接，每一晝素結構 包括薄膜電晶體、共用配線以及晝素電極。其中，共用配 線平行於掃描配線，晝素電極覆蓋於共用配線上，^在晝 素電極與共用配線的重疊處產生一儲存電容。其中，在每 一晝素結構的晝素電極與共用配線的重疊處有一第—垂直 =離與小於第一垂直距離的一第二垂直距離，在這些晝素 結構中的重疊處，第二垂直距離所在的區域的面積會從掃 ，配線輸入端區往遠離掃描配線輸入端區的方向逐漸滅 ^，以使這些儲存電容的大小自掃描配線輸入端區往遠離 掃描配線輸入端區的方向逐漸減少。 在本發明之一實施例中，上述之每一畫素結構中的第 二垂直距離為一變動垂直距離，這些變動垂直距離會從掃 描配線輸入端區往遠離掃描配線輸入端區的方向逐漸增 加。 在本發明之一實施例中，在這些畫素結構中，這些晝 素電極與其所對應的共用配線的重疊面積皆相同。 >· 26l88twf.doc/d 201003263 在本發明之一實施例中，上述之每一畫素結構中的全 常電極與共用配線之間夾有一閘絕緣層以及〜保護層。旦The symplectic electricity is in the form of a gate insulating layer and a protective layer between the substrate electrode and the known wiring in each of the above-described halogen structures. - In the embodiment, the above-described per-alkaline structure; only a gate insulating layer is sandwiched between the pixel electrode and the scanning wiring. On the wiring, a compensation capacitor is generated at the overlap of the pixel electrode and the scanning wiring. Wherein, at the overlap of the pixel electrode of each of the halogen structures and the scanning wiring, there is a first vertical distance and a second vertical distance smaller than the first vertical distance and an overlap in the pixel structures, the second vertical The area of the distance is gradually increased from the scanning wiring input end area to the direction away from the scanning wiring input end area, so that the size of these compensation capacitors gradually increases from the scanning wiring input end area to the scanning wiring input end area. . In the embodiment of the present invention, the second vertical distance in each of the above-described pixel structures is - the varying vertical distance. The varying vertical distance is gradually decreased from the scanning wiring input end region to the direction away from the scanning wiring input end region. In one embodiment of the present invention, in these halogen structures, the overlap areas of the 昼8 201003263 .26188 twf.doc/d electrodes and their corresponding scan lines are the same. In the embodiment of the present invention, each of the above-described halogen structure further includes a wiring ' disposed under the halogen electrode. In the embodiment of the present invention, a gate insulating layer and a protective layer are interposed between the germanium electrode and the scanning wiring in each of the above-described halogen structures. In an embodiment of the invention, only a gate insulating layer is interposed between the pixel electrode of each of the halogen structures and the scanning wiring. * + The present invention further provides a pixel array substrate comprising a substrate, a plurality of scanning wires, a plurality of data wires, and a plurality of pixel structures. Wherein, the substrate includes a display area and a scanning wiring input end area. A plurality of scanning wires and a plurality of wires are disposed in the display area, wherein the scanning wires extend into the input region of the scanning wires. A plurality of pixel structures are disposed in the display area, and each of the pixel structures is electrically connected to the corresponding scan wires and the data wires, and each of the pixel structures includes a film pen crystal, a common wiring, and a halogen electrode. Wherein the wiring is parallel to the scan wiring, and the halogen electrode is overlaid on the common wiring to generate a storage capacitor at the overlap of the pixel electrode and the common wiring. Wherein, at the overlap of the pixel electrode of each pixel structure and the common wiring, there is a variable vertical distance. These vertical distances in the pixel structure are from the scanning wiring input end region to the direction away from the scanning wiring input end region. Gradually increase so that the size of these storage capacitors gradually decreases from the scanning wiring input end region to the direction away from the scanning wiring input end region. In an embodiment of the present invention, in the above-described halogen structure, the overlapping areas of the pixel electrodes and the corresponding common wirings thereof are the same. In an embodiment of the present invention, a gate insulating layer and a protective sound are interposed between the 昼 26188 twf.doc/d 201003263 element electrode and the common wiring in each of the above-described pixel structures. To bring, and, to be, the sturdy towel, the 昼" electrode in the above-mentioned pixel structure, and the scanning wiring are only sandwiched with a gate insulating layer. The present invention further proposes a pixel array substrate. , a plurality of known wirings, (4) data wiring, and a plurality of pixel structures, wherein a certain board = display area and a scanning wiring input end area. A plurality of scanning wirings are arranged in the display area. Extending into the input area of the scanning wiring. A plurality of halogen structures are disposed in the display area, and each of the halogen structures is electrically connected to the corresponding scanning wiring and the data wiring, and each of the halogen structures includes a thin film transistor, a common wiring, and a halogen electrode, wherein the common wiring is parallel to the scan wiring, the halogen electrode covers the common wiring, and a storage capacitor is generated at an overlap of the halogen electrode and the common wiring. Among them, the halogen electrode in each halogen structure The overlap with the shared wiring has a first vertical = a second vertical distance from the first vertical distance, and an overlap in the pixel structure, the second vertical distance The accumulating direction is gradually removed from the scanning input end region away from the scanning wiring input end region, so that the size of the storage capacitors gradually decreases from the scanning wiring input end region to the direction away from the scanning wiring input end region. In one embodiment, the second vertical distance in each of the pixel structures is a varying vertical distance, and the varying vertical distance is gradually increased from the scanning wiring input end region to the direction away from the scanning wiring input end region. In one embodiment of the invention, in these pixel structures, the overlapping areas of the halogen electrodes and their corresponding common wirings are the same. >· 26l88twf.doc/d 201003263 In one embodiment of the present invention, the above A gate insulating layer and a protective layer are sandwiched between the full-normal electrode and the common wiring in each pixel structure.

去在本發明之一實施例中，上述之每一晝素結構^的查 素電極與掃描配線之間僅夾有一閘絕緣層。 AIn an embodiment of the present invention, only a gate insulating layer is interposed between the pixel electrode of each of the above-described pixel structures and the scanning wiring. A

+本發明之晝素陣列基板藉由改變每一個畫素結構中書 素電極與掃描配線間的垂直距離或改變晝素電極^共用= 線間的垂直距離，而調變位於其間的補償電容或儲^電^ t小’使同—條掃描配線上各個晝素結構具有相近二ς ^電壓，以提升畫素的顯示品f，進而避免液晶顯示器之 旦面發生閃爍的情形。 為讓本發明之上述和其他目的、特徵和優點能更明顯 懂，下文特舉較佳實施例，並配合所附圖式，作 明如下。 、…儿 【實施方式】 【弟—實施例】 圖2A繪示為根據本發明第一實施例之晝素陣列基板 的局部上視圖，而圖2B與圖2C分別繪示為圖2A中沿卩， 、本乂及II-II線之剖面圖。請參照圖2A，本實施例之晝素 陣列基板1GG包括—基板11Q、多條掃描配線112、多條資 $線m以及多個晝素結構p麵、Ρι_、p眶。其中， U〇包括顯示區110a、掃描配線輸入端區110b以及 貝，配線輸入端區110c。掃描配線112、資料配線114以 ^夕個晝素結構p_a、P_、P100C配置於顯示區ii〇a内。 旦素、'σ構Pl()()A、Pi〇〇B、Piooc與對應的掃描配線112與資料 11 201003263 26188twf.doc/d 配線114電性連接。其中 輸入端區110b内。+ The halogen array substrate of the present invention modulates the compensation capacitance therebetween or by changing the vertical distance between the pixel electrode and the scanning wiring in each pixel structure or changing the vertical distance between the pixel electrodes and the line The storage voltage is reduced by the voltage of each pixel structure on the same scanning strip to increase the display quality of the pixel, thereby avoiding the flickering of the surface of the liquid crystal display. The above and other objects, features and advantages of the present invention will become more apparent from [Embodiment] FIG. 2A is a partial top view of a pixel array substrate according to a first embodiment of the present invention, and FIG. 2B and FIG. 2C are respectively shown in FIG. , , and the section of the line II-II. Referring to FIG. 2A, the pixel array substrate 1GG of the present embodiment includes a substrate 11Q, a plurality of scanning lines 112, a plurality of lines m, and a plurality of pixel structures p-plane, Ρι_, p眶. The U 〇 includes a display area 110a, a scan line input end area 110b, and a bay, and a wiring input end area 110c. The scanning wiring 112 and the data wiring 114 are arranged in the display area ii 〇 a in the pixel structure p_a, P_, and P100C. The sigma, 'σ structure Pl()()A, Pi〇〇B, Piooc and the corresponding scan line 112 are electrically connected to the data line 11 201003263 26188 twf.doc/d. Wherein the input end zone 110b.

掃描配線112延伸至掃描配線 —請同時參照圖2A與圖％，圖2C以畫素結構I嫩中 的薄膜電晶體TFT_料制。每—晝素結構p_A、 Pioob、P1()〇c 包括薄膜電晶體 τρτ刚a、TFT1()()B、TFT1()()C 與 晝素電極 PE1()()a、pe1()()b、pe1()〇c。以薄膜電晶體 TFTi〇〇a 作為說明，薄膜電晶體TFT包括閘極120、通道層122以 及源極124與汲極126。其中，閘絕緣層128覆蓋閘極12〇, 保護層130覆蓋閘絕緣層128、通道層122以及源極124 與汲極126。晝素電極PE_a、PE⑽b、pE⑽c例如是配置 於保護層130上，藉由接觸窗132與汲極126電性連接。 於本實施例中，晝素電極PE驅、PE_、pE說覆蓋於掃 描配線112上方，兩者之間具有一重疊處(以斜線表示）。 再者，晝素結構P100A、P刚B、P則c還包括共用配線116， ’、〇又置於晝素笔極PEiqqa、PE励B、PE][⑽c下方。此外’於 本實施例中’閘絕緣層128覆蓋住薄膜電晶體TFT1()0A、 TFT100B、TFT100C、共用配線116與掃描配線112，保護層 13〇覆蓋住掃描配線112、資料配線114、共用配線116以 及閘絕緣層128。其中，掃描配線112、資料配線114、共 用配線116的材質例如是鉻、钽或其他金屬材料。晝素電 極PE刚A、PEIO〇B、PE10()C的材質例如是銦錫氧化物、銦辞 氧化物(Indium Zinc Oxide, IZO)、金屬或是其他導電材料。 請同時參照圖2A與2B，於本實施例中’晝素電極 ΡΕ1()()Α、ΡΕ·Β、PE!·:覆蓋於掃描配線112上，以在晝素 12 201003263 ..26188twf.doc/d 電極PE1()0A、pe1()()B、pEl()()C與掃描配線112的重疊處（以 斜線表示)產生一補償電容(cgd)a、（cgd)b、（CGD)C。其 中’晝素電極PE100A、I>E100B、PE100C與掃描配線112的重 疊處有-變動垂直距離D_、D麵、Di·，晝素結構 P_A、p雇B、P謂c中的變動垂直距離Di〇〇a、D_、 是從掃描配線輸人端區·往遠離該掃描配線輸入蠕區 ll〇b的方向逐漸減少，即D驅>D麵>Iw。已知電容 值的大小與上下電極間的介電層厚度成反比，因此，補償 電容(CGD)A、（CGD)B、（Cgd)c的大小與變動垂直距離 Di〇〇A、D10()B、D霞的大小成反比，故補償電容(Cgd)a、 (cgd)b、（cGD)c自掃描配線輸入端區11〇b往遠離該掃描 配線輸入端區ii〇b的方向逐漸增加，即(Cgd)a <( b < (Cgd)C。 請同時參照圖2A、2B以及圖2C，值得注意的是，在 本只％例中’以晝素結構ρι〇〇Α為例，畫素電極PE職例 =是藉由接觸窗m與汲極126電性連接，掃描配線m ^閘極120電性連接’因而畫素電極pE_A與掃描配線⑴ “所構成的補偵電谷CGD等同於没極126與閘極間之 ^容’也就是等陳絲式⑴中所定義的CGD。由於受掃 W號波形失真的影響，Vfd會自掃描配線輸人端區⑽ 在退離該掃描配線輸人端區11%的方向逐漸減少，因此， ，旦素結構 Ρΐ()()Α、Ρ_、Ρ_ 中（VFD) A >( VFD) B >( VFD) 而’於本實施例中，由於補償電容Cgd具有（ΜΑ GD B <(CGD)C的關係，根據方程式(1)，即可獲得饋 13 201003263 26188twf.doc/d )AKVfd)MVfd)c之結果，換句話說，利用調 酉正己中補償電容Cgd的大小，使得同一條掃描 的顯- 個晝素結構之鑌通電壓為相近，進而提升晝素 、、不叩貝’以避免液晶顯示器之晝面發生閃爍的問題。 值传提的疋，於本實施例中，畫素電極脆、 ^oob^ PE100C^#I,S,^ 112 Αι〇〇α . Αι〇〇β . 開处因此，各個晝素結構ρ·、P麵、Ρ·的 :目5 :月匕避免因晝素結構之開口率不同而影響液晶 •辛^之顯不效果的問題。再者，軸於本實施例中，晝 二弘極ΡΕ雇、ΡΕ100β、ρε刚c與掃描配線 =層m以及保護層130,但畫素電極與掃描二 也可以只有閘絕緣層。 【第二實施例】 圖3A緣示為根據本發明第二實施例之晝素陣列基板 =^視圖’而圖3B緣示為圖3A中沿14’線之剖面圖。 參照圖3A與圖3B，晝素陣列基板卿的結構愈圖 ^中的晝素陣列基板⑽相似，然而，在每—晝素結構 ιοο’Α、Pi〇0’B、pI〇〇，c 的書辛雷描 pp m 職 ElGG，B、PE_，c 田配線112的重疊處(以斜線表示)有—第 m着B、D1朦c與小於第一垂直距離的—第二^ 距離D2卿，A、D2勝B、D2·。其中，於上述重叠處中， 第—垂直距離D1綱，A、D1 _、D】就所在的 d:重疊面積aW、a1_、aw，第二垂直： _’a、D2刚，B、D2漏’c所在的區域具有第二重疊面積 14 26188twf.doc/(i 201003263 Λ2ι〇〇ά% A2i〇〇5b A2!〇o’b、M100，c，且第二重叠面積一 八2紙的大小是從掃插配線輸人端區11Gb往遠離掃描配 線輸入端區11%的方向逐漸增加，即A2⑽，a<A21()()，b< AAog’c。已知電容大小與上下電極間的重疊面積大小成正 =因此’補償電容⑽大小與 弟—面藉A 0 . ♦ C 10〇 A、A210()’b、A2i〇〇，c的大小成玉比，故補償 4主;(Cgd)B、（Cgd)C自掃描配線輸入端區ll〇b c : <描配線輪入端區110b的方向逐漸增加，也就是 么：)B <(CGD)C。 P_，B、^ t例中所述相似’由於晝素結構P觸，A、The scanning wiring 112 is extended to the scanning wiring - please refer to FIG. 2A and FIG. 2 at the same time, and FIG. 2C is made of the thin film transistor TFT_ in the pixel structure. Each of the halogen structure p_A, Pioob, P1()〇c includes a thin film transistor τρτ a, TFT1()()B, TFT1()()C and a halogen electrode PE1()()a, pe1()( ) b, pe1 () 〇 c. As a description of the thin film transistor TFTi〇〇a, the thin film transistor TFT includes a gate 120, a channel layer 122, and a source 124 and a drain 126. The gate insulating layer 128 covers the gate 12A, and the protective layer 130 covers the gate insulating layer 128, the channel layer 122, and the source 124 and the drain 126. The halogen electrodes PE_a, PE(10)b, and pE(10)c are disposed on the protective layer 130, for example, and are electrically connected to the drain 126 via the contact window 132. In the present embodiment, the halogen electrodes PE, PE_, and pE are covered over the scanning wiring 112 with an overlap (indicated by oblique lines) therebetween. Furthermore, the halogen structure P100A, P just B, and P then include the shared wiring 116, and the 〇 is placed under the enamel pen PEiqqa, PE excitation B, PE] [(10)c. Further, in the present embodiment, the gate insulating layer 128 covers the thin film transistor TFT1 (0A), the TFT 100B, the TFT 100C, the common wiring 116, and the scanning wiring 112, and the protective layer 13 covers the scanning wiring 112, the data wiring 114, and the shared wiring. 116 and a gate insulating layer 128. The material of the scanning wiring 112, the data wiring 114, and the common wiring 116 is, for example, chromium, tantalum or other metal material. The material of the halogen electrodes PE, A, PEIO, B, and PE10 (C) is, for example, indium tin oxide, Indium Zinc Oxide (IZO), metal, or other conductive material. Referring to FIG. 2A and FIG. 2B simultaneously, in the present embodiment, the 昼 ΡΕ ΡΕ ( ( ( ( ( PE PE PE PE PE PE PE PE PE PE 覆盖 覆盖 覆盖 覆盖 覆盖 覆盖 覆盖 覆盖 覆盖 覆盖 覆盖 覆盖 覆盖 扫描 扫描 扫描 扫描 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 /d electrode PE1()0A, pe1()B), pEl()()C and scan wiring 112 overlap (shown by oblique lines) to generate a compensation capacitor (cgd)a, (cgd)b, (CGD) C. Wherein the overlap between the elemental electrodes PE100A, I> E100B, PE100C and the scanning wiring 112 has a variable vertical distance D_, a D surface, a Di, a halogen structure P_A, a P, a P, and a variable vertical distance Di in the c. 〇〇a, D_, are gradually decreased from the scanning wiring input end region to the direction away from the scanning wiring input creep region 〇b, that is, D drive > D face > Iw. It is known that the magnitude of the capacitance is inversely proportional to the thickness of the dielectric layer between the upper and lower electrodes. Therefore, the magnitudes of the compensation capacitors (CGD) A, (CGD) B, and (Cgd) c and the varying vertical distances Di〇〇A, D10() B, D Xia is inversely proportional, so the compensation capacitors (Cgd)a, (cgd)b, (cGD)c gradually increase from the scanning wiring input end region 11〇b away from the scanning wiring input end region ii〇b. , that is, (Cgd)a <( b < (Cgd) C. Please refer to FIG. 2A, FIG. 2B and FIG. 2C at the same time, it is worth noting that in the present example only, the morphe structure ρι〇〇Α is taken as an example. , the pixel electrode PE example = is electrically connected to the drain 126 through the contact window m, the scan wiring m ^ gate 120 is electrically connected 'therefore the pixel electrode pE_A and the scan wiring (1) CGD is equivalent to the capacitance between the pole 126 and the gate. It is also the CGD defined in the filament type (1). Due to the distortion of the W waveform, the Vfd will retreat from the scanning wiring input end zone (10). The 11% direction of the input end region of the scanning wiring is gradually reduced. Therefore, the denier structure Ρΐ()()Α, Ρ_, Ρ_ (VFD) A > (VFD) B > (VFD) and real In the example, since the compensation capacitance Cgd has a relationship of (ΜΑ GD B < (CGD) C, according to the equation (1), the result of the feed 13 201003263 26188 twf.doc / d ) AKVfd ) MVfd) c can be obtained, in other words The size of the compensation capacitor Cgd in the 酉 酉 酉 , , , , , , 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 同一 补偿 补偿 补偿 补偿 补偿 补偿 补偿 补偿 补偿 补偿 补偿Problem. In the present embodiment, the pixel electrode is brittle, ^oob^PE100C^#I, S, ^ 112 Αι〇〇α . Αι〇〇β . Therefore, each pixel structure ρ ·, P-face, Ρ·: Mesh 5: The moon 匕 avoids the problem that the liquid crystal and the sensible effect are not affected by the difference in the aperture ratio of the halogen structure. Furthermore, in the present embodiment, the second axis is ΡΕ ΡΕ, ΡΕ 100β, ρ ε c and scan wiring = layer m and protective layer 130, but the pixel electrode and the scan two may also only have a gate insulating layer. [Second embodiment] FIG. 3A is shown as a second embodiment according to the present invention. For example, the pixel array substrate = ^ view ' and the edge of FIG. 3B is a cross-sectional view along line 14' in FIG. 3A. Referring to FIG. 3A As shown in Fig. 3B, the structure of the alizarin array substrate is similar to that of the alizarin array substrate (10), however, in each of the alizarin structures ιοο'Α, Pi〇0'B, pI〇〇, c Pp m job ElGG, B, PE_, c The overlap of the field wiring 112 (indicated by a slanted line) has - m, B, D1 朦 c and less than the first vertical distance - the second ^ distance D2 Qing, A, D2 Win B, D2·. Wherein, in the above overlap, the first-vertical distance D1, A, D1 _, D] is where d: overlap area aW, a1_, aw, second vertical: _'a, D2 just, B, D2 leak The area where 'c is located has a second overlap area of 14 26188 twf.doc/(i 201003263 Λ2ι〇〇ά% A2i〇〇5b A2!〇o'b, M100, c, and the second overlap area is 182 paper size is From the sweeping wiring input end region 11Gb to the direction away from the scanning wiring input end region by 11%, that is, A2 (10), a < A21 () (), b < AAog 'c. Knowing the size of the capacitor and the overlap between the upper and lower electrodes The size of the area is positive = so the size of the compensation capacitor (10) is the same as that of the younger one. ♦ C 10〇A, A210()'b, A2i〇〇, c are the size of the jade, so compensate 4 main; (Cgd)B (Cgd) C self-scanning wiring input end region ll 〇 bc : < The direction of the wiring wheel entering end region 110b is gradually increased, that is, B) (CGD) C. P_, B, ^ t are similar in the examples, due to the P structure of the alizarin structure, A,

、00，C内的各個補償電容CGD1有m <(C-)C 的關係，且(v D:有(C-)A <(Cgd)B 適當調整各個查 （FD )B >( Vfd ) C，因此在 i... 構、小後，各個晝素結 (v:^(vFD)B;e；^m得饋通電壓 晝素結構中補償電容Cgd的大小，、_調整各個 =個晝素結構之馈通電壓為相近，掃描配線上 ，a,b , pA2i-A2- :)，C的開。率相同，能避免因晝素、P100’B、 “夜晶顯示器之顯示效果-冓^開口率不同而影 冉者，雖然晝素電極 15 201003263.. 26188tw,doc/d PE100’a、PE100，b、PEjoo’c與掃描酉己線112之間夾有閘絕緣 層128以及保護層130，但在另一實施例中，晝素電極與 掃描配線間可以只有閘絕緣層。此外，在另一實施例中， 第二垂直距離為一變動垂直距離，此變動垂直距離是從掃 描配線輸入端區往遠離掃描配線輸入端區的方向逐漸減 少。 【第三實施例】 圖4A繪示為根據本發明第三實施例之晝素陣列基板 的局部上視圖，而圖4B繪示為圖4A中沿Ι-Γ線之剖面圖。 請參照圖4A’本實施例之晝素陣列基板200主要包括一基 板210、多條掃描配線212、多條資料配線214以及多個晝 素結構P2〇OA、P2〇〇B、P200C。其中，基板210包括顯示區 21〇a、掃描配線輸入端區21〇b以及資料配線輸入端區 210c。掃描配線212、資料配線214以及多個晝素結構 Ρ200Α、Ρ·β、P2〇〇c配置於顯示區210a内。每一晝素結構 P2〇oa、P2_、F»2,與對應的掃描配線212與資料配線214 電性連接。其中，掃描配線212延伸至掃描配線輸入端區 210b内。晝素結構ρ2〇〇Α、ρ·Β、p·。包括薄膜電晶體 TFT2〇OA、TFT2〇OB、TFT2〇0C、共用配線216以及晝素電極 pE2〇OA、四2_、pE2〇〇c。其中，共用配線216平行於掃描 配線212。薄膜電晶體TFT薦、TFT2_、TFT細c的結構 可以參照第一實施例，於此不再贅述。 請同時參照圖4A與圖4B，其中，晝素電極PE2qqa、 PE2〇ob、PE2·覆蓋於共用配線216上，且兩者之間例如是 16 26188twf.doc/d 夾有閘絕緣層228和保護層230，以在晝素電極pE2Q〇A、 PE2〇GB、PE2〇〇c與共用配線216的重疊處(以斜線表示)產生 儲存電谷(Cst)A、（CST)B 、（CST)C。其中，晝素電極 PE:·、PE2_、PE2〇oc與共用配線216的重疊處有一變動 垂直距離 D2〇〇A、D2_、d2()()C，晝素結構 p2〇〇a、p2()〇B、p2〇〇c 中的變動垂直距離、D2〇〇B、D2GGC是從掃描配線輸入 端區210b往遠離該掃描配線輸入端區21%的方向逐漸增 加，即D^oaSD2⑽B<D2〇〇c。已知電容值的大小與上下電 極間的介電層厚度成反比，因此，儲存電容(Cst)a 、 (CST)B、（CST)C的大小與變動垂直距離〕觀、d2_、D2〇〇c =大小成反比，故儲存電容(Cst)a、（Cst)b、（Cst)c自 掃描配線輸入端區210b往遠離該掃描配線輸入端區21〇b 的方向逐漸減少，即(CST)A >(CST)B >(CsT)c。 承上所述’根據方程式⑴，由於晝素結構卩赢彳麵、 p2〇〇c内的各個儲存電容Cst具有(Cst)a >(Cst)b >(Cst)c 的關係’且(VFD) A >( Vfd) B >( Vfd) c，目此在適當調整 各個晝素之儲存t容Cst社小後，各個錄結構ρ·、 、hooc即可獲得饋通電壓(Vfd)AKVfd)b^Vfd)c之結 果。換句^說’利用調整各個晝素之晝素儲存電容Cst的 大】使得同條掃描配線上的各個畫素結構之馈通電壓 ，相近’進而提升晝素的顯示品質，以避免液晶顯示器之 畫面發生閃爍的問題。 值仔-提的是，於本實施例中，晝素電極ρΕ2·、 Ε纖、PE蒙與共用配線216的重疊面積Α裏、&麵、 17 201003263 26188twf.doc/d A200C皆相同’因此，各個晝素結構P2〇〇a、P200B、p2〇〇c的 開口率相同，能避免因晝素結構之開口率不同而影響液晶 顯示器之顯示效果的問題。再者’雖然晝素電極pe2()()A、 PE2贿、pe200C與共用配線216之間夾有閘絕緣層228以及 保護層230，但在另一實施例中，晝素電極與共用配線間 可以只有閘絕緣層。 【第四實施例】 圖5A繪示為根據本發明第四實施例之畫素陣列基板 的局部上視圖，而圖5B繪示為圖5A中沿Ι-Γ線之剖面圖。 請同時參照圖5A與圖5B，晝素陣列基板200,的結構與圖 4八中的晝素陣列基板2〇〇相似，然而，在每一晝素結構 200’A、P2〇〇，B、P200，c 的晝素電極 ΡΕ2〇〇，α、PE200，B、PE200，C 與共用配線216的重疊處（以斜線表示）有一第一垂直距離 Dhoo’A、Dl2(KrB、〇i20()，c與小於第—垂直距離的一第二垂 ^距離D2200，A、D220〇，B、d22〇〇，c。值得注意的是’於本實 ^例中，第二垂直距離D22〇〇，A、D22()(),B、D22〇o，c為一變動 距離，此變動垂直距離會從掃描配線輸入端區21〇b ^ ^離掃描配線輸入端區2l〇b的方向逐漸增加，即d22〇〇’a ^^〇〇’b<D2200’c。其中，於上述重疊處中，第一垂直距 Α1 2〇〇’Α、m200’B、Dl2〇o，c所在的區域具有第一重疊面積 0〇A Al200’B、Al2〇〇，c’ 第二垂直距離 d22〇〇，a、d22〇〇’b、 A: 0〇c所在的區域具有第二重疊面積a2_，a、A2雙’B、 是：二且第二重疊面積Α22〇〇，Α、A2—、A22°°，C的大小 知描配線輸入端區鳩往遠離掃描配線輸入端區 18 201003263 26188twf.doc/d 201003263 26188twf.doc/dEach compensation capacitor CGD1 in 00, C has a relationship of m < (C-) C, and (v D: has (C-) A < (Cgd) B appropriately adjust each check (FD) B > Vfd ) C, therefore, after i... structure, small, each elementary junction (v:^(vFD)B;e;^m has the size of the compensation capacitor Cgd in the feedthrough voltage structure, _ adjust each = The feedthrough voltage of a single crystal structure is similar, on the scan wiring, a, b, pA2i-A2- :), C open. The rate is the same, can avoid the display of the crystal, P100'B, "Night crystal display" Effect - 冓 ^ different opening ratio, although the halogen electrode 15 201003263.. 26188tw, doc / d PE100'a, PE100, b, PEjoo'c and scanning 酉 line 112 between the gate insulation layer 128 And the protective layer 130, but in another embodiment, there may be only a gate insulating layer between the halogen electrode and the scan wiring. Further, in another embodiment, the second vertical distance is a varying vertical distance, and the varying vertical distance is The direction from the scanning wiring input end region to the direction away from the scanning wiring input end region is gradually reduced. [Third Embodiment] FIG. 4A illustrates a pixel array substrate according to a third embodiment of the present invention. 4A is a cross-sectional view along the Ι-Γ line in FIG. 4A. Referring to FIG. 4A, the pixel array substrate 200 of the present embodiment mainly includes a substrate 210, a plurality of scanning lines 212, and a plurality of strips. The data wiring 214 and the plurality of halogen structures P2 〇 OA, P2 〇〇 B, and P200C, wherein the substrate 210 includes a display area 21 〇 a, a scanning wiring input end area 21 〇 b, and a data wiring input end area 210 c. The scanning wiring 212 The data wiring 214 and the plurality of halogen structures Α200Α, Ρ·β, and P2〇〇c are disposed in the display area 210a. Each of the pixel structures P2〇oa, P2_, F»2, and the corresponding scan wiring 212 and data The wiring 214 is electrically connected, wherein the scanning wiring 212 extends into the scanning wiring input end region 210b. The halogen structure ρ2 〇〇Α, ρ·Β, p· includes thin film transistors TFT2〇OA, TFT2〇OB, TFT2〇 0C, the common wiring 216, and the halogen electrodes pE2 〇 OA, four 2_, pE2 〇〇 c. The common wiring 216 is parallel to the scanning wiring 212. The structure of the thin film transistor TFT, the TFT2_, and the TFT thin c can be referred to the first implementation. For example, it will not be described here. Please refer to FIG. 4A and FIG. 4B simultaneously. The halogen electrodes PE2qqa, PE2〇ob, PE2· are overlaid on the common wiring 216, and between them, for example, 16 26188 twf.doc/d is sandwiched with a gate insulating layer 228 and a protective layer 230 to be used in the pixel electrode pE2Q〇. A, PE2 〇 GB, PE2 〇〇 c and the shared wiring 216 overlap (shown by oblique lines) to generate storage valleys (Cst) A, (CST) B, (CST) C. Wherein, the overlap of the halogen electrodes PE:·, PE2_, PE2〇oc and the common wiring 216 has a vertical distance D2〇〇A, D2_, d2()()C, a halogen structure p2〇〇a, p2() The varying vertical distances in 〇B, p2〇〇c, D2〇〇B, D2GGC are gradually increased from the scanning wiring input end region 210b to the direction away from the input wiring area of the scanning wiring, that is, D^oaSD2(10)B<D2〇〇 c. It is known that the magnitude of the capacitance is inversely proportional to the thickness of the dielectric layer between the upper and lower electrodes. Therefore, the magnitudes of the storage capacitors (Cst)a, (CST)B, and (CST)C and the vertical distance of variation are observed, d2_, D2〇〇 c = the size is inversely proportional, so the storage capacitors (Cst) a, (Cst) b, (Cst) c gradually decrease from the scanning wiring input end region 210b away from the scanning wiring input end region 21 〇 b, that is, (CST) A > (CST) B > (CsT) c. According to the equation (1), since the pixel structure wins, the respective storage capacitors Cst in p2〇〇c have the relationship of (Cst)a >(Cst)b >(Cst)c' and VFD) A >( Vfd) B >( Vfd) c, after the appropriate adjustment of the storage capacity of each element, Cst, the recording structure ρ·, , hooc can obtain the feedthrough voltage (Vfd) The result of AKVfd)b^Vfd)c. In other words, the phrase "Using the adjustment of the individual storage capacitors Cst of the various elements" makes the feedthrough voltage of each pixel structure on the same scanning wiring similar, thereby improving the display quality of the pixel to avoid the liquid crystal display. The screen flickers. In the present embodiment, the overlapping area of the halogen electrode ρΕ2·, the Ε fiber, the PE 蒙 and the common wiring 216, the & face, 17 201003263 26188 twf.doc/d A200C are the same. The aperture ratios of the respective halogen structures P2〇〇a, P200B, and p2〇〇c are the same, and the problem of affecting the display effect of the liquid crystal display due to the difference in aperture ratio of the halogen structure can be avoided. Further, although the halogen electrode pe2()()A, PE2 bribe, the pe200C and the common wiring 216 have the gate insulating layer 228 and the protective layer 230 interposed therebetween, in another embodiment, the halogen electrode and the shared wiring compartment It is possible to have only the gate insulation. [Fourth Embodiment] Fig. 5A is a partial top view of a pixel array substrate according to a fourth embodiment of the present invention, and Fig. 5B is a cross-sectional view taken along line Ι-Γ in Fig. 5A. 5A and FIG. 5B, the structure of the halogen array substrate 200 is similar to that of the halogen array substrate 2 in FIG. The overlap of the pixel electrodes ΡΕ2〇〇, α, PE200, B, PE200, C of P200, c with the common wiring 216 (indicated by oblique lines) has a first vertical distance Dhoo'A, Dl2 (KrB, 〇i20(), c is a second perpendicular distance D2200, A, D220〇, B, d22〇〇, c which is smaller than the first vertical distance. It is worth noting that in the present example, the second vertical distance D22〇〇, A , D22()(), B, D22〇o, c is a variation distance, and the vertical distance of the variation gradually increases from the scanning wiring input end region 21〇b ^ ^ from the scanning wiring input end region 2l〇b, that is, D22〇〇'a ^^〇〇'b<D2200'c. wherein, in the above overlap, the first vertical distance Α1 2〇〇'Α, m200'B, Dl2〇o, c is in the region having the first The overlapping area is 0〇A Al200'B, Al2〇〇, c', the second vertical distance d22〇〇, a, d22〇〇'b, A: 0〇c is located in the region with the second overlapping area a2_, a, A2 double B, is: two and the second overlapping area Α22〇〇, Α, A2—, A22°°, the size of C is known to draw the input end region away from the scanning wiring input end area 18 201003263 26188twf.doc/d 201003263 26188twf. Doc/d

210b的方向逐漸減少，也就是Α22·>Α22_>Α22·。 已知電容大小與上下電極間的重疊面積大小成正比，因 此，儲存電容(CST)A、（cST)B 、（CST)C的大小與第二面 積Α2200，α、A2勘，B、A2着c以及第二垂直距離D22〇〇，A、 D22QQ，B、D22G()，C的大小成正比，故儲存電容（CsT)A 、 (CST)B、（cST)c自掃描配線輸入端區21〇b往遠離該掃描 配線輸入端區210b的方向逐漸減少，即(cST)A >(CST)B > (Cst)C 〇 與第三實施例中所述相似，由於晝素結構ρ·，Α、 P2〇〇’B、P2〇〇’c内的各個儲存電容CsT具有(CsT)A >(CsT)B > fWC的關係，且(VFD) A>( Vro)B >( VFD) c，因此在適當 ^正各個晝素之儲存電容的大小後，各個晝素結構 00 A 、P200，C即可獲得饋通電壓 金=)A (VFD)B气VFD)C之結果。換句話說，利用調整各個 儲存電容^的大小，使得同—條掃描配線上的各The direction of 210b is gradually reduced, that is, Α22·>Α22_>Α22·. It is known that the size of the capacitor is proportional to the size of the overlap between the upper and lower electrodes. Therefore, the size of the storage capacitors (CST) A, (cST)B, and (CST)C and the second area Α2200, α, A2, B, A2 c and the second vertical distance D22 〇〇, A, D22QQ, B, D22G (), C is proportional to the size, so the storage capacitors (CsT) A, (CST) B, (cST)c from the scan wiring input end region 21 〇b gradually decreases away from the scanning wiring input end region 210b, that is, (cST)A >(CST)B > (Cst)C 相似 is similar to that described in the third embodiment due to the pixel structure ρ· Each storage capacitor CsT in Α, P2〇〇'B, P2〇〇'c has a relationship of (CsT)A >(CsT)B > fWC, and (VFD) A>( Vro)B >( VFD) c, so after the appropriate storage capacitor size of each element, each pixel structure 00 A , P200, C can obtain the result of the feedthrough voltage gold =) A (VFD) B gas VFD) C. In other words, by adjusting the size of each storage capacitor ^, the same on the same scanning wiring

所 f構之饋通電壓為相同，進而提升晝素的顯示品 貝’以解決液晶顯示器之晝面閃爍的問題。 p值侍―提的是，於本實施例中，晝素電極pe2(K)，a、 2〇〇b PE2〇〇，c與共用配線216的第一重疊面積、 产ri:bAW與第二面積A22Q°’A、A22_、A2謂，c的面 白=i=，=此，各個晝素結構ρ_，α、ρ·，Β、 曰 如同，忐避免因晝素結構之開口率不同而影響液 不器之顯示效果的問題。再者，雖然晝素電極pe200，a、 0 B P^o’c與共用配線216之間夾有閘絕緣層228以 19 201003263 26188twf.doc/d 及保護層230’但在另一 , 間可以只有閘絕緣層。此外·晝$極與共用配線 的第二垂直距離一=可” 存電容的大小與第二面積的大=正^_ ’此時，儲 ^所述，本發簡由難每—個 極與掃描配線間的垂直距離與重叠面積，或是=:素電 共用配線間的垂直距離與重疊面積，以料蚩:垂-極與 描配線間的補償電容或畫素電盘與掃 電容的大小，使得同一條掃描配線 壓相近，以避免液晶顯示器之晝面發生閃燦問題。再 即使在各個晝素結構之晝素電極與掃描配線間或 ^ 與共用配線間的重疊面積相同的情況下，仍可藉由改ί上 述垂直距離或部份重疊面積來使各晝素的饋通電壓相同， 因而能使各個晝素結構的開口率一致，能避免因晝素結 之開口率不同而影響液晶顯示ϋ之顯示效果的問題。°此 =，本發明之晝素陣列基板的製造方法與現有在製程相 各’舉例來說’在晝素陣列基板的製程中使用半透光光罩， 即可形成上述變動於各個晝素結構中的變動垂直距離，故 不會造成生產成本的大幅增加。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 20 ..26188twf.doc/d 201003263 【圖式簡單說明】 圖U會示為習知-種晝素陣列基板的電路 圖2八！會示為根據本發明第—實施例之 ^ 的局部上視圖。 |素陣列基板 圖2B繪示為圖2A中沿14，線之剖面圖。 圖2C繪示為圖2A中沿Π_Π，線之剖面圖。The feedthrough voltage of the f-structure is the same, thereby improving the display product of the halogen to solve the problem of flickering of the liquid crystal display. In the present embodiment, the first overlapping area of the halogen electrodes pe2(K), a, 2〇〇b PE2〇〇, c and the common wiring 216, the yield ri: bAW and the second The area A22Q°'A, A22_, A2 is said, the white surface of c = i =, = this, the individual morpheme structures ρ_, α, ρ·, Β, 曰 are like, 忐 avoid affecting the liquid due to the difference in the aperture ratio of the halogen structure The problem of the display effect of the device. Furthermore, although the halogen electrode pe200, a, 0 BP^o'c and the common wiring 216 are sandwiched between the gate insulating layer 228 to 19 201003263 26188 twf.doc/d and the protective layer 230' but in another, only Brake insulation layer. In addition, the second vertical distance of the 极$ pole and the shared wiring is one = the size of the storage capacitor and the second area are larger = positive ^ _ ' At this time, the storage is simple, and the Scan the vertical distance and overlap area of the wiring, or = the vertical distance and overlap area of the common wiring between the wires: 蚩: the compensation capacitance between the vertical-pole and the traced wiring or the size of the micro-disk and the scan capacitor The pressure of the same scanning wiring is close to avoid the problem of flashing on the surface of the liquid crystal display. Even in the case where the overlapping area between the pixel electrode and the scanning wiring of each pixel structure or the common wiring is the same, The feedthrough voltage of each element can be made the same by changing the vertical distance or the partial overlap area, so that the aperture ratio of each elemental structure can be made uniform, and the liquid crystal can be prevented from being affected by the difference in aperture ratio of the elementary layer. The problem of the display effect of the crucible is displayed. This =, the manufacturing method of the alizarin array substrate of the present invention is different from the conventional process in the process, for example, by using a semi-transmissive mask in the process of the pixel array substrate, Forming the above changes The vertical distance of the variation in the structure of the individual elements does not cause a substantial increase in the production cost. Although the invention has been disclosed in the preferred embodiments as above, it is not intended to limit the invention, and anyone skilled in the art is not The scope of protection of the present invention is defined by the scope of the appended claims. 20..26188twf.doc/d 201003263 [Pictures] BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5 is a circuit diagram of a conventional-species halogen array substrate. FIG. 8 is a partial top view of the first embodiment of the present invention. FIG. 2B is a diagram of FIG. 2A. A cross-sectional view along line 14. Figure 2C is a cross-sectional view taken along line Π_Π in Figure 2A.

圖3Α繪示為根據本發明第二實施例 的局部上視圖。 -常陣列基板 圖3Β繪示為圖3Α中沿1-1，線之剖面圖。 圖4Α繪示為根據本發明第三實施例之晝素陣列基板 的局部上視圖。 土 圖4Β繪示為圖4Α中沿1-1，線之剖面圖。 圖5Α繪示為根據本發明第四實施例之晝素陣列基板 的局部上視圖。 土 圖5Β繪示為圖5Α中沿Ι-Γ線之剖面圖。 【主要元件符號說明】 10、100、100’、200、200’ ：晝素陣列基板 120 :閘極 126 :汲極 132 :接觸窗 110、210 :基板 110a、210a :顯示區 110b、210b :掃描配線輸入端區 110c、210c :資料配線輸入端區 21 .26188twf.doc/d 112、212、S10 :掃描配線 114、214、DIO :資料配線 116、216 :共用配線 122 :通道層 124 :源極 128、228 :閘絕緣層 130、230 :保護層Figure 3A is a partial top view of a second embodiment of the present invention. -Normal Array Substrate Figure 3A is a cross-sectional view taken along line 1-1 of Figure 3A. Figure 4 is a partial top plan view of a halogen array substrate in accordance with a third embodiment of the present invention. Figure 4Β is a cross-sectional view taken along line 1-1 of Figure 4Α. Figure 5A is a partial top plan view of a halogen array substrate in accordance with a fourth embodiment of the present invention. Figure 5Β is a cross-sectional view along the Ι-Γ line in Figure 5Α. [Description of main component symbols] 10, 100, 100', 200, 200': halogen array substrate 120: gate 126: drain 132: contact windows 110, 210: substrates 110a, 210a: display regions 110b, 210b: scan Wiring input end region 110c, 210c: data wiring input end region 21 .26188twf.doc/d 112, 212, S10: scan wiring 114, 214, DIO: data wiring 116, 216: common wiring 122: channel layer 124: source 128, 228: gate insulating layer 130, 230: protective layer

Aiooa、A1()0B、A10〇c、A200A、A200B、A200C : 重疊面積 AIioo’a、A1100’B、Al100，c、Al2〇〇’A、Al2〇〇，B、Al2〇〇，c : 第一重疊面積 A2100’a、A2100’B、A2100’c、A22〇〇’a、A22〇〇，b、A22〇〇’c : 第二重疊面積Aiooa, A1()0B, A10〇c, A200A, A200B, A200C : overlapping area AIioo'a, A1100'B, Al100, c, Al2〇〇'A, Al2〇〇, B, Al2〇〇, c: An overlapping area A2100'a, A2100'B, A2100'c, A22〇〇'a, A22〇〇, b, A22〇〇'c: second overlapping area

Cgd ·溥膜電晶體之閘極與〉及極間之電容 (CGD)A、（CGD)B、（CGD)C:補償電容 C]X .液晶電容Cgd · The gate of the germanium transistor and the capacitance between the pole and the pole (CGD) A, (CGD) B, (CGD) C: compensation capacitor C] X .

Cst、（Cst)A、（Cst)B、（Cst)C :儲存電容Cst, (Cst) A, (Cst) B, (Cst) C: storage capacitor

Diooa、Dioob、Diooc、D200A、D2〇〇b、D200C :變動垂直 距離Diooa, Dioob, Diooc, D200A, D2〇〇b, D200C: Change vertical distance

Dlioo’A、Dlioo’B、Dlioo’c、Dl2〇〇，A、Dl2〇〇’B、Dl2〇〇’C : 第一垂直距離 D21()〇，A、D21G〇，B、D〗·。、D22〇(rA、D22〇g’b、D22〇〇’c : 第二垂直距離Dlioo'A, Dlioo'B, Dlioo'c, Dl2〇〇, A, Dl2〇〇'B, Dl2〇〇'C: first vertical distance D21()〇, A, D21G〇, B, D〗. , D22〇(rA, D22〇g’b, D22〇〇’c : second vertical distance

PlOA、PlOB、PlOC、PlOOA、PlOOB、PlOOC、Pl00，A、PlOO’B、 PlOO’C、P200A、P200B、P2OOC、P200，A、P200’B、P200’C :晝素結 22 26188twf.doc/d 構 PEiooa ' PEioob ' PEiooc ' ΡΕ100Ά ' ΡΕιοοέ ' PElOO'C ' PE200A、PE200B、PE200C、 PE200，A、ΡΕ200Έ、PE200’C :晝素電 極 TFT·、TFT1GB、TFT1()C、TFT1G()A、TFTiGOB、TFT綱c、 ITTiqo’a、TFTh)〇，b、TFT1()()，C、TFT2G0A、TFT200B、TFT200C、 TFT2QQ’A、TFT2〇Q，B、TFT2〇〇，c :薄膜電晶體 23PlOA, PlOB, PlOC, P100A, P100B, P100C, P100, A, P100, B, P100, C, P200A, P200B, P2OOC, P200, A, P200'B, P200'C: 昼素结22 26188twf.doc/ d PEIOoa 'PEioob 'PEiooc ' ΡΕ100Ά ' ΡΕιοοέ ' PElOO'C 'PE200A, PE200B, PE200C, PE200, A, ΡΕ200Έ, PE200'C: Alizarin electrode TFT·, TFT1GB, TFT1()C, TFT1G()A, TFTiGOB, TFT class c, ITTiqo'a, TFTh)〇, b, TFT1()(), C, TFT2G0A, TFT200B, TFT200C, TFT2QQ'A, TFT2〇Q, B, TFT2〇〇, c: thin film transistor 23

Claims (1)

201003263 26188twf.doc/d 十、申請專利範圍： L一種晝素陣列基板，包括： 一基板’包括一顯示區以及一掃描配線輸入端區； 多條掃描配線與多條資料配線，配置於該顯示區内， 其中該些掃描配線延伸至該掃描配線輸入端區内；以及 多個晝素結構，配置於該顯示區内，每一晝素結構與 對應的該掃描配線與該資料配線電性連接，每一晝素結構 包括一薄膜電晶體與一晝素電極’ 其中，该晝素電極覆蓋於該掃描配線上，以在該畫素 電極與該掃描配線的重疊處產生一補償電容， 田其中，在每一晝素結構的該晝素電極與該掃描配線的 重宜處，、交動垂直距離，該些畫素結構中的該些變動垂 直距離疋從A掃描配線輸人端區往遠離該掃描配線輸入端 =方t逐漸減少，以使該些補償電容的大小自該掃描配 主遠_掃描配線輸人端區的方向逐漸增加。 1./ 在該些晝素晝素陣列基板’其中 的重疊面積皆相同。旦素祕與其所對應的掃描配線 每一 1項所逑之晝素陣列基板，其中 ΐ舰線，設砂缝錢極下方。 每-晝素結二:丄f:述之畫素陣列基板，其中 絕緣層以及-保護層“掃描配線之間夾有一間 5.如申請專鄉圍第1項所述之畫素陣舰板，其中 24 26l88twf.doc/d 201003263 結構中的該畫素電極與1•插配線之間僅夾有- 6·一種晝素陣列基板，包括： 包ΐ—顯示區以及—掃描配線輸入端區； 其置1顯示區内， 多個晝素結構，配置配，入端區：’·以及 掃描配線與該資料;接母 包括一薄膜電晶體與—晝素電極，薄 +炼_^;^4該旦素^*極覆盖於該掃描配線上，以在該書素 电極與物描配_重疊處產生—補償電容， - 重4: ’i每:ΐ素結構的該晝素電極與該掃摇配線的 二f些晝素結構中的該重疊處’該第二ίί 掃描配線輸人端區的方向逐漸增加，錢該 ^的亥 :::=配線輸入端區往遠離該掃描配線心 每一7畫如素=圍第第:;=畫=列基板’其中 些變動垂歧較m師描配線輸人额 線輸入端區的方向逐漸減少。 ㈣场私配 8·如申請專利範圍第6項所述之晝素陣列 些晝素結構中，該些晝素電極與其所對應的掃描配線的= 25 20 1 003263 26188twfdcK；/d 豐面積皆相同。 =如申請專利範圍第6項所述之 每-晝素結構更包括—共肢線，設置於織素電極下方中 一·如申睛專利範圍第6項所述之畫素陣列基板，其 问母一旦素結構巾的該晝素電極與該掃描配線之間夾有-閘絕緣層以及一保護層。 π ^如申請專利範圍第6項所述之晝僻列基板，其 1旦素!口構中的该晝素電極與該掃描配線之間僅爽有 一閘絕緣層。 12·—種晝素陣列基板，包括： 夕基板包括一顯示區以及一掃描配線輸入端區； 夕條,_财條㈣輯，配置於纖示區内， /、，些掃描配線延伸至該掃描配線輸入端區内；以及 夕個晝素結構，配置於該顯示區内，每一晝素結構與 〜Μ的，掃描配線與該資料配線電性連接，每一畫素結構 匕括專膜電晶體、一共用配線以及一晝素電極， ^中，該共用配線平行於該些掃描配線， 带其中，該晝素電極覆蓋於該共用配線上，以在該晝素 甩1該共用配線的重疊處產生-儲存電容， 中，在每一晝素結構的該晝素電極與該共用配線的 直二，有—變動垂直距離，該些晝素結構中的該些變動垂 區=離會從該掃描配線輪入端區往遠離該掃描配線輸入端 二轸方漸增加，以使該些儲存電容的大小自該掃描配 1入端區往遠離該掃描配線輸入端區的方向逐漸減少。 26 201003263 26l88twf.d〇c/d 請專利範圍第12項所述之晝素陣列基板， 配峻的ί:晝素結構中，該些晝素電極與其所對應的共用 配線的重g面積皆相同。 盆=請專利範圍第12項所述之晝素陣列基板， ^ 構中的該晝素電極與該共用配線之間炎有 一閘'%緣層以及一保護層。 立中t項所述之畫素陣列基板’ 絕二罐素電極與該掃描配線之間僅爽 16.—種晝素陣列基板，包括： ，一顯示區以及一掃描配線輸入端區； 立二ίΓ?與多條資料配線，配置於該顯示區内， 延伸至該掃描配線輸入端區内；以及 夕個晝素結構，配置於該顯示區内，每— 對應的，掃描配線與該資料配線電性連接，每—畫二士構 包括-薄膜電晶體、-共用配線以及_書素電 ° 其中，該共用配線平行於該些掃描二線包 其中，該晝素電極覆蓋於該共用配線上， 電極與該共用配線的重疊處產生一儲存電容，V旦常 ί每|素、1構的該晝素電極與該共用配線的 重疊處有-第-垂直距離與小於垂直距 ^一 垂直距離，在該些晝素結構中的該重疊處，該第二垂^ 離所在的£域的面積會賴掃描配線輪人藝 描配線輸人端區的方向逐漸減少，以使該·存電 27 201003263 ^i88twf.doc/d 小自該掃描配線輸人端區往遠_掃描配線輸人端區的方 向逐漸減少。 17.如申請專利範圍第16項所述之晝素陣列基板， 其中每-晝素結構中的該第二垂直距離為—變動垂直距 離，該些變誠直雜會從該掃描配雜人端區往遠離該 掃描配線輸入端區的方向逐漸增加。 項所述之晝素陣列基板， 極與其所對應的共用配線 18.如申請專利範圍第16 在該些晝素结構中’該些晝素電 的重疊面積皆相同。 19. 复，16項所述之晝素陣列基板， = 晝素電極與該共用配線之間夾有 一閘絕緣層以及一保護層。 人句 20.如申請專利範圍第16項㈣q 冓中的__掃描配線傳夾201003263 26188twf.doc/d X. Patent application scope: L A halogen matrix substrate comprises: a substrate 'including a display area and a scan wiring input end area; a plurality of scanning lines and a plurality of data lines arranged on the display In the area, the scan lines extend into the input area of the scan line; and a plurality of pixel structures are disposed in the display area, and each of the pixel structures and the corresponding scan line are electrically connected to the data line Each of the halogen structures includes a thin film transistor and a halogen electrode. The halogen electrode covers the scan line to generate a compensation capacitor at an overlap of the pixel electrode and the scan line. a vertical distance between the pixel electrode of each pixel structure and the scanning wiring, and the vertical distance of the variation in the pixel structure is away from the input end region of the A-scan wiring The scanning wiring input end=square t is gradually decreased, so that the magnitudes of the compensation capacitors gradually increase from the direction of the scanning distribution main-transmission wiring input end region. 1./ The overlap area is the same in each of the halogen substrate arrays. Each of the 扫描 阵列 秘 与其 与其 与其 与其 与其 与其 与其 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描Each 昼 结 丄 丄 丄 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : , in the 24 26l88twf.doc/d 201003263 structure, the pixel electrode and the 1/plug wire are only sandwiched between - 6 · a halogen array substrate, comprising: a package-display area and a scan wiring input end region; It is set in the display area, a plurality of halogen structures, configuration, and input areas: '· and scan wiring and the data; the mother includes a thin film transistor and a halogen electrode, thin + refining _ ^; ^ 4 The dummy layer is overlaid on the scan line to generate a compensation capacitor at the overlap of the pixel electrode and the object trace, - weight 4: 'i per: the pixel element of the halogen element and the Sweeping the overlap of the wiring structure of the second ' ' ' 该 该 该 该 该 该 该 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' : : : : : : : Each 7 paintings such as prime = circumference first:; = painting = column substrate 'these changes are more than the division of the input line of the input line The direction is gradually reduced. (4) Field private allocation 8. In the halogen structure of the halogen array described in item 6 of the patent application scope, the halogen electrodes and their corresponding scanning wirings are = 25 20 1 003263 26188 twfdcK; The abundance area is the same. = Each of the alizarin structures described in item 6 of the patent application scope includes a common limb line, which is disposed under the phonic electrode. The pixel described in item 6 of the scope of the patent application patent. The array substrate has a gate insulating layer and a protective layer interposed between the pixel electrode of the plain structure towel and the scanning wiring. π ^ The singular substrate according to claim 6 of the patent application, 1 素 ! 口 口 口 口 口 口 口 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12夕条, _ _ (4) series, arranged in the display area, /, some of the scan wiring extends into the input area of the scan line; and a 昼 昼 structure, arranged in the display area, each element Structure with ~Μ, scan wiring and the data wiring Electrically connected, each pixel structure includes a special film transistor, a common wiring, and a halogen electrode, wherein the common wiring is parallel to the scan lines, wherein the pixel electrode covers the common wiring And generating a storage capacitor at the overlap of the common wiring of the pixel ,1, wherein the 昼-electrode of each of the pixel structures and the straight line of the common wiring have a varying vertical distance, the 昼The varying vertical regions in the prime structure are gradually increased from the scanning wiring wheel inlet end region to the second scanning distance from the scanning wiring input end, so that the size of the storage capacitors is from the scanning matching 1 input end region. The direction away from the input end region of the scanning wiring is gradually reduced. 26 201003263 26l88twf.d〇c/d Please select the halogen array substrate according to item 12 of the patent scope, and the weight of the shared wiring of the halogen element is the same as the weight of the common wiring. . Basin = please refer to the halogen array substrate described in item 12 of the patent scope, where there is a gate '% edge layer and a protective layer between the halogen electrode and the common wiring. The pixel array substrate described in the middle item t is a cool pixel array substrate between the cathode electrode and the scanning wiring, and includes: a display area and a scanning wiring input end region; Γ 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与Electrically connected, each of the two-piece structure includes a thin film transistor, a common wiring, and a semiconductor wiring. The common wiring is parallel to the scanning two-wire package, and the halogen electrode covers the common wiring. a storage capacitor is generated at an overlap between the electrode and the common wiring, and a vertical distance between the pixel electrode and the common wiring is a vertical-to-vertical distance and a vertical distance smaller than a vertical distance. In the overlap of the pixel structures, the area of the second region where the second vertical separation is located is gradually reduced in the direction of the input end region of the scanning wiring wheel, so that the storage area is 27 201003263 ^i88twf.doc/d The input from the scanning wiring to the distal end region _ scanning line to the input end region gradually decreases. 17. The halogen array substrate according to claim 16, wherein the second vertical distance in each of the halogen structures is a variable vertical distance, and the change is straightforward from the scan. The area gradually increases away from the input wiring area of the scanning wiring. The halogen array substrate described in the above section, the poles corresponding to the common wiring 18. As in the patent scope, in the pixel structures, the overlapping areas of the halogens are the same. 19. In the above, the halogen substrate substrate of the item 16 has a gate insulating layer and a protective layer interposed between the halogen electrode and the common wiring. Human sentence 20. If you apply for patent scope, item 16 (4) q 冓 __ scan wiring clip 2828