201000391 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種微機電製造方法及其結構，特別是 指一種全新的可整合半導體製程之微機電前處理製造方 法及其結構，其能有效避免金屬不當侵蝕破壞，進而使内 部電路能與外部透過打線接合進行訊號傳輪。 【先前技術】 按’現今半導體微機電系統包含各種不同的半導體微 型結構’m“不可動的探針、流道、孔穴結構，或是一 些可動的科、連桿、絲㈤體勒或是撓性形變）等结 構。 、、口 將上述不同的結構和相關的半導體電路相互整合，即 可構成各種不_铸體應用；藉由製造方法提昇微機械 =構各料同的功能，是未來半㈣微機㈣統的關鍵指 [也疋未來進纟研究晶片時的嚴峻挑戰；若能研發改 進習知的技術’未來的發展性實無法預估。 目前製作微機電减浪丨哭β 及致動器系統皆需要在矽基 底上製作出懸浮式纟士描.1 ㈣製程必須採用了先進的半導 體技術’例如：濕叙 ^ 乾韻刻和犧牲層（sacrificial layer)去除等微機電專用作業。 201000391 的『^ΓΓ種快速有㈣刻，而且不致侧其它材料 合呈 1 etchant) ’因此’通常濕敍刻對不同材料 的『選擇性』 ㈣料外，由純學反趋不會對特 -方向有任何的偏好，因此濕钱刻本質上寸 :::r 一㈣。等向性峨= 果曰在縱向進行飯刻，而且也會有橫向的钱刻效 果輪向蝕刻會導致所褶『 ―致所㈠則飿』（undercut)的現象發生，· 相反的，在乾_(電漿糊） 離的氣體，乾㈣hi電水疋種部分解 ^料大優點即是『转向性钱刻』 (ams〇tropic etchlng)。然而，乾/ 蝕刻來得低（因為乾 …2"部比濕 互作H㈣ 機龍本上是—種物理交 作用，因此離子的撞擊不但可 同時會移除遮罩）。 的4膜，也 白用半導體製輕之結構如對石夕基底具微 =緣層進行金屬_，將直接二= 化4組成的光阻來做各種圖案的 = 阻來保護遍刻的區域，其 =述先 的強烈緣—㈣-—===) 201000391 其結構遭受破壞，故如何著重於保護層的製造方法及其結 構組成，進而避免該金屬連接層遭受银刻液侵#係為本發 明所欲解決之問題所在。 而為了能夠有效解決前述相關議題，本發明創作人基 於過去在微機電（Microelectric Machanic System, MEMS) 領域所累積的研發技術與經驗，於數次試驗及多方嘗試 後，終於發展出一種可整合半導體製程之微機電前處理製 造方法及其結構。 【發明内容】 本發明一種可整合半導體製程之微機電前處理製造 方法及其結構，其目的在於避免金屬不當蝕刻，使内部電 路能與外部透過打線等接合方式傳輸訊號。 為達成上述目的，本發明可整合半導體製程之微機電 前處理製造方法及其結構係於一矽基底上表面形成至少 一内具微機電結構的絕緣層，該微機電結構包含彼此獨立 的至少一微結構與數個金屬電路，該絕緣層成型一與金屬 電路及外部導體電性連結的金屬連接層，該金屬連接層係 外露於該絕緣層表面上受一保護層覆蓋進行蝕刻，或該金 屬連接層係内藏於該絕緣層表面下受該絕緣層覆蓋進行 201000391 名虫刻。 藉由前述進一步分析將可獲得下述功效：本發明金屬 連接層藉由該保護層保護進行#刻，或該金屬連接層透過 預先的光罩佈局設計，減少額外的光罩花費，並且藉由該 絕緣層保護進行蝕刻，讓蝕刻無法直接侵蝕該金屬連接 層，避免該金屬連接層遭受結構破壞，使外部導體透過與 該金屬連接層電性連結後，令該金屬電路透過打線與外部 接合進行傳輸訊號。 有關本發明為達成上述目的，所採用之技術、手段及 其他功效，茲列舉實施例並配合圖式詳細說明如後，相信 本發明之目的、特徵及其他優點，當可由之得一深入而具 體之暸解。 【實施方式】 本發明實施例請參閱第1圖至第11圖所示： 本發明可整合半導體製程之微機電前處理製造方法 及其結構詳細說明如下： 請參閱第1圖及第7圖所示，首先於一矽基底10上表面 11成型一絕緣層20,該保護層40採用的材質必須注意不會 與餘刻液（如硫酸）產生反應，該絕緣層2 0内具有微機電結 201000391 構21，該微機電結構21包含彼此獨立的至少一微結構 211、複數個金屬插銷堆疊層212及複數個金屬電路213， 該微機電結構21周侧預設有貫通該絕緣層20的蝕刻空間 201，該金屬插銷堆疊層212設於該蝕刻空間201中，各金 屬插銷堆疊層212係由鋁銅合金、鎢及鈦等金屬交互堆疊 而成，且各金屬插銷堆疊層212兩兩連接導通，前述金屬 插銷堆疊層212並未與該微機電結構21接觸； 該絕緣層20成型一與該金屬電路213電性連結的金屬 連接層30，使外部導體透過與該金屬連接層30電性連結， 讓該金屬電路213與外部導體進行訊號連結，該金屬連接 層30(請參閱第1圖及第2圖所示）係可外露於該絕緣層20 表面上，或該金屬連接層30(請參閱第7圖所示）係可内藏 於該絕緣層20表面下。 請參閱第3圖及第8圖所示，該金屬插銷堆疊層212係 經過蝕刻（係採用濕蝕刻或乾蝕刻）去除形成僅通過該絕 緣層2 0的姓刻空間2 01，但是該金屬插銷堆疊層212進行 刻前，必須先確定該金屬連接層30外露於該絕緣層20表面 上，或者該金屬連接層3 0内藏於該絕緣層2 0表面下； 當判斷該金屬連接層30處於外露狀態（請參閱第1圖 及第2圖所示）時，該金屬連接層3 0表面上必須沉積一保護 層4 0，避免該金屬連接層3 0受#刻侵I虫破壞； 10 201000391 當判斷該金屬連接層3 0處於内藏狀態時（請參閱第7 圖所示），該金屬連接層30表面已受該絕緣層20覆蓋，故 無須沉積一保護層4 0，同樣避免該金屬連接層3 0受鞋刻侵 蝕破壞； 但須注意的是該保護層40的材質必須採用不被蝕刻 破壞的材質，如該保護層40採用與該絕緣層20同樣材質， 或該保護層40採用鈍性金屬材質或非有機材質，以上材質 的採用必須注意不會與蝕刻液（如硫酸）產生反應，進而達 到該金屬連接層30於上設置該絕緣層20或該保護層40之 目的，且該金屬連接層30透過預先的光罩佈局設計減少額 外的光罩花費。 該金屬插銷堆疊層212去除之後，該微機電結構21將 受該絕緣層20包覆，根本不會曝露内部的微結構211或金 屬電路213。 請參閱第4圖及第9圖所示，該絕緣層20於表面旋佈一 光阻（Photoresist)層50，僅使該金屬連接層30上的保護 層4 0或該金屬連接層3 0上的絕緣層2 0外露。 請參閱第5圖及第10圖所示，該金屬連接層30上的保 護層40或該金屬連接層30上的絕緣層20係經過乾蝕刻（係 採用反應離子I虫刻Reactive Ion Etching, RIE)去除，使 11 201000391 該金屬連接層30外露於該絕緣層20表面。 請參閱第6圖及第11圖所示’該絕緣層2〇上的光阻層 50係經過蝕刻（係採用濕蝕刻或乾蝕刻氧電漿）去除，接續 後續製程。 藉前述可整合半導體製程之微機電前處理製造方法 及其結構；本發明產生的效果在於：該金屬連接層3〇受該 保護層40或該絕緣層2〇㈣下進純刻，避免該金屬連接 層30直接被蝕刻液不當侵蝕，進而維持外部導體、該 健層30及該金屬電路213三者彼此之間訊號傳輸的通 暢。 ’不上所逑’本發明『產業之可彻性』已顯而易見 且本案實施例露㈣雜技術，並未見於各刊物及傳 媒’亦未曾被公開使用，更具有不可輕忽的附加功效，故 本fx月的新穎性』以及『進步性』都已符合專利法規， 爰依法提㈣料敎巾請，析請,€查解日賜准專 利’實感德便。 12 201000391 【圖式簡單說明】 '第1圖至第6圖係本發明採用保護層保護金屬連接層之製 k方法及其結構示意圖。 *圖至第11圖係本發明採用絕緣層保護金屬連接層之製 造方法及其結構示意圖。 < 【主要元件符號說明】 《本發明》 矽基底10 上表面11 絕緣層20 蝕刻空間201 微機電結構21 微結構211 金屬插鱗堆疊層212 金屬電路213 金屬連接層3〇 光阻層50 保護層40201000391 IX. Description of the Invention: [Technical Field] The present invention relates to a microelectromechanical manufacturing method and structure thereof, and more particularly to a novel microelectromechanical pretreatment manufacturing method and structure thereof capable of integrating semiconductor processes, which can be effective Avoid metal undue erosion and damage, so that the internal circuit can be connected to the outside through the wire for signal transmission. [Prior Art] According to the 'current semiconductor MEMS system contains a variety of different semiconductor micro-structures 'm" immovable probes, runners, hole structures, or some movable branches, links, wires (five) body or scratch Structure, etc., and the above-mentioned different structures and related semiconductor circuits are integrated with each other to form various non-casting applications; the manufacturing method is used to improve the micro-mechanical = the same function of the materials, which is the next half. (4) The key point of the microcomputer (four) system is [also the serious challenge in the future research and development of the wafer; if the technology can be developed and improved, the future development cannot be predicted. Currently, the micro-electromechanical wave reduction and crying β and actuation are made. The system needs to make a floating gentleman's drawing on the crucible substrate. 1 (4) The process must use advanced semiconductor technology, such as: wet-drying and sacrificial layer removal, etc. 201000391 The "^" species is fast (four) engraved, and does not cause other materials to be combined with 1 etchant) 'so 'usually wet etched the "selectivity" of different materials (four), from pure There is no preference for the special-direction, so the wet money is essentially in the order of:::r one (four). Isotropic 峨 = fruit 曰 in the vertical direction, and there will also be a horizontal money engraving effect Etching will cause the pleats to be "undercut", and conversely, in the dry _ (electric paste) gas, the dry (four) hi electric water 部分 part of the solution is the advantage "ams〇tropic etchlng". However, the dry/etching is low (because the dry...2" part-to-wet interaction H(four) machine is a kind of physical interaction, so the impact of ions can not only be simultaneously Will remove the mask). The 4 film, also white semiconductor light structure, such as the stone 基底 substrate with micro = edge layer of metal _, will directly = = 4 composition of the photoresist to make a variety of patterns = resistance To protect the area of the engraving, the strong edge of the first--(four)--===) 201000391 The structure is damaged, so how to focus on the manufacturing method of the protective layer and its structural composition, and then avoid the silver metal layer Engraving intrusion # is the problem that the invention wants to solve. To solve the aforementioned related issues, the creators of the present invention have finally developed a micro-integrated semiconductor process based on the research and development techniques and experience accumulated in the field of Microelectric Machanic System (MEMS) in the past several experiments and various attempts. The present invention relates to a microelectromechanical pre-processing manufacturing method and a structure thereof which can integrate a semiconductor process, and the object thereof is to avoid improper etching of metal, and to enable the internal circuit to be bonded to the outside through a wire bonding method. To achieve the above object, the microelectromechanical pretreatment manufacturing method and the structure thereof for integrating the semiconductor process of the present invention are formed on the upper surface of a substrate to form at least one insulating layer having a microelectromechanical structure, the microelectromechanical structure being independent of each other. At least one microstructure and a plurality of metal circuits, the insulating layer forming a metal connecting layer electrically connected to the metal circuit and the outer conductor, the metal connecting layer being exposed on the surface of the insulating layer and covered by a protective layer for etching Or the metal connection layer is hidden under the surface of the insulating layer The insulating layer for covering the engraved 201000391 insects. By the foregoing further analysis, the following effects can be obtained: the metal connecting layer of the present invention is protected by the protective layer, or the metal connecting layer is designed through a pre-mask layout to reduce the cost of the additional mask, and by The insulating layer protects the etching, so that the etching cannot directly erode the metal connecting layer, and the metal connecting layer is prevented from being damaged by the structure, so that the external conductor is electrically connected to the metal connecting layer, and then the metal circuit is connected by wire bonding and external bonding. Transmit the signal. The present invention has been described with reference to the embodiments and the detailed description of the present invention. The objects, features and other advantages of the present invention are believed to be Understand. [Embodiment] Please refer to FIG. 1 to FIG. 11 for the embodiment of the present invention. The MEMS manufacturing method and the structure thereof for integrating the semiconductor process of the present invention are described in detail as follows: Please refer to FIG. 1 and FIG. 7 First, an insulating layer 20 is formed on the upper surface 11 of the substrate 10, and the material of the protective layer 40 must be careful not to react with a residual liquid (such as sulfuric acid) having a microelectromechanical junction 201000391. The microelectromechanical structure 21 includes at least one microstructure 211 independent of each other, a plurality of metal pin stack layers 212, and a plurality of metal circuits 213. The periphery of the microelectromechanical structure 21 is pre-formed with an etching space penetrating the insulating layer 20. 201, the metal pin stack layer 212 is disposed in the etching space 201, each metal pin stack layer 212 is formed by alternately stacking metal such as aluminum-copper alloy, tungsten, and titanium, and each metal pin stack layer 212 is connected and connected. The metal pin stack layer 212 is not in contact with the microelectromechanical structure 21; the insulating layer 20 forms a metal connection layer 30 electrically connected to the metal circuit 213, and the external conductor is transmitted through the metal. The metal layer 213 is electrically connected to the external conductor, and the metal connection layer 30 (see FIGS. 1 and 2) may be exposed on the surface of the insulating layer 20, or The metal connection layer 30 (see FIG. 7) can be embedded under the surface of the insulating layer 20. Referring to FIGS. 3 and 8 , the metal pin stack layer 212 is etched (by wet etching or dry etching) to form a surname space 2 01 only through the insulating layer 20, but the metal latch Before the stacking layer 212 is inscribed, the metal connecting layer 30 must be exposed on the surface of the insulating layer 20, or the metal connecting layer 30 is hidden under the surface of the insulating layer 20; when it is judged that the metal connecting layer 30 is In the exposed state (refer to FIG. 1 and FIG. 2), a protective layer 40 must be deposited on the surface of the metal connection layer 30 to prevent the metal connection layer 30 from being damaged by the invaders; 10 201000391 When it is judged that the metal connection layer 30 is in the built-in state (refer to FIG. 7), the surface of the metal connection layer 30 has been covered by the insulating layer 20, so that it is not necessary to deposit a protective layer 40, and the metal is also avoided. The bonding layer 30 is damaged by the erosion of the shoe; however, it should be noted that the material of the protective layer 40 must be made of a material that is not damaged by etching, for example, the protective layer 40 is made of the same material as the insulating layer 20, or the protective layer 40 is used. Blunt metal or non-organic The above materials must be used for the purpose of reacting with the etching solution (such as sulfuric acid), thereby achieving the purpose of providing the insulating layer 20 or the protective layer 40 on the metal connecting layer 30, and the metal connecting layer 30 is transmitted in advance. The reticle layout design reduces the cost of additional reticle. After the metal pin stack layer 212 is removed, the microelectromechanical structure 21 will be covered by the insulating layer 20 without exposing the internal microstructure 211 or the metal circuit 213 at all. Referring to FIG. 4 and FIG. 9, the insulating layer 20 is rotated on the surface of a photoresist layer 50, and only the protective layer 40 or the metal connecting layer 30 on the metal connecting layer 30 is disposed. The insulating layer 20 is exposed. Referring to FIGS. 5 and 10, the protective layer 40 on the metal connection layer 30 or the insulating layer 20 on the metal connection layer 30 is dry etched (reactive Ion Etching, RIE) And removing, so that the metal connection layer 30 is exposed on the surface of the insulating layer 20. Referring to Figures 6 and 11, the photoresist layer 50 on the insulating layer 2 is removed by etching (by wet etching or dry etching of oxygen plasma), followed by subsequent processes. The foregoing microelectromechanical pretreatment manufacturing method and structure thereof can be integrated into the semiconductor process; the effect of the invention is that the metal connection layer 3 is purely engraved by the protective layer 40 or the insulating layer 2(4) to avoid the metal The connecting layer 30 is directly eroded by the etching liquid, thereby maintaining the smooth transmission of signals between the external conductor, the bonding layer 30 and the metal circuit 213. 'There is no such thing as 'the industry's completeness' is obvious and the examples in this case show (four) miscellaneous technology, which has not been seen in the publications and the media' has not been publicly used, and has additional functions that cannot be neglected. The novelty of fx month and the "progressiveness" have been in compliance with the patent regulations, and 爰 提 ( 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 。 。 。 。 。 。 。 。 。 。 。 12 201000391 [Simplified description of the drawings] 'Fig. 1 to Fig. 6 are diagrams showing the method of manufacturing a protective layer for protecting a metal connecting layer and the structure thereof. * Fig. 11 is a schematic view showing a manufacturing method and a structure of the present invention for protecting a metal connecting layer by an insulating layer. < [Description of main component symbols] <<The present invention>> 矽 substrate 10 upper surface 11 insulating layer 20 etching space 201 MEMS structure 21 microstructure 211 metal scaly stacked layer 212 metal circuit 213 metal connection layer 3 〇 photoresist layer 50 protection Layer 40