200952574 . 九、發明說明： . 【發明所屬之技術領域】 _ 本發明係有關於一種電路板，尤指一種具有防電磁波 干擾之效果之電路板。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功 *旎、咼性能的方向研發。為滿足半導體封裴件高積集度 (Integration)以及微型化的封裝需求，提供多數主、 ❹被動兀件及線路載接之電路板，亦逐漸由單層板演變成多 層板，俾於有限的空間下，藉由層間連接技術擴大電路板 上可利用的電路面積以因應高電子密度之積體電路之使 用需求。 ,為提高電路板之佈線精密度，業界發展出一種增層技 術（Bui 1 d up) ’亦即在一核心板表面利用線路增層技術交 互形成複數介電層及線路層，並於該介電層中形成有複數 參導電結構’如導電盲孔（ — tive仏）及電鑛導通孔 (Plahng through h〇le，PTH)以供上下層線路之間的電 且為求訊號傳送時，避免在高頻環境中受外界電磁波 ^也，—護之線路的上下兩方或左右兩侧 汉有接地層’以猎由該接地層隔絕外界電磁波之干擾。 圖’係於承載板1Q上水平形成有 乐’丨電層12a，又於該第一介啻思,0 ^ ;丨電層12a上形成有至少— 110868 5 200952574 …線路13,於該第一介電層12a及該些線路13上形成有第 —二介電層12b’並於該第二介電層瓜上水平形成有第二 接地層lib’以藉由該第一及第二接地層Ua，ub防止外 界電磁波干擾該些線路13。 惟該第-及第二接地層Ua，nb係分別水平形成於 該承載板10及第二介電層12b上，使該第—及第二接地 _層lla，llb分別形成於該些線路13之上下位置，而形成 三層式之結構，使得整體厚度增加，而不利於薄化；又該 ❹第一及第二接地層lla，Ub僅能遮蔽上下方之電磁波的 干擾，對於左右兩側完全無遮蔽效果，且該第一及第二介 電層12a，12b具有相當厚度，使該第一接地層Ua與該些 線路13之間、或該第二接地層llb與該些線路13之間的 間隔較大，使該些線路13易受電磁波干擾，而影響訊號 之傳送。 請參閱第1B圖，與上述之習知構造不同處在於該接 ❹地層係嵌埋於線路之兩側；係於承載板1〇上形成有介電 層12’於該介電層12中嵌埋有至少一線路13及垂直設 置之複數垂直接地層11，且該些線路13形成於該垂直接 地層11之間’使該些垂直接地層Η位於該些線路13之 左右兩側’以藉由該些垂直接地層丨丨左右遮蔽該些線路 13。 惟’該些垂直接地層11僅左右遮蔽該些線路丨3，於 該些線路13之上下兩方並無遮蔽，故防止外界電磁波干 擾之效果較差。 6 110868 200952574 * 因此，雲於上述之問題 改為如何避免習知技術中，唁峻 前亟欲解決的課題。 （皮專相導除’實已成目 【發明内容】 馨於上述習知技術之缺失， -一種恭踗姑At^ ^^失本發明主要目的係在提供 .的干擾。 果1避免線路受外界電磁波 I發明主要目的係在提供—種電路板，能避免線 ©外界電磁波的干擾，並將電磁波等雜訊移除。、又 為達上述目的及其他目的，本發明揭露一種電路板， 係包括：承載板；至少一對之第一 ^ ^ t 禾水干接地層’係設於該 承載板上；介電層，係覆設於該承載板及第一水平接地層 上；至少-對之垂直接地層，係垂直設於該介電層中，並 對應電性連接各該第-水平接地層；以及至少一線路係 设於該介電層中，且位於該些垂直接地層之間。 ❹ 依上述之電路板，該承載板係為介電層、絕緣板或具 有線路之線路板；該介電層係由第一介電層及 層所組成，該第一介電層及第二介電層係為相同或不相同 之材質。 依上述之結構’該線路係設於該第一介電層上；該線 路係嵌埋於該第一介電層中，且與該第一介電層之表面齊 平；該線路係跨越該第一介電層及第二介電層之間的界 面’而嵌埋於該第一介電層及第二介電層之中。 依上所述’該至少一對之第一水平接地層係水平連接 110868 7 200952574 ‘成一體，以形成水平延伸接地層，並水平設於該承載板 上，或该至少一對之第一水平接地層係水平連接成一 —體，以形成水平延伸接地層，並嵌埋於該承載板中，且與 該承載板表面齊平；該水平延伸接地層之寬度大於或等 於兩相鄰之垂直接地層之間的寬度。 又依上所述，復包括第二水平接地層，係設於該第二 -”電層上，並電性連接該些垂直接地層；或該第二水平接 地層係嵌埋於該第二介電層中，且與該第二介電層表面齊 ❹平’並電性連接該些垂直接地層；該第二水平接地層之寬 度大於或等於兩相鄰之垂直接地層之間的寬度。 該些第一水平接地層之厚度尺寸係為相同或不同； 該些垂直接地層之厚度尺寸係為相同或+同；該些垂直 接地層位於第一介電層及第二介電層之厚度尺寸：為相 同或不同。 本發明復提供-種電路板’係包括：承載板；介電 參層，係覆設於該承載板上；至少一對垂直接地層，係 設於該介電層中；以及至少—線路，係設於該介電層内 部，且位於該至少一對之垂直接地層之間。 依上述之電路板，該承載板係為介電層、絕緣板或具 有線路之線路板；該介電層係由第—介電層及第二介雷 相㈣’該第-介電層及第二介電層係為 之材質。 &卜邳冋 依上述之結構’該線路係設於該第一介電声上. 線路係嵌埋於該第—介雷展 θ ’或該 于甘入埋於这弟”電層中，且與該第一介電層之表面 Π0868 8 200952574 齊平；或該線路係跨越該第_ ^ "電層及弟二介電層之間 的界面，而傲埋於該第一介雪恳 外 ^ 層及第二介電層之中。 依上所述，該此垂直接s 一玉直接地層之厚度尺寸係為相同或不 同；該些垂直接地層位於第—介恭 ;丨私層及第二介電層之厚 度尺寸係為相同或不同。 本發明之電路板，係將至少一對之垂直接地層垂直設 於介電層中，以及至少-線路係設於該介電層内部，且位 於該至少一對之垂直接地層之間；或該至少一對之垂直 ❹接地層垂直設於介電層中並電性連接第—水平接地層，以 及至少一線路，係設於該介電層内部，且位於該至少一對 之垂直接地層之間，俾以提高遮蔽效果，以降低外界電磁 波之干擾；又該至少一對之第一水平 體，以進-步包覆該些線路；又於該介電層上;二=: 水平接地層’以完整包覆該些線路，而能更完整提供遮蔽 效果’以避免外界電磁波干擾該些線路。 B【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 [第一實施例] 請參閱第2A至2D圖’係為本發明電路板第一實施例 之剖視圖。 ' 本發明之電路板，係於承载板20上設有至少一對之 第一水平接地層21，該承载板20係為介電層、絕緣板或 Ϊ10868 9 200952574 •具2線路之線路板，於該承載板20及第一水平接地層21 :上覆設由第一介電層22a及第二介電層22b所組成之^電 層22、’其中，該第一介電層22a及第二介電層2肋係為 相同或不相同之材質，於該第一介電層22a及第二介電層 22b中垂直叹有至少一對之垂直接地層且對應電性連 接各該第-水平接地層21，又於該第—介電層仏上設 有至少一線路2 4，使該線路2 4位於相鄰之垂 之間，並位於該介電芦22中，知笛9Α θ ©24係嵌埋於該第―介曰電 ：不；或該線路 电僧ZZa中且與該第一介雷層 =表：=，而能有效控制線路之形狀，並形成細間距線 路’如弟2B_&或該線路24係跨越 =第二介電層22b之間的界面22。，而歲埋於該第： 吉及第二介電層22b之中，如第2C圖所示；此 2 at =也層仏，咖，仏及各該第-水平接地層200952574. IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a circuit board, and more particularly to a circuit board having an effect of preventing electromagnetic interference. [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functionality and performance. In order to meet the high integration of semiconductor package components and miniaturized packaging requirements, most of the main, passive components and circuit-loaded circuit boards are provided, and gradually evolved from single-layer boards to multi-layer boards. In the space, the circuit area available on the circuit board is expanded by the interlayer connection technology to meet the needs of the integrated circuit with high electron density. In order to improve the wiring precision of the circuit board, the industry has developed a layer-up technology (Bui 1 d up), that is, a plurality of dielectric layers and circuit layers are alternately formed on the surface of a core board by using a line build-up technology. In the electrical layer, a plurality of conductive structures such as conductive blind holes (- tive 仏) and electric conduction vias (PTH) are provided for the electrical connection between the upper and lower lines and are transmitted for signal transmission. In the high-frequency environment, the external electromagnetic wave is also used, and the upper and lower sides of the line or the left and right sides of the line are protected by the grounding layer to isolate the electromagnetic wave from the ground. The figure 'is formed on the carrier board 1Q horizontally to form a music layer 12a, and on the first layer of the first layer, 0 ^ ; the layer 12a is formed with at least - 110868 5 200952574 ... line 13, at the first A second dielectric layer 12b' is formed on the dielectric layer 12a and the lines 13 and a second ground layer lib' is horizontally formed on the second dielectric layer to form the first and second ground layers. Ua, ub prevents external electromagnetic waves from interfering with the lines 13. The first and second ground layers Ua, nb are horizontally formed on the carrier 10 and the second dielectric layer 12b, respectively, so that the first and second ground layers 11a and 11b are formed on the lines 13 respectively. The upper and lower positions form a three-layer structure, so that the overall thickness is increased, which is disadvantageous for thinning; and the first and second ground layers 11a, Ub can only shield the interference of the upper and lower electromagnetic waves, for the left and right sides The first and second dielectric layers 12a, 12b have a considerable thickness, such that the first ground layer Ua and the lines 13 or the second ground layer 11b and the lines 13 The interval between the two is large, so that the lines 13 are susceptible to electromagnetic waves and affect the transmission of signals. Please refer to FIG. 1B , which differs from the above-mentioned conventional structure in that the interface layer is embedded on both sides of the line; a dielectric layer 12 ′ is formed on the carrier layer 1 嵌 in the dielectric layer 12 . At least one line 13 and a plurality of vertically disposed vertical ground layers 11 are buried, and the lines 13 are formed between the vertical ground layers 11 'so that the vertical ground layers are located on the left and right sides of the lines 13' The lines 13 are shielded from the left and right ground layers. However, the vertical grounding layers 11 shield the circuit lines 3 only to the left and right, and the upper and lower sides of the lines 13 are not shielded, so that the effect of preventing external electromagnetic wave interference is poor. 6 110868 200952574 * Therefore, the question of cloud in the above is changed to how to avoid the problem that the prior art wants to solve in the conventional technology. (Skin special phase guides to 'reality has been eye-catching' [invention content] Xin is missing in the above-mentioned conventional technology, - a kind of Gongyi Gu At ^ ^ ^ lost the main purpose of the invention is to provide interference. The main purpose of the external electromagnetic wave I invention is to provide a circuit board, which can avoid the interference of the external electromagnetic wave of the line ©, and remove the noise such as electromagnetic waves. Moreover, for the above purpose and other purposes, the present invention discloses a circuit board. The method includes: a carrier board; at least one pair of the first ^ ^ t and water dry ground layer ' is disposed on the carrier board; the dielectric layer is disposed on the carrier board and the first horizontal ground layer; at least - The vertical grounding layer is vertically disposed in the dielectric layer and electrically connected to each of the first-horizontal grounding layers; and at least one of the wires is disposed in the dielectric layer and located between the vertical grounding layers.依 according to the above circuit board, the carrier board is a dielectric layer, an insulating board or a circuit board having a line; the dielectric layer is composed of a first dielectric layer and a layer, the first dielectric layer and the second layer The dielectric layers are the same or different materials. The structure is disposed on the first dielectric layer; the circuit is embedded in the first dielectric layer and flush with a surface of the first dielectric layer; the circuit crosses the first An interface between a dielectric layer and a second dielectric layer is embedded in the first dielectric layer and the second dielectric layer. According to the above-mentioned at least one pair of first horizontal ground layer The horizontal connection 110868 7 200952574 is integrated to form a horizontally extending ground layer and horizontally disposed on the carrier plate, or the at least one pair of first horizontal ground layers are horizontally connected to form a body to form a horizontally extending ground layer. And embedded in the carrier plate and flush with the surface of the carrier plate; the width of the horizontally extending ground layer is greater than or equal to the width between two adjacent vertical ground layers. a horizontal ground layer is disposed on the second-"electric layer and electrically connected to the vertical ground layers; or the second horizontal ground layer is embedded in the second dielectric layer, and the second The surface of the dielectric layer is flush and electrically connected to the vertical ground layers; the second level The width of the formation is greater than or equal to the width between two adjacent vertical ground layers. The thicknesses of the first horizontal ground layers are the same or different; the thicknesses of the vertical ground layers are the same or the same; The vertical grounding layer is located at a thickness dimension of the first dielectric layer and the second dielectric layer: the same or different. The present invention provides a circuit board that includes: a carrier plate; a dielectric layer, which is coated on the a carrier board; at least one pair of vertical ground layers disposed in the dielectric layer; and at least a line disposed within the dielectric layer and between the at least one pair of vertical ground layers. a circuit board, the carrier board is a dielectric layer, an insulating board or a circuit board having a line; the dielectric layer is composed of a first dielectric layer and a second dielectric phase (4) 'the first dielectric layer and the second dielectric layer The electric layer is made of the material. & 邳冋 邳冋 according to the above structure 'The line is set on the first dielectric sound. The line is embedded in the first - shang θ ' or the burial This younger brother is in the electric layer and is flush with the surface of the first dielectric layer Π0868 8 200952574 Or the line spans the interface between the first and second dielectric layers, and is buried in the first and second dielectric layers. According to the above, the thickness dimension of the vertical layer of the vertical connection is the same or different; the vertical ground layer is located at the first layer; the thickness of the private layer and the second dielectric layer are the same or different. The circuit board of the present invention is characterized in that at least one pair of vertical ground layers are vertically disposed in the dielectric layer, and at least - the wiring is disposed inside the dielectric layer and between the at least one pair of vertical ground layers; or The at least one pair of vertical germanium ground layers are vertically disposed in the dielectric layer and electrically connected to the first horizontal ground layer, and at least one of the wires is disposed inside the dielectric layer and located at the at least one pair of vertical ground layers Between the two, to improve the shielding effect to reduce the interference of external electromagnetic waves; and the at least one pair of the first horizontal body, to cover the lines in a step-by-step manner; on the dielectric layer; two =: horizontal connection The formation 'completely covers the lines, and provides a more complete shielding effect' to avoid external electromagnetic waves from interfering with the lines. [Brief Description of the Invention] The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily appreciate the other advantages and effects of the present invention from the disclosure. [First Embodiment] Referring to Figures 2A to 2D, there is shown a cross-sectional view of a first embodiment of a circuit board of the present invention. The circuit board of the present invention is provided with at least one pair of first horizontal ground layers 21 on the carrier board 20, the carrier board 20 being a dielectric layer, an insulating board or a 86810868 9 200952574 • a circuit board having two lines. The carrier layer 20 and the first horizontal ground layer 21 are covered with an electric layer 22 composed of a first dielectric layer 22a and a second dielectric layer 22b, wherein the first dielectric layer 22a and the first dielectric layer 22a The ribs of the two dielectric layers 2 are the same or different materials, and at least one pair of vertical ground layers are vertically slanted in the first dielectric layer 22a and the second dielectric layer 22b, and the first one is electrically connected. The horizontal ground layer 21 is further provided with at least one line 24 on the first dielectric layer, so that the line 24 is located between the adjacent vertical and is located in the dielectric reed 22, and the flute 9 Α θ © The 24 series is embedded in the first dielectric: no; or the electrical circuit ZZa and the first dielectric layer = table: =, and can effectively control the shape of the line, and form a fine pitch line 2B_& or the line 24 spans the interface 22 between the second dielectric layers 22b. And the age is buried in the first: 吉 and the second dielectric layer 22b, as shown in Figure 2C; this 2 at = also layer, coffee, 仏 and each of the first-horizontal ground plane
Ulb之厚度尺寸係為相_不同 ❹ 需要，如第2D圖所示。 衣柱。又4之 [第二實施例] 請參閱第3A至3C圏，係為本發明一 之剖視圖；與前一實施例之不同處在於，該至= 一水平接地層係水平連接成一體。 、乐 如第3A及3A，圖所示，係將前 一 構，於該承載板20上至少—對之笛— 圖所不之結 平連接成-體，以形成水平延伸平接地層21係水 板20及水平延伸接地層21，上 ^^，於該承載 又由該苐—介電層22a 】10868 10 200952574 ' 及第二介電層22b所組成之介電層22，於該第一介電層 ;22a及第二介電層22b中垂直設有至少一對之垂直接地層 .23 ’且電性連接至該水平延伸接地層21，，又於該第一介 電層22a上設有至少一線路24，使該線路24位於相鄰之 垂直接地層23之間，並位於該介電層22中，且談水平延 伸接地層21’之寬度wl大於兩相鄰之垂直接地層23之間 的覓度w2,如第3A圖所示；或該且該水平延伸接地層21， 之寬度wl等於兩相鄰之垂直接地層23之間的寬度w2， ❺如第3A，圖所示。 如第3B及3B’圖所示，或該線路24係嵌埋於該第一 )丨私層22a中，且與該第一介電層2 2a之表面齊平，俾以 有效控制線路之形狀，並形成細間距線路，且該水平延伸 =地層21’之寬度wl大於兩相鄰之垂直接地層23之間的 寬度w2，如第3B圖所示；或該水平延伸接地層21，之寬 度Wl等於兩相鄰之垂直接地層23之間的寬度w2，如第 ❷3B’圖所示。 如第3C及3C’圖所示，或該線路24係跨越該第一介 電層22a及第二介電層22b之間的界面22c，而嵌埋於該 第一介電層22a及第二介電層22b之中，而能有效控制線 —之开V狀以形成細間距線路，且該水平延伸接地層2 1，之 ，度Wl大於兩相鄰之垂直接地層23之間的寬度w2，如 第3C圖所不，或該水平延伸接地層21，之寬度wi等於兩 相鄰之垂直接地層23之間的寬度W2，如第3C，圖所示。 [弟二貫施例] 110868 11 200952574 第三實施例 二'介電層上 請參閱第4A至4C圖，係為本發明電路板 之剖視圖；與前述實施例之不同處在於該第 0又β弟-水平接地層0 地声料承餘2G上設有水平延伸接 —曰21 ’於絲載板2G及水平延伸接地層21，上 第-介電層22a及第二介電層挪所組成之介電層二， 且該水平延伸接地|21，嵌埋於該第—介電们^中，又The thickness dimension of Ulb is phase _ different ❹ required, as shown in Figure 2D. Clothes column. [Second Embodiment] Please refer to Figs. 3A to 3C, which are cross-sectional views of the present invention; the difference from the previous embodiment is that the horizontal layer is horizontally connected integrally. As shown in Figs. 3A and 3A, the former structure is formed on the carrier board 20 at least - the flute - the figure is not connected to the body to form a horizontally extending flat ground layer 21 The water board 20 and the horizontally extending ground layer 21, the upper layer, and the dielectric layer 22 composed of the germanium-dielectric layer 22a 10868 10 200952574 ' and the second dielectric layer 22b, The dielectric layer 22a and the second dielectric layer 22b are vertically disposed with at least one pair of vertical ground layers .23' and electrically connected to the horizontally extending ground layer 21, and are further disposed on the first dielectric layer 22a. There is at least one line 24 such that the line 24 is located between the adjacent vertical ground layers 23 and is located in the dielectric layer 22, and the width w1 of the horizontally extending ground layer 21' is greater than the two adjacent vertical ground layers 23 The width w2 between, as shown in FIG. 3A; or the horizontal extension of the ground layer 21, the width wl is equal to the width w2 between two adjacent vertical ground layers 23, such as the 3A, as shown in the figure . As shown in FIGS. 3B and 3B', or the line 24 is embedded in the first) privacy layer 22a and flush with the surface of the first dielectric layer 22a, to effectively control the shape of the line. And forming a fine pitch line, and the horizontal extension=the width w1 of the ground layer 21' is greater than the width w2 between the two adjacent vertical ground layers 23, as shown in FIG. 3B; or the horizontally extending ground layer 21, the width Wl is equal to the width w2 between two adjacent vertical ground layers 23, as shown in Figure 3B'. As shown in FIGS. 3C and 3C', or the line 24 spans the interface 22c between the first dielectric layer 22a and the second dielectric layer 22b, and is embedded in the first dielectric layer 22a and the second In the dielectric layer 22b, the line-open V-shape can be effectively controlled to form a fine pitch line, and the horizontally extending ground layer 2 1, the degree W1 is greater than the width w2 between the two adjacent vertical ground layers 23. As shown in FIG. 3C, or the horizontally extending ground layer 21, the width wi is equal to the width W2 between two adjacent vertical ground layers 23, as shown in FIG. 3C. [Different embodiment] 110868 11 200952574 The third embodiment 2, the dielectric layer, please refer to the 4A to 4C drawings, which is a cross-sectional view of the circuit board of the present invention; the difference from the foregoing embodiment is that the 0th and βth Brother-horizontal grounding layer 0 The grounding material 2G is provided with a horizontal extension - 曰21' on the wire carrier 2G and the horizontally extending ground layer 21, and the upper dielectric layer 22a and the second dielectric layer are formed. Dielectric layer 2, and the horizontal extension ground |21, embedded in the first dielectric ^,
於該第-介電層22a及第二介電層22b中垂直設有至少一 對之垂直接地層23’且電性連接該水平延伸接地層21，丨 又於該第-介電層22a上設有至少—線路24，使0該線路 24位於相鄰之垂直接地層23之間，並位於該第一介電層 22a上，如第4A圖所示；或該線路24係嵌埋於該第一介 電層22a中，且與該第一介電層22a之表面齊平，如第 4B圖所示；該線路24係跨越該第一介電層22&及第二介 電層22b之間的界面22c，而嵌埋於該第一介電層22a及At least one pair of vertical ground layers 23' are vertically disposed in the first dielectric layer 22a and the second dielectric layer 22b, and electrically connected to the horizontally extending ground layer 21, and further on the first dielectric layer 22a. Providing at least a line 24 such that the line 24 is located between adjacent vertical ground layers 23 and on the first dielectric layer 22a as shown in FIG. 4A; or the line 24 is embedded in the line The first dielectric layer 22a is flush with the surface of the first dielectric layer 22a, as shown in FIG. 4B; the line 24 spans the first dielectric layer 22& and the second dielectric layer 22b. The interface 22c is embedded in the first dielectric layer 22a and
第二介電層22b之中，如第4C圖所示；且於該第二介電 層22b上:有弟二水平接地層25，並電性連接該至少一 對之垂直接地層23，如第4A圖所示；又該第二水平接地 層25係喪埋於該第二介電層22b中，且與該第二介電層 22b表面齊平，並電性連接該至少一對之垂直接地層23， 如第4B及4C圖所示。 又該第二水平接地層25之寬度w3大於兩相鄰之垂直 接地層23之間的寬度W2。 [第四實施例] 12 110868 200952574 請參閱第5A至5C圖，係A 士欲n口 + 、 加馮本發明電路板第四實施例 . 之剖視圖；與前述實施例之不Π + • ^ 不冋處在於水平延伸接地層 係嵌埋於該承載板中，且與該承 * 喊艰载板的表面齊平；又該水 平延伸接地層及第二水平接 接地層的見度等於兩相鄰之垂 直接地層之間的寬度。 ， 轉明之電路板，係於承載板20中設有水平延伸接 -^層21’’且該水平延伸接地層21，喪埋於該承載板2〇 中，於該承載板20及水平延伸接地層21,上覆設由第一 ©介電層22a及第二介電層22b 电屬Ub所組成之介電層22，且該 水平延伸接地層21’之上表面與該承載板2〇及第一介 層22a之間的界面齊平，於該第一介電層22a及第二介電 層22b中垂4設有至少—對之垂直接地層23，且對應電 性連接各該水平延伸接地層21，，又於該第一介電層❿ 上认有至 > 線路24，使該線路24位於相鄰之垂直接地 層23之間’如第5八圖所示；或該線路^係嵌埋於該第 ❹一介電層22a中’且與該第一介電層仏之表面齊平，如 第5B圖所示；或該線路24係跨越該第一介電層22&及第 二介電層22b之間的界面22c，而後埋於該第一介電層他 及第二介電層22b之中’如第5C圖所示；又該第二水平 接地層25係嵌埋於該第二介電層22b中，且與該第二介 電層22b表面齊平，並電性連接該至少一對之垂直接：層 23。 日 又該水平延伸接地層21，之寬度wl等於兩相鄰之垂 直接地層23之間的寬度w2;該第二水平接地層25之寬 110868 13 200952574 · /又…丁此兩相鄰之垂直接地層23之間的寬度w2。 [弟五貫施例] 凊芬閱第6A至6C圖，係為本發明電路板第五實施例 之職圖，與前述之各實施例之不同處在於該第一介電層 及第二介電層所組成之介電層中垂直設有至少一對之垂 直接地層。 本發明之電路板，係於該承載板20上設有第-介電 層22a及第二介電層挪所組成之介電層22，其中，該 第”电層22a及第二介電層22b係為相同或不相同之材 質於°亥第一介電層22a及第二介電層22b中垂直設有至 =對之垂直接地層23,於該第—介電層他上設有至 =線路24，使該線路24位於相鄰之垂直接地層之 日’如第6A圖所示；或該線路24係丧埋於該第一介電層 =1’且與該第一介電層22a之表面齊平，而能有效控 形广乂形成細間距線路，如第6 B圖所示；或該 ❹越該第—介電層^及第二介電層22b之間 ® f而联埋於該第一介電層22a及第二介電層挪 …，峡位於該二電 之厚度尺寸係為相及 電層挪中 了係為相同或不同，如第6D圖所示。 設於電路板’係將該至少-對之垂直接地層垂直 位於；丨* S ，以及至少一線路係設於該介電層内部，且 之垂直接地層之間；或至少-對之垂直接 “、垂直没於介電層中並電性連接該第一水平接地 110868 14 200952574 層，以及至少一線路係設於該介電層内部，且位於該至少 -對之垂直接地層之間，俾以提高遮蔽效果，以降低外界 電磁波之干擾；又該至少一對之第一水平接地層連接成 一體，以進一步包覆該些線路；又於該介電層上形成有第 =水平接地層，以完整包覆該些線路，而能更完整提供遮 蔽效果，以避免外界電磁波干擾該些線路。 上述貫施例係用以例示性說明本發明之原理及其功 欵，而非用於限制本發明。任何熟習此項技藝之人士均可 ®在不違背本發明之精神及範疇下，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範 園所列。 【圖式簡單説明】 第1A及1B圖係分別顯示習知具遮蔽結構之電路板剖 視示意圖； 第2A至2D圖係為本發明之電路板的第一實施例剖視 _示意圖； 第3A至3C圖係為本發明之電路板的第二實施例剖視 示意圖； 第3A’圖係為第3A圖之另一實施例剖視示意圖； 第3B’圖係為第3B圖之另一實施例剖視示意圖； 第3C’圖係為第3C圖之另一實施例剖視示意圖； 第4A至4C圖係為本發明之電路板的第三實施例剖視 示意圖； 第5A至5C圖係為本發明之電路板的第四實施例剖視 15 110868 200952574 示意圖；以及 第6A至6D圖係為本發明之電路板的第五實施例剖視 示意圖。 【主要元件符號說明】 10、20 承載板 11、23、23a、23b、23c 垂直接地層 11a 弟'~接地層 lib 弟—接地層 ❹ 12 、 22 介電層 12a ' 22a 第一介電層 12b 、 22b 第一介電層 13、24 線路 21 、 21a 、 21b 第一水平接地層 21， 水平延伸接地層 22c 界面 25 弟二^ ll, EL ❹ wl 、 w2 、 w3 * 卞丁银地層 寬度 110868 16The second dielectric layer 22b is as shown in FIG. 4C; and on the second dielectric layer 22b: a second horizontal ground layer 25 is electrically connected to the at least one pair of vertical ground layers 23, such as 4A; the second horizontal ground layer 25 is buried in the second dielectric layer 22b, and is flush with the surface of the second dielectric layer 22b, and electrically connected to the at least one pair The direct formation 23 is as shown in Figures 4B and 4C. Further, the width w3 of the second horizontal ground layer 25 is greater than the width W2 between the adjacent vertical ground layers 23. [Fourth Embodiment] 12 110868 200952574 Please refer to FIGS. 5A to 5C, which is a cross-sectional view of a fourth embodiment of the circuit board of the invention, which is the same as the foregoing embodiment. The horizontal extension layer is embedded in the carrier plate and is flush with the surface of the carrier; and the visibility of the horizontally extending ground layer and the second horizontal grounding layer is equal to two adjacent The width between the vertical ground planes. The circuit board of the invention is provided with a horizontally extending connection layer 21'' in the carrier board 20, and the horizontally extending grounding layer 21 is buried in the carrier board 2, and extends horizontally on the carrier board 20 The ground layer 21 is covered with a dielectric layer 22 composed of a first dielectric layer 22a and a second dielectric layer 22b, and the upper surface of the horizontally extending ground layer 21' and the carrier board 2 The interface between the first dielectric layer 22a and the second dielectric layer 22b are provided with at least a pair of vertical ground layers 23, and corresponding to the electrical connection. The ground layer 21 is further recognized on the first dielectric layer & to the line 24 such that the line 24 is located between the adjacent vertical ground layers 23 as shown in FIG. 5; or the line ^ Embedded in the first dielectric layer 22a' and flush with the surface of the first dielectric layer, as shown in FIG. 5B; or the line 24 spans the first dielectric layer 22& The interface 22c between the second dielectric layer 22b is buried in the first dielectric layer and the second dielectric layer 22b as shown in FIG. 5C; and the second horizontal ground layer 25 is further The second dielectric layer 22b is embedded in the second dielectric layer 22b and is flush with the surface of the second dielectric layer 22b, and electrically connected to the at least one pair of vertical layers: layer 23. The horizontally extending ground layer 21 has a width w1 equal to the width w2 between two adjacent vertical ground layers 23; the width of the second horizontal ground layer 25 is 110868 13 200952574 · /... The width w2 between the direct formations 23 is. The fifth embodiment of the present invention is a diagram of the fifth embodiment of the circuit board of the present invention. The difference from the foregoing embodiments lies in the first dielectric layer and the second dielectric layer. At least one pair of vertical ground layers are vertically disposed in the dielectric layer formed by the electrical layer. The circuit board of the present invention is provided with a dielectric layer 22 composed of a first dielectric layer 22a and a second dielectric layer on the carrier board 20, wherein the first electrical layer 22a and the second dielectric layer 22b is the same or different material. The first dielectric layer 22a and the second dielectric layer 22b are vertically disposed to the vertical ground layer 23, and the first dielectric layer is provided on the first dielectric layer. = line 24, such that the line 24 is located on the adjacent vertical ground plane 'as shown in FIG. 6A; or the line 24 is buried in the first dielectric layer = 1' and the first dielectric layer The surface of 22a is flush, and can effectively control the shape to form a fine pitch line, as shown in FIG. 6B; or the intersection between the first dielectric layer and the second dielectric layer 22b. Buried in the first dielectric layer 22a and the second dielectric layer ..., the gorge is located in the thickness of the second electrical system is the same or different in the phase and electrical layer, as shown in Figure 6D. The circuit board 'is located at least perpendicular to the vertical ground plane; 丨* S , and at least one line is disposed inside the dielectric layer and between the vertical ground layers; or at least-paired vertically ", vertically not in the dielectric layer and electrically connected to the first horizontal ground 110868 14 200952574 layer, and at least one line is disposed inside the dielectric layer and between the at least - pair of vertical ground layers, To improve the shielding effect to reduce the interference of external electromagnetic waves; and the at least one pair of first horizontal ground layers are integrally connected to further cover the lines; and the first horizontal ground layer is formed on the dielectric layer. By completely covering the lines, the shielding effect can be more completely provided to avoid external electromagnetic waves from interfering with the lines. The above-described embodiments are intended to illustrate the principles of the invention and its advantages, and are not intended to limit the invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as listed in the patent application section described later. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B are schematic cross-sectional views showing a conventional circuit board with a shield structure; FIGS. 2A to 2D are cross-sectional views of a first embodiment of the circuit board of the present invention; FIG. 3A 3C is a schematic cross-sectional view of a second embodiment of the circuit board of the present invention; FIG. 3A' is a cross-sectional view of another embodiment of FIG. 3A; and FIG. 3B' is another embodiment of FIG. 3B 3C' is a schematic cross-sectional view of another embodiment of the circuit board of FIG. 3; FIGS. 4A to 4C are schematic cross-sectional views of a third embodiment of the circuit board of the present invention; FIGS. 5A to 5C are diagrams A cross-sectional view of a fourth embodiment of the circuit board of the present invention is shown in FIG. 15 110868 200952574; and FIGS. 6A to 6D are cross-sectional views showing a fifth embodiment of the circuit board of the present invention. [Main component symbol description] 10, 20 carrier board 11, 23, 23a, 23b, 23c vertical ground layer 11a 弟 '~ ground layer lib brother - ground layer ❹ 12, 22 dielectric layer 12a ' 22a first dielectric layer 12b 22b first dielectric layer 13, 24 line 21, 21a, 21b first horizontal ground layer 21, horizontally extending ground layer 22c interface 25 brother ll, EL ❹ wl, w2, w3 * 卞丁银地层110868 16