200945456200945456
1 w irA 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種覆晶封裝方法，且特別是有關於 一種提高基板使用率之覆晶封裝方法。 【先前技術】 在科技日新月異的世代，利用積體電路元件所組成的 電子產品，已成為現代人日常生活中不可或缺的工具。隨 ® 著電子產品邁向輕薄短小之設計的潮流，半導體封裝技術 也相對地開發出許多高密度之半導體封裝的形式，例如覆 晶封裝件。 覆晶封裝製程中需要形成底膠於晶片與基板之間。然 而當晶片很薄或面積較大時，很容易發生溢膠問題。而溢 出的膠會污染鄰近晶片的銲墊，導致鄰近晶片之銲墊在隨 後的打線作業時，金線不易固定於被污染的銲墊上。而 且，近來客戶要求晶片尺寸日益縮小，使得晶片與鄰近晶 ® 片的銲墊之間的距離跟著配合縮短，因此導致溢出的底膠 更容易污染到鄰近晶片的銲墊。 【發明内容】 有鑑於此，本發明就是在提供一種覆晶封裝方法，於 開始形成底膠之處與鄰近晶片之銲墊之間形成一溝槽，當 底膠之溢膠發生時，溢膠會先填充溝槽内的空間而不會流 至鄰近晶片之銲墊，因此降低了污染鄰近晶片之銲墊的機 5 200945456 » ? * ~f ✓ a a i ^ 會，並且提高鄰近晶片於打線作業之成功率，以提高產品 良率並降低成本。並且，由於溝槽的形成，也使得晶片間 的距離可以拉近而不會有銲墊遭受底膠之溢膠污染的問 題，因此相同基板面積可以容納較多的晶片，使得基板使 用率提升。 根據本發明之一方面，提出一種覆晶封裝方法，包括 提供一基板，基板具有一切割道；形成〆絕緣層於基板 罄上，絕緣層具有一溝槽，溝槽係位於切割道上；將一晶片 δ又置於基板上，晶片之設置位置係位於溝槽之一侧且鄰近 於溝槽，晶片係以覆晶接合之方式電性連接於基板；以 及，從鄰近切割道之晶片之一侧開始形成一底膠於晶片與 基板之間。 為讓本發明之上述内容能更明顯易懂，下文特舉一較 佳實施例，並配合所附圖式，作詳細說明如下： ©【實施方式】 本發明提出一種覆晶封裝方法，包括提供一基板，基 板具有一切割道；形成一絕緣層於基板上，絕緣層具有一 溝槽’溝槽係位於切割道上；將—晶片設置於基板上，晶 片之设置位置係位於溝槽之一側且鄰近於溝槽，晶片係以 覆曰曰接S之方式電性連接於基板；以及，從鄰近切割道之 晶片之一側開始形成一底膠於晶片與基板之間。當底膠之 溢膠發生時，溢膠會先填充溝槽内空間而不會流至鄰近晶 片之銲墊，因此降低了污染鄰近晶片之銲墊的機會。以下 6 200945456 i νν**-?^ΙΓ/Λ. 係舉出較佳實施例做詳細說明，然此實施例僅為本發明 之發明精神下的幾種實施方式之一，其說明之文字與圖示 並不^對本發明之欲保護範®進行限縮。 5月參照第1圖’其繪示依照本發明較佳實施例之覆晶 封裝方法之流程圖。覆晶封裝方法包括以下步驟。首先， 請同時參照第2Α圖及第2Β ®，第2Α ®繪示本實施例之 基板之俯視圖’第2Β圖繪示第2Α圖中基板之前視圖。於 步驟102中’提供一基板202,基板202具有一切割道204。 • 接著’請同時參照第3Α圖及第3Β圖，第3Α圖繪示 本實施例之形成有絕緣層與銲墊之基板之俯視圖，第3Β 圖繪示第3Α圖中基板沿著ια-1Α，之剖視圖。於步驟104 中’形成一絕緣層206於基板202上’絕緣層206具有一 溝槽208 ’溝槽208係位於切割道204上。其中，絕緣層 2〇6係包括綠漆、隔離層、abf介電層（Ajinomoto Build-up film)或其它介電材質。溝槽2〇8之寬度係可以小於或等於 切割道204之寬度，溝槽208之長度係可小於或等於切割 Φ 道204之長度’本實施例係以溝槽208之寬度與長度分別 小於切割道204之寬度與長度為例作說明。另外，於本步 驊中’覆晶封裝方法更包括形成多個銲墊214於基板202 上’溝槽208例如係以一曝光顯影技術形成，溝槽208可 以在形成絕緣層2〇6中對應至銲墊214的開口 213之製程 中一併完成。因此，溝槽之形成是相當簡單的，而且不會 額外增加製程成本。 另外’溝槽208所形成的凹陷空間吸收了基板202在 7 200945456 1 TtHjy vrt\ 後續製程中因加熱動作所產生的熱膨脹量，使得基板202 整體之翹曲量（Warpage)降低，因此提升了覆晶封裝件的製 程良率。 然後’請同時參照第4A圖及第4B圖，第4A圖繪示 本實施例之設置有晶片之基板之俯視圖，第4B圖繪示第 4A圖中基板沿著1Β·1Β’之剖視圖。於步驟106中，將一 晶片210設置於基板202上，晶片210之設置位置係位於 溝槽208之一侧且鄰近於溝槽208，晶片210係以覆晶接 ® 合之方式電性連接於基板202。此外，晶片210更具有多 個錫球211，晶片210係藉由錫球211與基板202電性連 接。此外，於本步驟中，亦可形成另一晶片212於基板 202上，晶片210與晶片212係分別位於切割道204之兩 側。晶片212可以直接設置於基板202上或是堆疊在覆晶 式晶片上，本實施例係以堆疊在覆晶式晶片215之形式為 例作說明。基板202上具有的銲墊214係用以與晶片212 電性連接，電性連接的方式係可採用打線技術完成’為了 ® 使金線的長度適中，銲墊214係形成於切割道2〇4與晶片 212之間。 然後，請同時參照第5圖其繪示本實施例之形成底膠 時之基板之俯視圖。於步驟108中，從鄰近切割道204之 晶片210之一側219開始形成底膠216於晶片21〇與基板 202之間，當底膠216開始被放置於鄰近於晶片21〇之一 側219時’藉由虹吸原理，底膠216會慢慢被吸入晶片210 與基板202之間。其中，形成底膝216的方式係$採用1 w irA IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a flip chip packaging method, and more particularly to a flip chip packaging method for improving substrate utilization. [Prior Art] In the ever-changing generation of technology, electronic products made up of integrated circuit components have become an indispensable tool in modern people's daily lives. With the trend of electronic products moving toward thin and light designs, semiconductor packaging technology has also relatively developed many high-density semiconductor package forms, such as flip-chip packages. In the flip chip packaging process, it is necessary to form a primer between the wafer and the substrate. However, when the wafer is thin or large, the problem of overflowing is easy to occur. The spilled glue will contaminate the pads of adjacent wafers, causing the pads adjacent to the wafer to be less likely to be attached to the contaminated pads during subsequent wire bonding operations. Moreover, recently, customers have been demanding a shrinking wafer size, which has shortened the distance between the wafer and the pads of adjacent wafers, thus causing the overflow primer to more easily contaminate the pads adjacent to the wafer. SUMMARY OF THE INVENTION In view of the above, the present invention provides a flip chip packaging method, forming a trench between a pad and a pad adjacent to a wafer at the beginning of forming a primer, and overflowing when the glue of the primer occurs. The space in the trench will be filled first without flowing to the pad of the adjacent wafer, thereby reducing the contamination of the adjacent pad by the machine 5 200945456 » ? * ~f ✓ aai ^ and increasing the proximity of the wafer to the wire bonding operation Success rate to increase product yield and reduce costs. Moreover, due to the formation of the grooves, the distance between the wafers can be made close without the problem that the pads are contaminated by the glue of the primer, so that the same substrate area can accommodate more wafers, so that the substrate utilization rate is improved. According to an aspect of the present invention, a flip chip packaging method is provided, comprising: providing a substrate having a dicing street; forming a 〆 insulating layer on the substrate ,, the insulating layer having a trench, the trench being located on the scribe line; The wafer δ is again placed on the substrate, the wafer is disposed on one side of the trench and adjacent to the trench, and the wafer is electrically connected to the substrate by flip chip bonding; and, from one side of the wafer adjacent to the dicing street A primer is initially formed between the wafer and the substrate. In order to make the above description of the present invention more comprehensible, a preferred embodiment will be described below in detail with reference to the accompanying drawings. a substrate having a dicing street; forming an insulating layer on the substrate, the insulating layer having a trench groove on the scribe line; and the wafer being disposed on the substrate, the wafer being disposed on one side of the trench And adjacent to the trench, the chip is electrically connected to the substrate by means of a cover S; and a primer is formed between the wafer and the substrate from one side of the wafer adjacent to the scribe line. When the glue overflow occurs, the overflow will fill the space inside the trench without flowing to the pads of the adjacent wafer, thus reducing the chance of contaminating the pads of adjacent wafers. The following 6 200945456 i νν**-?^ΙΓ/Λ. exemplifies the preferred embodiment, but this embodiment is only one of several embodiments of the inventive spirit of the present invention, The illustration does not limit the intended protection of the present invention. A flow chart of a flip chip packaging method in accordance with a preferred embodiment of the present invention is shown in FIG. The flip chip packaging method includes the following steps. First, please refer to Fig. 2 and Fig. 2, and Fig. 2 shows a plan view of the substrate of the present embodiment. Fig. 2 is a front view of the substrate in Fig. 2 . In step 102, a substrate 202 is provided, and the substrate 202 has a dicing street 204. • Next, please refer to the 3rd and 3rd drawings at the same time. The third drawing shows the top view of the substrate with the insulating layer and the bonding pad formed in this embodiment, and the third drawing shows the substrate along the ια-1 in the third drawing. , the cross-sectional view. In step 104, an insulating layer 206 is formed on the substrate 202. The insulating layer 206 has a trench 208' in which the trench 208 is located on the scribe line 204. The insulating layer 2〇6 includes a green lacquer, a spacer layer, an abf dielectric layer (Ajinomoto Build-up film) or other dielectric material. The width of the trenches 2〇8 may be less than or equal to the width of the dicing streets 204, and the length of the trenches 208 may be less than or equal to the length of the Φ-cut dies 204. In this embodiment, the width and length of the trenches 208 are respectively smaller than the length of the trenches 208. The width and length of the track 204 are exemplified. In addition, in the present step, the flip chip packaging method further includes forming a plurality of pads 214 on the substrate 202. The trench 208 is formed by, for example, an exposure and development technique, and the trench 208 may be formed in the insulating layer 2〇6. The process is completed in the process of opening 213 of the pad 214. Therefore, the formation of the trench is relatively simple and does not add additional process cost. In addition, the recessed space formed by the trench 208 absorbs the amount of thermal expansion of the substrate 202 due to the heating action in the subsequent process of 7 200945456 1 TtHjy vrt\, so that the warpage of the substrate 202 is reduced, thereby improving the coverage. Process yield of the crystal package. Then, please refer to FIG. 4A and FIG. 4B at the same time. FIG. 4A is a plan view showing the substrate on which the wafer is disposed in the embodiment, and FIG. 4B is a cross-sectional view showing the substrate in FIG. 4A along 1Β·1Β. In step 106, a wafer 210 is disposed on the substrate 202. The wafer 210 is disposed on one side of the trench 208 and adjacent to the trench 208. The wafer 210 is electrically connected to the wafer. Substrate 202. In addition, the wafer 210 further has a plurality of solder balls 211, and the wafer 210 is electrically connected to the substrate 202 by the solder balls 211. In addition, in this step, another wafer 212 may be formed on the substrate 202, and the wafer 210 and the wafer 212 are respectively located on both sides of the dicing street 204. The wafer 212 may be disposed directly on the substrate 202 or stacked on the flip chip. This embodiment is described by way of example in the form of a flip chip 215. The pad 214 is provided on the substrate 202 for electrically connecting to the wafer 212. The electrical connection can be done by wire bonding technology. In order to make the length of the gold wire moderate, the pad 214 is formed on the cutting channel 2〇4. Between the wafer 212 and the wafer 212. Then, referring to Fig. 5, a plan view of the substrate in the case of forming the primer in the embodiment is shown. In step 108, a primer 216 is formed between the wafer 21A and the substrate 202 from one side 219 of the wafer 210 adjacent the scribe line 204, when the primer 216 begins to be placed adjacent to one side 219 of the wafer 21 By the principle of siphoning, the primer 216 is slowly drawn between the wafer 210 and the substrate 202. Among them, the way to form the bottom knee 216 is $
S 200945456 1 VV U 7 11··Γν 喷射（Jetting)方式或點膠方式（Dispensing or No-Flow)。 在不形成溝槽的情況下，於形成底膠的過程當中， 假如有溢膠產生，則溢膠將可能污染到銲墊。請參照第 6 A圖，其繪示不形成溝槽時，溢膠分佈之示意圖。當絕 緣層206不具溝槽時，底膠之一溢膠221因為沒有溝槽 可以被容納，所以只能順勢流至鄰近晶片，例如是晶片 212，之銲墊214上，而使銲墊214受到汙染。因此導致 在後續的打線作業中，金線無法穩固地黏著於銲墊214 • 上。在這種情況下，則必需加大晶片210與銲墊214的 間距來降低銲墊214受到汙染的機率。如此，將會浪費 基板202之可使用的空間。 於形成底膠的過程當中，如果有溢膠產生的話，本 實施例將可有效地使溢膠避免污染到鄰近晶片之銲墊。 請參照第6B圖，其繪示本實施例之形成有凹槽之覆晶 封裝方法之溢膠分佈示意圖。底膠216之一溢膠218會 先流進溝槽208之空間内，而避免了溢膠218流至銲墊 ® 214而污染銲墊214，如此，晶粒210與銲墊214的間距 不需加大，因此而節省基板202之可使用的空間。 此外，為了電性連接晶片212與銲墊214,於步驟108 後，覆晶封裝方法更可包括形成多條金線217之步驟。請 參照第7A圖及第7B圖，第7A圖繪示本實施例之形成有 多條金線之基板之俯視圖，第7B圖繪示第7A圖中基板沿 者1C-1C’之剖視圖。藉由打線作業，形成多條金線217連 接晶片212與銲墊214,以使晶片212經由金線217與銲 9 200945456 墊214電性連接。 此外，於步驟108後，覆晶封裝方法更可包括沿著切 割道204切割基板202，以形成覆晶封裴件22〇之步驟。 請參照第8圖’其繪示本實施例之覆晶封裝件之示音圖。 使用一切割刀222切割基板202後，形成覆晶封裝件22〇 及224’其中’為了保護金線217免於受潮及外物侵蝕， 在切割前以封膠226覆蓋晶片212及金線217。 此外’在切割過程中’由於絕緣層2〇6的質地較軟， • 在切割完後很容易在邊緣形成毛邊。然而，由於溝槽的 形成，使得具有溝槽之切割道所具有的絕緣層成份相較 於不具有溝槽之切割道所具有的絕緣層成份還少，當絕 緣層的成份較少時，切割後的覆晶封裝件所殘留的毛邊 也自然地變得較少。如此，有助於覆晶封震件成品品質的 提升。 在打線作業中’為了使金線能夠穩固^於鋒墊214 ❹上，銲墊須保持潔淨，不能夠有雜質在銲整上，否則金線 墊上。若銲墊污染過於嚴重，例如是底膠2;6 2膠^至鲜墊214上（如第6A圖所示），甚 打線的不良問題。所以本實施例之溝槽之形成，= 之溢膠218發生時，溢膝218會先填充溝槽: 間而不會流至銲塾214上，因此降低了污染銲塾叫 的機會，使後續的打線作業中的金線217，可 。此外’由於溝槽的形成，使得:膠的區 域範圍也可以被控制的較小，晶片間的距離得以拉近，以 200945456 1 vv j y l rH. 使基板容納更多的晶片而提高基板的使用率。 請參照第9圖，其繪示本實施例之溝槽之另一結構 之示意圖。絕緣層302具有多個溝槽304，溝槽304係位 於切割道306上。本發明之覆晶封裝方法所形成的溝槽並 不侷限第1圖之溝槽形式，溝槽的分佈係可隨著覆晶封裝 件於基板上的分佈方式而配合變更。因此，多種溝槽的配 置方式增加了製程的規劃彈性。 此外，溝槽的尺寸可以配合底膠量調整，例如，底膠 ❿ 量因配合產品尺寸而需要較多時，溝槽的尺寸則可以配合 形成容積較大的溝槽以容納更多的溢膠量。如此，使得溢 膠的區域範圍仍可以被控制的較小。 本發明上述實施例所揭露之覆晶封裝方法，具有多項 優點，以下僅列舉部分優點說明如下： 1)溝槽之形成，使得鄰近晶片之銲墊受到底膠污染的 機率降低，提高了後續打線作業之成功率及確保打線品 質。 ® 2)溝槽的形成，使得溢膠的區域範圍可以縮小，因此 晶片間的距離得以縮短，使得相同的基板面積可以容納更 多尺寸較小的晶粒。因此提高了基板的使用率。 3) 溝槽之形成，使得質地較軟的絕緣層數量減少，在 基板切割成覆晶封裝件後，覆晶封裝件的切割邊緣所殘留 的毛邊也減少了，因此提升了覆晶封裝件的成品品質。 4) 溝槽之形成，使得基板翹曲量降低，因此提升了覆 晶封裝件的製程良率。 200945456 綜上所述，雖然本發明已以一較佳實施例揭露如上， 然其並非用以限定本發明。本發明所屬技術領域中具有通 常知識者，在不脫離本發明之精神和範圍内，當可作各種 之更動與潤飾。因此，本發明之保護範圍當視後附之申請 專利範圍所界定者為準。S 200945456 1 VV U 7 11··Γν Jetting method or Dispensing or No-Flow. In the case where no groove is formed, if a glue is generated during the process of forming the primer, the glue may contaminate the pad. Please refer to FIG. 6A, which shows a schematic diagram of the overflow distribution when no groove is formed. When the insulating layer 206 has no grooves, one of the primers 221 can be accommodated because there is no groove, so it can only flow to the adjacent wafer, for example, the wafer 212, the pad 214, and the pad 214 is subjected to Pollution. As a result, the gold wire cannot be firmly adhered to the pad 214 in the subsequent wire bonding operation. In this case, it is necessary to increase the distance between the wafer 210 and the pad 214 to reduce the probability of contamination of the pad 214. As such, the usable space of the substrate 202 will be wasted. In the process of forming the primer, if there is overflow gel, the embodiment can effectively prevent the overflow glue from contaminating the pads of adjacent wafers. Please refer to FIG. 6B, which illustrates a schematic diagram of the overflow distribution of the flip chip flip chip forming method of the present embodiment. An overflow 218 of the primer 216 first flows into the space of the trench 208, and prevents the overflow 218 from flowing to the pad® 214 to contaminate the pad 214. Thus, the spacing between the die 210 and the pad 214 is not required. This increases, thereby saving space available for the substrate 202. In addition, in order to electrically connect the wafer 212 and the pad 214, after the step 108, the flip chip packaging method may further include the step of forming a plurality of gold wires 217. Referring to FIGS. 7A and 7B, FIG. 7A is a plan view showing a substrate on which a plurality of gold wires are formed in the embodiment, and FIG. 7B is a cross-sectional view showing the substrate edge 1C-1C' in FIG. 7A. A plurality of gold wires 217 are connected to the wafer 212 and the pad 214 by wire bonding to electrically connect the wafer 212 to the pad 214 via the gold wire 217. In addition, after step 108, the flip chip packaging method may further include the step of cutting the substrate 202 along the dicing street 204 to form the flip chip 22 〇. Please refer to FIG. 8 for a sound diagram of the flip chip package of the embodiment. After the substrate 202 is cut using a dicing blade 222, the flip chip packages 22 and 224' are formed to protect the gold wire 217 from moisture and foreign matter, and the wafer 212 and the gold wire 217 are covered with the sealant 226 before cutting. In addition, the thickness of the insulating layer 2〇6 is soft during the cutting process. • It is easy to form a burr at the edge after cutting. However, due to the formation of the grooves, the scribe lines having the grooves have less insulating layer composition than the etched lines having no grooves, and when the insulating layer has less composition, the cutting is performed. The burrs remaining in the subsequent flip chip package also naturally become less. In this way, it contributes to the improvement of the quality of the finished product of the crystal sealing device. In the wire-laying operation, in order to make the gold wire stable on the front pad 214, the pad must be kept clean and there should be no impurities on the soldering, otherwise the gold wire pad. If the soldering pad is too polluted, for example, the primer 2; 6 2 glue to the fresh pad 214 (as shown in Figure 6A), the problem of the wire is poor. Therefore, when the groove of the embodiment is formed, when the overflow glue 218 occurs, the overflow knee 218 will fill the groove first: and will not flow to the welding 214, thereby reducing the chance of contaminating the welding squeak and making subsequent The gold line 217 in the line work can be. In addition, due to the formation of the grooves, the area of the glue can also be controlled to be small, and the distance between the wafers can be narrowed to increase the substrate usage by allowing the substrate to accommodate more wafers at 200945456 1 vv jyl rH. . Referring to Figure 9, a schematic view of another structure of the trench of the embodiment is shown. The insulating layer 302 has a plurality of trenches 304 that are located on the scribe lines 306. The trench formed by the flip chip packaging method of the present invention is not limited to the trench pattern of Fig. 1, and the distribution of the trench can be changed in accordance with the manner in which the flip chip package is distributed on the substrate. Therefore, the configuration of the various grooves increases the planning flexibility of the process. In addition, the size of the groove can be adjusted according to the amount of the primer. For example, when the amount of the bottom rubber is required to match the size of the product, the size of the groove can be matched to form a groove having a larger volume to accommodate more overflow. the amount. In this way, the area of the overflow can still be controlled to be small. The flip chip packaging method disclosed in the above embodiments of the present invention has a plurality of advantages. The following only some of the advantages are described as follows: 1) The formation of the trenches reduces the probability of contamination of the pads adjacent to the wafer by the primer, and improves the subsequent bonding. The success rate of the work and the quality of the wire. ® 2) The formation of the grooves allows the area of the overflow to be reduced, so the distance between the wafers is shortened, so that the same substrate area can accommodate more small-sized grains. Therefore, the use rate of the substrate is improved. 3) The formation of the trenches reduces the number of layers of the softer insulating layer. After the substrate is cut into the flip chip package, the remaining edges of the chip edge of the flip chip package are also reduced, thereby improving the flip chip package. Finished product quality. 4) The formation of the trenches reduces the amount of warpage of the substrate, thereby improving the process yield of the flip chip package. In conclusion, the present invention has been disclosed above in a preferred embodiment, and is not intended to limit the invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
12 200945456 【圖式簡單說明】 第1圖繪示依照本發明較佳實施例之覆晶封裝方法 之流程圖。 第2A圖繪示本實施例之基板之俯視圖。 第2B圖繪示第2A圖中基板之前視圖。 第3A圖繪示本實施例之形成有絕緣層與銲墊之基板 之俯視圖。 第3B圖繪示第3A圖中基板沿著1A-1A’之剖視圖。 • 第4A圖繪示本實施例之設置有晶片之基板之俯視 圖。 第4B圖繪示第4A圖中基板沿著1B-1B’之剖視圖。 第5圖繪示本實施例之形成底膠時之基板之俯視圖。 第6A圖繪示不形成溝槽時，溢膠分佈之示意圖。 第6B圖繪示本實施例之形成有凹槽之覆晶封裝方 法之溢膠分佈示意圖。 第7A圖繪示本實施例之形成有多條金線之基板之俯 視圖。 第7B圖繪示第7A圖中基板沿者1C-1C’之剖視圖。 第8圖繪示本實施例之覆晶封裝件之示意圖。 第9圖繪示本實施例之溝槽之另一結構之示意圖。 13 200945456 _ ____ 【主要元件符號說明】 202 :基板 204、306 :切割道 206、302 :絕緣層 208、304 :溝槽 210、212 :晶片 211 :錫球 213 :開口12 200945456 [Simple Description of the Drawings] FIG. 1 is a flow chart showing a flip chip packaging method in accordance with a preferred embodiment of the present invention. FIG. 2A is a plan view showing the substrate of the embodiment. FIG. 2B is a front view of the substrate in FIG. 2A. Fig. 3A is a plan view showing the substrate on which the insulating layer and the pad are formed in the embodiment. Fig. 3B is a cross-sectional view of the substrate taken along line 1A-1A' in Fig. 3A. • Fig. 4A is a plan view showing the substrate on which the wafer is provided in the embodiment. Fig. 4B is a cross-sectional view of the substrate taken along line 1B-1B' in Fig. 4A. Fig. 5 is a plan view showing the substrate in the form of a primer in the embodiment. FIG. 6A is a schematic view showing the distribution of the overflow gel when no groove is formed. Fig. 6B is a schematic view showing the distribution of the overflow gel of the flip chip forming method of the present embodiment. Fig. 7A is a plan view showing the substrate on which a plurality of gold wires are formed in the embodiment. Fig. 7B is a cross-sectional view showing the substrate edge 1C-1C' in Fig. 7A. FIG. 8 is a schematic view showing the flip chip package of the embodiment. FIG. 9 is a schematic view showing another structure of the trench of the embodiment. 13 200945456 _ ____ [Main component symbol description] 202: Substrate 204, 306: dicing street 206, 302: insulating layer 208, 304: trench 210, 212: wafer 211: solder ball 213: opening
214 :銲墊 215 :覆晶式晶片 216 :底膠 217 :金線 218、221 :溢膠 219 : —側 220、224 :覆晶式晶片 222 :切割刀 226 :封膠214: solder pad 215: flip chip 216: primer 217: gold wire 218, 221: overflow glue 219: - side 220, 224: flip chip 222: cutting blade 226: sealant