200945049 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種對依時間分割而共享位址與資料的 • ADMUX記憶體（以下簡稱「記憶體」）進行控制的記憶體控制 • 裝置。 【先前技術】 圖1 1係表示δ己憶體與§己憶體控制襄置之柄接構成的第1 ❹ 習知例。如圖11所示，於記憶體控制裝置（110)耦接有記憶 體0(130)與記憶體1(140)。在本例中，分別具備有二組必 要之全部信號（例如參照專利文獻1)。 例如： 記憶體控制裝置（110)的CLKO(lll)耦接於記憶體0(130)的 CLKC131)； 記憶體控制裝置（110)的CLK1(121)搞接於記憶體i(i4〇)的 ❹ CLKC141); 記憶體控制裝置（110)的NADV0(112)耦接於記憶體〇(130) 的 NADVC132); ’ 記憶體控制裝置（110)的NADV1C122)耦接於記憶體1(140) ' 的 NADVC142); 記憶體控制裝置（110)的NCS0C113)耦接於記憶體0(130)的 NCSC133)； 記憶體控制裝置（110)的NCS1(123)耦接於記憶體1(140)的 098110826 3 200945049 NCSC143); 記憶體控制裝置（110)的NOEOC114)耦接於記憶體0(130)的 NOEC134); 記憶體控制裝置（11〇)的NOE1C124)耦接於記憶體1(140)的 NOS(144); 記憶體控制裝置（110)的NWE0C115)耦接於記憶體0(130)的 NWE(135)； 記憶體控制裝置（110)的NWE1(125)耦接於記憶體1(140)的 NWEC145); :〇](417)耦接於記憶體 :〇](427)耦接於記憶體 :〇](416)耦接於記憶體 :〇](426)耦接於記憶體 記憶體控制裝置（110)的A0[11 0(130)的 A[26 : 16](137); 記憶體控制裝置（110)的Al[ll 1(140)的 A[26 : 16](147); 記憶體控制裝置（110)的D0[15 0(130)的 D[15 : 0](136); 記憶體控制裝置（110)的Dl[15 1(140)的 D[15 : 0](146)。 圖12係表示記憶體與記憶體控制裝置之耦接構成的第2 習知例。如圖12所示’第2習知例中，晶片選擇信號 NCSC113、123)以外的記憶體控制裝置（11〇)之cLKO(lll)、 NADVO(112)、NOEO(114)、NWEO(115)、A[11: 1](417)、D[15 : 0](416) ’均共享耦接於記憶體〇(13〇)與記憶體1(14〇)。 098110826 4 200945049 例如： 記憶體控制裝置（110)的CLKO(lll)耦接於記憶體0(130)的 CLKC131)與記憶體 1(140)的 CLKC141); 記憶體控制裝置（110)的NADV0C112)耦接於記憶體0(130) - 的 NADV(132)與記憶體 1(140)的 NADV(142); 記憶體控制裝置（110)的NOEO(114)耦接於記憶體0(130)的 N0EC134)與記憶體 1(140)的 N0EC144); ❹ 記憶體控制裝置（110)的NWE0C115)耦接於記憶體0(130)的 NWEC135)與記憶體 1(140)的丽E(145); 記憶體控制裝置（110)的A0[11 : 0](417)耦接於記憶體 0(130)的 A[26:6](137)與記憶體 1(140)的 A[26:6](147); 記憶體控制裝置（110)的D0[15 : 0](416)耦接於記憶體 0(130)的 D[15:0](136)與記憶體 1(140)的 D[15:0](146); 記憶體控制裝置（110)的NCS0(113)耦接於記憶體〇(13〇)的 © NCSC133); 記憶體控制裝置（11〇)的NCS1(123)耦接於記憶體kmo)的 NCSC143)。 圖13係第2習知例耦接構成之時序圖一例。此情況，可 將記憶體0(130)與記憶體Κ140)設為各一次地從週期24〇 起記憶體0(130)接受存取，從週期611起記憶體1(14〇)接 受存取。 (專利文獻1)日本專利特開平8_77〇66號公報 098110826 5 200945049 【發明内容】 (發明所欲解決之問題） 近年來，搭載有記憶體控制裝置的LSI、或包含搭載有記 憶體控制裴置的LSI之系統，正朝高功能化演進。在實現此 種搭載有記憶體控制裝置的LSI時，就成本面之要求，必須 將外部輸出入信號線之耦接條數設為最小限度。此外，就性 能面而言’外部記憶體存取的通量大多會成為系統瓶頸。為 了解決此項瓶頸’便設計複數組耦接記憶體所必要之全部信 號線，或除晶片選擇信號以外均共享。但是，外部輸出入^ 號線之耦接條數最小限度化與高通量化係難以兼顧。 本發明目的在於提供-種兼顧信號線之耗接條數的最小 限度化與高通量化的記憶體控制裝置。 (解決問題之手段） 本發明提供一種記憶體控制裝置，係對以時間分割而共享 位址與資料的複數記憶體進行控制之記憶體控制襞置；^第 1記憶體之資料匯流排寬度以上的位址以第2記憶體的資料 匯流排位7C來展現，將上述第2記憶體之資料匯流排寬度以 上的位址以上述第1記憶體的資料匯流排位元來展現，而同 時對上述複數記憶體進行存取。 上述記憶體控制裝置係對上述複數記憶體同時執行讀取 與寫入。 上述S己憶體控制裝置係根據存取類別而變更對上述複數 098110826 〆 200945049 記憶體進行之存取方法。 上述記憶體控制裝置係根據設定暫存器之值而變更對上 述极數記憶體進行之存取方法。 本發明提供一種含有上述記憶體控制裝置的系統。 -本發明提供一種記憶體耦接方法’係將對以時間分割而共 享位址與資料的複數記憶體進行控制之記憶體控制裝置耦 接於上述複數記憶體的記憶體熬接方法；上述記憶體控制裝 ❿置係將第1記憶體之資料匯流排寬度以上的位址以第2記憶 體之資料匯流排位元來展現，將上述第2記憶體之資料匯流 排寬度以上的位址以上述第丨記憶體之資料匯流排位元來 展現，而同時對上述複數記憶體進行存取。 (發明效果） 根據本發明之記憶體控制裝置，可兼顧信號線麵接條數之 最小限度化與高通量化。亦即，相較於習知，可預估到以必 要最小限度之針腳數即可大幅提升性能。又，因為可使用' 有之記憶體，因而不僅LSI，亦可降低系統整體之成本與 現高性能之系統。 ~ 【實施方式】 以下’參照圖式說明本發明之實施形態。 (第1實施形態） 圖 1係表示記憶體與記憶體控制裝置之耦接構成的 實施形態。圖1中，就與圖11相同的構成要件据 第 賦予相同的 098110826 7 200945049 元件符號，而省略說明。另外，圖1中之記憶體〇(13〇)與 記憶體1(140)，為依時間分割而共享位址與資料的時脈同 步型ADMUX記憶體。 於第1實施形態中，如圖1所示’記憶體控制裝置（1 1 〇 ) 之D[31 : 0](116)由如下方式進行輛接。於記憶體〇(13〇) 的八[26:16](137)耦接0[26:16](116)，於〇[15:〇](136) 耦接D[15 : 0](116)。另一方面，於記憶體1(140)的a[26 : 16](147)耦接 D[10:0](116)’於 D[15:0](146)耦接 D[31 : 16](116)。 更進一步，於第1實施形態中， 記憶體控制裝置（110)的CLKO(lll)係耦接於記憶體0(130) 的 CLKC131)與記憶體 1(140)的 CLKC141); 記憶體控制裝置（110)的NADV0C112)係耦接於記憶體〇(13〇) 的 NADVC132); 記憶體控制裝置（11〇)的NADV1(122)係耦接於記憶體1(14〇) 的 NADVC142); s己憶體控制展置（11 〇)的NCS0(113)係輕接於記憶體〇(13〇) 的 NCSC133); 記憶體控制裴置（110)的NCSK123)係耦接於記憶體1(14〇) 的 NCS(143); 記憶體控制裝置（110)的NOEO(114)係耗接於記憶體Q(i3〇) 的 N0E(134); 098110826 〇 200945049 記憶體控制裝置（110)的N0E1(124)係耦接於記憶體1(140) 的 N0SC144); 記憶體控制裝置（110)的NWE0(115)係耦接於記憶體〇(13〇) 的 NWEC135); • 記憶體控制裝置（110)的NWE1C125)係耦接於記憶體1(140) 的 NWS(145)。 當記憶體0(130)與記憶體1(140)的各信號線條數為32 ❹條時，在圖U所示之第1習知例中需要64條信號線，但根 據第1實施形態之耗接構成，以41條信號線即可耦接。 再者’在圖12所示之第2習知例中以33條信號線可進行 耦接，但第2習知例中共享記憶體控制裝置（11〇)的 NCS0C113)及NCS1C123)以外之信號。因此，如表示第2習 知例之時序圖的圖13所示，必須使記憶體〇(13〇)與記憶體 1(140)各一次地接受存取，成為從週期24〇起記憶體〇(13〇) ❹接受存取，從週期611起記憶體1(14〇)接受存取。 圖2為第1實施形態減構成之時序圖第】例。根據第i 實施形態’虽如圖2所示進行存取時，依對記憶體〇(13〇) 設有位址AG⑽）的週期⑽）之下個週期（241)，對記憶體 1(140)設定健A1(251)。若蚊為將記㈣Q(i3_讀取 延遲期（260)與s己憶體1(14〇)的讀取延遲期（2了〇)以元件符 嬈242所不之週期進行輸出，則可將記憶體 0(130)之讀取 貝料（252)與此憶冑1(14Q)之讀取資料（253)同時讀取 098110826 9 200945049 (254)。 如此，在第1實施形態中，抑制信號線之耦接條數，相較 於圖12所示之第2習知例，因為可同時讀取的資料位元寬 度達到2倍，因此可達成約2倍之通量。 圖3為第1實施形態耦接構成之時序圖第2例。如圖3 所示，對記憶體0(130)設定讀取延遲期（36〇)，並對記憶體 1(140)設定寫入延遲期（370)，則來自記憶體〇(〗3〇)的讀取 資料（252)可以符號340所示之週期被讀取。此外，以符號 242所示之週期由記憶體控制裝置（11〇)設定資料（35〇)，藉 此亦可同時進行寫入動作。 (第2實施形態） 於第1實施形態中’僅記憶體控制裝置（110)的D[31 : 0](116)係由5己憶體0(130)與記憶體i(i4〇)所共享，但亦可 以增加共享信號線的形式來實施。圖4為表示記憶體與記憶 體控制裝置之耦接構成的第2實施形態。圖4中，就與圖1 及圖11相同之構成要件賦予相同之元件符號而省略說明。 於第2實施形態中，如圖4所示，以如下方式耦接記憶體 控制裝置（110)之D[31: 〇](116)。於記憶體〇(13〇)之A[26: 16](137)柄接〇[26:16](116)，於〇[15:0](136)耦接0[15: 〇](116)。另一方面，於記憶體 1(14〇)的 a[26 : 16](147) 輕接〇[10:0](116)’於〇[15:0](146)耦接〇[31:16](116)。 更進一步’於第2實施形態中， 098110826 10 200945049 記憶體控制裝置（110)的CLKO(lll)係耦接於記憶體〇(i30) 的 CLKC131)與記憶體 i(i4〇)的 CLKC141); 記憶體控制裝置（11〇)的NCS0C113)係耦接於記憶體〇(13〇) 的 NCS(133)與記憶體 1(140)的 NCSC143); -記憶體控制裝置（11〇)的NOEOU14)係耦接於記憶體〇(13〇) 的 N0EC134)與記憶體 1(140)的 N0EC144); 記憶體控制裝置（110)的NWE0C115)係耦接於記憶體0(i30) ❹ 的 NWEC135)與記憶體 1(140)的 NWEC145)。 再者，記憶體控制裝置（110)的NADV0(112)並非共享而是 耦接於記憶體0(130)的NADVC132); 記憶體控制裝置（110)的NADV1C122)並非共享而是耦接於 記憶體 1(140)的 NADVC142)。 當記憶體0(130)與記憶體1(140)的各信號線條數為32 條時’在圖11所示之第1習知例中需要64條信號線，但根 ❹ 據第2實施形態之耦接構成，以38條信號線即可耦接。此 外’記憶體控制裝置（110)的信號線耦接條數為少於圖1所 示之第1實施形態的構成，而亦可提升通量。 圖5為第2實施形態耦接構成之時序圖第1例。如圖5 所示。對記憶體0(130)設定6週期的讀取延遲期（260)，對 記憶體1(140)設定5週期的讀取延遲期（670)，藉此可僅由 記憶體控制裝置（110)的NADV1之控制對2個記憶體〇(13〇) 與記憶體1(140)進行存取’而在週期242以後可同時進行 098110826 11 200945049 資料讀取。 另外，記憶體控制裝置（110)的D[31 : 0](116)以外之信 號線未必要保持共享。即使無該共享的情況下，亦可較圖 11所不之第1習知例大幅減少信號線數，可獲得於圖所 不之第2習知例約2倍的通量。所以，本發明並不受限於上 述實施形態。此外，所有信號線的位元寬度並不受限於上述 說明的數值。又，讀取延遲期（26〇、270、360、670)或寫入 延遲期（370)，只要對記憶體設定系統上所必要值便可，未 必要為上述說明的延遲期。更進一步，本發明不受限於2 個記憶體0(130)與記憶體i(i4〇)，亦可由3個以上的記憶 體所構成。 (第3實施形態） 圖6為表示具備有記憶體控制裝置、2個CPU與DMAC的 系統之方塊圖。在圖6所示之系統（9〇〇)中，記憶體控制裝 置（110)、CPU0(910)及 CPUK920)、和 DMAC(930)，經由匯 流排（940)而分別耦接。另外，CPU0(910)、CPU1(920)及 DMAC(930)為對記憶體〇(13〇)或記憶體i(14〇)進行存取之 發出源（1200)。 在第3實施形態中，如圖7存取位元寬度不同情況下的記 憶體存取類別例所示，亦可設計記憶體控制裝置（110)成為 依照存取發出源（1200)所發出之存取位元寬度的不同，而對 記憶體0(130)與記憶體K140)同時進行存取、或各別進行 098110826 12 200945049 存取。此外，如圖8存取發出源（12〇〇)不同情況下的記憶體 存取類別例所示，亦可設計記憶體控制裝置（η〇)成為依照 存取發出源（1200)之不同，而對記憶體〇(13〇)與記憶體 1(140)同時進行存取、或各別進行存取。 • 圖9表示至同時對記憶體0(130)與記憶體1(140)進行存 取為止的系統（900)之起動順序例。另外，設有記憶體控制 裝置（110 )’以在系統（9 〇 〇)剛起動不久後的狀態下記憶體控 Φ 制裝置（110)對記憶體0(130)進行存取。在系統（900)剛起 動不久後，便執行從記憶體〇(13q)之讀取處理（丨⑽〇)， CPU0(91G)便開始處理。圓（⑽）在有效執行本發明功能的 程式（1001)内對暫存器（160)進行控制。圖1〇為表示暫存器 設定例之圖。如® 10所示，暫存器值〇3〇〇)之初期狀態為 「〇」，在暫存器值（13〇〇)的情況下，便僅對記憶體〇(13〇) 執打存取。當執行程式（1001)而將暫存器（16〇)的暫存器值 ® (13GG)設定為「1」，則可有效地執行作為本發明功能的同時 存取。 另外，在上述說明中，雖將暫存器（160)的暫存器值（13〇〇) P又為〇」或1」’但未必為該等值。此外，當暫存器值（1300) 為〇」時，可對記憶體0(130)進行存取，但未必一定對記 憶體0(130)進行存取，即使對記憶體1(14〇)進行存取，亦 可較圖11所7F之第1 f知例大幅減少信號線數。又，可獲 得圖12所示之第2習知例約2倍的通量。 098110826 13 200945049 另外，系統（900)並不受限在CPUO(91〇)、cpui(92〇)及 DMAC(93G)經由匯流排⑽）而相互輕接的構成，即使為其他 的構成亦可達到同樣的效果。此外，存取類別並不受限於圖 7存取位it寬度不同情況下的記憶體存取類別例、與圖8所 示存取發出源（_)不同情況下的記憶體存取類別例，即使 將上述存取類別定義適用在其他實施形態，亦可較圖11所 不之第1習知例大幅減少信號線數。又，可獲得圖丨2所示 之第2習知例約2倍的通量。 雖已詳細或參照特定實施態樣來說明本發明惟在不脫離 本發明精神與範圍下，發明所屬技術領域者可施以各種變更 與修正。 本申請案係以2 0 0 8 * 4月7日申請的日本專利申請案（特 願2008-099259)為基礎’且參照該案内容而弓丨用於本案'中。 (產業上之可利用性） 本發明之記憶體控制裝置較習知技術因增加必要最小限 度之針腳數而可實現大幅之性能提升。且，因為可使用現有 之記憶體，因而作為以時間分割而共享位址與資料的呓憶體 之控制裝置等尤其有用。 【圖式簡單說明】 圖1為表示記憶體與記憶體控制裝置之耦接構成的第工 實施形態。 圊2為第1實施形態搞接構成之時序圖第1彳列。 098110826 14 200945049 圖3為第1實施形態輕接構成之時序圖第2例 圖4為表示記憶體與記憶體控制裝置之輕接構成的第 實施形態。 圖5為第2實施形態耦接構成之時序圖第i例 個CPU及DMAC的 圖6為表示具備有記憶體控制裝置 系統之方塊圖。 圖7為存取位元寬度;^情況下的記憶體存取類別例。 ❹ ® 8為存取發出源不同情況下的記憶體存取類別例。 圖9為系統的起動順序例。 圖10為暫存器設定例。 圖η為表示記憶體與記憶體控制裝置之輪接構成的第！ 圖12為表示記憶體與記憶體控制裝置之耦接構成的第2 習知例。200945049 VI. Description of the Invention: [Technical Field] The present invention relates to a memory control device for controlling ADMUX memory (hereinafter referred to as "memory") that shares time and data by time division. [Prior Art] Fig. 1 is a first conventional example showing the configuration of the handle of the δ-resonance and the §-remembered control device. As shown in Fig. 11, a memory 0 (130) and a memory 1 (140) are coupled to the memory control device (110). In this example, there are two sets of necessary signals (for example, refer to Patent Document 1). For example: CLKO (111) of the memory control device (110) is coupled to the CLKC 131 of the memory 0 (130); CLK1 (121) of the memory control device (110) is connected to the memory i (i4 〇) CLK CLKC141); NADV0 (112) of the memory control device (110) is coupled to the NADVC132 of the memory port (130); 'NADV1C122 of the memory control device (110) is coupled to the memory 1 (140)' The NCSVC 142 of the memory control device (110) is coupled to the NCSC 133 of the memory 0 (130); the NCS1 (123) of the memory control device (110) is coupled to the 098110826 of the memory 1 (140). 3 200945049 NCSC143); NOEOC 114) of memory control device (110) is coupled to NOEC 134 of memory 0 (130); NOE1C124 of memory control device (11 〇) is coupled to NOS of memory 1 (140) (144); NWE0C115 of the memory control device (110) is coupled to the NWE (135) of the memory 0 (130); NWE1 (125) of the memory control device (110) is coupled to the memory 1 (140) NWEC145); :〇] (417) coupled to the memory: 〇] (427) coupled to the memory: 〇] (416) coupled to the memory: 〇] (426) coupled to the memory memory Control device (110) A0 [11 0 (130) A[26:16](137); A[26:16](147) of Al[ll 1(140) of memory control device (110); D0[15 0(130) of memory control device (110) D[15: 0] (136) of the memory control device (110) D[15 1 (140) D[15: 0] (146). Fig. 12 is a second conventional example showing a configuration in which a memory and a memory control device are coupled. As shown in FIG. 12, in the second conventional example, the memory control device (11〇) other than the wafer selection signals NCSC 113 and 123, cLKO (lll), NADVO (112), NOEO (114), and NWEO (115) A[11: 1](417), D[15:0](416)' are all coupled to the memory port (13〇) and the memory 1 (14〇). 098110826 4 200945049 For example: CLKO (111) of the memory control device (110) is coupled to CLKC 131 of the memory 0 (130) and CLKC 141 of the memory 1 (140); NADV0C 112 of the memory control device (110) The NADV (132) coupled to the memory 0 (130) - is coupled to the NADV (142) of the memory 1 (140); the NOEO (114) of the memory control device (110) is coupled to the memory 0 (130) N0EC 134) and memory 1 (140) N0EC 144); 记忆 memory control device (110) NWE0C115) coupled to memory 0 (130) NWEC 135) and memory 1 (140) 丽 E (145); A0[11:0](417) of the memory control device (110) is coupled to A[26:6] (137) of the memory 0 (130) and A[26:6] of the memory 1 (140). (147); D0[15:0] (416) of the memory control device (110) is coupled to D[15:0] (136) of the memory 0 (130) and D of the memory 1 (140). 15:0] (146); NCS0 (113) of the memory control device (110) is coupled to the memory 〇 (13〇) © NCSC133); the memory control device (11〇) is coupled to the NCS1 (123) NCSC143) in memory kmo). Fig. 13 is a diagram showing an example of a timing chart of the second conventional example coupling configuration. In this case, the memory 0 (130) and the memory Κ 140) can be accessed from the memory 24 (130) from the cycle 24, and the memory 1 (14 接受) can be accessed from the cycle 611. . (Patent Document 1) Japanese Patent Laid-Open No. Hei 8-77-66 No. 098110826 5 200945049 [Explanation of the Invention] In recent years, an LSI equipped with a memory control device or a memory control device is mounted thereon. The LSI system is evolving toward high functionality. When such an LSI equipped with a memory control device is realized, it is necessary to minimize the number of couplings of the external input/output signal lines in order to meet the cost. In addition, in terms of performance, the flux of external memory access is mostly a system bottleneck. In order to solve this bottleneck, all the signal lines necessary for the complex array to be coupled to the memory are designed or shared except for the wafer selection signal. However, it is difficult to balance the minimum number of couplings of the external input and output lines with the high-pass quantization system. SUMMARY OF THE INVENTION An object of the present invention is to provide a memory control device which minimizes the number of lines of signal lines and high-pass quantization. (Means for Solving the Problem) The present invention provides a memory control device which is a memory control device for controlling a plurality of memories which share addresses and data by time division; ^ above the data bus width of the first memory The address of the second memory is displayed in the data bus rank 7C, and the address above the data bus width of the second memory is represented by the data bus of the first memory, and at the same time The above plurality of memories are accessed. The memory control device simultaneously performs reading and writing on the plurality of memories. The above-described S-review control device changes the access method to the above-mentioned plural 098110826 〆 200945049 memory according to the access type. The memory control device changes the access method to the above-mentioned number of bits based on the value of the setting register. The present invention provides a system including the above memory control device. The present invention provides a memory coupling method for coupling a memory control device that controls time-division and sharing a plurality of addresses and data to a memory connection method of the plurality of memories; The body control device displays the address above the data bus width of the first memory in the data bus location of the second memory, and sets the address of the second memory to be above the data bus width. The data of the above-mentioned second memory is displayed by the bus level bit, and at the same time, the above-mentioned complex memory is accessed. (Effect of the Invention) According to the memory control device of the present invention, both the minimum number of signal line surface contacts and the high-pass quantization can be achieved. That is, it is estimated that the performance can be greatly improved with the minimum number of stitches as compared with the conventional one. Moreover, since the memory can be used, not only the LSI but also the system as a whole and the high performance system can be reduced. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. (First Embodiment) Fig. 1 shows an embodiment in which a memory and a memory control device are coupled to each other. In Fig. 1, the same constituent elements as those of Fig. 11 are assigned the same reference numerals of 098110826 7 200945049, and the description is omitted. In addition, the memory 〇 (13〇) and the memory 1 (140) in Fig. 1 are clock-synchronized ADMUX memories that share addresses and data in time division. In the first embodiment, D[31:0] (116) of the 'memory control device (1 1 〇 ) shown in Fig. 1 is connected as follows. In the memory 〇 (13〇), eight [26:16] (137) are coupled to 0[26:16](116), and 〇[15:〇](136) is coupled to D[15:0](116). ). On the other hand, a[26:16](147) of memory 1 (140) is coupled to D[10:0](116)' to D[15:0](146) coupled to D[31:16 ] (116). Further, in the first embodiment, the CLKO (111) of the memory control device (110) is coupled to the CLKC 131 of the memory 0 (130) and the CLKC 141 of the memory 1 (140); the memory control device (110) of NADV0C112) is coupled to the memory 〇 (13〇) of NADVC132); the memory control device (11〇) of NADV1 (122) is coupled to the memory 1 (14 〇) of NADVC142); The NCS0 (113) of the memory control display (11 〇) is lightly connected to the memory 〇 (13 〇) of the NCSC 133); the memory control device (110) of the NCSK123) is coupled to the memory 1 (14) NC) NCS (143); NOEO (114) of memory control device (110) is consumed by N0E (134) of memory Q (i3 〇); 098110826 〇 200945049 N0E1 of memory control device (110) ( 124) is coupled to the memory 1 (140) of the NOSSC 144); the memory control device (110) NWE0 (115) is coupled to the memory 〇 (13 〇) NWEC 135); • memory control device (110 NWE1C125) is coupled to NWS (145) of memory 1 (140). When the number of signal lines of the memory 0 (130) and the memory 1 (140) is 32, the number of signal lines is required in the first conventional example shown in Fig. U, but according to the first embodiment. Consumable structure, can be coupled with 41 signal lines. Furthermore, in the second conventional example shown in FIG. 12, 33 signal lines can be coupled, but in the second conventional example, signals other than NCS0C113) and NCS1C123) of the shared memory control device (11A) are shared. . Therefore, as shown in Fig. 13 showing the timing chart of the second conventional example, it is necessary to receive the memory 〇 (13 〇) and the memory 1 (140) once, and the memory 从 from the cycle 24 〇 (13〇) ❹ Accepts access, and memory 1 (14〇) accepts access from cycle 611. Fig. 2 is a view showing an example of a timing chart of the first embodiment. According to the i-th embodiment, when access is performed as shown in FIG. 2, the period (10) of the address (10) of the memory 〇 (13 〇) is set to the next period (241), and the memory 1 (140) is used. ) Set health A1 (251). The mosquitoes are output in the period of the symbol 242, which is the period of the reading delay period (2) of the (4) Q (i3_reading delay period (260) and the sufficiency 1 (14〇)). The reading material (252) of the memory 0 (130) and the reading data (253) of the memory 1 (14Q) are simultaneously read 098110826 9 200945049 (254). Thus, in the first embodiment, the suppression is performed. The number of couplings of the signal lines is comparable to that of the second conventional example shown in FIG. 12, since the width of the data bits that can be simultaneously read is twice, so that about twice the flux can be achieved. The second example of the timing chart of the configuration of the embodiment is coupled. As shown in FIG. 3, the read delay period (36 〇) is set for the memory 0 (130), and the write delay period is set for the memory 1 (140) ( 370), the read data (252) from the memory port ("3") can be read in the period indicated by the symbol 340. Further, the period indicated by the symbol 242 is set by the memory control device (11〇). In the first embodiment, the D[31:0] (116) of the memory control device (110) is based on the data (35 〇).忆忆体0(130) The memory i (i4〇) is shared, but it can also be implemented by adding a shared signal line. Fig. 4 is a second embodiment showing the coupling structure of the memory and the memory control device. 1 and the same components as those in FIG. 11 are denoted by the same reference numerals, and the description thereof will be omitted. In the second embodiment, as shown in FIG. 4, D[31: 〇] of the memory control device (110) is coupled as follows ( 116). In the memory 〇 (13〇) A[26: 16] (137) handle 〇 [26: 16] (116), 〇 [15:0] (136) coupled 0 [15: 〇 ] (116). On the other hand, in memory 1 (14〇) a[26: 16](147) is connected to 〇[10:0](116)' at 〇[15:0](146) 〇[31:16](116). Further, in the second embodiment, CLK110 (1011) of the memory control device (110) is coupled to the CLKC 131 of the memory 〇 (i30) and CLKC141 of memory i (i4〇); NCS0C113 of memory control device (11〇) is coupled to NCS (133) of memory 〇 (13〇) and NCSC 143 of memory 1 (140); The memory control device (11〇) NOEOU14) is coupled to the memory 〇 (13〇) of NOEC134) and memory 1 (140) N0EC144); NWE0C115 memory control means (110)) is coupled to the system memory 0 (i30) ❹ the NWEC135) NWEC145 and memory 1 (140)). Furthermore, the NADV0 (112) of the memory control device (110) is not shared but is coupled to the NADVC 132 of the memory 0 (130); the NADV1C122 of the memory control device (110) is not shared but coupled to the memory. Body 1 (140) of NADVC142). When the number of signal lines of the memory 0 (130) and the memory 1 (140) is 32, "the first conventional example shown in FIG. 11 requires 64 signal lines, but according to the second embodiment. The coupling is configured to be coupled by 38 signal lines. Further, the number of signal line couplings of the memory control device (110) is smaller than that of the first embodiment shown in Fig. 1, and the flux can be increased. Fig. 5 is a first example of a timing chart of the coupling configuration of the second embodiment. As shown in Figure 5. A six-cycle read delay period (260) is set for the memory 0 (130), and a five-cycle read delay period (670) is set for the memory 1 (140), whereby the memory control device (110) can be used only. The control of NADV1 accesses two memory ports (13〇) and memory 1 (140)', and after cycle 242, 098110826 11 200945049 data can be read simultaneously. Further, the signal lines other than D[31: 0] (116) of the memory control device (110) are not necessarily shared. Even in the case where there is no such sharing, the number of signal lines can be greatly reduced as compared with the first conventional example shown in Fig. 11, and the flux of about twice the second conventional example can be obtained. Therefore, the present invention is not limited to the above embodiments. In addition, the bit width of all signal lines is not limited to the values described above. Further, the read delay period (26 〇, 270, 360, 670) or the write lag period (370), as long as the value necessary for the system is set for the memory, it is not necessary to be the delay period described above. Furthermore, the present invention is not limited to two memories 0 (130) and memory i (i4 〇), and may be composed of three or more memories. (Third Embodiment) Fig. 6 is a block diagram showing a system including a memory control device, two CPUs, and a DMAC. In the system (9A) shown in Fig. 6, the memory control device (110), the CPU0 (910) and the CPU K920), and the DMAC (930) are respectively coupled via the bus bar (940). Further, CPU0 (910), CPU 1 (920), and DMAC (930) are emission sources (1200) for accessing the memory (13) or the memory i (14). In the third embodiment, as shown in the example of the memory access type in the case where the access bit width is different as shown in Fig. 7, the memory control device (110) may be designed to be issued in accordance with the access source (1200). The access bit width is different, and the memory 0 (130) and the memory K 140) are simultaneously accessed, or the 098110826 12 200945049 is accessed separately. In addition, as shown in the example of the memory access category in the case where the access source (12〇〇) is different, the memory control device (n〇) may be designed to be different according to the access source (1200). The memory 〇 (13 〇) and the memory 1 (140) are simultaneously accessed or accessed separately. • Fig. 9 shows an example of the startup sequence of the system (900) until the memory 0 (130) and the memory 1 (140) are simultaneously accessed. Further, the memory control device (110) is provided to access the memory 0 (130) by the memory control device (110) in a state immediately after the system (9 〇 〇) is started. Immediately after the system (900) has just started, the reading process (丨(10)〇) from the memory port (13q) is executed, and the CPU 0 (91G) starts processing. The circle ((10)) controls the register (160) in a program (1001) that effectively performs the functions of the present invention. Fig. 1A is a diagram showing an example of setting of a register. As shown in ® 10, the initial state of the register value 〇3〇〇) is “〇”, and in the case of the scratchpad value (13〇〇), only the memory 〇(13〇) is saved. take. When the program (1001) is executed and the register value (13GG) of the scratchpad (16〇) is set to "1", simultaneous access as a function of the present invention can be efficiently performed. Further, in the above description, the register value (13〇〇) P of the register (160) is 〇" or 1"', but is not necessarily the same value. In addition, when the scratchpad value (1300) is 〇", the memory 0 (130) can be accessed, but the memory 0 (130) is not necessarily accessed, even for the memory 1 (14 〇) By accessing, the number of signal lines can be greatly reduced as compared with the first f example of 7F of Fig. 11. Further, a flux of about twice the second conventional example shown in Fig. 12 can be obtained. 098110826 13 200945049 In addition, the system (900) is not limited to the configuration in which the CPUO (91〇), cpui (92〇), and DMAC (93G) are connected to each other via the bus bar (10), even if it is configured for other configurations. The same effect. Further, the access type is not limited to the memory access type example in the case where the access bit width of FIG. 7 is different, and the memory access type example in the case where the access source (_) is different from the access source (_) shown in FIG. Even if the above-described access category definition is applied to other embodiments, the number of signal lines can be greatly reduced as compared with the first conventional example not shown in FIG. Further, a flux of about twice the second conventional example shown in Fig. 2 can be obtained. The present invention has been described in detail with reference to the specific embodiments thereof. The present application is based on Japanese Patent Application No. 2008-099259 filed on Apr. 7, the entire disclosure of which is hereby incorporated by reference. (Industrial Applicability) The memory control device of the present invention can achieve a large performance improvement by increasing the number of stitches required to be minimum as compared with the prior art. Further, since the existing memory can be used, it is particularly useful as a control device for sharing the address and the data in time division. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a configuration in which a memory and a memory control device are coupled.圊2 is the first sequence of the timing chart of the first embodiment. 098110826 14 200945049 Fig. 3 is a second example of a timing chart of a light-weight configuration of the first embodiment. Fig. 4 is a view showing a first embodiment of a light-weight configuration of a memory and a memory control device. Fig. 5 is a timing chart showing the configuration of the second embodiment. The first example of the CPU and the DMAC. Fig. 6 is a block diagram showing the system including the memory control device. Fig. 7 is an example of a memory access category in the case of access bit width; ❹ ® 8 is an example of a memory access category in which the source of the access is different. Figure 9 is an example of the starting sequence of the system. Fig. 10 shows an example of setting of a register. Figure η shows the structure of the rotation of the memory and the memory control device! Fig. 12 is a second conventional example showing a configuration in which a memory and a memory control device are coupled.
圖13為第2習知例耦接構成之時序圖一例。 【主要元件符號說明】 110 記憶體控制裝置 111、 121、131、141 同步時脈信號(正邏輯） 112、 122、132、142 位址確定信號（負邏輯） 113、 123、133、143晶片選擇信號（負邏輯） 114、 124、134、144 讀取賦能信號（負邏輯） 115、 125、135、145 寫入賦能信號（負邏輯） 098110826 15 200945049 116 位址信號或資料信號 130 、 140 ADMUX記憶體 136、146、416 資料信號 137、147、417 位址信號 160 使本發明功能有效的暫存器 210 記憶體控制裝置（11〇)傳送接收的信號 時序 220 記憶體0(130)傳送接收的信號時序 230 記憶體1(140)傳送接收的信號時序 240 對記憶體0(130)設定位址的時序 241 對記憶體0(130)設定位址的時序 242 從記憶體0(130)與記憶體1(140)同時所 讀取到的最初資料 250 對記憶體0(130)的位址 251 對記憶體1(140)的位址 252 來自記憶體0(130)的讀取資料 253 來自記憶體1(140)的讀取資料 254 從記憶體0(130)與記憶體1(140)同時讀 取到的資料 260 > 270 ' 360 ' 670 讀取延遲期 340 從記憶體0(130)的資料(252)讀取時序 370 寫入延遲期 16 098110826 200945049 611 對記憶體1(140)開始存取 900 糸統 910 、 920 運算裝置 930 直接記憶體存取控制器 940 匯流排 1001 使本發明功能有效的程式 1200 存取發出源 1300 表示本發明有效/無效的暫存器值 ❿ 098110826 17Fig. 13 is a view showing an example of a timing chart of the second conventional example coupling configuration. [Main component symbol description] 110 Memory control device 111, 121, 131, 141 Synchronous clock signal (positive logic) 112, 122, 132, 142 Address determination signal (negative logic) 113, 123, 133, 143 wafer selection Signal (negative logic) 114, 124, 134, 144 read enable signal (negative logic) 115, 125, 135, 145 write enable signal (negative logic) 098110826 15 200945049 116 address or data signal 130, 140 ADMUX memory 136, 146, 416 data signal 137, 147, 417 address signal 160 enables the register 210 memory control device (11 〇) of the present invention to transmit and receive the signal timing 220 memory 0 (130) Received Signal Timing 230 Memory 1 (140) Transmit Received Signal Timing 240 Timing of Address Setting for Memory 0 (130) 241 Timing of Setting Address for Memory 0 (130) 242 From Memory 0 (130) The initial data 250 read from the memory 1 (140) is the address 251 of the memory 0 (130). The address 252 of the memory 1 (140) is read from the memory 0 (130). Reading data from memory 1 (140) 254 Data 260 > 270 '360 ' 670 read from the memory 0 (130) and the memory 1 (140) 270 read delay period 340 read the data from the memory 0 (130) (252) timing 370 Write delay period 16 098110826 200945049 611 Start access to memory 1 (140) 900 910, 920 arithmetic device 930 direct memory access controller 940 bus bar 1001 to enable the function of the present invention 1200 access source 1300 represents the valid/invalid register value of the present invention ❿ 098110826 17