200939410 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種晶片承載器以及晶片封裝結構，特別是關 於一種能增進散熱效益之晶片承載器以及晶片封裝結構。 【先前技術】 隨著積體電路(integrated circuit, 1C)相關技術的發展，晶片内 部的電路複雜度以及密度快速增加，因此晶片在運作時所產生的 ❹ 熱能也逐漸上升。以目前常見的電子裝置，如個人電腦、行動電 話、顯不裝置等而言’其内部高積集度(integrati〇n)的積體電路晶 片會在運作時產生大量的熱能。為了使晶片能維持正常運作並避 免溫度過高造成的效能下降或損壞，熟知該項技術領域人士必須 在設計高複雜度/密度之晶片時，一併提出維持晶片正常工作溫度 的解決方案。 於先韵技術中，曰曰片主要可藉由打線接合(％^wb) 技術、予日日日接合(flip chip，FC)技術或是捲帶自動接合(tape 二ornate bonding, TAB)技術與晶片承載器(carri )電 動接合技術具有:能在可撓性基材層上直性: 利用，性基材層完成電子元件的立體組裝；以及能夠 2二動f連結及具可撓曲性之晶片封裝體等優點，因此 腦、液晶顯示器/電視、記憶卡等電子產品 如弟1圖所示 封裝，構7主要包含可攙性基材層以 tH、議77以及封膠體78。可撓性基材ϊ 7〇Τ 板:該導電線路層72形成於該可撓性基材層70、之 表面702 ;並且該防銲層74則形成於該導電線路層π上， 200939410 路層72因污染而產生短路。晶片76具有一主動面 ，該主動面762設置有複數個凸塊766 ’該些 72之電性連^至導電線路層72，以完成晶片76與導電線路層 764 熱片77可藉由散熱膏79黏附於晶片76之背面 望计151、/^ 78則形成於可撓性基材層70與晶片76之間，以覆 盍並固疋該些凸塊766。 Ο ❹ 然散熱片77可增加晶片76的散熱速度，但晶片封 7二體厚度會增加，健#77的重量也可能會使可撓 =材層7G產生f曲或變形’影響晶片％的正常運作，並且晶 生社躺⑽並且料域㉟丨76耦接之 ^電線路層72 ’該散熱片77係黏附於晶片76之背面764，豆傳 ¥路徑較遠，散熱效果較差。 /、 【發明内容】 因此，本發明之一範疇在於提供一種增進散熱效益之晶片承 載斋，以解決先前技術中的問題。 根據一，佳具體實施例，本發明之晶片承載器包含一可撓性 基材層以及複數個導電線路。該可撓性基材層具有一 及相對於該第-表面之—第二表面，並且該等導電線路形^該 第一表面上。特別地，該可撓性基材層於對應該等導電線路中之 至少一，電線路的位置形成至少一穿孔’該穿孔不會使該第一表 ，與該第二表面形成電性連接，並且該穿孔被該導電線路完全覆 去 〇BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer carrier and a chip package structure, and more particularly to a wafer carrier and a chip package structure which can improve heat dissipation efficiency. [Prior Art] With the development of related circuits (1C), the circuit complexity and density inside the wafer are rapidly increased, so that the heat generated by the wafer during operation is gradually increased. In the current common electronic devices, such as personal computers, mobile phones, display devices, etc., the internal integrated circuit chips of the internal integration process generate a large amount of thermal energy during operation. In order to maintain the normal operation of the wafer and avoid the performance degradation or damage caused by excessive temperature, those skilled in the art must propose a solution to maintain the normal operating temperature of the wafer when designing a high complexity/density wafer. In Yu Xianyun's technology, the cymbal film can be mainly connected by wire bonding (%^wb) technology, flip chip (FC) technology or tape automatic bonding (TAB) technology. The wafer carrier (carri) electro-bonding technology has the following features: straightness on the flexible substrate layer: three-dimensional assembly of electronic components by using the substrate layer; and two-way f-connection and flexibility The advantages of the chip package and the like are such that the electronic products such as the brain, the liquid crystal display, the television, and the memory card are packaged as shown in FIG. 1 , and the structure 7 mainly includes the adhesive substrate layer tH, the substrate 77, and the sealant 78. Flexible substrate ϊ 7〇Τ plate: the conductive circuit layer 72 is formed on the flexible substrate layer 70, the surface 702; and the solder resist layer 74 is formed on the conductive circuit layer π, 200939410 road layer 72 Short circuit due to pollution. The wafer 76 has an active surface 762, and the active surface 762 is provided with a plurality of bumps 766' electrically connected to the conductive circuit layer 72 to complete the wafer 76 and the conductive circuit layer 764. The back surface 151, / 78, which is adhered to the wafer 76, is formed between the flexible substrate layer 70 and the wafer 76 to cover and fix the bumps 766. ❹ 散热 散热 散热 散热 散热 散热 散热 可 可 可 可 可 可 可 可 可 散热 散热 散热 散热 散热 散热 散热 散热 散热 晶片 晶片 晶片 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热 散热Operation, and the crystal living room is lying (10) and the material field 35丨76 is coupled to the electric circuit layer 72'. The heat sink 77 is adhered to the back side 764 of the wafer 76, and the bean transfer path is far away, and the heat dissipation effect is poor. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a wafer carrier that enhances heat dissipation benefits to solve the problems of the prior art. According to a preferred embodiment, the wafer carrier of the present invention comprises a flexible substrate layer and a plurality of conductive traces. The flexible substrate layer has a second surface opposite the first surface, and the conductive traces are formed on the first surface. In particular, the flexible substrate layer forms at least one through hole at a position corresponding to at least one of the conductive lines, and the through hole does not cause the first surface to be electrically connected to the second surface. And the perforation is completely covered by the conductive line
TTTT 本發明之另一範噃在於提供一種晶片封裝結構，其具有良好 散熱功效，並且可解決先前技術中的問題。 八 7 200939410 根據-較佳具體實施例，本發明之晶片封裝結構 性基材層、複數個導電線路以及一晶片。該可撓性基材層且有二 弟-表面以及相對於該第—表面之—第二表面，該第—表^ 含一晶片接合區。該等導電線路形成於該第一表面上，並且 晶片接合區内向外延伸。此外，該晶片設置於該晶 了 並且包含複數個接點分職接該料電線路。特观可挽性 ίΐ層於對f該等導電線路中之至少-導電線路的位置形成ΐ少 會使該第一表面與該第二表面形成電性連接， 亚且S亥牙孔被§玄導電線路完全覆蓋。 ❹ ❹ 式得點與精神可以藉由以下的發明詳述及所附圖 【實施方式】 結構 本發明提供—種可增進散熱效益之W承翻以及晶片封裝 -具3 及第2Β圖，第2Α圖係根據本發明之 明i-且體載器示意圖；® 2Β圖則係繪示根據本發 之晶。本關實酬所揭露 TAB)技術之帶式軟性捲㈣動接合_邮ormted bonding， 材層:弟二圖f示’晶片承載器1可包含可撓性基 (Polyimide，PI)、°可撓性基材層10可由聚醯亞胺 其他合適的材料所製^ ^f^°lyethylene terePhthalate，PET)或 二表面104，並且診第具有第一表面102以及相對之第 供晶片接合固定之^ ϋ上定義有晶片接合區1〇8，以 其他適當的方式时化 h電線路12可以銅減由侧或 基材層H)於Si，ίΐζ—表面102上。進一步，可捷性 …至V —導電線路12的位置形成至少一個穿孔 200939410 106自第一表面102貫穿至第二表面104。特別地，該等穿孔1〇6 不會使第一表面102與第二表面104形成電性連接(換言之， 明之晶片承載器所包含之穿孔與習知技術中用以導通第一表面丄 ^二表面之孔洞不同）’並且，穿孔1〇6可被導電線路12完全^ 蓋。 此外，如第2B圖所示，本發明之晶片承載器}可進一步包 含防銲層18，其局部覆蓋該等導電線路12，以防止導電線路12 • 因污染而產生短路。 ❹ 請參見第3A圖以及第3B圖，第3A圖以及第3B圖皆係根 據本發明之具體實施例的晶片承載器剖面圖。相較於前述具體實 施例，晶片承載器，第3A圖所繪示之晶片承載器丨進一步包含 散熱^ 14，其塗佈於第二表面104上並填滿穿孔1〇6。請注意， 政熱賞14可使用任何適當的材料。並且於實務中，散熱膏μ不 一定要填滿穿孔106，而可以僅覆蓋穿孔1〇6或以不同程度適當 地填入穿孔106中。 田 一此外，相較於鈿述具體實施例的晶片承載器，第3B圖所繪 示之晶片承載器1進一步包含散熱構件16，其設置於第二表面 ❹ 1〇4上並覆盍穿孔106。請注意，散熱構件16可使用任何適當的 材料製成。並且於實務中，散熱構件16也可以為同時覆蓋若干 穿孔106的較大型單一構件。此外，散熱構件16可以是散熱鰭 片（heat_dissipating fin)、熱導管(heat pipe)、熱導柱(heat column)或 其他適合的形式。 於實際應用中，穿孔並不一定要自第一表面貫穿至第二表 面:而可視情況調整其深度以及孔徑大小。此外，產生熱量較多 的區域可設置較多的穿孔，而產生熱量較少的區域則設置少量穿 孔或不須設置穿孔。此外，於實際應用中，前述之散熱膏以及散 熱構件也可相互搭配使用於本發明之晶片承載器。 9 200939410 請-併參見第4Α圖以及第4Β圖，第4α圖係繪示根據 明之一具體實施例的晶片封裝結構示意圖，而第4Β圖 ^TTTT Another aspect of the present invention is to provide a chip package structure which has a good heat dissipation effect and which solves the problems in the prior art. VIII 7 200939410 According to a preferred embodiment, the wafer of the present invention encapsulates a structural substrate layer, a plurality of conductive traces, and a wafer. The flexible substrate layer has a second surface and a second surface opposite the first surface, the first surface comprising a wafer bonding region. The conductive traces are formed on the first surface and extend outwardly within the wafer bond region. In addition, the wafer is disposed on the crystal and includes a plurality of contacts to be connected to the power line. The feature of the at least one of the conductive lines of the conductive lines is such that the first surface is electrically connected to the second surface, and the second surface is electrically connected to the second surface. The conductive lines are completely covered. ❹ 式 式 点 精神 精神 精神 精神 精神 可以 可以 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 结构 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及BRIEF DESCRIPTION OF THE DRAWINGS The present invention is a schematic diagram of a body carrier according to the invention, and the Fig. 2 is a diagram showing the crystal according to the present invention. The tape reel reveals the TAB) technology of the flexible tape (four) dynamic bonding _ mail ormted bonding, material layer: brother two figure f shows that the wafer carrier 1 can contain flexible (Polyimide, PI), ° flexible The substrate layer 10 can be made of other suitable materials of polyamidimide, or the two surfaces 104, and the first surface 102 and the opposite wafer are bonded and fixed. Wafer junction area 〇8 is defined above, and in other suitable manner, the HV circuit 12 can be copper reduced from the side or substrate layer H) to the Si, ΐζ-surface 102. Further, the at least one perforation ... to V - the position of the conductive line 12 forms at least one perforation 200939410 106 from the first surface 102 to the second surface 104. In particular, the perforations 1〇6 do not electrically connect the first surface 102 with the second surface 104 (in other words, the perforations included in the wafer carrier are used to turn on the first surface in the prior art) The holes in the surface are different) 'And, the perforations 1〇6 can be completely covered by the conductive lines 12. Further, as shown in Fig. 2B, the wafer carrier of the present invention can further include a solder resist layer 18 partially covering the conductive traces 12 to prevent the conductive traces 12 from being short-circuited due to contamination. Referring to Figures 3A and 3B, Figures 3A and 3B are cross-sectional views of a wafer carrier in accordance with an embodiment of the present invention. In contrast to the foregoing specific embodiment, the wafer carrier, the wafer carrier of Figure 3A, further includes heat sinks 14, which are applied to the second surface 104 and fill the perforations 1〇6. Please note that the Registrar 14 can use any suitable material. In practice, the thermal grease μ does not have to fill the perforations 106, but may only cover the perforations 1〇6 or fill the perforations 106 appropriately to varying degrees. In addition, in comparison to the wafer carrier of the specific embodiment, the wafer carrier 1 illustrated in FIG. 3B further includes a heat dissipating member 16 disposed on the second surface ❹1〇4 and covering the through hole 106. . Note that the heat dissipating member 16 can be made of any suitable material. Also in practice, the heat dissipating member 16 can also be a larger single member that simultaneously covers a plurality of perforations 106. Further, the heat dissipating member 16 may be a heat_dissipating fin, a heat pipe, a heat column, or other suitable form. In practical applications, the perforation does not have to extend from the first surface to the second surface: the depth and the aperture size can be adjusted as appropriate. In addition, more perforations may be provided in areas where heat is generated, and a small amount of perforations may be provided in regions where less heat is generated or without perforations. Further, in practical applications, the aforementioned heat dissipating paste and heat dissipating member may also be used in combination with the wafer carrier of the present invention. 9 200939410 Please-see also FIG. 4 and FIG. 4, FIG. 4α is a schematic diagram showing the structure of a chip package according to a specific embodiment of the present invention, and FIG. 4 is a diagram.
根據本發明之一具體實施例的晶片封裝結構之剖面圖。、…W7F 如第4A圖以及第4B圖所示，除了前述之可挽性 =導電線路32之外，晶片封裝結構3還可包含晶片％ Ο Ο «材層 3〇W^i_(P〇lyimide’ PI)、聚賴化合物(p ^ 其他合適的材料所製成，並且其具有第—表面地以及相(』第 =表=〇4。此外’第-表面3〇2上包含晶片接合區期弟 夕卜，導電線路32可以編藉由侧或其他適當的方式圖案^ 成於第-表面302上’並且自晶片接合區内向外延伸了 / =設ΐΓίΐ接合ί308㈧，並且包含複數個接點(未繪=於 圖中）以及相對應之複數個凸塊(bump) 342以分 收 …於實際謝，凸塊342可用金、銅‘=== 材料所製成。 辣U通田的 進一步’如第4B圖所示，本發明之晶片_結構 3防鋅層38以及封膠體抑。如前所述，防銲層3 導電線路32，以防止導電線路32目污染喊生短路 體^ 則形成於晶片34與可撓性基材層3〇之間，以 此H9 342，並提供適當的封裝保護以防止電性短路與塵埃污染二-鬼 特別地，如上所述，可撓性基材層3〇於 Γ表的面位Γίίί二穿rG6 ’並且其不會使忒==Ϊ ^表面3〇4形成電性連接。穿孔3〇6可被各導電線路32完^ 於實喊γ ^與可触騎層可藉 (Tape :财 Package，TCP)、覆曰曰曰薄膜 COF)或其他合義職技躺行封|。 P η _ package， 如上所述’本發明之晶片封裝結構也可視需求加人前述之散 200939410 ί 件’以增進散熱效率。此外，於實際應财，穿 孔並不一疋要自第一表面貫穿至第二表面，而可視 況 f以、。此外’產生熱量較多的區域可設置較多的、ί 孔，而產生熱I較少的區域則設置少量穿孔或不須設置穿孔。 ^目較^知技術，本發明之晶片承載器以 進散1效果的目的，舰以散熱膏及 =其散熱麟。此外，穿孔的設置可根據 她綱《繼祕丨，= ❹ 本發明之範嘴加以限制。相反地，具體實施例來對 及具相等性賴於本發鑛申^“ 各種改變 ❹ π 200939410 【圖式簡單說明】 第1圖係先前技術中的晶片封裝結構之剖面圖。 第2A圖係本發明之一具體實施例的晶片承栽器示意圖。 第2B圖係本發明之一具體實施例的晶片承載器剖面圖。 第3A圖係本發明之—具體實施例的晶片承載器剖面圖。 第3B圖係本發明之一具體實施例的晶片承載器剖面圖。 第4A圖係本發明之—具體實施例的晶片封裝結構示意圖。 第4B圖係本發明之一 【主要元件符號說明】 •具體實施例的晶片封裝結構剖面圖。 1 _晶片承載器 10、30、70 :可撓性基材層 102、302:第一表面 106、306 :穿孔 104、304 :第二表面 108、308 :晶片接合區 12、32 :導電線路 14、79 :散熱膏 16 :散熱構件 18、38、74 :防銲層 3、7.晶片封裝結構 34、76 .晶片 342、766 :凸塊 39、78 :封膠體 702 :上表面 72 :導電線路層 762 :主動面 77 :散熱片 764 ··背面 12A cross-sectional view of a wafer package structure in accordance with an embodiment of the present invention. W7F As shown in FIG. 4A and FIG. 4B, in addition to the aforementioned pullability = conductive line 32, the chip package structure 3 may further include wafer % Ο Ο «Material 3 〇 W ^ i_ (P〇lyimide 'PI), poly-lysate compound (p ^ other suitable materials, and it has a first surface and a phase (" = = table = 〇 4. In addition, the first surface - surface 3 〇 2 contains the wafer junction area In other words, the conductive traces 32 may be patterned on the first surface 302 by side or other suitable means and extend outward from the wafer bond region / / ΐΓ ΐ ΐ ί ί 308 (eight), and include a plurality of contacts ( Unpainted = in the figure) and the corresponding plurality of bumps 342 to separate... In actual thanks, the bumps 342 can be made of gold and copper '=== materials. As shown in Fig. 4B, the wafer-structure 3 zinc-proof layer 38 and the encapsulant of the present invention are as described above, and the solder resist layer 3 is provided with a conductive line 32 to prevent the conductive line 32 from being contaminated by the short circuit. Between the wafer 34 and the flexible substrate layer 3〇, with H9 342, and providing appropriate package protection to prevent electricity Short circuit and dust pollution II - Ghost In particular, as described above, the flexible substrate layer 3 is placed on the surface of the surface Γ ί ί ί ί ί ί ί 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且 并且Connection. The perforation 3〇6 can be completed by each conductive line 32. The actual yoke can be yed with the tactile layer (Tape: TCP, TCP) or other suitable skills. P η _ package, as described above, 'the chip package structure of the present invention can also add the aforementioned 200939410 ί pieces' to improve the heat dissipation efficiency. In addition, in actual accounting, the perforation is not the same as the first The surface penetrates to the second surface, and the condition f is, in addition, 'the area where the heat is generated may be provided with more holes, and the area where the heat I is less is provided with a small number of perforations or no need to provide perforations. Compared with the known technology, the wafer carrier of the present invention has the purpose of the dispersion 1 effect, and the ship is provided with a heat-dissipating paste and a heat-dissipating lining. In addition, the setting of the perforation can be based on her outline, following the tips of the invention. The mouth is limited. Conversely, the specific embodiment is equivalent and depends on the mine. ^ "Various changes π π 200939410 [Simplified description of the drawings] Fig. 1 is a cross-sectional view of a wafer package structure in the prior art. Fig. 2A is a schematic view of a wafer carrier according to an embodiment of the present invention. A cross-sectional view of a wafer carrier of one embodiment of the present invention. Fig. 3A is a cross-sectional view of a wafer carrier of a specific embodiment of the present invention. Fig. 3B is a cross-sectional view of a wafer carrier of one embodiment of the present invention. 4A is a schematic view of a wafer package structure of a specific embodiment of the present invention. FIG. 4B is a view of the present invention. [Main element symbol description] A sectional view of a wafer package structure of a specific embodiment. 1 _ wafer carrier 10, 30, 70: flexible substrate layer 102, 302: first surface 106, 306: perforations 104, 304: second surface 108, 308: wafer bonding regions 12, 32: conductive lines 14 79: heat-dissipating paste 16: heat-dissipating members 18, 38, 74: solder resist layers 3, 7. chip package structures 34, 76. wafers 342, 766: bumps 39, 78: sealant 702: upper surface 72: conductive lines Layer 762: active surface 77: heat sink 764 · · back 12