200935491 九、發明說明： 【發明所屬之技術領域】 本發明關於一種顯示面板及其方法，特別是關於一種整合 既有製程以增加單位面積儲存電容之薄膜電晶體-液晶顯示元 , 件(TFT-LCD)結構及其形成方法。 【先前技術】 積相對，小’且影像品質非常好，因此已逐漸取代體積龐大的 陰極線管顯示ϋ。而薄膜電晶體液晶顯示器為液晶顯示器的主 流t一、’其包含薄膜電晶體_設置於其上之一基板，且與具 有=色滤光_之另—基板補設置，並形成液晶層於兩基板 ❹ 就相同螢幕尺寸而言，液晶顯示器使用非常少的電力，體 參考圖9A及9B， ’顯示習知顯示面板之罝一蚩冬从4目200935491 IX. Description of the Invention: [Technical Field] The present invention relates to a display panel and a method thereof, and more particularly to a thin film transistor-liquid crystal display element (TFT- integrated with an existing process to increase a storage capacitance per unit area) LCD) structure and its formation method. [Prior Art] The product is relatively small, and the image quality is very good, so it has gradually replaced the bulky cathode tube display. The thin film transistor liquid crystal display is the mainstream of the liquid crystal display, which comprises a thin film transistor disposed on one of the substrates, and is provided with a substrate having a color filter, and forms a liquid crystal layer in two Substrate ❹ In terms of the same screen size, the liquid crystal display uses very little power. Referring to Figures 9A and 9B, the display of the conventional display panel is from 4 mesh.
^因此，相對地使得電容元件92所需耗 質劣化。此問 ，單位畫素的 用的基板面積增大，、^ _^ Therefore, the required quality of the capacitive element 92 is relatively deteriorated. This question, the area of the substrate used by the unit pixel is increased, ^ _
而越趨嚴重。 200935491 因此，迫切需要提出一種提升單位儲存電容並同時提升開 口率之顯示面板及其製造方法。 【發明内容】 鑑於上述先刖技術的不足’本發明一方面在於提供一種形 成顯示面板之方法’其整合既有的製程無需額外的圖案化製 程，即可增加單位面積之儲存電容，以提供更佳的顯示品質。 ❹And the more serious it is. 200935491 Therefore, there is an urgent need to propose a display panel that improves unit storage capacitance while improving the opening ratio and a method of manufacturing the same. SUMMARY OF THE INVENTION In view of the above-mentioned deficiencies of the prior art, an aspect of the present invention provides a method for forming a display panel, which integrates an existing process without an additional patterning process, thereby increasing the storage capacitance per unit area to provide more Good display quality. ❹
於一實施例，本發明提供一種形成顯示面板之方法，其包 含：提供一基板；形成一電晶體元件於基板上，其中電晶體元 件自基板依序包含一閘極層、一閘極介電層、一半導體層、源 極/没極電極、一絕緣層以及一透明電極；形成一凹凸狀、纟士構' 於基板上，且與電晶體元件相鄰，其中凹凸狀結構係於電晶體 元件之源極/汲極電極形成前，藉由選自形成閘極層、閘極介 電層、以及半導體層之製程所形成；以及形成—電容元件於;^ 凸狀結構，其中電容元件與凹凸狀結構共形，且電容元件係藉 由形成源極/汲極電極、絕緣層以及透明電極之製程所妒成、θ 於各例示實施例’形成凹凸狀結構之步驟可包含藉由 閘極層之製程、形成閘極介電層之製程、形成半導體層之^' 程、形成閘極層及閘極介電層之製程、形成閘極層及半曰導 成閘極介電層及半導體層之製程、或形成閉極/、 閘極；丨電層、以及半導體層之製程所形成。 日 8 200935491 _本發懈另-方面提供—種具有電容元件之顯 不面板，以增加儲存電容面積，而達到增加儲存電容之目的。 於一實施例’本發明之顯示面板包含：一第一 =基板相對第-基板設置、以及—液晶層夾於第 =笑一電晶體元件於-基板上… ❹ ❹ 體兀件自基板依序包含-閘極層、—祕介電層、 及極電極、一絕緣層以及—透明電極；一凹凸狀結 且與電晶體元件相鄰，其中凹凸狀結構係於電晶 η 電極形成前，藉由選自形成閘極層、閘極 Μ電層、以及半導體層之製程所形成；以及一電容元件於凹凸 狀結構，其中電容元件與凹凸狀結構共形。 、 再者’於另一實施例中，第二基板包含 ，目對電容元件設置’以使第-基板及第二基板間具有二= 隙，供容納液晶層。 力个间 【實施方式】 本發明揭露-種齡祕及其製造方法，其具有凹凸狀 錢容轉，喊顺加齡電容且不影 e甚&升開口率之目的。此外，本發明方法整合既有的 程無需額外的圖案化製程’即可增加單位面積之儲存電容，以 提供更佳賴示品質。為了使本發明之敘述更加詳盡與完備， 本發明之上述及其他面向、特徵及優勢將在以下各種更特定之 200935491 ===_㈣㈣，料_的參考編 的相同構件。另外並= 们疋不赞月並不限於特定實施例的細節描述。 之單圖艮據本發明之一實施例而繪示顯示面板 件11〇、—一電m面示意圖。各顯示畫素包含一電晶體元 ❹ ^^，接觸結構(未繪示)^^ 胃中可減少製造電容元件120時m 積進而可相對提升顯示區130的顯示 增加單位儲存電容，如圖1B所示。亦即， Ο 共形的凹凸狀，而增 於凹凸狀結構15G係藉由選自‘體元 ‘戶 刻、閑極介電層、以及半導體層之製程 二月二成電；==;，案:製程。以下 iso之各實施例。件110不同步驟，形成凹凸狀結構 參考圖2八-犯’於本發明第—實施例之顯示面板，其凹凸 狀、、、。構隱係於電晶體元件⑽之源概極電極辦形成 200935491 洳’藉由形成閘極層101之製程所形成。如圖2A所示，本發 明方法包含提供一基板100 ;然後於基板1〇〇上形成一導體 層。舉例而言’基板〗00可為玻璃基板，而導體層可為鉬、鋁、 鈦、銅、銀或其合金等金屬層。而後，利用微影、蝕刻等圖案 化步驟，界定閘極圖案及複數個凹凸結構圖案於導體層，使得 一部份導體層被圖案化成為閛極層101，而另一部份導體層被 圖案化成為凹凸狀結構150A，如圖2A所示。接著，繼續完 〇 成電晶體元件u〇及電容元件12〇的製程步驟。舉例而言，依 序形成閘極介電層102於閘極層101上，形成半導體層1〇3 於閘極介電層1G2上，該半導體層1G3可包括—非晶發層(a_si) 與經由沉積或離子摻雜形成的歐姆接觸層，且利用圖案化 製程界定電晶體元件110之半導體層1〇3及閉極介電層1〇2， 並同時去除凹凸結構150A上之半導體層103及閘極介電層 102。於一例示實施例，閘極介電層1〇2可為氧化矽層、氮化 矽層、氮氧化矽層等單層或多層結構。形成一圖案化半導體層 於電晶體元件110上方。而後，魏式地戦雜層於整個結 Ο 構上’並利用圖案化製程以定出源極/ 凹凸結構職上界定出電容元件12()之第—電歸 圖2C所不。形成絕緣層1〇5於源極/汲極電極1〇4及第一電極 層121上’以作為電晶體元件11〇之層間介電層以及電容元件 120之電容介電層122。此時，於界定絕緣層1〇5於源極/沒極 電極刚上時，同時形成一接觸開口 105A以暴露出源極/汲極 電極104。而後’形成一圖案化透明電極層106，透過接觸開 口 105A與電aa體元件則電性相連’而於電容介電層m上 11 200935491In one embodiment, the present invention provides a method of forming a display panel, comprising: providing a substrate; forming a transistor component on the substrate, wherein the transistor component sequentially includes a gate layer and a gate dielectric from the substrate a layer, a semiconductor layer, a source/polar electrode, an insulating layer, and a transparent electrode; forming a concave-convex shape, a gentleman's structure on the substrate, and adjacent to the transistor element, wherein the concave-convex structure is attached to the transistor Before the source/drain electrodes of the device are formed, formed by a process selected from the group consisting of forming a gate layer, a gate dielectric layer, and a semiconductor layer; and forming a capacitor element in the convex structure, wherein the capacitor element is The concave-convex structure is conformal, and the capacitor element is formed by a process of forming a source/drain electrode, an insulating layer, and a transparent electrode, and θ is formed by forming a concave-convex structure in each of the exemplary embodiments. The process of the layer, the process of forming the gate dielectric layer, the process of forming the semiconductor layer, the process of forming the gate layer and the gate dielectric layer, forming the gate layer and the semi-turned gate dielectric layer and the semiconductor Layer system Form, or form a closed-pole /, gate; tantalum layer, and semiconductor layer process. Day 8 200935491 _ This is a further aspect - providing a display panel with capacitive components to increase the storage capacitor area and increase the storage capacitance. In an embodiment, the display panel of the present invention comprises: a first=substrate opposite to the first substrate, and a liquid crystal layer sandwiched between the first and the elliptical-optical elements on the substrate... ❹ ❹ body parts from the substrate sequentially Including a gate layer, a secret dielectric layer, and a pole electrode, an insulating layer and a transparent electrode; a concave-convex junction adjacent to the transistor element, wherein the concave-convex structure is formed before the formation of the electro-crystalline η electrode Formed by a process selected from the group consisting of forming a gate layer, a gate electrode, and a semiconductor layer; and a capacitor element in the concave-convex structure, wherein the capacitor element conforms to the relief structure. Further, in another embodiment, the second substrate includes a plurality of capacitance elements disposed to have a gap between the first substrate and the second substrate for accommodating the liquid crystal layer. [Embodiment] The present invention discloses an age-related secret and a manufacturing method thereof, which have a concave-convex shape and a capacity change, and the purpose of the aging capacitor is not affected. In addition, the method of the present invention integrates existing processes without the need for an additional patterning process to increase the storage capacitance per unit area to provide better quality. In order to make the description of the present invention more detailed and complete, the above-mentioned and other aspects, features and advantages of the present invention will be in the following specific components of the more specific reference of 200935491 ===_(4)(4). In addition, it is not limited to the detailed description of the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS A single panel of a display panel 11 is shown in accordance with an embodiment of the present invention. Each display pixel includes a transistor element ❹ ^^, and the contact structure (not shown) can reduce the m product in the stomach when the capacitor element 120 is fabricated, thereby increasing the unit storage capacitance relative to the display of the display area 130, as shown in FIG. 1B. Shown. That is, Ο conformal concavo-convex shape, and the addition of the concavo-convex structure 15G is performed by a process selected from the group consisting of a 'body element', a dummy dielectric layer, and a semiconductor layer; Case: Process. The following various embodiments of iso. The member 110 has different steps to form a concave-convex structure. Referring to Fig. 2, the display panel of the first embodiment of the present invention has an uneven shape. The source is formed by the source electrode assembly of the transistor element (10). 200935491 洳' is formed by the process of forming the gate layer 101. As shown in Figure 2A, the method of the present invention includes providing a substrate 100; then forming a conductor layer on the substrate 1A. For example, the substrate 00 can be a glass substrate, and the conductor layer can be a metal layer such as molybdenum, aluminum, titanium, copper, silver, or alloys thereof. Then, using a patterning step such as lithography or etching, the gate pattern and the plurality of relief structures are defined on the conductor layer such that a portion of the conductor layer is patterned into the drain layer 101, and another portion of the conductor layer is patterned. The uneven structure 150A is formed as shown in FIG. 2A. Then, the process steps of completing the transistor element u〇 and the capacitor element 12〇 are continued. For example, the gate dielectric layer 102 is sequentially formed on the gate layer 101 to form a semiconductor layer 1 〇 3 on the gate dielectric layer 1G2, and the semiconductor layer 1G3 may include an amorphous layer (a_si) and An ohmic contact layer formed by deposition or ion doping, and defining a semiconductor layer 1 〇 3 and a closed dielectric layer 1 〇 2 of the transistor element 110 by a patterning process, and simultaneously removing the semiconductor layer 103 on the relief structure 150A and Gate dielectric layer 102. In an exemplary embodiment, the gate dielectric layer 1〇2 may be a single layer or a multilayer structure such as a hafnium oxide layer, a tantalum nitride layer, or a hafnium oxynitride layer. A patterned semiconductor layer is formed over the transistor element 110. Then, the Wei-type doping layer is applied to the entire structure and the patterning process is used to define the source/concave structure to define the first-electrode of the capacitive element 12(). An insulating layer 1?5 is formed on the source/drain electrodes 1?4 and the first electrode layer 121' as an interlayer dielectric layer of the transistor element 11 and a capacitor dielectric layer 122 of the capacitor element 120. At this time, a contact opening 105A is simultaneously formed to expose the source/drain electrode 104 when the insulating layer 1?5 is defined on the source/dot electrode. Then, a patterned transparent electrode layer 106 is formed, which is electrically connected to the electrical aa body element through the contact opening 105A and is disposed on the capacitor dielectric layer 11 200935491
❹ 之透明電極則作為電容元件120之第二電極層123，如圖2D 所示。如此一來’即可藉由變更一個光罩設計，並整合現有製 程步驟而形成凹凸狀結構150A於基板100上，且與電晶體元 件110相鄰’其中凹凸狀結構150八係於電晶體元件110之源 極/汲極電極104形成前’藉由形成閘極層ι〇1之製程所形成。 亦即’本發明於此實施例僅需變更定義閘極層1〇1的光罩圖 案，使其同時具有凹凸狀結構圖案，於姓刻閘極層1〇1時，即 可同時形成凹凸狀結構150A。再者，形成電容元件12〇於凹 凸狀結構150A，可使得電容元件120與凹凸狀結構150A共 形，而可増加單位面積的電容量提升開口率。此外，電容元件 巧包含第-電極層12卜電容介電層122、及第二電極層123) 係藉由形成源極/:及極電極1〇4、絕緣層1〇5以及透明電極1〇6 之製輕所形成，無需額外製程而可實質降低製造成本。 麥哼圖3A-3B ’於本發明第二實施例之顯示面板，其凹凸 ^結構150B係於電晶體元件11〇之源極/沒極電極1〇4形成 藉由形成閘極層1〇1及閘極介電層1〇2之製程所形成。本 =明方法剌賴影、_等_化步驟 ί 1〇2於閘極層⑼上之後，同時界定閉極介電層1〇2、^ :101及複數個凹凸結構15〇Β，使得凹凸狀結構⑽Β係由 Ζ的閘極介電層102及開極層101之材料所構成。選替地， :明亦可在第-實施例界定閘極層101及複數個第一層凹 ^構職後，於界定閘極介電層搬時再次界定由間極介 θ 02之材料構成之第二層凹凸結構刪，於第一層凹凸結 12 200935491 構150A上，而形成凹凸結構15〇B。接著，繼續完成電晶體 元件110及電容元件120的製程步驟，如圖3A所示，其類似 於第一實施例接續形成半導體層1〇3之步驟，於此不再贅述。 亦即，本發明於此實施例藉由變更定義閘極層1〇1的光罩圖案 及/或閘極介電層102的光罩圖案，使其同時具有凹凸狀結構 圖案，於蝕刻閘極層1〇1及閘極介電層1〇2時，即可同時形成 凹凸狀結構150B。再者，如上所述，形成電容元件12〇於雙 層堆疊(即閘極層101及閘極介電層1〇2)之凹凸狀結構15〇B 上，可使得與凹凸狀結構15〇B共形之電容元件12〇具有更顯 著的凹凸狀(即凹凸狀結構之高度差較大）’如圖3B所示。， 參考圖4A-4B ’於本發明第三實施例之顯示面板，其凹凸 狀結構150C係於電晶體元件no之源極/沒極電極1〇4形成 前，藉由形成閘極層ίο卜閘極介電層102、及半導體層1〇3 ，製程所形成。如圖4A所示，本發明方法係利用微影、蝕刻 等圖案化步驟，可於依序形成閘極層1〇1、閘極介電層1〇2及 半導體層103於基板100上之後，同時界定包含半導體層 103、閘極介電層1〇2及閘極層1〇1之閘極結構及複數個凹凸 結構150C，使得凹凸狀結構150C係由部份的半導體層1〇3、 閘極介電層102及閘極層1〇1之材料所構成。選替地，本發明 亦可在第二實施例界定第一層凹凸結構丨5〇A及第二層凹凸社 構1地後，於界定半導體層1〇3時再次界定由半導體層^ 之材料構成之第三層凹凸結構150C，於第二層凹凸結構15〇B， 上，而形成凹凸結構150C。接著，繼續完成電晶體元件11〇 13 200935491 及電容tc件120的製程步驟’其類似於第一實施例接續形成源 極/汲極電極104之步驟’於此不再贅述。亦即，本發明於此 實施例藉由變更定義閘極層10卜閘極介電層1〇2、及/或半導 體層103的光罩圖案’使其同時具有凹凸狀結構圖案於侧 後即可同時形成凹凸狀結構15GC。再者，如上所述，形成電 容元件120於三層堆疊(即閘極層1(H、閘極介電層1〇2及半 導體層103)之凹凸狀結構i5〇c上，可使得與凹凸狀結構The transparent electrode of ❹ serves as the second electrode layer 123 of the capacitor element 120, as shown in Fig. 2D. In this way, the concave-convex structure 150A can be formed on the substrate 100 by changing a mask design and integrating the existing process steps, and adjacent to the transistor element 110. The concave-convex structure 150 is attached to the transistor element. The source/drain electrode 104 of 110 is formed before the process of forming the gate layer ι1. That is, the embodiment of the present invention only needs to change the mask pattern defining the gate layer 1〇1 so as to have a concave-convex structure pattern at the same time, and when the gate layer 1〇1 is surnamed, the concave and convex shape can be simultaneously formed. Structure 150A. Furthermore, the formation of the capacitive element 12 in the concave convex structure 150A allows the capacitive element 120 to be conformed to the concave-convex structure 150A, and the capacitance per unit area can be increased to increase the aperture ratio. In addition, the capacitive element includes the first electrode layer 12 and the second electrode layer 122, and the first electrode layer 12 and the second electrode layer 123 are formed by forming the source/: and the electrode 1〇4, the insulating layer 1〇5, and the transparent electrode 1〇. The system is made of light, and the manufacturing cost can be substantially reduced without additional processes. 3A-3B' In the display panel of the second embodiment of the present invention, the bump structure 150B is formed on the source/dot electrode 1〇4 of the transistor element 11〇 by forming the gate layer 1〇1 And the gate dielectric layer 1〇2 process is formed. After the gate layer (9) is applied, the closed dielectric layer 1〇2, ^:101, and a plurality of concave and convex structures 15〇Β are simultaneously defined, so that the bump is embossed. The structure (10) is composed of the material of the gate dielectric layer 102 and the open layer 101 of the germanium. Alternatively, after the gate electrode layer 101 and the plurality of first layer recesses are defined in the first embodiment, the material of the interpolar dielectric layer θ 02 may be again defined when the gate dielectric layer is defined. The second layer of the concavo-convex structure is deleted on the first layer of the concavo-convex junction 12 200935491 structure 150A to form the concavo-convex structure 15〇B. Then, the process steps of the transistor element 110 and the capacitor element 120 are continued, as shown in FIG. 3A, which is similar to the step of forming the semiconductor layer 1〇3 in the first embodiment, and details are not described herein again. That is, in this embodiment, the reticle pattern defining the gate layer 1 〇 1 and/or the reticle pattern of the gate dielectric layer 102 are modified to have a concave-convex structure pattern at the same time. When the layer 1〇1 and the gate dielectric layer 1〇2, the uneven structure 150B can be simultaneously formed. Furthermore, as described above, the capacitive element 12 is formed on the uneven structure 15〇B of the two-layer stack (ie, the gate layer 101 and the gate dielectric layer 1〇2), so that the concave-convex structure 15〇B can be made. The conformal capacitive element 12A has a more pronounced concavo-convex shape (i.e., the height difference of the uneven structure is large) as shown in Fig. 3B. Referring to FIGS. 4A-4B, a display panel according to a third embodiment of the present invention has a concave-convex structure 150C formed before the source/dot electrode 1〇4 of the transistor element no is formed by forming a gate layer. The gate dielectric layer 102 and the semiconductor layer 1〇3 are formed by a process. As shown in FIG. 4A, the method of the present invention utilizes a patterning step such as lithography or etching to sequentially form the gate layer 1〇1, the gate dielectric layer 1〇2, and the semiconductor layer 103 on the substrate 100. At the same time, the gate structure including the semiconductor layer 103, the gate dielectric layer 1〇2 and the gate layer 1〇1 and the plurality of concave and convex structures 150C are defined such that the concave-convex structure 150C is composed of a part of the semiconductor layer 1〇3, the gate The material of the pole dielectric layer 102 and the gate layer 1〇1 is formed. Alternatively, the present invention may further define the material of the semiconductor layer when defining the semiconductor layer 1〇3 after defining the first layer uneven structure 丨5〇A and the second layer uneven structure 1 in the second embodiment. The third layer uneven structure 150C is formed on the second uneven structure 15B, and the uneven structure 150C is formed. Next, the process steps of the transistor element 11 〇 13 200935491 and the capacitor tc 120 are continued. The steps of forming the source/drain electrode 104 in succession similar to the first embodiment will not be described herein. That is, the embodiment of the present invention changes the gate layer 10 of the gate layer 10, and/or the mask pattern of the semiconductor layer 103 to have a concave-convex structure pattern on the side. The uneven structure 15GC can be formed at the same time. Furthermore, as described above, the capacitor element 120 is formed on the three-layer stack (ie, the bump layer 1 (H, the gate dielectric layer 1 〇 2 and the semiconductor layer 103) has a concave-convex structure i5 〇 c, which allows Structure
150C 共形之電容7C件120具有較第二實闕更顯著的凹凸狀(即凹 凸狀結構之高度差更大），如圖所示。 參考圖5A_5B，於本發明第四實施例之顯示面板，其凹凸 狀結構150D係於電晶體元件11〇之源極/沒極電極1〇4形成 前，僅藉由形成閘極介電層1〇2之製程所形成。如圖5A所示， 本發明方法於毯覆式地形成一導體層於基板丨〇〇上後，利用微 影、、钱刻等圖案化步驟’僅界定閘極圖案於導體層使得導體 層，圖案化成為閘極層1(n，而於此階段不形成凹凸狀結構。 接著’毯覆式形成閘極介電層1G2於隨化後的閘極層1〇1 上，並且利用圖案化製程界定閘極介電層102於閘極層1〇1 上’同時界定複數個㈤凸結構15〇D，使得凹凸結構15〇D僅 由閘極”電層102之材料構成。而後，繼續完成電晶體元件 110及電容元件120㈣程步驟，其類似於第一實施例接續形 ，半導體層103之步驟，於此不再贅述。亦即，本發明於此實 施例藉由變更定朗極介電層1G2的光罩醜，使其同時具有 凹凸狀結構圖案，於餘刻閘極介電層102時，即可同時形成凹 200935491 凸狀結構150D。再者’形成電容元件12〇於凹凸狀結構15〇D， 可使得電容元件120與凹凸狀結構15〇D共形，且電容元件12〇 係藉由形成源極/没極電極1〇4、絕緣層ι〇5以及透明電極1〇6 之製程所形成，如圖5B所示。 ❹ ❹ 參考圖6A-6B，於本發明第五實施例之顯示面板，其凹凸 =結構150E係於電晶體元件11〇之源極/沒極電極1〇4形成 前’藉由形成閘極介電層1〇2及半導體層1〇3之製程所形成。 如圖6A所示’本發明方法形成閘極層1〇1之步驟類似於圖 之第四實施例，係於毯覆式地形成一導體層於基板励上後， =甩微影_等圖案化步驟，僅界定__於導體層，使 得導體層案化成為嶋層1Q卜織於此實糊，可毯覆 式地形成;|電層及半導體層於整個結構上，並圖案化以界定閉 極”電層1〇2及半導體層1〇3，同時界定複數個凹凸結構 =〇E ’使得凹凸狀結構15呢係由部份的閘極介電層⑽及半 田，層1〇3之材料所構成。選替地，本發明亦可在第四實施例 及複數個第—層凹凸結構15GD後，於界 f凸結構咖，於第一層凹凸結構漏上，而开^凸结 料完成益體元件UG及電容元件120的 /，、項似於第—實施例接續形成源極/沒極電極104 柯料。抑，本發册財關藉由變更定 宰:1〇2的光罩圖案及/或半導體層103的光罩圖 茶’使/、叫具有凹凸狀結構圖案。於飯刻_介電層1〇2 15 200935491 及半導體層103時，即可同時形成凹凸狀結構15〇E。再者， 如上所述’藉由形成源極Λ及極電極1〇4、絕緣層1〇5以及透明 電極106之製程，形成電容元件12〇之第一電極121、電容介 電層122及第二電極123於雙層堆疊(即閘極介電層1〇2及半 導體層103)之凹凸狀結構15〇ε上，可使得與凹凸狀結構 150Ε 共形之電容元件120具有較第四實施例之凹凸狀結構15〇D更 顯著的凹凸狀(即凹凸狀結構之高度差較大），如圖6B所示。 ❹ 參考圖7Α·7Β ’於本㈣第六實_之顯和板，其凹凸 狀結構150F係於電晶體元件11〇之源極/沒極電極1〇4形成 前，藉由形成半導體層1G3之製程所形成。如S7A所示，本 發明方法於毯覆式地形成-導體層及介電層於基板1〇〇上 後’利用微影、侧等圖案化步驟，僅界定閘極圖案使得導 體層及介電層被圖案化成為閘極層1〇1及閘極介電層1〇2。接 著’毯覆式形成半導體層103於包含閘極層1〇1及閘極介電層 102之結構上，並且利用圖案化製程界定半導體層103於閘極 介電層102上，同時界定複數個凹凸結構15〇F，使得凹凸結 構M0F僅由半導體層i〇3之材料構成。*後，繼續完成電晶 體το件110及電容元件12〇㈣程步驟，其類似於第一實施例 接續形成源極/祕 1()4之步驟，於此不再魏。亦即， 本發明於此實施例藉由變更定義半導體層1〇3的光罩圖案，使 其同時具有凹凸狀結構圖案，於钱刻半導體層1〇3時，即可同 時形成凹凸狀結構服。再者，形成電容元件12()於凹凸狀 、、、。構150F，可使得電容元件12〇與凹凸狀結構i5〇f共形，且 16 200935491 電谷元件120係藉由形成源極/沒極電極1〇4、絕緣層1〇5以及 透明電極106之製程所形成，如圖7B所示。 此外’本發明同時提供一種顯示面板，其具有如上所述之 凹凸狀的電容元件。參考圖8，於一實施例，顯示面板j包含 ，基板10、第二基板2〇相對於第一基板1〇設置、以及液 晶層30夾於第一基板1〇及第二基板2〇之間。於此實施例， ❹ 第一基板10可包含電晶體元件110、凹凸狀結構150於基板 1〇〇上、電容元件120於凹凸狀結構15〇上。亦即，第一基板 10可為上述第-至第六實施例中具有不同凹凸結構 i5〇a-i5〇f之任-基板結構。其中電晶體元件11〇自基板1〇〇 依序包含閘極層1G卜閘極介電層1G2、包含雜級極擴散區 103A及通道區ι〇3Β於其間之半導體層⑽、源極级極電極 1 曰04、絕緣層1〇5以及透明電極1〇6。凹凸狀結構15〇係與電 晶體元件no相鄭，且凹凸狀結構15〇係於電晶體元件11〇之 ’原極/汲極電極104形▲前，藉由選自形成閘極層101、閘極介 f層102、以及半導體層1〇3之製程所形成。因電容元件⑼ 係形成於凹凸狀結構⑼上，使得電容元件⑽與凹凸狀結構 150共开^。一如此’即可達成本發明於給定面積下，藉由形成凹 凸狀=元件12〇而增加單位儲存電容之功效。相對而言對 於給定單_存電容而言，本發日續由形成凹凸狀電容元件 120可有效縮減所需耗用的基板面積*有效增加顯示面板 開口率。 200935491 此外，第二基板2〇包含一具有濾光層21〇之基板2〇〇(例 如玻璃基板)上、-凸塊22〇於滤光層21〇上以及一共同電 極230於，慮光層21〇及凸塊22〇上。其中，滤光層別係用以 過濾、背光模組(未繪示)所提供之光源為狀波長之光束，且濾 光^ 2io相對於電容元件⑼之位置界定一開口扣。凸塊π。 覆蓋此開口 212，使得凸塊22G係相對電容元件12G設置，以 使第-基板10及第二基板20間具有不同尺寸之間隙(如dl及 d2所示），供容納液晶層3〇。換言之，單位畫素内因不同尺寸 之間隙(如dl及d2所示）’可使得經凸塊22〇折射而被電容元 件120反射的光(如箭頭a所示)具有光行進路徑長度u，其 與未經電容元件反射之穿透光(如箭頭B所示)具有的光行進 路徑長度L2差異降至最小’進而達到均勻顯示的功效。凸塊 220的材料可為任何達到上述目的之適當材料，例如介電層， 但不以此為限。 日 此外，本發明雖以數個矩形形狀表示凹凸狀結構15〇，熟 Ο 此技藝者當知本發明所欲形成之凹凸狀結構依據不同應用及 設計需求可包含其他的幾何形狀，例如拱型、三角形等"，而凹 凸狀結構的數目亦不以實施例所示為限’其可為任何適當數目 且可為連續或不連續形狀。此外’舉例而言，凹凸狀社:較佳 具有約0.1 yrn至2/zm之厚度(亦即南度差），然而凹凸狀纟士構 之厚度可依所欲形成之電容元件變化，不以實施例所述為'丨^。 以上所述僅為本發明之較佳實施例而已，並非用以阳+本The 150C conformal capacitor 7C member 120 has a more pronounced concavo-convex shape than the second solid (i.e., the height difference of the concave convex structure is larger) as shown. Referring to FIGS. 5A-5B, in the display panel of the fourth embodiment of the present invention, the concave-convex structure 150D is formed before the source/dot electrode 1〇4 of the transistor element 11 is formed, and only the gate dielectric layer 1 is formed. The process of 〇2 is formed. As shown in FIG. 5A, after the method of the present invention forms a conductor layer on the substrate on the substrate, the patterning step of lithography, etching, etc. is used to define only the gate pattern on the conductor layer to make the conductor layer. Patterning becomes the gate layer 1 (n, and no uneven structure is formed at this stage. Then, the gate dielectric layer 1G2 is formed on the gate layer 1〇1 after the blanket, and the patterning process is utilized. Defining the gate dielectric layer 102 on the gate layer 1〇1 simultaneously defines a plurality of (five) convex structures 15〇D such that the relief structure 15〇D is composed only of the material of the gate “electric layer 102.” The steps of the crystal element 110 and the capacitor element 120 are similar to those of the first embodiment, and the steps of the semiconductor layer 103 are omitted here. That is, the present invention changes the dielectric layer by changing the dielectric layer. The mask of 1G2 is ugly, so that it has a concave-convex structure pattern at the same time. When the gate dielectric layer 102 is left, the concave 200935491 convex structure 150D can be simultaneously formed. Further, the capacitive element 12 is formed on the concave-convex structure 15 〇D, the capacitive element 120 and the concave-convex structure 15 can be made The 〇D is conformal, and the capacitor element 12 is formed by a process of forming the source/dot electrode 1〇4, the insulating layer 〇5, and the transparent electrode 1〇6, as shown in FIG. 5B. ❹ ❹ Reference drawing 6A-6B, in the display panel of the fifth embodiment of the present invention, the bump = structure 150E is formed before the source/dot electrode 1〇4 of the transistor element 11 is formed by forming the gate dielectric layer 1〇. 2 and the process of the semiconductor layer 1〇3. As shown in FIG. 6A, the step of forming the gate layer 1〇1 by the method of the present invention is similar to the fourth embodiment of the figure, forming a conductor layer in a blanket manner. After the substrate is energized, the patterning step of 甩 甩 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The semiconductor layer is over the entire structure and patterned to define the closed-electrode "electrode layer 1"2 and the semiconductor layer 1"3, while defining a plurality of concavo-convex structures = 〇E' such that the concavo-convex structure 15 is partially gated The dielectric layer (10) and the field, the material of the layer 1〇3. Alternatively, the invention may also be in the fourth embodiment and the plurality of first layer recesses After the structure 15GD, the convex structure of the first layer is leaked on the first layer, and the convex material is used to complete the body element UG and the capacitance element 120, and the item is similar to the first embodiment to form the source. / No-electrode electrode 104. In this book, the fiscal certificate is changed to a fixed pattern: a mask pattern of 1〇2 and/or a mask pattern of the semiconductor layer 103 is made to have a concave-convex structure pattern. In the case of the rice layer _ dielectric layer 1 〇 2 15 200935491 and the semiconductor layer 103, the uneven structure 15 〇 E can be simultaneously formed. Further, as described above, 'by forming the source Λ and the electrode 1 〇 4, the insulation The process of the layer 1〇5 and the transparent electrode 106 forms the first electrode 121 of the capacitor element 12, the capacitor dielectric layer 122 and the second electrode 123 in a double layer stack (ie, the gate dielectric layer 1〇2 and the semiconductor layer 103) The concavo-convex structure 15 〇 ε can make the capacitance element 120 conforming to the concavo-convex structure 150 具有 have a more prominent concavo-convex shape than the concavo-convex structure 15 〇 D of the fourth embodiment (that is, the height difference of the concavo-convex structure is higher Large), as shown in Figure 6B. ❹ Referring to FIG. 7Α·7Β 'in this (four) sixth real_ display panel, the concave-convex structure 150F is formed before the source/dot electrode 1〇4 of the transistor element 11〇, by forming the semiconductor layer 1G3 The process is formed. As shown in S7A, the method of the present invention uses a lithography, side, etc. patterning step after blanket-forming the conductor layer and the dielectric layer on the substrate 1 to define only the gate pattern such that the conductor layer and the dielectric layer The layer is patterned into a gate layer 1〇1 and a gate dielectric layer 1〇2. Then, the semiconductor layer 103 is formed on the structure including the gate layer 1〇1 and the gate dielectric layer 102, and the semiconductor layer 103 is defined on the gate dielectric layer 102 by using a patterning process, and a plurality of layers are defined. The uneven structure 15〇F is such that the uneven structure M0F is composed only of the material of the semiconductor layer i〇3. After that, the steps of the electro-optical device 110 and the capacitive element 12 (four) steps are continued, which is similar to the step of forming the source/secret 1 () 4 in the first embodiment, and is not used here. That is, in the embodiment of the present invention, the reticle pattern defining the semiconductor layer 1 〇 3 is changed to have a concave-convex structure pattern at the same time, and when the semiconductor layer 1 〇 3 is etched, the embossed structure can be simultaneously formed. . Further, the capacitor element 12 is formed in a concavo-convex shape. The structure 150F is such that the capacitive element 12 is conformal to the concave-convex structure i5〇f, and the 16200935491 electric valley element 120 is formed by forming the source/dot electrode 1〇4, the insulating layer 1〇5, and the transparent electrode 106. The process is formed as shown in Fig. 7B. Further, the present invention simultaneously provides a display panel having a concave-convex capacitive element as described above. Referring to FIG. 8 , in an embodiment, the display panel j includes a substrate 10 , a second substrate 2 , disposed opposite to the first substrate 1 , and a liquid crystal layer 30 sandwiched between the first substrate 1 and the second substrate 2 . . In this embodiment, the first substrate 10 may include a transistor element 110, a concave-convex structure 150 on the substrate 1, and a capacitive element 120 on the concave-convex structure 15A. That is, the first substrate 10 may be any substrate structure having different uneven structures i5〇a-i5〇f in the above-described first to sixth embodiments. The transistor element 11 includes a gate layer 1G, a gate dielectric layer 1G2, a semiconductor layer (10) including a hetero-polar diffusion region 103A and a channel region ι〇3, and a source-level electrode. Electrode 1 曰 04, insulating layer 1 〇 5, and transparent electrode 1 〇 6. The concavo-convex structure 15 is in phase with the transistor element no, and the concavo-convex structure 15 is before the 'primary/drain electrode 104 shape ▲ of the transistor element 11', and is selected from the step of forming the gate layer 101, The gate dielectric layer 102 and the semiconductor layer 1〇3 are formed. Since the capacitive element (9) is formed on the uneven structure (9), the capacitive element (10) is opened together with the uneven structure 150. By doing so, it is possible to achieve the effect of the present invention to increase the unit storage capacitance by forming a concave convex shape = element 12 给 under a given area. Relatively speaking, for a given single-capacitance capacitor, the formation of the concave-convex capacitive element 120 can effectively reduce the required substrate area* to effectively increase the aperture ratio of the display panel. 200935491 In addition, the second substrate 2 〇 includes a substrate 2 〇〇 having a filter layer 21 〇〇 (for example, a glass substrate), a bump 22 〇 on the filter layer 21 以及, and a common electrode 230 , the light shielding layer 21 〇 and the bump 22 〇. The filter layer is used for filtering, the light source provided by the backlight module (not shown) is a light beam of a wavelength, and the filter is defined by an opening buckle with respect to the position of the capacitive element (9). Bump π. The opening 212 is covered such that the bumps 22G are disposed relative to the capacitive element 12G such that the first substrate 10 and the second substrate 20 have gaps of different sizes (as indicated by dl and d2) for accommodating the liquid crystal layer 3''. In other words, the unit pixels are different in the gaps of different sizes (as indicated by dl and d2) so that the light reflected by the convex element 22 而 and reflected by the capacitive element 120 (as indicated by the arrow a) has a light travel path length u, which The difference in the length of the light travel path L2 with the transmitted light reflected by the non-capacitive element (as indicated by the arrow B) is minimized to achieve the effect of uniform display. The material of the bumps 220 may be any suitable material for achieving the above purpose, such as a dielectric layer, but is not limited thereto. In addition, although the present invention expresses the concave-convex structure 15 数 in a plurality of rectangular shapes, it is known to those skilled in the art that the concave-convex structure to be formed by the present invention may include other geometric shapes according to different applications and design requirements, such as arching. And triangles, etc., and the number of embossed structures is not limited to the examples shown. It may be any suitable number and may be continuous or discontinuous. Further, 'for example, the embossing: preferably has a thickness of about 0.1 yrn to 2/zm (that is, a south difference), but the thickness of the embossed gentleman can vary depending on the desired capacitive element, not The embodiment is described as '丨^. The above description is only a preferred embodiment of the present invention, and is not used for yang + this
顯示面板之各階 200935491 【圖式簡單說明】 之單圖係根據本發歡-實施_繪示顯示面板 之早畫素的上視及截面示意圖； 极 段之顯示本發明第—實施例製作顯示面板之各階 段之圖3Β_示本伽第三實_製作_面板之各階 圖4Α_4Β係顯示本發明第三實施例 夜之示意圖； 段之=Α^5Β係顯示本發明第四實施例製作顯示面板之各階 段之:=6Β係顯示本發明第五實施例製作顯示面板之各階 圖 7Α-7Β 禮 η _ 段之示意圖；#.、标本發六實施例製作顯和板之各階 發明―實施狀騎岐之讀、圖；以及 面示意圖。軸示f知顯示面板之單—晝素的上視及截 19 200935491Each step of the display panel 200935491 [Simplified description of the drawing] The single drawing of the display panel according to the present invention - the upper and lower cross-sectional views of the display panel of the display panel; the display of the pole segments - the display panel of the first embodiment of the present invention FIG. 3 Β 示 本 第三 第三 第三 第三 第三 制作 制作 制作 制作 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; At each stage of the following: =6Β shows the various steps of the display panel of the fifth embodiment of the present invention. Figure 7Α-7Β η _ _ section schematic diagram; #., specimens of the six embodiments of the production of the display board of the various stages of the invention - implementation ride Reading, drawing; and surface diagram. The axis shows the top view of the display panel and the cut-off 19 200935491
【主要元件符號說明】 1 顯示面板 10 第一基板 20 第二基板 30 液晶層 91 薄膜電晶體元件 92A、92B 電極板 92 電容元件 93 顯不區 94 資料線 100 基板 101 閘極層 102 閘極介電層 103 半導體層 104 源極/汲極電極 105 A 接觸開口 105 絕緣層 106 透明電極 110 電晶體元件 120 電容元件 121 第一電極層 122 電容介電層 20 200935491[Main component symbol description] 1 display panel 10 first substrate 20 second substrate 30 liquid crystal layer 91 thin film transistor element 92A, 92B electrode plate 92 capacitive element 93 display area 94 data line 100 substrate 101 gate layer 102 gate dielectric Electrical layer 103 semiconductor layer 104 source/drain electrode 105 A contact opening 105 insulating layer 106 transparent electrode 110 transistor element 120 capacitive element 121 first electrode layer 122 capacitor dielectric layer 20 200935491
123 第二電極層 130 顯不區 140 資料線 150、150A、 150B、150C、150D、150E、 150B，、 .第二層凹凸結構 150C， 第三層凹凸結構 150E’ 第二層凹凸結構 210 濾光層 220 凸塊 230 共同電極 凹凸狀結構 ❹ 21123 second electrode layer 130 display area 140 data lines 150, 150A, 150B, 150C, 150D, 150E, 150B, . second layer relief structure 150C, third layer relief structure 150E' second layer relief structure 210 filter Layer 220 bump 230 common electrode concave-convex structure ❹ 21