200935227 ’九、發明說明： *【發明所屬之技術領域】 本發明係關於一種SPI (SeHal Pedphefal Interface，串列週邊設備介面）設備通訊電路。 【先前技術】 在電腦系統中，SPI是一種允許在兩種設備（一 個稱主设備，另一個稱從設備）之間進行串列資料交 ❹換之介面。SPI最常應用於電腦系統之cpu(Central Processing Unit ’中央處理器）與週邊晶片之間之通 訊電路糸統中，當SPI匯流排有晶片選擇cs ( chip Select)訊號時’ SPI匯流排才可進行資料之接收和發送， 一般CPU所挺供之SPI匯流排數量有限。 請參考圖1 ,當CPU 1〇〇需要透過SPI匯流排 300 與 PIC ( Peripheral Interface controller，週邊設 備控制器）200進行通訊時，通常之做法是：該pic © 200之SPI匯流排控制單元透過該sp〗匯流排3〇〇 與該C P U 10 0之S PI匯流排控制單元相連，即該 €?11100之晶片選擇埠€8與該卩1匸200之一控制埠 P相連，該CPU 100之串列資料輸出埠SD0與該PIC 200之資料登錄埠DIN相連’該CPU 100之串列資 料登錄埠SDI與該PIC 200之資料輸出淳D〇UT相 連，該CPU 100之串列時脈埠SCLK與該PIC 200 之時脈谭S相連’該PIC 200連接一前端裝置4〇〇 (如記憶體），該PIC 200接收該前端裝置4〇〇之 200935227 • 資訊並將該資訊傳送給該CPU 100,並將該CPU 100 •發送之指令轉換為控制訊號傳送給該前端裝置400 以控制其完成相應之操作。 習知技術中，該CPU 100透過該SPI匯流排300僅能 與一個該PIC 200通訊，當該CPU 100需透過SPI匯流排 300與多個PIC 200進行通訊時，則會產生SPI匯流排不 夠使用之問題。 0【發明内容】 鑒於上述内容，有必要提供一種可擴充SPI匯流排之 SPI設備通訊電路，以解決SPI匯流排使用數量不足之問 題。 一種SPI設備通訊電路，包括一主設備、複數從 設備及SPI匯流排，該主設備包括一 SPI匯流排控 制單元，該主設備之SPI匯流排控制單元包括一晶 片選擇埠，每一從設備包括一 SPI匯流排控制單元， 〇其中一從設備包括複數GPIO引腳，每一從設備之 SPI匯流排控制單元包括一選通埠，該主設備之晶片 選擇埠連接具 GPIO引腳之從設備之選通埠，該 GPIO引腳分別連接其他從設備之SPI匯流排控制單 元之選通埠，當該主設備與該等從設備通訊時，該主設 備發送一具有位址訊號之指令給該具GPIO引腳之從設 備，該具GPIO引腳之從設備判斷該位址訊號是否與 自己之一致，如果一致則執行該主設備發送之指 令，如果不一致則接收該主設備發送之指令並透過其 200935227 GPIO引腳將該指令中之位址訊號傳送給其他從設備之奶 匯流排控制單元之選通埠，其他從設備判斷該指令中之位 址訊號是否與自己之位址訊號相一致，如果一致^執行該200935227 </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> < Desc/Clms Page number> [Prior Art] In a computer system, SPI is an interface that allows serial data exchange between two devices (one called a master device and the other called a slave device). SPI is most commonly used in the communication circuit between the CPU (Central Processing Unit 'central processing unit) and the peripheral chip of the computer system. When the SPI bus has a chip select cs (chip Select) signal, the SPI bus can only be used. For the receiving and sending of data, the number of SPI busbars that the CPU generally provides is limited. Referring to FIG. 1, when the CPU 1 needs to communicate with the PIC (Peripheral Interface Controller) 200 through the SPI bus 300, the usual practice is: the pic IMS SPI bus control unit transmits the The sp bus 3 is connected to the S PI bus control unit of the CPU 10, that is, the wafer selection of the €11100 is connected to the control port P of the 卩1匸200, and the CPU 100 is connected. The column data output 埠SD0 is connected to the data register 埠DIN of the PIC 200. The serial data registration 埠SDI of the CPU 100 is connected to the data output 淳D〇UT of the PIC 200, and the serial clock 埠SCLK of the CPU 100 is The PIC 200 is connected to a clock device S connected to a front end device 4 (such as a memory), and the PIC 200 receives the front end device 4 200935227 • information and transmits the information to the CPU 100, The CPU 100 • the transmitted command is converted into a control signal and transmitted to the front end device 400 to control the completion of the corresponding operation. In the prior art, the CPU 100 can only communicate with one PIC 200 through the SPI bus 300. When the CPU 100 needs to communicate with multiple PICs 200 through the SPI bus 300, the SPI bus is insufficient for use. The problem. 0 [Invention] In view of the above, it is necessary to provide an SPI device communication circuit that can expand the SPI bus to solve the problem of insufficient number of SPI buss. An SPI device communication circuit includes a master device, a plurality of slave devices, and an SPI bus bar. The master device includes an SPI bus bar control unit, and the SPI bus bar control unit of the master device includes a chip selection port, and each slave device includes An SPI bus control unit, wherein one of the slave devices includes a plurality of GPIO pins, and each slave device's SPI bus bar control unit includes a strobe device, and the master device chip selects a slave device with a GPIO pin After the strobe, the GPIO pins are respectively connected to the strobes of the SPI bus control units of the other slave devices. When the master device communicates with the slave devices, the master device sends an instruction with an address signal to the device. The slave device of the GPIO pin, the slave device with the GPIO pin determines whether the address signal is consistent with oneself, and if yes, executes the instruction sent by the master device, and if not, receives the command sent by the master device and passes through the command 200935227 The GPIO pin transmits the address signal in the instruction to the strobe of the milk bus control unit of the other slave device, and the other slave devices judge the command. Bit signal whether the site is consistent with the address signal of its own, if the implementation of the agreement ^
主設備所發送之指令，如衫—㈣錢行該主設備所= 送之指令。 X 相較習知技術，該CPU之SPI s流排控制單元透過 該SPI匯流排發送指令訊號給每一 PIC之SPI匯流排控制 〇單元，設置一 PIC可以直接與該CPU進行通訊，透過該 PIC之GPI0引腳進-步控制其他PIC可以與該CPU進行 通訊’使該CPU透過設置之PIC擴充了 SPI匯流排之 使用數量。 【實施方式】 請參考圖2，本發明SPI設備通訊電路之較佳實施方 式包括一主設備10 (如CPU)，四個從設備如PIC 2〇、 22、24及26，SPI匯流排30及四個前端裝置4〇、 〇 42、44及46，該從設備及該前端裝置之數量可根據 實際情況相應地增加或減少。 該CPU 10包括一 SPI匯流排控制單元，該SPI 匯流排控制單元包括一晶片選擇埠CS、一串列資料 輸出埠SDO、一串列資料登錄埠SDI及—串列時脈 埠 SCLK。 每一 PIC包括一 SPI匯流排控制單元及複數 GPI0( General purpose input/output，通用輪入輸出） 引腳。該PIC 20之SPI匯流排控制單元包括一選通 200935227 • 埠P0，該PIC 22之SPI匯流排控制單元包括一選通 -埠P1，該PIC 24之SPI匯流排控制單元包括一選通 埠P2，談PIC 26之SPI匯流排控制單元包括一選通 埠P3，每一 PIC還包括一資料登錄埠DIN、一資料 輸出埠D0UT及一時脈埠S。 其中，該CPU 10之SPI匯流排控制單元透過該 SPI匯流排30分別與該等PIC20、PIC22、PIC24及 _ P 1C26之SPI匯流排控制單元相連，即該CPU 10之 〇 SPI匯流排控制單元之晶片選擇璋CS與該PIC20之 選通埠P0相連，該CPU 10之串列資料輸出埠SDO 分別連接該等PIC20、PIC22、PIC24及PIC26之資 料登錄埠DIN，該CPU 10之串列資料登錄埠SDI 分別連接該等PIC20、PIC22、PIC24及PIC26之資 料輸出埠DOUT，該CPU 10之串列時脈埠分別連接 該等 PIC20、PIC22、PIC24 及 PIC26 之時脈槔 S。 〇該PIC20之三個GPIO引腳分別連接該等PIC22、 PIC24及 PIC26之 SPI匯流排控制單元之選通埠 PI、P2 及 P3，該等 PIC20、PIC22、PIC24 及 PIC26 分別連接前端裝置40、42、44、46，該等PIC 20、 22、24、26接收對應前端裝置40、42、44、46之 資訊並將該資訊傳送給該CPU 10，並將該CPU 10 發送之指令轉換為控制訊號傳送給該等前端裝置 4 0、4 2、4 4、4 6以控制其完成相應之操作。 本實施方式中，利用該PIC20之三個GPIO引 10 200935227 腳可以將SPI匯流排擴充為四組，進而可以連接四 * 個 PIC 。 工作時，當該CPU 10與多個PIC通訊時，首先必須 為每一 PIC設定一個位址訊號，當該CPU 10向該PIC發 送指令時先送出一位址訊號，每一 pic判斷該位址訊號是 否與自己之位址訊號相一致，如果一致則執行該CPU 10 所發送之指令，如果不一致則不執行該CPU 10所發送之 Q指令。當該CPU 10發出之指令中之位址訊號與該PIC20 之位址訊號一致時，則該CPU 10與該PIC20進行通訊， 當該CPU10發出之指令中之位址訊號與該PIC20之位址 訊號不一致時，該PIC20接收該CPU 10發送之指令並透 過其GPIO引腳將該指令訊號中之位址訊號傳送給該等 PIC22、PIC24及PIC26之SPI匯流排控制單元之選通 埠PI、P2及P3，該等PIC22、PIC24及PIC26判斷該 指令中之位址訊號是否與自己之位址訊號相一致，如果一 〇致則執行該CPU 10所發送之指令，如果不一致則不執行 該CPU 10所發送之指令，因此該CPU 10透過其發送之指 令中之位址訊號選擇一 PIC與自己通訊。 透過本發明之實施方式，該CPU 10之SPI匯流排控 制單元透過該SPI匯流排30發送指令訊號給一 PIC之SPI 匯流排控制單元，設置該PIC可以直接與該CPU10進行通 訊，透過該PIC之GPIO引腳進一步控制其他PIC可以與 該CPU 10進行通訊，從而解決了 SPI匯流排不夠使用之 問題。該SPI通訊電路方法簡單、成本低。 11 200935227 利申述、，本發明符合發明專利要件，爰伕法提出專 ^ ，以上所述者僅為本發明之具體實施方式，^ 凡熟悉本案技藝之人+，乂, 也万式，舉 在犮依本^明精相作之等效修 飾或變化，白應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 圖1為習知之SPI設備通訊原理圖。 Ο 圖2為本發明SPI設備通訊電路之較佳實施方式之原 理圖。 【主要元件符號說明】 主設備 10 從設僙 2〇、22、24、26 SPI匯流排30 前端裝置4〇、42、44、46The instructions sent by the master device, such as the shirt-(four) money line, the master device = send instructions. Compared with the prior art, the SPI s stream control unit of the CPU sends a command signal to each PIC SPI bus control unit through the SPI bus, and a PIC can be directly communicated with the CPU through the PIC. The GPI0 pin advances to control other PICs to communicate with the CPU' to enable the CPU to expand the number of SPI busses used by the set PIC. [Embodiment] Referring to FIG. 2, a preferred embodiment of the SPI device communication circuit of the present invention includes a master device 10 (such as a CPU), four slave devices such as PIC 2, 22, 24, and 26, and a SPI bus 30. The four front-end devices 4〇, 〇42, 44 and 46, the number of the slave device and the front-end device can be increased or decreased according to the actual situation. The CPU 10 includes an SPI bus control unit including a chip select 埠CS, a serial data output 埠SDO, a serial data register 埠SDI, and a serial clock 埠SCLK. Each PIC includes a SPI bus control unit and a plurality of GPI0 (General purpose input/output) pins. The PIC 20 SPI bus control unit includes a strobe 200935227 • 埠P0, the PIC 22 SPI bus control unit includes a strobe-埠P1, and the PIC 24 SPI bus control unit includes a strobe P2 The PIC 26 SPI bus control unit includes a strobe P3, and each PIC further includes a data register 埠 DIN, a data output 埠 D0UT, and a clock 埠 S. The SPI bus control unit of the CPU 10 is connected to the SPI bus control units of the PIC20, PIC22, PIC24, and _P1C26 through the SPI bus 30, that is, the SPI bus control unit of the CPU 10. The chip select 璋CS is connected to the PIC20 strobe 埠P0, and the serial data output 埠SDO of the CPU 10 is respectively connected to the PIC20, PIC22, PIC24, and PIC26 data registration 埠DIN, and the CPU 10 serial data registration 埠SDI is connected to the data outputs 埠DOUT of the PIC20, PIC22, PIC24, and PIC26, respectively. The serial clock of the CPU 10 is connected to the clocks S of the PIC20, PIC22, PIC24, and PIC26, respectively.三个The three GPIO pins of the PIC20 are connected to the strobes PI, P2 and P3 of the PIC24, PIC24 and PIC26 SPI bus control units respectively. The PIC20, PIC22, PIC24 and PIC26 are connected to the front-end devices 40 and 42 respectively. 44, 46, the PIC 20, 22, 24, 26 receive the information corresponding to the front end device 40, 42, 44, 46 and transmit the information to the CPU 10, and convert the command sent by the CPU 10 into a control signal It is transmitted to the front end devices 40, 4 2, 4 4, 4 6 to control their completion of the corresponding operations. In this embodiment, the PIC bus can be expanded into four groups by using the three GPIO pins of the PIC20, and the four PICs can be connected. During operation, when the CPU 10 communicates with multiple PICs, an address signal must first be set for each PIC. When the CPU 10 sends an instruction to the PIC, a bit signal is sent first, and each pic determines the address. Whether the signal is consistent with its own address signal, if it is consistent, the instruction sent by the CPU 10 is executed, and if it is inconsistent, the Q command sent by the CPU 10 is not executed. When the address signal in the instruction issued by the CPU 10 coincides with the address signal of the PIC20, the CPU 10 communicates with the PIC20, and the address signal in the instruction issued by the CPU 10 and the address signal of the PIC20 In case of inconsistency, the PIC20 receives the command sent by the CPU 10 and transmits the address signal in the command signal through the GPIO pin to the strobes PI, P2 of the SPI bus control units of the PIC22, PIC24 and PIC26. P3, the PIC22, the PIC24, and the PIC26 determine whether the address signal in the instruction is consistent with the address signal of the instruction, and if so, execute the instruction sent by the CPU 10. If not, the CPU 10 is not executed. The instruction is sent, so the CPU 10 selects a PIC to communicate with itself through the address signal in the instruction sent by the CPU 10. Through the embodiment of the present invention, the SPI bus control unit of the CPU 10 sends an instruction signal to the SPI busbar control unit through the SPI bus 30, and the PIC can directly communicate with the CPU 10 through the PIC. The GPIO pin further controls other PICs to communicate with the CPU 10, thereby solving the problem of insufficient use of the SPI bus. The SPI communication circuit is simple in method and low in cost. 11 200935227 Lishen said that the present invention meets the requirements of the invention patent, and the above-mentioned method is only a specific embodiment of the present invention. ^ Those who are familiar with the skill of the present invention are +, 乂, 万, Equivalent modifications or changes in accordance with the principles of this article shall be covered by the following patents. [Simple description of the diagram] Figure 1 is a schematic diagram of the communication of the conventional SPI device. Figure 2 is a schematic diagram of a preferred embodiment of a communication circuit for an SPI device of the present invention. [Main component symbol description] Master device 10 Slave 2僙, 22, 24, 26 SPI busbar 30 Front-end devices 4〇, 42, 44, 46
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