TW200931531A - Method for forming cu wiring - Google Patents

Method for forming cu wiring Download PDF

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Publication number
TW200931531A
TW200931531A TW97140653A TW97140653A TW200931531A TW 200931531 A TW200931531 A TW 200931531A TW 97140653 A TW97140653 A TW 97140653A TW 97140653 A TW97140653 A TW 97140653A TW 200931531 A TW200931531 A TW 200931531A
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Taiwan
Prior art keywords
layer
forming
wiring
hole
trench
Prior art date
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TW97140653A
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Chinese (zh)
Inventor
Tatsuo Hatano
Atsushi Gomi
Yasushi Mizusawa
Masamichi Hara
Takashi Sakuma
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Tokyo Electron Ltd
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Publication of TW200931531A publication Critical patent/TW200931531A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for forming a Cu wiring is provided with a step of preparing a structure having a silicon substrate, a Low-k film, which is on the substrate with a trench, and a barrier layer on the film; a step of forming a layer to be wetted, on the barrier layer by CVD by using a metal material to be wetted with Cu; a step of forming a Cu layer by PVD on the layer to be wetted; and a step of heating the silicon substrate to have the Cu layer flow after forming the Cu layer and making Cu flow into a trench.

Description

200931531 九、發明說明 【發明所屬之技術領域】 本發明是例如有關在形成於半導體晶圓等的基板之具 有溝槽或洞的低介電常數層間絶縁膜等所定的層隔著障蔽 層來形成Cu配線之Cu配線的形成方法。 【先前技術】 u 近來’對應於半導體裝置的高速化、配線圖案的微細 化、高集成化的要求’而被要求配線間的電容降低及配線 的導電性提升及電遷移（Electromigration)耐性的提升， 因應於此的技術，有配線材料使用比鋁（A1)或鎢（W) 更導電性高且電遷移耐性佳的銅（Cu)，使用低介電常數 膜（Low-k膜）作爲層間絶縁膜之Cu多層配線技術受到 注目。 此時的Cu配線的形成方法，例如在形成有溝槽或洞 φ 的Low-k膜，以濺射爲代表的物理蒸鍍法（PVD)來形成 由Ta、TaN、Ti等所構成的障蔽層，在其上同樣藉由PVD 來形成Cu種子（seed)層，更在其上實施Cu電鍍的技術 爲人所知（例如特開平1 1 -340226號公報）。 然而，半導體裝置的設計規範（Design Rule)日益微 細化，在今後的3 2nm節點以後，像上述特開平 11-340226公報所揭示那樣的技術是難以藉由階梯覆蓋率 (Step Coverage)本質低的PVD來形成Cu種子層於溝槽 或洞内，因此可預料在洞内形成電鍍的情形也是困難的。 -5- 200931531 並且，在電鍍製程中是在埋入微細配線時，必需添加 劑，其管理上花費很大的成本，成爲成本提高的要因。而 且，該添加劑會殘留於配線，成爲配線電阻上昇的要因。 【發明內容】 本發明的目的是在於提供一種即使在微細的溝槽或洞 也可確實地埋入Cu之Cu配線的形成方法。 0 本發明的其他目的是在於提供一種可不用電鍍，或極 力減少電鍍的使用，來形成Cu配線之Cu配線的形成方 法。 若根據本發明的第1觀點，則可提供一種Cu配線的 形成方法，其特徵係具有下列步驟： 準備一具有：基板、及形成於其上之具有溝槽或洞的 所定的層、及形成於其上的障蔽層之構造體； 在上述障蔽層上藉由CVD來形成以Cu會浸潤的金屬 〇 材料所構成的被浸潤層； 在上述被浸潤層上藉由PVD來形成Cu層；及 在形成Cu層之後’加熱基板來使Cu層流動’在溝槽 或洞内流入c u。 在上述第1觀點中，上述CU層的厚度’較理想是5 〜5 Onm 〇 若根據本發明的第2觀點，則可提供一種Cu配線的 形成方法，其特徵係具有下列步驟： 準備一具有：基板、及形成於其上之具有溝槽或洞的 -6 - 200931531 所定的層、及形成於其上的障蔽層之構造體； 在上述障蔽層上藉由CVD來形成以Cu會浸潤的金屬 材料所構成的被浸潤層； 在上述被浸潤層上藉由PVD來形成Cu層； 在形成Cu層之後，加熱基板來使Cu層流動，至溝槽 或洞内的途中流入Cu;及 然後，形成Cu電鍍層，將溝槽或洞予以完全塡埋。 @ 在上述第2觀點中，上述Cu層的厚度，較理想是5 〜3 0 nm 〇 在上述第1、第2觀點中，上述被浸潤層，較理想是 以Ru所構成。並且，加熱上述基板時的温度，較理想是 250〜350 °C。又，上述被浸潤層的厚度，較理想是1〜 5nm ° 若根據本發明，則在障蔽層上，PVD之Cu層的形成 前，藉由階梯覆蓋率佳的CVD來形成以Cu會浸潤的金屬 ❹ 材料所構成的被浸潤層，藉此也可使被浸潤層遍及微細的 溝槽或洞，然後在被浸潤層上藉由PVD來形成Cu層，因 此即使Cu層未進入微細溝槽或洞内，還是可藉由之後的 加熱來使溝槽或洞的周圍的Cu層沿著被浸潤層來流入溝 槽或洞内’確實地使Cu充塡於溝槽或洞内。由於如此地 藉由純度高之PVD使Cu層流動於溝槽或洞内來充塡 Cu ’因此不需要Cu電鍍，且即使利用Cu電鑛，也會因 爲是輔助性者，所以可解決或減輕電鍍的添加劑等的問 題。 200931531 【實施方式】 以下’參照圖面來具體說明有關本發明的實施形態。 圖1是用以說明本發明的Cu配線的形成方法之一例 的流程圖，圖2A〜2D是表示該等的工序的工序剖面圖。 首先’如圖2A所示，準備：在矽基板】上形成L〇w_ k膜2，藉由光蝕刻技術（ph〇t〇-lithography )來形成溝槽 Ο (或洞）3之後’在全面形成障蔽層4之構造（工序 1) 。在此’構成障蔽層4的材料，可舉Ta、TaN、Ti 等。亦可爲TaN及Ta的積層膜。 其次’如圖2B所示’在障蔽層4上，藉由CVD來形 成以Cu會浸潤的金屬材料所構成的被浸潤層5 (工序 2) 。所謂C u會浸潤的金屬材料是對c u具有親和性者， 相當於晶格常數與Cu接近的金屬。基於如此的點，此被 浸潤層5是以RU爲佳。Ru是對Cvi的浸潤性極高的材 ® 料’晶格常數爲2.34埃（A)極接近Cu的2.23埃。Ru 的CVD成膜’可使用rU3(CO)12作爲原料氣體，以壓力： 1·3〜66.5Pa、温度：15〇〜250°C的條件來進行。構成被浸 潤層5的金屬材料，其他還可適用Ir、c〇等的貴金屬系 材料。此被浸潤層5的厚度，較理想是1〜5nm程度。 又’此被浸潤層5，由確保與Cu的親和性的觀點來看， 較理想是高純度者，純度爲99 %以上者爲佳。 其次’如圖2C所示，在被浸潤層5之上藉由濺射等 的PVD來形成Cu層6 (工序3 )。在以濺射來形成Cu層 200931531 6時，可在濺射裝置設置Cu靶，以處理 〜13.3Pa，温度：-30〜30°C的條件，ί 行。PVD因爲階梯覆蓋率差，所以溝槽 入，特別是線寬、亦即洞徑或溝槽寬比 圖示般，幾乎其中Cu不會進入。 因此，形成Cu層6之後，加熱矽3 流動，如圖2D所示，在溝槽（或洞）] 0 4)。藉此，可使Cu充塡於溝槽（或洞 加熱温度較理想是250〜3 5 0 °C的範圍。 Cu難流動，若高於3 50°C，貝U Cu會容 層的Low-k膜2等造成不良影響之虞。 的觀點來看，較理想是260°C以上。又 不適的觀點來看，300 t以下較爲理想。 爲了藉由如此的加熱之Cu的流二 洞）3，雖也會依溝槽等的體積而定，但 〇 理想是5〜50nm程度。 此加熱處理是例如在處理室内的平 處理室内一面導入惰性氣體、例如Ar Η□氣體，一面排氣，將處理室内維持於 真空，藉由埋設於平台的電阻加熱器來 來進行。 一邊參照圖3Α〜3C —邊具體説明 圖2C的狀態下加熱矽基板1 (圖3Α) 動，溝槽（或洞）3的周圍部份的Cu層 [室内的壓力：0.67 安照常用方法來進 (或洞）3内難進 3 2nm更小時，如 S板1來使Cu層6 ί内流入Cu (工序 )3内。此情況的 若比250°C低，則 易凝集，且有對底 由使流動性更良好 ，由消除凝集等的 、來塡埋溝槽（或 Cu層6的厚度較 台載置矽基板，在 氣體或N□氣體或 1 33 3Pa程度的高 加熱矽基板，藉此 有關工序4。若在 ，則Cu層6會流 的Cu會沿著被浸 -9- 200931531 潤層5來流至洞3内（圖3B)。然後，流入的Cu會慢慢 地埋入溝槽（或洞）3，經由圖3C的狀態，如圖2D所 示，完全以Cu來埋入溝槽（或洞）3内，形成Cu配線 層。因爲如此地將Cu層6的Cu予以流入至溝槽（或洞） 3内來形成Cu配線層，所以Cu層6爲了埋入溝槽（或 洞）3，必須形成充分的厚度。 如此不使Cu凝集來流至溝槽（或洞）3内，是因爲 0 構成被浸潤層5的材料對於Ru等之Cu而言爲浸潤性且親 和性佳的金屬，在所被加熱的Cu浸潤至被浸潤層5的狀 態下流動。 在本實施形態，Cu是沿著被浸潤層5而流動，而於 溝槽（或洞）3内的被浸潤層5的全面形成Cu，接著Cu 會塡埋溝槽（或洞）3而去，因此可在不使空隙（void ) 等的缺陷產生的情形下埋入Cu。 又，由於被浸潤層5是藉由階梯覆蓋率佳的CVD來 Ο 形成，因此可形成於溝槽（或洞）3的内面全面，在其上 藉由PVD來形成Cu層6之後，加熱基板，藉此Cu會在 浸潤於被浸潤層5的狀態下沿著被浸潤層5來流動至洞3 内，所以即使在極狹窄的洞内也可埋入Cu。因此，可持 高可靠度來形成比以往的PVD之Cu種子+Cu電鍍困難的 線寬32nm更窄的Cu配線。又，由於Cu配線爲極高純度 之PVD所形成者，不使用Cu電鍍，因此不會有在Cu配 線殘留添加劑而使得配線電阻上昇的情況發生。 以上是顯示有關使以PVD所形成的Cu層6流動於溝 -10- 200931531 槽（或洞）3内全部而埋入時，但有時難以充分的厚度來 形成Cu層6，或應埋入Cu的溝槽（或洞）的體積大時， 難以全部在Cu層6的流動下涵蓋。在那樣的情況時，如 圖4A、4B所示，較理想是使Cu層6流動，至洞3的途 中埋入Cu (圖4A )，然後，輔助性地形成Cu電鍍層7 (圖4B)。藉此，即使只靠Cu層6而無法充分地埋入洞 時，還是可形成Cu配線。此情況的Cu層6之流動前的厚 @ 度，較理想是5〜30nm程度。 此情況，Cu電鍍只是輔助性地使用，其量少，因此 可將伴隨Cu電鍍的添加劑之配線電阻的増大等不妥壓制 到最少限度。 另外，在實施本發明時，亦可使用完全另一個的裝置 來進行被浸潤層的形成、Cu層的形成、之後的加熱處 理，或使用集群式的多處理室系統，不破壞真空地連續進 行該等處理的一部份或全部。又，亦可將形成障蔽層的處 G 理室含於多處理室系統。 其次，說明有關實際實施本發明的結果。 在此，首先，準備一在矽基板上形成厚度2 OOnm的 Low-k膜（SiOC )，且藉由光蝕刻技術在Low-k膜形成直 徑分別爲3 Onm、65nm、85nm的溝槽，在其上以灘射來形 成厚度4nm的Ti障蔽層之構造體，在該等的障蔽層上全 面形成厚度2nm的Ru膜作爲被浸潤層，更在其上藉由濺 射以10nm的厚度形成Cu層而製作樣品。然後，在Ar氣 體環境中，以260°C來加熱該等樣品，而使Cu層流動於洞 -11 - 200931531 内。圖5是表示該時的剖面之掃描型顯微鏡（SEM )照 片。如圖5所示，任何寬的溝槽皆可看見藉由260 °C的加 熱在溝槽内被充塡Cu的部份。因此，根據本發明，可在 溝槽内埋入Cu而形成Cu配線。 其次，準備一在矽基板上形成厚度200nm的Low-k 膜（SiOC)，且在Low-k膜形成寬分別爲30nm、50nm、 70nm的溝槽，在其上以濺射來形成厚度4nm的Ti障蔽層 @ 之構造體，在該等的障蔽層上全面地形成厚度2 nm的Ru 膜作爲被浸潤層，更在其上藉由濺射以1 〇nm的厚度形成 Cu層而製作樣品。然後，在Ar氣體環境中，分別以 1 50°C、200°C、2 60°C、3 00°C、3 50°C 來加熱該等樣品、而 使Cu層流動於洞内。圖6是表示該時的平面的掃描型顯 微鏡（SEM )照片。爲了比較，有關維持加熱前的成膜 (as depo )的樣品亦同樣地顯示於圖6。如圖6所示，加 熱温度至200°C爲止，狀態爲as depo不變，確認未產生 ❹ Cu的流入。相對的，加熱温度爲260°C以上，可知Cu會 流動而流入溝槽内。但，在加熱温度350 °C，可知在溝槽 寬70nm的樣品，Cu會良好地流入溝槽内，但在溝槽寬 3 0nm及5 0nm則會發生Cu的凝集。因此，可確認形成Cu 層之後的加熱，較理想是25 0〜3 50°C的範圍。 另外’本發明並非限於上述實施形態，亦可實施各種 的變形。例如，上述實施形態是顯示有關使用Low-k膜作 爲被蝕刻層的情況，但並非限於此，亦可爲其他的膜。 又，顯不有關使用砂基板作爲基板的例子，但亦可爲其他 -12- 200931531 的半導體基板，或半導體基板以外的基板。 【圖式簡單說明】 圖1是用以說明本發明的Cu配線的形成方法之一例 的流程圖。 圖2A是用以說明本發明的CU配線的形成方法之一例 的工序剖面圖。 © 圖2B是用以說明本發明的Cu配線的形成方法之一例 的工序剖面圖。 圖2C是用以說明本發明的Cu配線的形成方法之一例 的工序剖面圖。 圖2D是用以說明本發明的Cu配線的形成方法之一例 的工序剖面圖。 圖3A是用以說明加熱時的Cu的流動擧動的剖面圖。 圖3B是用以說明加熱時的Cu的流動擧動的剖面圖。 〇 圖3C是用以說明加熱時的Cu的流動擧動的剖面圖。 圖4A是表示藉由加熱來使Cu流動於溝槽内後實施 Cu電鍍時的程序之工序剖面圖。 圖4B是表示藉由加熱來使Cu流動於溝槽内後實施 Cu電鑛時的程序之工序剖面圖。 圖5是改變溝槽寬來實際進行本發明的方法時的樣品 的剖面狀態的掃描型顯微鏡照片。 圖6是改變溝槽寬及加熱時的温度來實際進行本發明 的方法時的樣品的平面狀態的操作型顯微鏡照片。 -13- 200931531 【主要元件符號說明 1 :矽基板 2 : Low-k 膜 3 :溝槽（或洞） 4 :障蔽層 5 :被浸潤層 6 : C u 層 7 : Cu電鑛層In the present invention, for example, a layer formed of a low dielectric constant interlayer insulating film having a groove or a hole formed in a substrate such as a semiconductor wafer or the like is formed with a barrier layer interposed therebetween. A method of forming Cu wiring of Cu wiring. [Prior Art] Recently, in response to the demand for higher speed of semiconductor devices, miniaturization of wiring patterns, and higher integration, it is required to reduce the capacitance between wirings, improve the conductivity of wiring, and improve the resistance of electromigration. According to the technology, a wiring material is made of copper (Cu) which is more conductive and has better electromigration resistance than aluminum (A1) or tungsten (W), and a low dielectric constant film (Low-k film) is used as the interlayer. The Cu multilayer wiring technology of the insulating film has attracted attention. In the method of forming the Cu wiring at this time, for example, a Low-k film in which a trench or a hole φ is formed, and a physical vapor deposition method (PVD) typified by sputtering is used to form a barrier formed of Ta, TaN, Ti, or the like. A layer on which a Cu seed layer is formed by PVD is also known, and a technique of performing Cu plating thereon is known (for example, Japanese Laid-Open Patent Publication No. Hei No. Hei No. Hei. However, the design rule of the semiconductor device is becoming more and more detailed, and the technique disclosed in the above-mentioned Japanese Patent Publication No. Hei 11-340226 is difficult to be substantially low by the step coverage. The PVD is used to form a Cu seed layer in the trench or hole, so it is expected that it is difficult to form a plating in the hole. -5- 200931531 Moreover, in the case of embedding fine wiring in the electroplating process, it is necessary to add an additive, which is expensive to manage and becomes a factor for cost increase. Further, the additive remains in the wiring, which causes a rise in wiring resistance. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a Cu wiring in which Cu can be surely buried even in a fine trench or hole. Another object of the present invention is to provide a method of forming a Cu wiring which can form a Cu wiring without using electroplating or minimizing the use of electroplating. According to a first aspect of the present invention, a method of forming a Cu wiring can be provided, which has the following steps: preparing a substrate having a predetermined layer having a trench or a hole formed thereon, and forming a structure of a barrier layer thereon; a wetted layer formed of a metal tantalum material impregnated with Cu by CVD on the barrier layer; and a Cu layer formed by PVD on the wetted layer; After the Cu layer is formed, 'heating the substrate to flow the Cu layer' flows into the cu in the trench or the hole. In the above first aspect, the thickness ' of the CU layer is preferably 5 to 5 Onm. According to the second aspect of the present invention, a method of forming a Cu wiring can be provided, which has the following steps: a substrate, and a layer defined by -6 - 200931531 having a groove or a hole formed thereon, and a structure of a barrier layer formed thereon; forming a layer infiltrated by Cu by CVD on the barrier layer a wetted layer composed of a metal material; a Cu layer formed by PVD on the wetted layer; after the Cu layer is formed, the substrate is heated to flow the Cu layer, and Cu flows into the trench or the hole; and then A Cu plating layer is formed to completely bury the trench or hole. In the second aspect, the thickness of the Cu layer is preferably 5 to 30 nm. In the first and second aspects, the wetted layer is preferably made of Ru. Further, the temperature at the time of heating the substrate is preferably 250 to 350 °C. Further, the thickness of the wetted layer is preferably 1 to 5 nm. According to the present invention, before the formation of the Cu layer of PVD on the barrier layer, CVD is performed by CVD with good step coverage. a wetting layer composed of a metal ruthenium material, whereby the immersed layer can be spread over fine grooves or holes, and then a Cu layer is formed by PVD on the immersed layer, so even if the Cu layer does not enter the fine groove or In the hole, the Cu layer around the trench or the hole may flow into the trench or the hole along the layer to be wetted by the subsequent heating to surely fill the groove in the trench or the hole. Since the Cu layer is filled in the trench or the hole by the high purity PVD to fill the Cu', Cu plating is not required, and even if the Cu electric ore is used, it can be solved or mitigated because it is an auxiliary person. Problems with plating additives, etc. [Embodiment] Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings. Fig. 1 is a flow chart for explaining an example of a method of forming a Cu wiring of the present invention, and Figs. 2A to 2D are process cross-sectional views showing the steps. First, as shown in FIG. 2A, preparation: forming a L〇w_k film 2 on a germanium substrate, and forming a trench Ο (or hole) 3 by photolithography (ph〇t〇-lithography) The structure of the barrier layer 4 is formed (step 1). Here, the material constituting the barrier layer 4 may, for example, be Ta, TaN or Ti. It can also be a laminated film of TaN and Ta. Next, as shown in Fig. 2B, on the barrier layer 4, the wetting layer 5 composed of a metal material infiltrated with Cu is formed by CVD (Step 2). The metal material in which C u is infiltrated is an affinity for c u , and corresponds to a metal having a lattice constant close to that of Cu. Based on such a point, the wetting layer 5 is preferably RU. Ru is a highly invasive material for Cvi. The lattice constant is 2.34 angstroms (A) very close to 2.23 angstroms of Cu. The CVD film formation of Ru can be carried out using rU3(CO)12 as a material gas at a pressure of 1-3 to 66.5 Pa and a temperature of 15 to 250 °C. The metal material constituting the wetting layer 5 may be a noble metal material such as Ir or c. The thickness of the wetted layer 5 is preferably about 1 to 5 nm. Further, the wetted layer 5 is preferably one having a purity of 99% or more from the viewpoint of ensuring affinity with Cu. Next, as shown in Fig. 2C, the Cu layer 6 is formed on the wetted layer 5 by PVD such as sputtering (step 3). When a Cu layer is formed by sputtering at 200931531, a Cu target can be disposed in a sputtering apparatus to process a temperature of ～13.3 Pa and a temperature of -30 to 30 ° C. Since PVD has a poor step coverage, the groove is introduced, especially the line width, that is, the hole diameter or the groove width ratio, and almost Cu does not enter. Therefore, after the Cu layer 6 is formed, the crucible 3 flows, as shown in Fig. 2D, in the trench (or hole)] 0 4). Thereby, Cu can be filled in the trench (or the hole heating temperature is preferably in the range of 250 to 350 ° C. Cu is difficult to flow, and if it is higher than 3 50 ° C, the shell U Cu will accommodate the layer of Low- The k-film 2 and the like cause adverse effects. From the viewpoint of the viewpoint, it is preferably 260 ° C or more. From the viewpoint of discomfort, it is preferable to be 300 t or less. In order to pass the two holes of the heated Cu flow) 3, although depending on the volume of the groove or the like, the 〇 is ideally about 5 to 50 nm. This heat treatment is carried out, for example, by introducing an inert gas, for example, Ar Η gas, into the flat processing chamber in the processing chamber while exhausting the chamber, maintaining the chamber in a vacuum, and immersing it in a heater. Referring to Figures 3A to 3C, the Cu layer of the surrounding portion of the groove (or hole) 3 is heated in the state of Fig. 2C. [Indoor pressure: 0.67 An ordinary method is used. Into the (or hole) 3 is difficult to enter 3 2nm smaller, such as S plate 1 to make the Cu layer 6 ί into Cu (process) 3. In this case, if it is lower than 250 ° C, it is easy to aggregate, and the bottom layer is made to have better fluidity, and the groove is buried by eliminating agglomeration or the like (or the thickness of the Cu layer 6 is higher than that of the substrate. Heating the substrate in a gas or N gas or a high degree of 133 3Pa, whereby the process 4 is concerned. If so, the Cu which will flow in the Cu layer 6 will flow to the hole along the layer 5 to be immersed 9-200931531. 3 (Fig. 3B). Then, the inflowing Cu will slowly bury the groove (or hole) 3, and through the state of Fig. 3C, as shown in Fig. 2D, the groove (or hole) is completely buried with Cu. In the case of 3, a Cu wiring layer is formed. Since Cu of the Cu layer 6 is flowed into the trench (or hole) 3 to form a Cu wiring layer, the Cu layer 6 must be buried in the trench (or hole) 3 in order to embed the Cu wiring layer. A sufficient thickness is formed. Therefore, the Cu is not aggregated and flows into the groove (or the hole) 3 because the material constituting the wetted layer 5 is a metal which is wettable and has good affinity for Cu such as Ru. The heated Cu flows into the state of being wetted by the wetting layer 5. In the present embodiment, Cu flows along the wetted layer 5, and in the groove (or hole) 3 Cu is formed in the entire wetted layer 5, and then Cu is buried in the trench (or hole) 3, so that Cu can be buried without causing defects such as voids. The wetting layer 5 is formed by CVD with good step coverage, and thus can be formed on the inner surface of the trench (or hole) 3, and after the Cu layer 6 is formed by PVD, the substrate is heated, thereby Cu Since it flows into the hole 3 along the wetted layer 5 while being wetted by the wetting layer 5, Cu can be buried even in a very narrow hole. Therefore, it is possible to form a higher reliability than the conventional one. CuD of PVD + Cu plating with a narrow line width of 32 nm is difficult. In addition, since the Cu wiring is formed of PVD of extremely high purity, Cu plating is not used, so there is no wiring residue in the Cu wiring. The above is the case where the Cu layer 6 formed by PVD flows in the groove-10-200931531 groove (or hole) 3 and is buried. However, it may be difficult to form a Cu layer with sufficient thickness. 6, or when the volume of the groove (or hole) to be buried in Cu is large, it is difficult to In the case where the flow of the Cu layer 6 is covered, in such a case, as shown in Figs. 4A and 4B, it is preferable to flow the Cu layer 6 and embed Cu in the middle of the hole 3 (Fig. 4A), and then auxiliaryly form. The Cu plating layer 7 (Fig. 4B), whereby the Cu wiring can be formed even when the hole cannot be sufficiently buried only by the Cu layer 6. In this case, the thickness of the Cu layer 6 before the flow is preferably @ In the case of Cu to 5 nm, in this case, Cu plating is used only in an auxiliary manner, and the amount thereof is small, so that the wiring resistance of the additive accompanying Cu plating can be suppressed to a minimum. Further, in the practice of the present invention, the formation of the wetting layer, the formation of the Cu layer, the subsequent heat treatment, or the use of a cluster-type multi-treatment chamber system may be carried out using a completely other apparatus, and the continuous operation may be performed without breaking the vacuum. Some or all of these processes. Further, the chamber in which the barrier layer is formed may be contained in the multi-treatment chamber system. Next, the results relating to the actual implementation of the present invention will be explained. Here, first, a Low-k film (SiOC) having a thickness of 200 nm is formed on the germanium substrate, and trenches having diameters of 3 Onm, 65 nm, and 85 nm are formed in the Low-k film by photolithography. A structure in which a Ti barrier layer having a thickness of 4 nm is formed by a beach, and a Ru film having a thickness of 2 nm is formed as a layer to be wetted on the barrier layer, and Cu is formed thereon by sputtering at a thickness of 10 nm. Make samples by layer. Then, in an Ar gas atmosphere, the samples were heated at 260 ° C, and the Cu layer was allowed to flow in the holes -11 - 200931531. Fig. 5 is a scanning-type microscope (SEM) photograph showing a cross section at this time. As shown in Fig. 5, the portion of the trench that is filled with Cu by heating at 260 °C can be seen in any of the wide trenches. Therefore, according to the present invention, Cu wiring can be formed by embedding Cu in the trench. Next, a Low-k film (SiOC) having a thickness of 200 nm was formed on the germanium substrate, and trenches having widths of 30 nm, 50 nm, and 70 nm were formed on the Low-k film, and a thickness of 4 nm was formed thereon by sputtering. In the structure of the Ti barrier layer @, a Ru film having a thickness of 2 nm was formed as a wetted layer on the barrier layers, and a Cu layer was formed by sputtering at a thickness of 1 〇 nm to prepare a sample. Then, in an Ar gas atmosphere, the samples were heated at 150 ° C, 200 ° C, 2 60 ° C, 300 ° C, and 3 50 ° C, respectively, to cause the Cu layer to flow in the holes. Fig. 6 is a scanning electron microscope (SEM) photograph showing a plane at this time. For comparison, a sample for maintaining the film formation (as depo) before heating is also shown in Fig. 6. As shown in Fig. 6, the heating temperature was up to 200 ° C, and the state was as depo, and it was confirmed that no inflow of cerium Cu occurred. On the other hand, when the heating temperature is 260 ° C or higher, it is understood that Cu flows and flows into the grooves. However, at a heating temperature of 350 °C, it was found that Cu penetrated well into the trench in a sample having a groove width of 70 nm, but Cu was aggregated at a groove width of 30 nm and 50 nm. Therefore, it was confirmed that the heating after the formation of the Cu layer is preferably in the range of 25 0 to 3 50 °C. Further, the present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, the case where the Low-k film is used as the layer to be etched is shown, but the present invention is not limited thereto, and may be another film. Further, although an example in which a sand substrate is used as a substrate is used, it may be another semiconductor substrate of -12-200931531 or a substrate other than the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart for explaining an example of a method of forming a Cu wiring of the present invention. Fig. 2A is a cross-sectional view showing the steps of an example of a method of forming a CU wiring of the present invention. Fig. 2B is a cross-sectional view showing the steps of an example of a method of forming the Cu wiring of the present invention. Fig. 2C is a cross-sectional view showing the steps of an example of a method of forming a Cu wiring of the present invention. Fig. 2D is a cross-sectional view showing the steps of an example of a method of forming a Cu wiring of the present invention. 3A is a cross-sectional view for explaining a flow behavior of Cu during heating. 3B is a cross-sectional view for explaining a flow behavior of Cu during heating. 3C is a cross-sectional view for explaining the flow behavior of Cu during heating. Fig. 4A is a cross-sectional view showing the procedure of performing Cu plating after flowing Cu into the trench by heating. Fig. 4B is a cross-sectional view showing the procedure of a process of performing Cu electrowinning after flowing Cu into a groove by heating. Fig. 5 is a scanning type micrograph of a cross-sectional state of a sample when the width of the groove is changed to actually carry out the method of the present invention. Fig. 6 is an operation-type microscope photograph of the planar state of the sample when the method of the present invention is actually carried out by changing the width of the groove and the temperature at the time of heating. -13- 200931531 [Description of main component symbols 1 : 矽 substrate 2 : Low-k film 3 : trench (or hole) 4 : barrier layer 5 : wetted layer 6 : C u layer 7 : Cu electric ore layer

Claims (1)

200931531 十、申請專利範圓 1 · 一種Cu配線的形成方法，其特徵係具有下列步 驟： 準備一具有：基板、及形成於其上之具有溝槽或洞的 所定的層、及形成於其上的障蔽層之構造體； 在上述障蔽層上藉由CVD來形成以Cu會浸潤的金屬 材料所構成的被浸潤層； ❹ 在上述被浸潤層上藉由PVD來形成Cu層；及 在形成Cu層之後，加熱基板來使Cu層流動，在溝槽 或洞内流入Cu。 2. 如申請專利範圍第1項之Cu配線的形成方法，其 中，上述Cu層的厚度爲5〜50nm。 3. 如申請專利範圍第1項之Cu配線的形成方法，其 中，上述被浸潤層爲Ru所構成。 4. 如申請專利範圍第1項之Cu配線的形成方法，其 翁 中，加熱上述基板時的温度爲25 0〜3 5 0°C。 5. 如申請專利範圍第1項之Cu配線的形成方法，其 中’上述被浸潤層的厚度爲1〜5nm。 6. —種Cu配線的形成方法，其特徵係具有下列步 驟： 準備一具有：基板、及形成於其上之具有溝槽或洞的 所定的層、及形成於其上的障蔽層之構造體； 在上述障蔽層上藉由CVD來形成以Cu會浸潤的金屬 材料所構成的被浸潤層； -15- 200931531 在上述被浸潤層上藉由PVD來形成Cu層； 在形成Cu層之後，加熱基板來使Cu層流動，至溝槽 或洞内的途中流入Cu;及 然後，形成Cu電鍍層，將溝槽或洞予以完全塡埋。 7 _如申請專利範圍第6項之C u配線的形成方法，_ 中，上述Cu層的厚度爲5〜30nm。 8_如申請專利範圍第6項之Cu配線的形成方法，_ 〇 中，上述被浸潤層爲Ru所構成。 9_如申請專利範圍第6項之Cu配線的形成方法，_ 中，加熱上述基板時的温度爲250〜350 °C。 10.如申請專利範圍第6項之Cu配線的形成方法，其 中，上述被浸潤層的厚度爲1〜5nm。200931531 X. Patent application specification 1 A method for forming a Cu wiring has the following steps: preparing a substrate having a predetermined layer having a trench or a hole formed thereon, and formed thereon a structure of the barrier layer; a wetted layer formed of a metal material impregnated with Cu by CVD on the barrier layer; 形成 a Cu layer formed by PVD on the wetted layer; and Cu is formed After the layer, the substrate is heated to flow the Cu layer, and Cu flows into the grooves or holes. 2. The method of forming a Cu wiring according to the first aspect of the invention, wherein the thickness of the Cu layer is 5 to 50 nm. 3. The method of forming a Cu wiring according to the first aspect of the invention, wherein the wetted layer is made of Ru. 4. The method for forming a Cu wiring according to claim 1, wherein the temperature at which the substrate is heated is 25 0 to 350 °C. 5. The method of forming a Cu wiring according to the first aspect of the invention, wherein the thickness of the wetted layer is 1 to 5 nm. 6. A method of forming a Cu wiring, characterized by the steps of: preparing a structure having: a substrate, and a predetermined layer having a trench or a hole formed thereon, and a barrier layer formed thereon Forming a wetting layer composed of a metal material impregnated with Cu by CVD on the barrier layer; -15-200931531 forming a Cu layer by PVD on the above-mentioned impregnated layer; heating after forming the Cu layer The substrate causes the Cu layer to flow, and Cu flows into the trench or the hole; and then, a Cu plating layer is formed to completely bury the trench or the hole. 7 _ As in the method of forming the Cu wiring of the sixth item of the patent application, in the above, the thickness of the Cu layer is 5 to 30 nm. 8_ The method for forming a Cu wiring according to item 6 of the patent application scope, wherein the wetted layer is made of Ru. 9_ The method for forming a Cu wiring according to item 6 of the patent application scope, wherein the temperature at which the substrate is heated is 250 to 350 °C. 10. The method of forming a Cu wiring according to claim 6, wherein the thickness of the wetting layer is 1 to 5 nm. -16--16-
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