TW200926376A - Wafer level chip scale package of an image sensor by means of through hole interconnection and method for manufacturing the same - Google Patents

Wafer level chip scale package of an image sensor by means of through hole interconnection and method for manufacturing the same Download PDF

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Publication number
TW200926376A
TW200926376A TW097118768A TW97118768A TW200926376A TW 200926376 A TW200926376 A TW 200926376A TW 097118768 A TW097118768 A TW 097118768A TW 97118768 A TW97118768 A TW 97118768A TW 200926376 A TW200926376 A TW 200926376A
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Taiwan
Prior art keywords
wafer
electrode
image detector
wafer substrate
conductive material
Prior art date
Application number
TW097118768A
Other languages
Chinese (zh)
Inventor
Tae-Seok Park
Young-Sung Kim
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Tae-Seok Park
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020070049202A external-priority patent/KR100897761B1/en
Priority claimed from KR1020070056453A external-priority patent/KR100903553B1/en
Application filed by Tae-Seok Park filed Critical Tae-Seok Park
Publication of TW200926376A publication Critical patent/TW200926376A/en

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Abstract

The present invention relates to a wafer level chip scale package of an image sensor by means of through hole interconnection and a method for manufacturing the same, in which through hole-interconnected electrodes, through holes filled with metals, are induced to the back side of a wafer substrate. In this structure, a length of wiring can be minimized to decrease a power loss and speed up signal transfer. A wafer level chip scale package of an image sensor by means of through hole interconnection in accordance with one embodiment of the present invention comprises: an image sensor for converting light from outside to an electrical signal, the image sensor being located on the front side of a wafer substrate; the electrode pads for outputting the electrical signal made in the image sensor, the electrode pads being located on the wafer substrate and extending into a dicing street; a through hole-interconnected electrode for transferring the electrical signal outputted from the electrode pads to the back side of the wafer substrate; and bumps on the through hole interconnected electrode. We call the technology in the present invention as "J-connection technology".

Description

200926376 九、發明説明： 【發明所屬之技術領域】 本發明係關於一種影像偵測器及其製造方法，且更具 體地，係關於用於可攜式應用產品（例如手機、行動通訊終 端機等）的攝影元件及其製造方法。 【先前技術】 大致而言，影像偵測器為一種將光學影像轉換呈電子 ® 訊號的半導體元件’並用以儲存影像訊號，以及將訊號傳 送至顯示裝置。影像偵測器粗略可分類為兩種，即，一種 為電荷耦合器（charge-coupled Device，CCD )，而另一禮 為互補性金屬氧化物半導體（Complementary Metal-Oxide Semiconductor，CMOS ) » CCD影像偵測器利用在電荷傳送 方向上連續地控制電位阱（potential well)的深度來傳送電 荷。CMOS影像偵測器則是利用包含於晝素單元中的一或 多個電晶體與光電二極趙，來進行影像偵測，其尹光電二 Φ 極體作為光感測器之用。 影像偵測器（例如CCD影像偵測器與CM〇s影像偵測 器）已廣泛地用於手機或個人數位助理（pers〇nal digiul assistances，PDAs)等的攝影裝置。近來，可攜式裝置（例如 手機）則要求被製造成更小且更薄，讓使用者便於攜帶。因 此，若可能的話’需使用於前述手機中的攝影元件在偵測 器晶片尺寸大小下，其高度與長度乘以寬度的尺寸儘可能 5200926376 IX. INSTRUCTIONS: TECHNICAL FIELD The present invention relates to an image detector and a method of fabricating the same, and more particularly to a portable application product (such as a mobile phone, a mobile communication terminal, etc.) A photographic element and a method of manufacturing the same. [Prior Art] In general, an image detector is a semiconductor device that converts an optical image into an electronic signal and stores image signals and transmits signals to a display device. Image detectors can be roughly classified into two types, that is, one is a charge-coupled device (CCD), and the other is a complementary metal-oxide semiconductor (CMOS) » CCD image. The detector transfers the charge by continuously controlling the depth of the potential well in the charge transfer direction. The CMOS image detector uses one or more transistors and photodiodes included in the pixel unit for image detection, and the Yin photoelectric two Φ pole body is used as a light sensor. Image detectors (such as CCD image detectors and CM〇s image detectors) have been widely used in photography devices such as mobile phones or personal digital assistants (PDAs). Recently, portable devices (e.g., mobile phones) have been required to be made smaller and thinner for the user to carry. Therefore, if possible, the photographic element used in the aforementioned mobile phone should have the height and length multiplied by the width of the detector chip size as much as possible.

200926376 的小。 影像偵測器晶片係在最後的封裴製程中， 電路板（printed circuit board，PCB)的上方部份 的影像偵測器則組裝於攝影裝置中。 由於影像偵測窗與從影像偵測窗輸入/輸 極片，乃形成在同一平面上，因而影像偵測器 法輕易地利用一般方法進行。因此，需要經由 bonding)、線結合（wire bonding)等方式，將攝 化到PCB上。就這點而言，使用習知製程封裝 具有增加的尚度與尺寸，因而在現今較為輕薄 裝置的趨勢下，要製造具有内建攝影元件的可 顯得困難。 已開發出晶®級晶片尺寸封裝（Wafer Scale Package，WL-CSP)方法，作為解決前述尺 種模組化方法。 在 WL-CSP方法中，偵測器晶片則利用 (Anisotropic Conductive Film, ACF)> 與軟性 (flexible printed circuit board, FPCB)或网,】性 (rigid printed circuit board, RPCB)接合。依據 法，凸塊位在形成於晶圓級之偵測晶片上的電 之後，ACF與PCB則經處理以形成孔洞，該此 對應於已形成於偵測晶片上的偵測單元β接著， ACF與PCB則層層放置並以熱與壓力接合，以 件。 連接至印刷 ’且經封裝 出訊號的電 的模組化無 片結法（die 影裝置模組 的攝影元件 短小可楼式 攜式裝置則 Level Chip 寸問題的一 異向導電膜 印刷電路板 印刷電路板 WL-CSP 方 極片上，且 孔洞的大小 1憤測晶片、 形成攝影組 200926376 然而，在使用 ACF的接合方法中，由於PCB會利用 ACF接合於形成在偵測器的凸塊片上，因此在製造PCB 時，需要窗之有限側地（side land)中的精細線路。此外， 在PCB上製造孔洞以形成窗時所產生的碎片會殘留，並降 低元件組裝的產量。再則，使用ACF的接合方法尚有其他 缺點。 尤其是，在ACF上形成窗以及利用窗將影像偵測器與 PCB進行前置接合（pre-bonding)的過程，無法容易地自動 化，且前述過程乃以手動進行，進而造成產量的下降。 第1圖為利用習知技術經處理以封裝之影像偵測器的 剖面圖。 為了解決線結合的問題，一家以色列公司 Shellcase 以開發出一種技術。依據Shellcase的技術，環氧樹脂13 係用以將第一覆蓋玻璃14貼附於矽晶圓11之正面，而電 極片1 9與偵測單元1 2則形成於矽晶圓11上。接著，矽晶 圓11的背面則經過研磨以移除預定深度的背面，並經過蝕 刻以露出電極片19。當電極片19露出時，則將第二覆蓋 玻璃1 5貼附上去，並進行蝕刻以露出電極片19。之後， 進行銅濺鍍，因而電極片19可與矽晶圓之背面電性連接。 再來，在使用光學微影的方式，於整個銅膜表面從電 極片到矽晶圓的背面之處形成外部電極之後，接著形成絕 緣層1 7。選擇性地蝕刻絕緣層1 7以露出外部電極，且接 著形成錫球凸塊1 6。而藉由沿著裁切線1 8裁切矽晶圓， 則可獲得經封裝的影像偵測器。前述封裝影像偵測器的過 7 200926376 程具有其缺點，該缺點為由於濺鍍到因 上的銅的緣故，造成難以利用光學微影 背面上形成電極片。 第2圖為利用另一習知技術，經處 測器剖面圖。 參照第2圖，所形成的矽晶圓2 1在 片22與影像偵測器23，且覆蓋玻璃24 _ 正面。矽晶圓2 1的背面則經研磨至一預 用深反應離子蚀亥1j.法（deep reactive ion 對對應於正面上之電極片下方處的矽晶 性钱刻，直到梦晶圓正面上的電極片22 來，則形成介層洞2 7。利用電鍍或無電 層洞2 7，且在以金屬填充的介層洞上， 之後，沿著裁切線2 6裁切矽晶圓，以獲 測器。然而，於此例示中，難以在矽晶S 置處形成介層洞 27，使介層窗能夠位4 ❹下。 此外，前述習知技術結合了覆蓋玻 偵測器以及簡易處理的保護。於習知技 射或吸收部份從外界進入感側器的光， 因而致使偵測器敏感度的下降。再則， 逐漸微小化，且已全力地開發出具有超 畫質CMOS影像偵測器，故前述從覆蓋 測器的敏感度而言，甚至是更大的問題 钱刻所形成之斜面 的方式在砍晶圓的 理以封裝的影像偵 表面上係具有電極 則貼附於矽晶圓的 定深度，且之後利 etching method)， 圓從背面進行選擇 露出為止。如此5 電鍍以金屬充填介 形成錫球凸塊25。 得經封裝的影像偵 ϋ 21背面的特定位 Ε對應的電極片 22 璃的貼附，以作為 術中，覆蓋玻璃反 會造成光的損失並 由於近來畫素尺寸 過2百萬畫素的高 玻璃的光損失對偵 ，且由於所使用覆 8 200926376 蓋玻璃的高價格，造成使用覆蓋玻璃封裝的偵測器晶片亦 昂貴。 【發明内容】 本發明將解決之問題 已提出本發明以克服前述習知技術中的問題。因此， 本發明的目的為提供一種利用穿孔互連方式之影像偵測器 的晶圓級晶片尺寸（大小）封裝，以及其製造方法，其中穿 孔互連電極（填充了金屬的穿孔）係導用於晶圓基板的背 面。於此結構中，可使電線的長度最小化，以降低功率的 損失並加速訊號傳遞。 技術方法 依據本發明之一態樣，提供一種利用穿孔互連方式之 影像偵測器的晶圓級晶片尺寸封裝，其包含：一影像偵測 器，用以將來自外界的光轉換成電子.訊號，該影像偵測器 位在一晶圓基板的正面上；數個電極片，用以輸出在該影 像偵測器中所產生的電子訊號，該些電極片係位在該晶圓 基板上，並延伸至靠近或延伸入一裁切道中；數個穿孔互 連電極，用以將該從該些電極片輸出的電子訊號，傳送至 該晶圓基板的背面；以及數個凸塊，於該些穿孔互連電極 上。 依據本發明之另一態樣，提供一種利用穿孔互連方式 製造一影像偵測器之一晶圓級晶片尺寸封裝的方法，該方 法包含下列步驟：形成一影像偵測器與數個電極片於一晶 9 200926376 圓基板上，使該些電極片延伸至靠近或延伸入一裁切道 中；形成數個與該些電極片相鄰的介層洞；形成一絕緣層 於該些介層洞的内表面上，並以導電材料填充該些介廣 洞；研磨並蝕刻該晶圓基板的背面’以露出該些介層洞的 導電材料；形成一絕緣層於該晶圓基板的背面上；以及形 成數個凸塊於該導電材料上》Small for 200926376. The image detector chip is in the final sealing process, and the image detector of the upper part of the printed circuit board (PCB) is assembled in the photographic device. Since the image detecting window and the input/receiving sheet of the image detecting window are formed on the same plane, the image detector method is easily performed by a general method. Therefore, it needs to be transferred to the PCB via bonding, wire bonding, and the like. In this regard, the use of conventional process packages has an increased degree of detail and size, so that it is difficult to fabricate built-in photographic elements in the trend of today's thinner devices. A Wafer Scale Package (WL-CSP) method has been developed as a solution to the aforementioned modularization method. In the WL-CSP method, the detector chip is bonded using a (Anisotropic Conductive Film, ACF) & a flexible printed circuit board (FPCB) or a rigid printed circuit board (RDD). According to the method, after the bump is located on the wafer-level detection wafer, the ACF and the PCB are processed to form a hole, which corresponds to the detection unit β formed on the detection wafer. Next, ACF The PCB is placed in layers and joined by heat and pressure. Modular chip-free connection to the printed 'encoded-out signal' (the photographic component of the die-shadow device module is short and the stackable device is a differential chip printed on a different size film) Circuit board WL-CSP square pole piece, and hole size 1 inversion chip, forming photography group 200926376 However, in the bonding method using ACF, since the PCB will be bonded to the bump piece formed on the detector by ACF, In the manufacture of PCBs, fine lines in the limited side land of the window are required. In addition, debris generated when holes are formed in the PCB to form the window may remain and the yield of component assembly is reduced. Further, using ACF There are other disadvantages to the bonding method. In particular, the process of forming a window on the ACF and pre-bonding the image detector to the PCB using a window cannot be easily automated, and the foregoing process is performed manually. , which in turn causes a drop in production. Figure 1 is a cross-sectional view of an image detector that has been processed and packaged using conventional techniques. To solve the problem of line bonding, a color The Shell Company developed a technology. According to the Shellcase technology, the epoxy 13 is used to attach the first cover glass 14 to the front side of the germanium wafer 11, and the electrode sheet 19 and the detecting unit 12 are formed. Next, the back surface of the germanium wafer 11 is ground to remove the back surface of a predetermined depth, and is etched to expose the electrode sheet 19. When the electrode sheet 19 is exposed, the second cover glass 15 is exposed. Attached and etched to expose the electrode sheet 19. After that, copper sputtering is performed, so that the electrode sheet 19 can be electrically connected to the back surface of the germanium wafer. Further, in the manner of using optical lithography, the entire copper film is used. After the surface forms an external electrode from the electrode sheet to the back surface of the germanium wafer, an insulating layer 17 is then formed. The insulating layer 17 is selectively etched to expose the external electrode, and then the solder ball bump 16 is formed. A packaged image detector can be obtained by cutting the wafer along the cutting line 18. The packaged image detector has its drawbacks, which are due to the sputtering of copper. Cause, it is difficult to use light The electrode sheet is formed on the back surface of the lithography. Fig. 2 is a cross-sectional view of the detector by another conventional technique. Referring to Fig. 2, the formed germanium wafer 2 1 is on the sheet 22 and the image detector 23, and Covering the glass 24 _ front side. The back side of the wafer 2 1 is ground to a pre-use deep reactive ion etching method (deep reactive ion to correspond to the twin crystal money under the electrode sheet on the front side until The electrode sheet 22 on the front side of the wafer is formed to form a via hole 27. The electroplated or electroless layer hole 27 is used, and on the via hole filled with metal, and then cut along the cutting line 26. Wafer to the detector. However, in this illustration, it is difficult to form a via hole 27 at the twin S placement, so that the via can be placed at 4 ❹. In addition, the aforementioned prior art combines the protection of a cover glass detector with ease of handling. It is known in the art to absorb or absorb part of the light entering the side sensor from the outside, thus causing a decrease in the sensitivity of the detector. Furthermore, it has become more and more miniaturized, and has developed a super-picture quality CMOS image detector. Therefore, in terms of the sensitivity of the cover detector, even the larger problem is formed by the way of the slope. The wafer is cut to the surface of the image. The surface of the image is attached to the fixed depth of the wafer, and then the round is selected from the back. Such 5 electroplating forms a solder ball bump 25 with a metal filling. The encapsulated image detector 21 is attached to the corresponding electrode sheet 22 on the back side of the lens, as a high glass that is used during surgery to cover the glass and cause light loss due to the recent pixel size of 2 million pixels. The loss of light is detected, and because of the high price of the cover glass used in 20098376, it is also expensive to use a detector chip that covers the glass package. SUMMARY OF THE INVENTION Problems to be Solved by the Invention The present invention has been made to overcome the problems in the prior art described above. Accordingly, it is an object of the present invention to provide a wafer level wafer size (size) package using a perforated interconnect image detector, and a method of fabricating the same, in which a perforated interconnect electrode (perforated metal filled) is used On the back side of the wafer substrate. In this configuration, the length of the wire can be minimized to reduce power loss and accelerate signal transmission. Technical Solution According to one aspect of the present invention, a wafer level wafer size package using a perforated interconnect image detector is provided, comprising: an image detector for converting light from the outside into electrons. a signal detector is disposed on a front surface of a wafer substrate; a plurality of electrode sheets for outputting electronic signals generated in the image detector, the electrode sheets being tied to the wafer substrate And extending into or extending into a cutting path; a plurality of perforated interconnecting electrodes for transmitting the electronic signals output from the electrode sheets to the back surface of the wafer substrate; and a plurality of bumps The perforations are interconnected on the electrodes. According to another aspect of the present invention, a method for fabricating a wafer level wafer size package of an image detector by using a via interconnection method is provided, the method comprising the steps of: forming an image detector and a plurality of electrode sheets On a circular substrate, the electrode sheets are extended to extend or extend into a cutting path; a plurality of via holes adjacent to the electrode sheets are formed; and an insulating layer is formed in the via holes On the inner surface, filling the dielectric holes with a conductive material; grinding and etching the back surface of the wafer substrate to expose the conductive material of the via holes; forming an insulating layer on the back surface of the wafer substrate; And forming a plurality of bumps on the conductive material"

依據本發明之又一態樣，提供一種利用穿孔.互速方式 製造一影像偵測器之一晶圓級晶片尺寸封裝的方法，該方 法包含下列步驟：形成一影像偵測器與數個電極片於一晶 圓基板上，使該些電極片延伸至靠近或延伸入一裁切道 〒丨形成數個與該些電極片相鄰的介層洞：研磨該晶圓基 板的背面’直到露出該些介層洞以形成數個穿孔為土；形 緣層於該晶圓基板的背面與該些穿孔的内表面上’ 並以導電材料填充該些穿孔；以及形成數個凸塊於該導電 材料上。 免涵的結t 器，且Γ月的益處為可不使用覆蓋玻璃來保護影像名 二卜而：：低封装影像镇測器的高度與價格。 而將電線县疮 W益處為其可利帛#電極帛人介層丨 阳將電線長度最小 且接著將電極導入曰層祠係穿過晶圓基板… 的最小化，其可基板的“，另外，依據電線， 尤其是 力率的損失並提高訊號傳遞速度。 、足’本發明核士 、 璃的情形下會產注 的益處為其可防止若使用覆3 的光損失，且即使在高度清晰影像名 10 200926376 器的微小化下，可降低影像偵測器敏感度與影像品質的下 降。 【實施方式】 ❹ ❹ 於說明書與申請專利範圍中所使用的術語與用字不應 以原本或字面意思解釋而限定。反倒是應依據本發明之構 想來建構意思與概念，見不違反發明人可適當地定義術語 之概念’以便以最佳方式描述他/她的發明的原則。 雖然本發明已以一特定例示實施例揭露，然其並非用 以限定本發明’本發明之保護範圍當視後附之申請專利範 固所界定者為準。任何熟習此技藝者，在不脫離本發明之 精神和範圍内’當可作各種之更動與潤飾。於下文中，本 發明之較佳實施例將參照所附圖示進行詳細描述。 第3至30圖缯示依據本發明之一實施例，經由穿孔互 連之影像偵測器的晶圓級晶片尺寸封裝，及其製造方法。 參照第3-4圖，偵測器係形成於基板14〇之上部份的 外層（未繪不）上’且在各偵測器的各晝素上，形成數個電According to still another aspect of the present invention, a method for fabricating a wafer level wafer size package of a image detector using a perforation and mutual speed method is provided, the method comprising the steps of: forming an image detector and a plurality of electrodes On a wafer substrate, the electrode sheets are extended to extend or extend into a cutting lane to form a plurality of via holes adjacent to the electrode sheets: grinding the back surface of the wafer substrate until exposed The via holes are formed to form a plurality of vias as the soil; the edge layer is on the back surface of the wafer substrate and the inner surfaces of the through holes and fill the through holes with a conductive material; and forming a plurality of bumps on the conductive On the material. The cul-de-suppressed t-sector, and the benefit of the moon is that it can protect the image name without using cover glass: the height and price of the low-package image detector. The benefit of the wire county sore is that it can minimize the length of the wire and then introduce the electrode into the layer of the wafer through the wafer substrate, which can be used for the substrate. According to the electric wire, especially the loss of the force rate and the speed of the signal transmission. The benefit of the invention in the case of the invention is that it can prevent the loss of light if the cover 3 is used, and even if it is highly clear Under the miniaturization of image name 10 200926376, the sensitivity of image detector and the degradation of image quality can be reduced. [Embodiment] 术语 术语 The terms and words used in the specification and patent application should not be original or literal. The meaning is limited to the explanation. Instead, the meaning and concept should be constructed in accordance with the concept of the present invention, and the principle that the inventor can appropriately define the term 'in order to describe his/her invention in an optimal manner should be considered. Although the present invention has been The disclosure of the present invention is not intended to limit the scope of the invention, which is defined by the appended claims. The present invention can be variously modified and retouched without departing from the spirit and scope of the invention. In the following, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Figures 3 to 30 A wafer level wafer size package of an image detector interconnected via vias, and a method of fabricating the same according to an embodiment of the present invention. Referring to Figures 3-4, a detector is formed on a substrate 14 Part of the outer layer (not drawn) is on the 'and on each element of each detector, forming several electricity

CMOS ….、队，凡乃v不艰： 影像偵測器110。基板140例如可為矽晶圓基才 依據本發明之一實施例 所形成的電極片可延展至裁 切道中 裁切道為在沿箸裁切線裁 切基板時將移除之區 域。由於前述延展，電極 形成附加的電極片至裁切 片可增加其長度。此外，可藉由 道中’來獲得前述延展，其中所 11 200926376 附加的電極片電性連接至CMOS影像偵測器1 1 0原本的電 極片。於此時’附加形成的電極片具有與原來的電極片相 等或更大的面猜。 首先，參照第3圖’膜13〇貼附至晶圓基板14〇之正 面。依據本發明’膜可為光阻（photoresist，PR)或乾膜光阻 (dry film resist，DFR)。 在將膜130貼附至晶圓基板140的正面後，光會穿過 ® 具有已形成圖案的遮罩（未螬·示）而照射至膜上，並接著使 膜顯影。於此方式中，所形成的圓案露出了各電極片12〇 的一部份，以及部份晶圓基板，如第4圖所示。虛線方塊 中的區域，即「裁切道j代表著將藉由裁切移除的部份。 各電極片120與晶圓基板所露出的部份在表面上具有 一氧化層（未繪示）。氧化層會被部份移除以在靠近裁切道 處形成介層洞’進而能與電極片接觸。 接著’參照第5a圖’對位在與電極片ι2〇相鄰之晶圓 © 基板140正面的暴露部份進行濕蝕刻或乾蝕刻，以形成具 有數微米或數十微米（μιη)的直徑，而深度在約100μιη到約 3 00μιη範圍内的介層洞15〇。 依據本發明之實施例’用以形成介層洞1 5 0的乾蝕刻 可藉由深反應離子钱刻（deep reactive ion etching, deep RIE)進行。在蝕刻之時’由於暴露於電極板120之表面上 的鋁層會保護電極板免受深反應離子蝕刻，因而僅能對晶 12 200926376 圓基板進行選擇性地蚀刻。 第5b 面的—部份，而介層洞CMOS ...., team, where is v is not difficult: image detector 110. The substrate 140 can be, for example, a germanium wafer substrate. The electrode sheets formed in accordance with an embodiment of the present invention can be extended into the cutting lane. The cutting lanes are regions that will be removed when the substrate is cut along the tangential line. Due to the aforementioned extension, the electrode forms an additional electrode sheet to the cut sheet to increase its length. In addition, the foregoing extension can be obtained by the middle of the channel, wherein the additional electrode pads of the 2009 2009376 are electrically connected to the original electrode pieces of the CMOS image detector 1 1 0. At this time, the electrode sheets additionally formed have a surface guess equal to or larger than the original electrode sheets. First, the film 13A of Fig. 3 is attached to the front surface of the wafer substrate 14A. The film according to the present invention may be photoresist (PR) or dry film resist (DFR). After the film 130 is attached to the front side of the wafer substrate 140, the light is irradiated onto the film through a mask having a pattern (not shown), and then the film is developed. In this manner, the formed circle exposes a portion of each of the electrode sheets 12A and a portion of the wafer substrate as shown in FIG. The area in the dashed box, that is, "the cutting path j represents the portion to be removed by the cutting. The exposed portion of each of the electrode sheets 120 and the wafer substrate has an oxide layer on the surface (not shown). The oxide layer is partially removed to form a via hole near the trimming track, which in turn can be in contact with the electrode sheet. Next, 'refer to FIG. 5a' to align the wafer adjacent to the electrode sheet ι2〇. The exposed portion of the front surface of the 140 is wet etched or dry etched to form a via having a diameter of several micrometers or tens of micrometers (μm) and a depth of about 100 μm to about 300 μm. The 'dry etching for forming the via hole 150 can be performed by deep reactive ion etching (deep RIE). At the time of etching 'because of the aluminum exposed on the surface of the electrode plate 120 The layer protects the electrode plate from deep reactive ion etching, so it can only selectively etch the crystal 12 200926376 round substrate. Part 5b - part, and via hole

第5b圖顯示晶圓基板14〇正 150 c 介層： 形成穿孔互連電極 氧化膜外，各電極片120 β 以露除其鋁層。而介層洞 基板形成’故介層洞150乃位在與電極片12〇的相鄰之處。 據此’將於下文中進行描述的穿孔互連電極l71，可電性 連接至電極片的側面與正面。 參照第6圖，利用電漿輔助式化學氣相沈積 (plasma-enhanced chemical vapor deposition，PECVD)技 術、乾氧化技術或濕氧化技術，在介層洞15〇的内表面上 形成絕緣層160。絕緣層可包含氧化膜與氮化膜豬的任一 © 者或兩者，較佳為氧化矽膜與氮化矽膜、 依據本發明之另一實施例，在形成介層洞150之後， 利用化學機械研磨法（chemical mechanical polishing ， CMP)等處理，對基板的背面進行研磨，直到露出介層洞以 形成穿孔。在此之後，於基板的背面上以及穿孔的内表面 上形成絕緣層。絕緣層可包含氧化膜與氮化膜中的任一者 或兩者，較佳為氧化矽膜與氮化矽膜。 13Figure 5b shows the wafer substrate 14 〇 150 c interlayer: forming a perforated interconnect electrode Outside the oxide film, each electrode sheet 120 β is exposed to the aluminum layer. The via hole substrate is formed so that the via hole 150 is located adjacent to the electrode pad 12A. The perforated interconnect electrode 111, which will be described hereinafter, can be electrically connected to the side and front side of the electrode sheet. Referring to Fig. 6, an insulating layer 160 is formed on the inner surface of the via hole 15 by a plasma-enhanced chemical vapor deposition (PECVD) technique, a dry oxidation technique or a wet oxidation technique. The insulating layer may comprise any one or both of an oxide film and a nitride film pig, preferably a ruthenium oxide film and a tantalum nitride film, according to another embodiment of the present invention, after forming the via hole 150, A chemical mechanical polishing (CMP) process or the like is performed to polish the back surface of the substrate until a via hole is exposed to form a via. After that, an insulating layer is formed on the back surface of the substrate and on the inner surface of the perforation. The insulating layer may comprise either or both of an oxide film and a nitride film, preferably a hafnium oxide film and a tantalum nitride film. 13

基板 200926376 參照第7圖’利用電錢法形成金屬層i7〇以填充具有 絕緣層160於其表面上的介層洞15〇，並覆蓋電極片12〇。 據此’以此形成的金屬層可電性連接電極片。 依據本發明之實施例，若金屬層17〇係以堆疊的形式 電艘於電極片120的正面上，則可降低電極片12〇與利用 電鍍所形成之金屬層170的接觸電阻，此係因其電性接觸 面積增加的緣故》 依據本發明，其較佳以具有良好導電性的金屬（例如 金銅等）作為金屬層17〇。同時，電鍍可在利用濺鍍等方 法於絕緣層160上，形成預定厚度的種晶層之後再進行。 在利用導電材料填充介層洞150之後，對晶園基板14〇 的背面進行研磨，直到露出導電材料為止，如第8圖所示。 在完成研磨之後，介層、洞150中的金屬則形成了穿透晶圓 基板140的穿孔互連電極。 接著，參照第9圖，對晶圓基板14()的背面進行選求 性，姓刻，進而使穿孔互連電極171從晶圓基板之經蝕亥 的背面突出一預定厚度。依據本發明可蝕刻晶圓基板自 背面义從晶圓基板經蝕刻的背面’露出高50μιη或少;5 5〇=的導電#料，且較佳地，從晶圓基板經㈣的背面ί 出高1〇μΠ1或少於ΙΟμπι的導電材料。 之後’參照第則，利用乾氧化法或濕氧化 14〇 的昔 Α β , ΟΛ 的者面形成絕緣層180。絕緣層18〇包含氧化膜 14 200926376 或氮化膜中的任-者或兩者。於此時，絕緣層180所具有 之高，的厚度較佳為使穿孔互連電極從晶固基板的背面突 出的咼度’或者低於前述使穿孔互連電極突出的高度。 參照第"圏，在絕緣層180形成之後，塗佈光感性光 阻（ph〇t〇sensitive resist，pSR)19〇，且之後圖案化以露出穿 孔互連電極171〇在此之後，於穿孔互連電極上形成 凸塊。依據本發明，凸塊可為錫球凸塊或柱形凸塊（StudSubstrate 200926376 Referring to Fig. 7, the metal layer i7 is formed by an electric money method to fill the via hole 15 of the insulating layer 160 on the surface thereof, and to cover the electrode sheet 12A. According to this, the metal layer thus formed can be electrically connected to the electrode sheet. According to the embodiment of the present invention, if the metal layer 17 is electrically connected to the front surface of the electrode sheet 120 in a stacked manner, the contact resistance between the electrode sheet 12 and the metal layer 170 formed by electroplating can be reduced. According to the present invention, it is preferable to use a metal having good conductivity (for example, gold, copper, or the like) as the metal layer 17〇. Meanwhile, electroplating may be performed after forming a seed layer of a predetermined thickness on the insulating layer 160 by sputtering or the like. After the via hole 150 is filled with a conductive material, the back surface of the crystal substrate 14A is polished until the conductive material is exposed, as shown in FIG. After the grinding is completed, the metal in the via, hole 150 forms a perforated interconnect electrode that penetrates the wafer substrate 140. Next, referring to Fig. 9, the back surface of the wafer substrate 14 () is selectively selected, and the perforated interconnect electrode 171 is protruded from the back surface of the wafer substrate by a predetermined thickness. According to the present invention, the etchable wafer substrate is exposed from the back side of the wafer substrate by an etched back surface to expose 50 μm or less; 5 5 〇 = conductive material, and preferably, from the wafer substrate via the back surface of (4) A conductive material that is 1 μμΠ1 or less than ΙΟμπι. Thereafter, referring to the first step, the insulating layer 180 is formed by a dry oxidation method or a wet oxidized 14 Å. The insulating layer 18 〇 includes either or both of the oxide film 14 200926376 or the nitride film. At this time, the insulating layer 180 has a height which is preferably such that the perforated interconnecting electrode protrudes from the back surface of the crystal-solid substrate or lower than the height at which the perforated interconnecting electrode protrudes. Referring to the "圏, after the formation of the insulating layer 180, a photo-sensitive resist (pSR) 19 Å is applied, and then patterned to expose the punctured interconnect electrode 171, after which, in the perforation A bump is formed on the interconnect electrode. According to the invention, the bumps can be tin ball bumps or stud bumps (Stud

Bump)。錫球凸塊可利用例如下述兩種處理方法形成。 第12-16圖為依據本發明之第一實施例，形成錫球凸 塊的過程。 參’、、' 第12圖，在經圖案化的光感性光阻上塗覆光阻 (photoresist，PR)210，並進行圖案化以露出穿孔互連電極 17卜 如上述’於本發明令，所形成的介層洞150乃與在影 像偵測器之表面上的電極片12〇相鄰並以金屬填充而以 金屬填充的介層洞係用以製造穿過晶圓基板直至其背面的 穿孔互連電極。因此，本發明能使晶圓直接安裝在一剛性 印刷電路板或軟性印刷電路板上。換言之，本㈣能製作 出晶圓與印刷電路板的最短互連。此外，由於直接的互連， 因此本發明可藉由線結合使來自互連的阻抗最小化，使功 率的損失最低’以及加快訊號傳遞。 參照第13囷’為了形成烊料凸塊利用網印技術（screen 15 200926376 printing technique)將錫膏220印在露出的穿孔互連電極上β 之後使錫膏迴焊（reflow)以具有球的形式，如第μ圖 示。參照第15圖，將基板背面上的光阻21〇移除，以及 基板正面上已利用電鍍填充介層洞的金屬層17〇平坦化 以露出膜130。之後將膜130移除。 依據本發明之實施例’係使錫膏迴焊以形成球形 塊，並對凸塊表面進行清潔以及平坦化。此可使雜質移核 © 且增加接觸表面積，進而達到改善的導電性。 參照第16圖，在移除膜13 0之後，藉由沿著裁切 a-a’裁切晶圓，將晶圓單一化（singuiated)成個別的晶片 現在’利用穿孔互連的方法進行處理的晶圓級晶片尺寸 裝之影像偵測器係已完成。 第17-25圖顯示依據本發明之第二實施例，形成錫 &塊的過程。經圖案化的光感性光阻190係藉由固化處 而硬化。光感性光阻圖案化乃導致穿孔互連電極與從晶 〇 背面上電極171延伸之錫球凸塊重佈（redistribution)間 電性接觸〇 如上述，於本發明中，介層洞1 5 0則在影像偵測器 表面上鄰近電極片丨2〇處形成並以金屬填充，而以金屬 充的介層洞係用以製造穿過晶圓基板直至其背面的穿孔 連電極《因此，本發明能使晶圓直接安裝在一剛性印刷 路板或軟性印刷電路板上。換言之，本發明能製作出曰 且 所 將 凸 * > 線 〇 封 球 理 圓 的 之 填 互 電 圓 16 200926376 與印刷電路板的最短互連。此外，由於直接的互連，因此 本發明可藉由線結合使來自互連的阻抗最小化，使功率的 損失最低，以及加快訊號傳遞。 參照第1 7圖，阻障層2 0 0係設置在經圖案化光感性光 阻190的整個表面上，以形成從導線延伸的穿孔互連電極 171。阻障層為堆疊的球限制金屬層（bau limiting metallurgy, BLM)或凸塊底部金屬層（under bump ❹ metallurgy，UBM)。 在大型積體電路中，阻障層200乃形成於鋁或其合金 的電極片120以及將於下述步驟中形成的錫球凸塊220 間，且阻障層改善了穿孔互連電極171舆錫球凸塊220的 黏附，防止了它們之間的擴散。特別是，由於前述阻障層 在錫球凸塊220的形狀上具有巨大的影孿，故阻障層稱為 球限制金屬層（BLM) » 依據本發明之阻障層，其可包含銅/鉻/銅（Cu/Cr/Cu) 〇 或鉻/銅/金（Cr/Cu/Au)。在Cr/Cu/Au的情況下，Cr層對以 鋁材料所製成的電極片120展現了良好的黏附，鋼層預防 了錫球凸塊之錫的擴散，而鋁層則防止了銅的氧化。 參照第18圖，在沉積阻障層200之後，將阻障層200 平坦化以移除形成於光感性光阻190上的部份阻障層2 0 0。 參照第19圖，將塗覆的厚光阻（pr)圖案化，以露出所 沉積的阻障層。參照第20與21圖，錫膏220係如第20 17 200926376Bump). The solder ball bumps can be formed by, for example, the following two processing methods. Figures 12-16 illustrate the process of forming solder ball bumps in accordance with a first embodiment of the present invention. Referring to ',,' Fig. 12, a photoresist (PR) 210 is coated on the patterned photo-sensitive photoresist, and patterned to expose the perforated interconnect electrode 17 as described above. The via hole 150 is formed adjacent to the electrode pad 12 在 on the surface of the image detector and filled with metal and filled with metal to form a via hole through the wafer substrate until the back surface thereof Connect the electrodes. Therefore, the present invention enables the wafer to be mounted directly on a rigid printed circuit board or a flexible printed circuit board. In other words, this (4) can produce the shortest interconnection between the wafer and the printed circuit board. Moreover, due to the direct interconnection, the present invention minimizes the impedance from the interconnect by wire bonding, minimizing power loss' and speeding up signal transfer. Referring to page 13', in order to form a solder bump, a solder paste 220 is printed on the exposed via interconnect electrode by a screen printing technique (screen 15 200926376 printing technique), and the solder paste is reflowed in the form of a ball. , as shown in the μ. Referring to Fig. 15, the photoresist 21 on the back surface of the substrate is removed, and the metal layer 17 on the front surface of the substrate which has been filled with a via hole by plating is planarized to expose the film 130. The film 130 is then removed. In accordance with an embodiment of the present invention, the solder paste is reflowed to form a spherical block, and the surface of the bump is cleaned and planarized. This allows the impurities to move through the nucleus and increase the contact surface area to achieve improved conductivity. Referring to Figure 16, after the film 130 is removed, the wafer is singuied into individual wafers by cutting the wafer along the cut a-a'. Wafer-level wafer size mounted image detectors have been completed. Figures 17-25 show the process of forming a tin & block in accordance with a second embodiment of the present invention. The patterned photo-sensitive photoresist 190 is cured by curing. Photosensitive photoresist patterning results in electrical contact between the via interconnecting electrode and the solder ball bump redistribution extending from the upper electrode 171 on the back side of the wafer. As described above, in the present invention, the via 1 500 Formed on the surface of the image detector adjacent to the electrode sheet 2丨 and filled with metal, and the metal-filled via hole is used to manufacture a via electrode connected to the back surface of the wafer substrate. Therefore, the present invention The wafer can be mounted directly on a rigid printed circuit board or flexible printed circuit board. In other words, the present invention is capable of fabricating the shortest interconnection of the interdigitated circle 16 200926376 with the printed circuit board of the yoke and the yoke. Moreover, due to the direct interconnection, the present invention minimizes impedance from the interconnect by wire bonding, minimizes power loss, and speeds up signal transfer. Referring to Figure 17, a barrier layer 200 is disposed over the entire surface of the patterned photo-inductive photoresist 190 to form a perforated interconnect electrode 171 extending from the wire. The barrier layer is a stacked bau limiting metallurgy (BLM) or an under bump ❹ metallurgy (UBM). In the large integrated circuit, the barrier layer 200 is formed between the electrode sheets 120 of aluminum or an alloy thereof and the solder ball bumps 220 which will be formed in the following steps, and the barrier layer improves the via interconnection electrodes 171. The adhesion of the solder ball bumps 220 prevents diffusion between them. In particular, since the foregoing barrier layer has a large influence on the shape of the solder ball bump 220, the barrier layer is referred to as a ball-restricted metal layer (BLM). The barrier layer according to the present invention may comprise copper/ Chromium/copper (Cu/Cr/Cu) tantalum or chromium/copper/gold (Cr/Cu/Au). In the case of Cr/Cu/Au, the Cr layer exhibits good adhesion to the electrode sheet 120 made of aluminum material, the steel layer prevents the diffusion of tin of the solder ball bump, and the aluminum layer prevents copper. Oxidation. Referring to FIG. 18, after the barrier layer 200 is deposited, the barrier layer 200 is planarized to remove a portion of the barrier layer 200 formed on the photo-sensitive photoresist 190. Referring to Figure 19, the coated thick photoresist (pr) is patterned to expose the deposited barrier layer. Referring to Figures 20 and 21, solder paste 220 is like the 20th 17 200926376

圖中所示進行印刷，且接著如第21圖中所示進行迴焊。 此之後，將光阻2 1 0移除，以形成球形的錫球凸塊2 2 0 如第22圖中所示。 再來，參照第23圖，將經電鍍以填充介層洞1 50的 屬層170平坦化，直至露出膜130，其中膜130可為PR 乾膜光阻（DFR)。之後，將露出的膜130移除。參照第 圖，沿著裁切線a-a’裁切晶圓，以將晶圓單一化成晶片 第 2 5圖顯示利用穿孔互連的方法進行處理的晶圓級晶 尺寸封裝之影像偵測器係已完成。以前述穿孔互連製造 像偵測器的技術乃命名為「J-連接技術」。 不同於習知技術的覆蓋玻璃，依據本發明，係使用 來保護影像偵測器。包含光阻或乾膜光阻的膜1 3 0則塗 在晶圓基板的正面上，且在緊接在裁切晶圓前移除。據址 本發明可防止在使用覆蓋玻璃的情況下所產生的光損失 進而避免影像偵測器敏感度與影像品質的降低。尤其是 依據本發明，在未使用覆蓋玻璃且晶圓基板背面係經研 的情形下，可製造出所封裝的影像偵測器整個厚度僅 ΙΟΟμιη至3 00μιη，且可利用所封裝的影像偵測器來製造 度最小，且乘上寬度後乃在晶片尺寸範圍中的微小化攝 元件。 第26-30圖顯示依據本發明之另一實施例，形成柱 凸塊的過程。 在 金 或 24 〇 片 影 膜 覆 磨 約 高 影 形 18 200926376 參照第2 6圖，對利用上述參照第3 - 7圖所述之步驟進 行處理的晶圓基板從其背面進行研磨，直炱露出金屬為 止，以形成穿孔互連電極。在完成研磨之後’僅對基板選 擇性地研磨。依據本發明，可蝕刻基板背面’以使穿孔互 連電極_從基板背面突出約50μιη或少於50μΐη ’且較佳地’ 突出約10 μιη至30 μιη。且接著，形成絕緣層180。 再來，參照第27圖，塗佈光感性光阻190，並圖案化 φ 以露出穿孔171。在此之後’如第28圖所示’利用電鍍技 術，於穿孔互速電極171上形成柱形凸塊240。 於此時，枉形凸塊240可包含銅/錫/金（Cu/Sn/Au)，且 柱形凸塊240的高度係使柱形凸塊高於光感性光阻1 90。 參照第29圖，在形成柱形凸塊240之後，平坦化基板 疋面上的金屬層170，且之後移除膜130。之後，延裁切線 a_a，裁切基板’以形成各個影像偵測晶片’如第3 0圖所示。 儘管本發明已揭示部分較佳實施例，當理解的是熟習 技藝者在不脫離本發明的範圍下’可進行修改與潤飾，如 ® 申請專利範圍所界定者。 【阖式簡單說明】 第1圖與第2圖係利用—習知技術，經處理以封裝之 彩像偵測器的剖面圖。 第3 -11圖係繪示依照本發明一實施例，在形成凸塊前 ，法〆晶圓基板的過程。 製造 19 200926376 第12-16圖為依據本發明之第一實施例，形成錫球凸 塊的過程。 第17-25圖顯示依據本發明之第二實施例，形成錫球 凸塊的過程。 第2 6-30圖顯示依據本發明之另一實施例，形成柱形 凸塊的過程。Printing is performed as shown in the drawing, and then reflow is performed as shown in Fig. 21. Thereafter, the photoresist 2 10 0 is removed to form a spherical tin ball bump 2 2 0 as shown in FIG. Further, referring to Fig. 23, the genus layer 170 electroplated to fill the via hole 150 is planarized until the film 130 is exposed, wherein the film 130 may be a PR dry film photoresist (DFR). Thereafter, the exposed film 130 is removed. Referring to the figure, the wafer is cut along the cutting line a-a' to singulate the wafer into a wafer. FIG. 25 shows a wafer level crystal size package image detector system processed by the method of puncturing interconnection. completed. The technique of fabricating an image detector using the aforementioned perforated interconnect is named "J-Connect Technology". Unlike the cover glass of the prior art, in accordance with the present invention, it is used to protect the image detector. A film 130 comprising a photoresist or dry film photoresist is applied to the front side of the wafer substrate and removed immediately prior to cutting the wafer. The present invention prevents loss of light generated in the case of using a cover glass and thereby avoids degradation of image detector sensitivity and image quality. In particular, according to the present invention, in the case where the cover glass is not used and the back surface of the wafer substrate is subjected to research, the entire thickness of the packaged image detector can be manufactured only from ΙΟΟμηη to 300 μιη, and the packaged image detector can be utilized. The miniaturized component that is the smallest in manufacturing and multiplied by the width is in the wafer size range. Figures 26-30 show the process of forming stud bumps in accordance with another embodiment of the present invention. Grinding a gold or a 24 影 film to a high image 18 200926376 Referring to Figure 26, the wafer substrate processed by the steps described above with reference to Figures 3 - 7 is polished from the back side thereof, and exposed The metal is formed to form a perforated interconnect electrode. After the completion of the grinding, only the substrate was selectively ground. According to the present invention, the back surface of the substrate can be etched so that the perforated interconnecting electrodes _ protrude from the back surface of the substrate by about 50 μm or less and preferably by about 10 μm to 30 μm. And then, the insulating layer 180 is formed. Next, referring to Fig. 27, the photo-sensitive resist 190 is applied, and φ is patterned to expose the through holes 171. Thereafter, as shown in Fig. 28, a stud bump 240 is formed on the perforated mutual velocity electrode 171 by electroplating. At this time, the dove bump 240 may comprise copper/tin/gold (Cu/Sn/Au), and the height of the stud bump 240 is such that the stud bump is higher than the photo-sensitive resist 1 90. Referring to Fig. 29, after the stud bumps 240 are formed, the metal layer 170 on the face of the substrate is planarized, and then the film 130 is removed. Thereafter, the tangent line a_a is cut, and the substrate 'is cut to form each image detecting wafer' as shown in Fig. 30. While the invention has been described in terms of a preferred embodiment, it is understood that modifications and modifications may be made by those skilled in the art without departing from the scope of the invention. [Simple description of the 阖] Fig. 1 and Fig. 2 are cross-sectional views of the color image detector processed by the conventional technique. 3-11 are views showing a process of fusing a wafer substrate before forming a bump according to an embodiment of the present invention. Manufacture 19 200926376 Figures 12-16 show the process of forming solder ball bumps in accordance with a first embodiment of the present invention. Figures 17-25 show the process of forming solder ball bumps in accordance with a second embodiment of the present invention. Figures 2-6-30 illustrate the process of forming stud bumps in accordance with another embodiment of the present invention.

12偵測單元 14第一覆蓋玻璃 1 6錫球凸塊 18裁切線 2 1梦晶圓 23影像偵測器 25錫球凸塊 2 7介層洞 120電極片 140晶圓基板 1 6 0絕緣層 1 7 1穿孔互連電極 190光感性光阻 210光阻 240柱形凸塊 【主要元件符號說明】 11梦晶圓 1 3環氧樹脂 15第二覆蓋玻璃 1 7絕緣層 19電極片 22電極片 24覆蓋玻璃 26裁切線 110 CMOS影像偵測器 130膜 1 5 0介層洞 170金屬層 1 8 0絕緣層 2 0 0阻障層 220錫球凸塊 a-a’裁切線 2012 detection unit 14 first cover glass 1 6 tin ball bump 18 cutting line 2 1 dream wafer 23 image detector 25 solder ball bump 2 7 interlayer hole 120 electrode sheet 140 wafer substrate 1 60 insulation layer 1 7 1 perforated interconnect electrode 190 light inductive photoresist 210 photoresist 240 stud bump [main component symbol description] 11 dream wafer 1 3 epoxy resin 15 second cover glass 1 7 insulating layer 19 electrode sheet 22 electrode sheet 24 cover glass 26 cutting line 110 CMOS image detector 130 film 1 50 hole layer 170 metal layer 1 8 0 insulation layer 2 0 0 barrier layer 220 tin ball bump a-a' cutting line 20

Claims (1)

200926376 十、申請專利範圍： 1 · 一種利用穿孔互連方式之影像偵測器的晶圓級晶片 寸封裝，其包含： 一影像偵測器，用以將來自外界的光轉換成電子 號，該影像偵測器位在一晶圓基板的正面上； 數個電極片，用以輸出在該影像偵測器中所產生的 子訊號，該些電極片係位在該晶圓基板上，並延伸至靠 或延伸入一裁切道中； 數個穿孔互連電極，用以將該從該些電極片輸出的 子訊號，傳送至該晶圓基板的背面；以及 數個凸塊，於該些穿孔互連電極上。 2 ·如申請專利範圍第1項所述之利用穿孔互連方式之影 偵測器的晶圓級晶片尺寸封裝，其中該穿孔互連電極係 由蝕刻該晶圓基板的部份正面，以形成一介層洞並以導 材料填充該介層洞而形成，且該晶圓基板的該部份正面 與該電極片相鄰。 3.如申請專利範圍第2項所述之利用穿孔互連方式之影 偵測器的晶圓級晶片尺寸封裝，其中該形成於該介層洞 的導電材料係延伸以部份或完全覆蓋與該介層洞相鄰之 電極片的一側面或該正面。 尺 訊 電 近 電 像 藉 電 係 像 中 該 21 200926376 4.如申請專利範圍第3項所述之利用穿孔互連方式之影像 偵測器的晶圓級晶片尺寸封裝，更包含一氧化膜形成於該 介層洞的内表面上。 5 ·如申請專利範圍第2項所述之利用穿孔互連方式之影像 偵測器的晶圓級晶片尺寸封裝，其中該介層洞係藉由一電 鍍處理以填充該導電材料。 6. 如申請專利範圍第2項所述之利用穿孔互連方式之影像 偵測器的晶圓級晶片尺寸封裝，其中該介層洞具有一約 ΙΟΟμιη至約300μιη的深度。 7. 如申請專利範圍第1項所述之利用穿孔互連方式之影像 偵測器的晶圓級晶片尺寸封裝，其中該凸塊為一錫球凸塊 或一柱形凸塊。 ❹ 8. 如申請專利範圍第1項所述之利用穿孔互連方式之影像 偵測器的晶圓級晶片尺寸封裝，更包含一阻障層，用以改 善該穿孔互連電極至該凸塊的黏附，並防止其間的擴散。 9.如申請專利範圍第8項所述之利用穿孔互連方式之 影像偵測器的晶圓級晶片尺寸封裝，其中該阻障層包含球 限制金屬層（ball limiting metallurgy，BLM)或凸塊底部金 22 200926376 屬層（under bump metallurgy, UBM) ° 10. 如申請專利範圍第8項所述之利用穿孔互連方式之影 像偵測器的晶圓級晶片尺寸封裝，其中該阻障層使用銅/ 絡/銅或絡/銅/金中的任一者。 11. 一種利用穿孔互連方式製造一影像偵測器之一晶圓級 晶片尺寸封裝的方法，該方法包含下列步驟： 形成一影像偵測器與數個電極片於—晶圓基板上，使 該些電極片延伸至靠近或延伸入一裁切道中； 形成數個與該些電極片相鄰的介層洞； 形成一絕緣層於該些介層洞的内表面上，並以導電材 料填充該些介層洞； 研磨並姓刻該晶圓基板的背面，以露出該些介層洞的 導電材料； 形成一絕緣層於該晶圓基板的背面上；以及 形成數個凸塊於該導電材料上。 12. 一種利用穿孔互連方式製造一影像偵測器之一晶圓級 晶片尺寸封裝的方法，該方法包含下列步驟： 形成一影像偵測器與數個電極片於—晶圓基板上，使 該些電極片延伸至靠近或延伸入一裁切道中； 形成數個與該些電極片相鄰的介層洞； 23 數 面 13 ❹ 圓 的 14 數 與 ❿ 基 15 光 16 數 200926376 研磨該晶圓基板的背面，直到露出該些介層 個穿孔為止； 形成一絕緣層於該晶圓基板的背面與該些穿 上，並以導電材料填充該些穿孔；以及 形成數個凸塊於該導電材料上。 .如申請專利範圍第11項所述之方法，其中該 基板背面的步驟係被執行，以從該晶圓基板之 背面露出高50μιη或少於50μιη的導電材料。 .如申請專利範圍第11或12項所述之方法，其 個與該些電極片相鄰之介層洞的步驟，包含： 形成一膜於該晶圓基板的正面上，其中該影 該些電極片已形成於該晶圓基板上； 圖案化該膜，以露出各個電極片的一部分以 板的一部份；以及 蝕刻該晶圓基板之該與該些電極片相鄰的部 .如申請專利範圍第14項所述之方法，其中該 阻（photoresist, PR)或乾膜光阻（dry film resist, .如申請專利範圍第11或12項所述之方法，其 個凸塊於該導電材料上的步驟，包含下列步驟 洞以形成 孔的内表 银刻該晶 該經蝕刻 t該形成 像偵測器 及該晶圓 分。 該膜為一 DFR)。 中該形成 24 200926376 圖案化一形成於該晶圓基板之背面上的光感性光阻， 以露出該導電材料； 圖案化一形成於該光感性光阻整個表面上的光阻，以 露出該導電材料； 塗覆錫膏於該導電材料上；200926376 X. Patent Application Range: 1 · A wafer level wafer package using a perforated interconnect image detector, comprising: an image detector for converting light from the outside into an electronic number, The image detector is located on the front surface of the wafer substrate; the plurality of electrode sheets are used for outputting the sub-signals generated in the image detector, and the electrode sheets are tied on the wafer substrate and extended Abutting or extending into a cutting lane; a plurality of perforated interconnecting electrodes for transferring the sub-signals output from the electrode sheets to a back surface of the wafer substrate; and a plurality of bumps at the perforations On the interconnect electrode. The wafer level wafer size package of the shadow detector using the perforated interconnection method according to claim 1, wherein the perforated interconnection electrode is formed by etching a front portion of the wafer substrate to form a front surface of the wafer substrate A via hole is formed by filling the via hole with a conductive material, and a portion of the front surface of the wafer substrate is adjacent to the electrode sheet. 3. The wafer level wafer size package of the shadow detector using the perforated interconnection method according to claim 2, wherein the conductive material formed in the via hole is extended partially or completely. One side of the electrode sheet adjacent to the via hole or the front side. The chip-level wafer size package of the image detector using the perforated interconnection method, as described in claim 3 of the patent application, further includes an oxide film formation. On the inner surface of the via. 5. The wafer level wafer size package of the image detector using the perforated interconnection method of claim 2, wherein the via hole is filled with the conductive material by an electroplating process. 6. The wafer level wafer size package of the image detector using the perforated interconnect method of claim 2, wherein the via hole has a depth of from about ιμηη to about 300 μm. 7. The wafer level wafer size package of the image detector using the perforated interconnection method according to claim 1, wherein the bump is a solder ball bump or a stud bump. ❹ 8. The wafer level wafer size package of the image detector using the perforated interconnection method according to claim 1, further comprising a barrier layer for improving the via interconnection electrode to the bump Adhere and prevent the spread between them. 9. The wafer level wafer size package of the image detector using a perforated interconnection method according to claim 8, wherein the barrier layer comprises a ball limiting metallurgy (BLM) or a bump Bottom gold 22 200926376 genus layer (under bump metallurgy, UBM) ° 10. A wafer level wafer size package using a perforated interconnect image detector as described in claim 8 wherein the barrier layer is used Any of copper/coupling/copper or cord/copper/gold. 11. A method of fabricating a wafer level wafer size package using a via interconnect method, the method comprising the steps of: forming an image detector and a plurality of electrode pads on a wafer substrate The electrode sheets extend to be adjacent to or extend into a cutting path; form a plurality of via holes adjacent to the electrode sheets; form an insulating layer on the inner surface of the via holes, and fill the conductive material The interlayer holes are polished and engraved on the back surface of the wafer substrate to expose the conductive material of the via holes; an insulating layer is formed on the back surface of the wafer substrate; and a plurality of bumps are formed on the conductive layer On the material. 12. A method of fabricating a wafer level wafer size package using a via interconnect method, the method comprising the steps of: forming an image detector and a plurality of electrode pads on a wafer substrate The electrode sheets extend close to or extend into a cutting path; form a plurality of via holes adjacent to the electrode sheets; 23 number 13 ❹ round 14 number and ❿ base 15 light 16 number 200926376 grinding the crystal a back surface of the circular substrate until the vias are exposed; forming an insulating layer on the back surface of the wafer substrate and the through holes, and filling the through holes with a conductive material; and forming a plurality of bumps on the conductive On the material. The method of claim 11, wherein the step of the back side of the substrate is performed to expose a conductive material having a height of 50 μm or less from the back surface of the wafer substrate. The method of claim 11 or 12, wherein the step of forming a via hole adjacent to the electrode pads comprises: forming a film on a front surface of the wafer substrate, wherein the shadows are An electrode sheet is formed on the wafer substrate; the film is patterned to expose a portion of each of the electrode sheets to a portion of the board; and the portion of the wafer substrate adjacent to the electrode sheets is etched. The method of claim 14, wherein the resist (PR) or the dry film resist (such as the method of claim 11 or 12, wherein the bumps are conductive The step on the material comprises the steps of forming a hole in the inner surface of the hole, engraving the crystal, and etching the t to form an image detector and the wafer. The film is a DFR). Forming 24 200926376 to pattern a photo-sensitive photoresist formed on the back surface of the wafer substrate to expose the conductive material; patterning a photoresist formed on the entire surface of the photo-sensitive photoresist to expose the conductive Material; coating a solder paste on the conductive material; 對該錫膏施以一迴焊處理，以形成數個錫球凸塊； 清潔該些錫球凸塊；以及 平坦化該些錫球凸璲的表面。 17.如申請專利範圍第11或12項所述之方法，其中該形成 數個凸塊於該導電材料上的步驟，包含下列步驟： 圖案化一形成於該晶圓基板之背面上的光感性光阻； 沉積一阻障層於該光感性光阻的整個表面上； 平坦化該阻障層，以露出該光感性光阻； 圖案化一所形成的光阻，以露出該阻障層； 將錫膏塗覆於該阻障層上；以及 對該錫膏施以一迴流處理。 18.如申請專利範圍第11或12項所述之方法，其中該形成 該些凸塊於該導電材料上的步驟，包含下列步驟： 圖案化一形成於該晶圓基板之背面上的光感性光阻， 以露出該導電材料； 圖案化一形成於該光感性光阻之整個表面上的光阻， 25 200926376 以露出該導電材料；以及 形成數個柱形凸塊於該導電材料上。 19.如申請專利範圍第18項所述之方法，其中該柱形凸塊 係藉由於層中設置銅、錫、金中的任一者或多者而形成。The solder paste is subjected to a reflow process to form a plurality of solder ball bumps; the solder ball bumps are cleaned; and the surface of the solder ball bumps is planarized. 17. The method of claim 11 or 12, wherein the step of forming a plurality of bumps on the conductive material comprises the steps of: patterning a light sensation formed on a back surface of the wafer substrate a photoresist layer is deposited on the entire surface of the photo-sensitive photoresist; planarizing the barrier layer to expose the photo-sensitive photoresist; patterning a formed photoresist to expose the barrier layer; Applying a solder paste to the barrier layer; and applying a reflow treatment to the solder paste. 18. The method of claim 11 or 12, wherein the step of forming the bumps on the conductive material comprises the steps of: patterning a light sensation formed on a back surface of the wafer substrate a photoresist to expose the conductive material; patterning a photoresist formed on the entire surface of the photo-sensitive photoresist, 25 200926376 to expose the conductive material; and forming a plurality of stud bumps on the conductive material. 19. The method of claim 18, wherein the stud bump is formed by providing one or more of copper, tin, and gold in the layer. 20.如申請專利範圍第11或12項所述之方法，其中該介 層洞具有一約ΙΟΟμιη至約300μιη範圍内的深度。 ❿ 26The method of claim 11 or 12, wherein the via has a depth ranging from about ΙΟΟμηη to about 300 μηη. ❿ 26
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