TW200924058A - Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias - Google Patents

Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias Download PDF

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Publication number
TW200924058A
TW200924058A TW097126073A TW97126073A TW200924058A TW 200924058 A TW200924058 A TW 200924058A TW 097126073 A TW097126073 A TW 097126073A TW 97126073 A TW97126073 A TW 97126073A TW 200924058 A TW200924058 A TW 200924058A
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Taiwan
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layer
dielectric
top surface
opening
dielectric layer
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TW097126073A
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Chinese (zh)
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Tulipe Douglas C La Jr
Mark Todhunter Robson
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Ibm
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Priority claimed from US11/853,139 external-priority patent/US7704869B2/en
Priority claimed from US11/853,118 external-priority patent/US7723851B2/en
Application filed by Ibm filed Critical Ibm
Publication of TW200924058A publication Critical patent/TW200924058A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for forming a high aspect ratio via opening through multiple dielectric layers, a structure of a high aspect ratio electrically conductive via, methods for forming three-dimension integrated circuits, and structures of three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.

Description

200924058 九、發明說明： 【發明所屬之技術領域】 本發明有關積體電路的領域，尤其有關在積體電 路中製造超深介層的結構及方法以及製造三維積體電 路的結構及方法。 【先前技術】 為了減少佔用面積及提高積體電路的速度，已提 出各種三維積體電路結構。傳統的積體電路結構為二 維，因為所有主動裝置均形成於相同半導體層中的相 同平面。三維積體電路利用垂直堆疊的半導體層，其 中主動裝置形成於堆疊之半導體層的每一半導體層 中〇 三維積體電路的製造對於將不同半導體層中的裝 置互連一起的方法尤其具有諸多挑戰。這些互連線的 總深度將超過1.5 um，其中直徑在0.2 um以下的範圍 中。要用高品質、零瑕疵的金屬來填充深度與寬度之 縱橫比如此大的介層會很困難。尤其，大縱橫比的金 屬填充及極深的介層通常含有增加介層電阻的空隙， 因而導致良率損失並減少裝置可靠性。因此，本技術 200924058 極需克服上述的缺點及限制。 【發明内容】 本發明之第-方面為-種方法，其包含：在 板之-頂面上形成-银刻停止層；在該钱刻停止居: -頂面上形成一第一介電層；在該第一介電層之二 面上形成一輪廓調整層；在該輪廓調整層之—頂貝 ，成-第二介電層；在該第二介電層之—頂面上 成像層；在該成像層中形成—開口，該第 之該頂面的-區域暴露於該開口的一底部令；以2 整層具有選擇性的第一钱刻化學作用對該第 反應揭子_，以形成-穿過該第二 性的ί二::化:作二介電層具有選擇 ’以使該開口延伸穿過該輪廓調整層，·以 =輪廓, 周整層具有選擇性及對該银刻停埋 =三钱刻化學作用對該第-介電層進行; 該第i及=使該開口延伸穿過該第一介電層；以-對 對节蝕介電層具有選擇性的第四蝕刻化學作用 刻停止層進行反應性離 成像層後，，“Π;:::頂=㈣ 層層牙過邊輪廓調整層、穿過該第—介電 之〇蝕刻停止層至該基板的該頂面。 200924058 本發明之第二方面係該第—方面，1 刻化學作用對該第二介電層不具有選擇性。以弟三餘 ^一本發明之第三方面係該第—方面，其 弟二蝕刻化學作用係相同的化學作用。 〇 及 及 #本1明之第四方面係該第—方面， 弟四蝕刻化學作用係相同的化學作用。 Λ ㈣對該卿止層進行上 本發明之第六方面係該第一方面， =及第二介電層包含氧切，且該輪廊 钱刻停止層包含氮切。 月n 本發明之第七方面係該第一方面，其 -介電層之該頂面處在與該第：肩 的第-方向中所測量之該開 面Μ 輪廓調整層的該頂面處在該第 二第二寬度且大於在該基板的d:r 見 方向中所測量之該開口的—第三寬度，該第 200924058 於或等於該第三寬度；及其中從該第二介電層的該頂 面至S亥基板的該頂面處在—與該第一方向垂直的第二 方向中所測量之該㈣口的-深度與該第一寬度的一比 率等於或大於五。 本發明之第八方面係該第一方面，i 牛 括：在該移除該成像層後，用導電體填充該開口 雪耱t發明之第九方面係該第八方面，其中該用-導 電體填充該開口包含：在該開口之側壁及—底部上方 =-氮化组層；在該氮化组層上沈積在該 上沈積-種子銅層；在該種子銅層上電鍍一電鍍 =層丄該電鑛銅層完全填充該開口中的剩餘空間；及 方：二匕學機械拋光’以從該第二介電層之該頂面上 :: 層、該钽層、該種子銅層、及該電鍍 Ο 本發明之第十方面係該第—方面，其中該成像層 在該第—介電層的該頂面上包括—在—抗反射^= 方及該在該成像層中形成該開口包含i過 化輕射、顯影該曝光 初始轴刻化學作二4 光阻層保護的一 刻。 予作料純反射塗層進行反應性離子餘 200924058 钱列之第十—方面係該第十方面，其中該初始 :化=該初始、第二及第四錄學作用= -第本月之第十二方面為一種方法’其包含：形成 的Γΐϊ，該第一基板包括：電連接至-組線路層 每一線路層在-相應介電層中包括導 線路^—在線路層之離該基板最遠之—最上方 最上^路ΐ面上的餘刻停止層’該钱刻停止層與該 頂線路接觸；及在該蝕刻停止層之-二基第二電接合層；形成-第二基板，該第 合層之二面卜ί—介電接合層’·一在該第二介電接 層:―頂而卜W埋藏氧化物層’ 一在該埋藏氧化物 ί以介電W隱、導體層，該半導體層包括在該石夕層 广隔離而互相電絕緣的第二電晶體 =了=;介電質隔離之—頂面上的輪廊 ΐ的接合層的—頂面與該第二介電接ί ΐϋ 第—及第二介電接合層、該埋藏 m 二該介 r ％層之—頂面上形成—成像層，·在該成像 形成-開口 ’該第-介電層之該頂面的一區ί暴 200924058 底部中；以—對該輪廓調整 = 用對該第-介電層進行反應性 雕卞蚀刻，以形成—穿過該第一 . 對該第一及第二介電層具有選擇二 用，輪廓調整層進行反應性離子敍刻作 =穿過該輪廓調整層；以一對該輪 心： =該=止層具有選擇性的第三_;= 延伸穿反，以使該開口 以及該線路具有選擇性的第四關化學二層 反應性離烟，該 ;開:從該第-介電層的該頂面延伸穿過::::敕 層、穿過該第二介電層、穿過該第二介電層輪：:整 該蝕刻停止層至該線路的一 ^ 牙之 該開口，該導電體與該:路4面觸及用-導崎 一产本t月之第十二方面為結構，其包含：-基板； 展之二：:二頂面上的第—介電層；在該第-介電 二頁面亡的-第二介電層；在該第二介電声之— 介電層;在該第三介電層之，上 該基的；：該頂面延伸至 在*該第四in ^亥弟四”電層之該頂面處 /、弟四…之該頂面平行的第—方向中所測量 -10- 200924058 之該開口的一第一寬度大於在該第三介電層的該頂面 處在該第-方向中所測量之朗口的―第二寬度且大 於在該基板的-頂面處在該第—方向巾所測量之該開 口的一第二寬度，該第二寬度大於或等於該第三寬 度；從該第四介電層的該頂面至該基板的該頂面處在 二5該第一方向垂直的第二方向中所測量之該開口的200924058 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to the field of integrated circuits, and more particularly to structures and methods for fabricating ultra-deep vias in integrated circuits and structures and methods for fabricating three-dimensional integrated circuits. [Prior Art] In order to reduce the occupied area and increase the speed of the integrated circuit, various three-dimensional integrated circuit structures have been proposed. The conventional integrated circuit structure is two-dimensional because all active devices are formed in the same plane in the same semiconductor layer. The three-dimensional integrated circuit utilizes vertically stacked semiconductor layers in which active devices are formed in each of the semiconductor layers of the stacked semiconductor layers. The fabrication of three-dimensional integrated circuits is particularly challenging for methods of interconnecting devices in different semiconductor layers. . The total depth of these interconnects will exceed 1.5 um with a diameter below 0.2 um. It is difficult to fill the depth and width of the layer with a high-quality, zero-twist metal. In particular, metal aspect fill and very deep vias of large aspect ratio typically contain voids that increase the dielectric resistance, resulting in loss of yield and reduced device reliability. Therefore, the present technology 200924058 is in great need to overcome the above disadvantages and limitations. SUMMARY OF THE INVENTION A first aspect of the invention is a method comprising: forming a silver engraving stop layer on a top surface of the board; stopping at the money: forming a first dielectric layer on the top surface Forming a contour adjustment layer on two sides of the first dielectric layer; forming a top-second dielectric layer on the contour adjustment layer; and forming an imaging layer on a top surface of the second dielectric layer Forming an opening in the image forming layer, the first portion of the top surface being exposed to a bottom of the opening; and the second layer having a selective first chemical chemistry to the first reaction _, To form - pass through the second λ:: two dielectric layers have a choice 'to extend the opening through the contour adjustment layer, · = contour, the entire layer is selective and Silver engraving = trivalent chemical action on the first dielectric layer; the ith and = extending the opening through the first dielectric layer; - aligning the pitting dielectric layer After the fourth etching chemistry is performed to stop the reactive layer from the imaging layer, "Π;::: top = (4) layered tooth edge contouring layer, through the first dielectric The etch stop layer is then applied to the top surface of the substrate. 200924058 The second aspect of the invention is the first aspect, wherein the first chemical action is not selective to the second dielectric layer. The third aspect is the first aspect, and the second etch chemistry is the same chemistry. The fourth aspect of the present invention is the same chemistry, and the fourth etch chemistry is the same chemistry. (4) The sixth aspect of the present invention is the first aspect, wherein the second dielectric layer comprises oxygen dicing, and the crater stop layer comprises nitrogen cut. Aspect of the first aspect, wherein the top surface of the dielectric layer is at the second second width of the top surface of the opening surface 轮廓 contouring layer measured in the first direction of the first shoulder And greater than a third width of the opening measured in the d:r see direction of the substrate, the 200924058 is equal to or equal to the third width; and the top surface of the second dielectric layer to the S The top surface of the substrate is measured in a second direction perpendicular to the first direction The ratio of the depth of the (four) port to the first width is equal to or greater than five. The eighth aspect of the invention is the first aspect, i: enclosing the opening with the electrical conductor after the removing the imaging layer The ninth aspect of the invention is the eighth aspect, wherein the filling the opening with the electric conductor comprises: a sidewall of the opening and a bottom layer of the nitride layer; and depositing on the nitride layer Depositing a seed-seed copper layer; electroplating a plating layer on the seed copper layer; the electro-mineral copper layer completely filling the remaining space in the opening; and: 匕 匕 机械 mechanical polishing 'from the second dielectric The top surface of the layer: a layer, the germanium layer, the seed copper layer, and the electroplated crucible, the tenth aspect of the invention, wherein the image forming layer is on the top surface of the first dielectric layer The inclusion of the -in-anti-reflection^= square and the formation of the opening in the imaging layer comprises i-lighting, developing the initial polarization of the exposure to protect the quaternary photoresist layer. The material is purely reflective coating for the reactive ion balance 200924058. The tenth aspect of the money is the tenth aspect, wherein the initial: chemical = the initial, second and fourth recordings = - the tenth of the month The second aspect is a method comprising: forming a germanium, the first substrate comprising: electrically connected to the group of wiring layers, each of the wiring layers, the corresponding dielectric layer including a conductive line, and the most Far away—the remaining stop layer on the uppermost topmost surface of the uppermost surface of the uppermost surface of the upper surface of the uppermost surface of the uppermost surface of the uppermost surface of the upper etching layer; and the second electrically conductive layer of the second electrode in the etching stop layer; The second layer of the first layer is a dielectric junction layer, and the second dielectric layer is: the top layer is buried with an oxide layer, and the buried oxide layer is dielectrically hidden. a layer, the semiconductor layer comprising a second transistor that is widely isolated and electrically insulated from each other in the layer; the dielectric isolation - the top surface of the bonding layer of the turret on the top surface and the second Dielectric connection ΐϋ ΐϋ - and the second dielectric junction layer, the buried m 2 the dielectric layer - the top surface - formed An image layer, in the bottom of the imaging formation-opening of the top surface of the first dielectric layer ί 暴 200924058; to - adjust the contour = reactive etched with the first dielectric layer Etching to form through the first. The first and second dielectric layers are selectively used, and the contour adjustment layer performs reactive ion characterization to pass through the contour adjustment layer; : = the = stop layer has a selective third _; = extended through, so that the opening and the line have a selective fourth chemical double layer reactive smoke, which; from: the first The top surface of the electrical layer extends through the :::: germanium layer, through the second dielectric layer, through the second dielectric layer wheel: the entire etch stop layer to the one of the lines The opening, the conductor and the surface of the road 4 are in contact with - the fourth aspect of the guide, the structure comprises: - a substrate; the second: the first dielectric layer on the top surface a second dielectric layer on the first dielectric layer; a dielectric layer on the second dielectric layer; a base layer on the third dielectric layer; the top surface extension a first width of the opening measured in the first direction parallel to the top surface of the fourth in ^ 亥 四 ” ” / 、 、 、 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 The top surface of the third dielectric layer is at a second width of the lands measured in the first direction and greater than one of the openings measured at the top surface of the substrate at the first direction a second width, the second width being greater than or equal to the third width; measuring from the top surface of the fourth dielectric layer to the top surface of the substrate in a second direction perpendicular to the first direction The opening

C :咏度與該第三寬度的—比率等於或大於五；及 充該開口的導電體。 具 本發明之第十四方面係該第十三方面，其 第一及第二介電層包含氮化石夕 〜 層包含-氧化石夕。 i亥弟—及第四介電 第之第十五方面係該第十三方面，盆中·节 芯第三介電層各自分別具有相應:度Ξ 〜第一"電層的—厚度或該 少五倍；及該第―、第二 ；丨巧的—厚度小至 總厚度大於或等於約w米。—、及相介電層的- 本發明之第十六方面係該 包n埋於該第四介電層’其進—步 第一矽層中的第—電曰曰體，—、一矽層，一在該 電接點，哕接點+社日日—在该第四介電層中的導 按及接點電接觸該第一雷曰辨· ^ν 層之一頂面上的第—日日豆，一在第四介電 組㈣層’在該第—組線路層中 200924058 的一或多個線路將該接點電連接至該開口中的該導電 體；及該基板包括一接觸該第一介電層之一底面的第 二組線路層，在該第二組線路層中的一線路或多個線 路將該開口中的該導電體電連接至形成於一第二矽層 中與該第二組線路層之一底面接觸的一第二電晶體。 本發明之第十七方面係該第十三方面，其中：該 第一及第三介電層分別包含一選自由以下項目組成之 群組的材料：低溫氧化物、高密度電漿氧化物、以及 電漿增強化學氣相沈積氧化物、超高密度電漿氧化 物、四乙氧基石夕烧氧化物、旋塗氧化物及其層。 本發明之第十八方面係該第十三方面，其中：該 第二及第四介電層分別包含一選自由以下項目組成之 群組的材料.氣化碎、碳_化砍、乳氣化碎、氧碳化碎 及 Nblock(SiCNH)。 本發明之第十九方面係該第十三方面，其中該導 電體包含：一在該開口之側壁及一底部上方的氮化钽 層；一在該II化组層上的组層；一在該组層上的種子 銅層；及一在該種子銅層上的電鍍銅層，該電鍍銅層 完全填充該開口中的剩餘空間。 本發明之第二十方面係該第十三方面，其中該第 200924058 二介電層包含多個介電層。 〜本發明之第二十—方面係該第十三方面，其中該 弟二介電層包含第五、第六、及第七 / 介電層鄰接該第二介電声， B q第五 第七介電層之間。 ^介電層在該第五及 本發明之第二十二方面係該第二十 ==電層延伸穿過在第二介電層之一底面； δ 、" θ之頂面間之一矽層的區域。 -美2一十三方面係一結構，其包含：-第 一^曰體。\ —基板包括：電連接至—組線路層的第 電曰日，^-祕層在—域介電層巾包括 ，之-公組線路層之離該基板最遠之 上:W止層，刻停止層與該:： =層：線路接觸；在該#刻停止層之一頂面上 與該韻刻停止;：:頂弟一介電接合層之一底面 基板接觸， ·—第二基板，該第二 " 弟一介電接合層；在該第二介電接合層 之-頂埋藏氧化物層；一在該埋藏氧化物‘ 隔離而互相電包括在該石夕層中以介電質 部上及在該介電質 电日日肢’ 一在该石夕層之—頂 貝^硪之—頂面上的輪廓調整層，·及 Ο u 200924058 -在該輪_整層之-頂面上的介電層；該第 接合層之接合至該埋藏氧化物之一底面的一頂面；— 從該介電層之該頂面延伸穿顿輪廓調整層 介電質隔離、穿過該埋藏氧化物層、穿過該第一及^ 二介電接合層、及穿過㈣刻停止層至該線路之 面的開口；及一填充該開口的導雷 、 線路電接觸。 —该導電體與該 【實施方式】 導發:=;施例之示範性 體基板UK)中的是全1A f ’形成於半導 了盲而"η線〇5°形成於基板10〇之 ^11：^ -i 電層125上的县® -人+ 〜风&弟—介 10A 的第二介電層13〇。形成於第三介雷厗 130之頂部上的是輪廓 、 電运 〗35上的是第四介月:層丄35。：成於輪廓調整層 一、Ge:層或， 介電二 四介電層140组二甩八層130、輪摩調整層135、及第 述根據本發明之具體實施例之一二在下文所 、1 1之二維積體電路的製造中 -14 - 200924058 :成！=電介層的結構。因此，在-實例中，蝕 及第—介電層120代表在下方半導體基 第二介電層125、第三介電層⑽、輪廓 坌占及第四介電層140代表在上方半導體層 接ί ?第二介電層12°*125代表將兩 〇 ^反。起的氧化物接合層。第三介電層130代 ί在石夕覆絕緣體_)基板之埋藏氧化物層(順)上的 "電質溝渠隔離㈤或介電質淺溝渠隔離(STI)。 根5本發明之具體實施例之三維積體電路的模 ，：刻工止…呢化石夕且在一實例中約為親 ，’苐1電層i 20為低溫氧切(LT〇)且在 二介於約25〇〇 A及約3500 A厚’第二介電層125為 LTO且在一實例中為介於約25〇〇 A及約％㈨人厚’、，'、 為高密度^切(卿)氧化物熱氧化 在貝例中約為3600 A厚，輪廓調整層135 化夕且在貫例中約為500 A厚，及第四介電層1， 為Hdp氧化物且在一實例中約為47〇〇人厚—每 例中，金屬線路105包含銅。第三介電層13〇 只 人^ 弟四 ^丨電層140的HDP氧化物可分別用電漿增強化學氣相 沈積（PECVD)氧化物、超高密度電漿(UHP)氧化物;;、目 乙氡基矽烷(TEOS)氧化物、或旋塗氧化物來取代。四 刻吟止層115及輪廓調整層〗3 5的氮化石夕可分別用石山 化矽、氧氮化矽、氧碳化矽、或Nblock(SiCNH)來^ 200924058 代。在氧化物熔合接合的應用中’第一及第二介電層 為LTO，但在其他應用中可分別為熱氧化物' HDp ^ 化物、PECVD氧化物、UDP氧化物、TE〇s氧化物、 或旋塗氧化物。在一實例中，蝕刻停止層115及輪廓 凋整層135的厚度可分別比第四介電層14〇的厚度或 第一、第二及第三介電層120、125及130的結合厚度 小約5倍。 LTO氧化物是在約350。〇以下的溫度下所形成的 ，化矽。在一實例中，LT0氧化物係在電漿增強化學 氣相沈積(PECVD)製程中使用N2〇來形成。HDp氧化 物係特別製備以彼此互相熔合接合。 第一、第二、第三及第四介電層120、125、130 ! 140有利的是第一相似材料（如，氧化石夕），而蝕刻 铮止層115及輪廓調整層135有利的是第二相似材料 (如，氮化矽），其中第二材料可相對於第一材料加以 選擇性電漿蝕刻。 在圖1B巾’在第四介電層上形成選擇性抗反射 =層（ARC)145 ’及在ARC的頂部上形成光阻層15〇。 I過圖案化光罩將光阻層15G曝光於光化輻射 ，然後 再顯影光阻層，將光罩圖案轉印至光阻層，即可在光 阻層丨50中以微影方式形成開口 155。在開口丨55的 200924058 底部暴露ARC 145的區域。ARC 145係為底部ARC 或BARC，因其係在光阻層150下形成。可替代使用 在光阻上方形成的頂部ARC(TARC)，或TARC及 BARC二者皆可使用。將光阻層及ARC(即，BARC、 TARC或BARC及TARC二者）的組合定義為成像層。 在圖1C中，使用蝕刻ARC 145比光阻層150快 的反應性離子蝕刻（RIE)(即，對ARC進行對145光阻 層150具有選擇性的RIE)移除在圖iB的開口 155中 暴露之ARC 145的區域’以在開口 155A的底部中暴 路第四介電層14〇的區域。餘刻arc 145的實例RIE 製程包括用混合的CF4/CHF3/Ar/〇2氣體衍生電漿來蝕 整層I35快的Rig(即，對第四C: a ratio of the twist to the third width is equal to or greater than five; and an electric conductor filling the opening. A fourteenth aspect of the invention is the thirteenth aspect, wherein the first and second dielectric layers comprise a nitride layer and the layer comprises - oxidized stone. In the thirteenth aspect, the thirteenth aspect of the fourth dielectric layer, the third dielectric layer of the basin and the core are respectively corresponding to: thickness 〜 ~ first " electrical layer - thickness or This is five times less; and the first and second; well-behaved - the thickness is as small as the total thickness is greater than or equal to about w meters. - and the phase dielectric layer - the sixteenth aspect of the invention is that the package n is buried in the fourth dielectric layer 'the first electrode layer of the step into the first layer, - a a layer, a contact point at the electrical contact, a contact point, a social day-to-day contact, and a contact point in the fourth dielectric layer electrically contacting the first surface of the first ray layer a day-to-day bean, wherein at the fourth dielectric layer (four) layer, one or more lines of the 200924058 in the first group of circuit layers electrically connect the contact to the electrical conductor in the opening; and the substrate comprises a a second set of circuit layers contacting a bottom surface of the first dielectric layer, and one or more of the second set of circuit layers electrically connecting the electrical conductors in the opening to a second germanium layer a second transistor in contact with a bottom surface of one of the second set of circuit layers. The seventeenth aspect of the invention, wherein the first and third dielectric layers respectively comprise a material selected from the group consisting of low temperature oxides, high density plasma oxides, And plasma enhanced chemical vapor deposited oxides, ultra high density plasma oxides, tetraethoxy cerium oxide oxides, spin-on oxides and layers thereof. The eighteenth aspect of the present invention, wherein the second and fourth dielectric layers respectively comprise a material selected from the group consisting of gasification, carbonization, and milk. Fragmentation, oxycarbonation and Nblock (SiCNH). The nineteenth aspect of the invention, wherein the electrical conductor comprises: a layer of tantalum nitride on a side wall of the opening and a bottom; a layer on the layer of the group II; a seed copper layer on the set of layers; and an electroplated copper layer on the seed copper layer, the electroplated copper layer completely filling the remaining space in the opening. A twentieth aspect of the invention is the thirteenth aspect, wherein the second dielectric layer of the 200924058 comprises a plurality of dielectric layers. The twentieth aspect of the present invention, wherein the second dielectric layer comprises a fifth, sixth, and seventh/dielectric layer adjacent to the second dielectric sound, B q fifth Between seven dielectric layers. ^ dielectric layer in the fifth and the twenty-second aspect of the invention is the twentieth == electrical layer extends through one of the bottom surfaces of the second dielectric layer; δ, " one of the top surfaces of θ The area of the enamel layer. - The beauty of the 21st aspect is a structure comprising: - the first ^ body. The substrate comprises: an electrical connection to the first circuit layer of the circuit layer, wherein the layer of the dielectric layer comprises: the farthest from the substrate of the group circuit layer: the W layer, The engraving stop layer and the ::=layer: line contact; on the top surface of the #刻止层 layer and the rhyme stop;:: the top substrate of one of the dielectric bonding layers is in contact with the bottom substrate, the second substrate a second dielectric layer; a buried oxide layer at the top of the second dielectric bonding layer; and a dielectric layer included in the buried oxide to be electrically isolated in the layer The contour adjustment layer on the top surface of the material and the dielectric surface of the dielectric electric day, the top surface of the stone layer, and the top surface of the scorpion layer, and the Ο u 200924058 - in the round _ the whole layer - a dielectric layer on the top surface; a top surface of the first bonding layer bonded to a bottom surface of the buried oxide; - a dielectric barrier from the top surface of the dielectric layer The buried oxide layer, the opening through the first and second dielectric bonding layers, and the opening through the (four) stop layer to the surface of the line; and a guide filling the opening Thunder, line electrical contact. - the electric conductor and the [embodiment] of the embodiment: (in the exemplary body substrate UK of the embodiment), all 1A f 'is formed in the semi-conductive blind and "η-line 〇5° is formed on the substrate 10〇 ^11:^ -i County layer on the electric layer 125 - person + ~ wind & brother - the second dielectric layer 13A of 10A. Formed on the top of the third Thunder 130 is the outline, and the electricity is on the 35th is the fourth month: layer 35. : forming a contour adjustment layer, a Ge: layer or a dielectric dielectric layer 140, a layer 28, a wheel adjustment layer 135, and a second embodiment of the present invention according to the present invention. , 1 1 of the 2D integrated circuit manufacturing -14 - 200924058 : Cheng! = structure of the dielectric layer. Thus, in the example, the etched and first dielectric layer 120 represents the lower semiconductor-based second dielectric layer 125, the third dielectric layer (10), the outline and the fourth dielectric layer 140 representing the upper semiconductor layer ? The second dielectric layer 12°*125 represents two turns. Oxide bonding layer. The third dielectric layer 130 is a "electrical trench isolation (5) or dielectric shallow trench isolation (STI) on the buried oxide layer (shun) of the substrate). The model of the three-dimensional integrated circuit of the specific embodiment of the present invention is: a fossilized stone and, in one example, a pro- ing, the 苐1 electric layer i 20 is a low temperature oxygen dicing (LT 〇) and in two Between about 25 〇〇A and about 3500 Å thick 'the second dielectric layer 125 is LTO and in one example is between about 25 〇〇A and about % (nine) people thick ',, ', for high density ^ cut (Q) The thermal oxidation of oxide is about 3600 A thick in the shell case, the contour adjustment layer 135 is etched and is about 500 A thick in the case, and the fourth dielectric layer 1 is Hdp oxide and in an example. The middle is about 47 inches thick - in each case, the metal line 105 contains copper. The third dielectric layer 13 〇 ^ 弟 HD HD HD 的 的 的 的 的 的 HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD Substituted by oxime oxime (TEOS) oxide or spin-on oxide. The nitriding layer of the four-time stop layer 115 and the contour-regulating layer 〖3 5 can be respectively used for stone generation, yttrium oxynitride, yttrium oxynitride, or Nblock (SiCNH). In the case of oxide fusion bonding, the first and second dielectric layers are LTO, but in other applications they may be thermal oxide 'HDp^, PECVD oxide, UDP oxide, TE〇s oxide, Or spin coating oxide. In one example, the thickness of the etch stop layer 115 and the contoured layer 135 may be less than the thickness of the fourth dielectric layer 14 or the combined thickness of the first, second, and third dielectric layers 120, 125, and 130, respectively. About 5 times. The LTO oxide is at about 350. 〇 formed at the following temperatures, phlegm. In one example, the LT0 oxide is formed using N2 yttrium in a plasma enhanced chemical vapor deposition (PECVD) process. The HDp oxide systems are specifically prepared to be fused to each other. The first, second, third, and fourth dielectric layers 120, 125, 130! 140 are advantageously a first similar material (e.g., oxidized oxide), and the etch stop layer 115 and the contouring layer 135 are advantageously A second similar material (eg, tantalum nitride), wherein the second material is selectively plasma etchable relative to the first material. In Fig. 1B, a selective anti-reflection layer (ARC) 145' is formed on the fourth dielectric layer and a photoresist layer 15 is formed on the top of the ARC. I pass the patterned mask to expose the photoresist layer 15G to actinic radiation, then develop the photoresist layer, transfer the mask pattern to the photoresist layer, and form an opening in the photoresist layer 50 in a lithographic manner. 155. The area of the ARC 145 is exposed at the bottom of 200924058 of the opening 丨55. The ARC 145 is a bottom ARC or BARC because it is formed under the photoresist layer 150. An alternate top ARC (TARC) formed over the photoresist, or both TARC and BARC can be used. A combination of a photoresist layer and an ARC (ie, both BARC, TARC or BARC and TARC) is defined as an imaging layer. In FIG. 1C, a reactive ion etch (RIE) that etches the ARC 145 faster than the photoresist layer 150 (ie, RIE that is selective for the ARC to the 145 photoresist layer 150) is removed in the opening 155 of FIG. The area of the exposed ARC 145 'has the area of the fourth dielectric layer 14 暴 in the bottom of the opening 155A. Example of the engraving arc 145 The RIE process consists of etching a layer of I35 fast Rig with a mixed CF4/CHF3/Ar/〇2 gas-derived plasma (ie, for the fourth

在圖1D中，使用蝕刻第四介電層14〇比輪廓調 對第四介電層140進行對輪廓 :的RIE)移除在圖ic的開口 層140的區域，以在開口 155B 罾的區域。請注意，光阻層15〇 層140的RIE蝕刻所侵蝕。在 3 口大於在光阻層之底面的開 實例RIE製程包括用混合的 漿來蝕刻。此化學作用（在適當 、壓力及氣流下）可蝕刻氧化 200924058 矽比氮化矽快約25倍。 在圖1E中，使用蝕刻輪廓調整層135比第三介電 層130快的RIE(即，對輪廓調整層135進行對第三介 電層130具有選擇性的RIE)移除在圖1D的開口 155B 中暴露之輪廓調整層135的區域，以在開口 155C的 底部中暴露第三介電層的區域。蝕刻輪廓調整層的實 例RIE製程包括用混合的CHF3/CF4/Ar氣體衍生電漿 來蝕刻。此化學作用（在適當的偏壓、正向及反向功 率、壓力及氣流下）可蝕刻氮化矽比氧化矽快約4倍。 有利的是將輪廓調整層135(及蝕刻停止層115)保持得 越薄越好。 在圖1F中，使用蝕刻第三、第二及第一介電層 130、125及120比蝕刻停止層115及輪廓調整層135 快的RIE(即，對第三介電層130進行對蝕刻停止層115 及輪廓調整層135具有選擇性的RIE)移除在圖1E的 開口 155C中暴露之第三介電層130的區域連同在圖 1E的開口 155C下對準之第二及第一介電層125及120 的區域，以在開口 155D的底部中暴露蝕刻停止層的 區域。蝕刻第三、第二及第一介電層130、125及120 的實例RIE製程包括用混合的CO/C4F8/Ar氣體衍生電 漿來钱刻。請注意，光阻層1 50及ARC 145進一步為 第三介電層130、第二介電層丨25及第一介電層120 200924058 的RIE蝕刻所侵蝕。此蝕刻對第四介電層140不具有 選擇性，且結合光阻層150及ARC 145的進一步侵 蝕，在形成穿過第四介電層140之開口 155D的區域 中形成開口 155D的倒錐形上方區域160。區域160中 開口 155D的側壁以在側壁及與基板100之頂面110 平行的平面之間所測量的角度"an呈錐形。開口 155D 的下方區域165係形成穿過輪廓調整層135及第三、 第二及第一介電層130、125及120。區域165中開口 155D的側壁呈現在側壁及與基板100之頂面110平行 的平面之間所測量的角度V’。開口 155D具有在第四 介電層140的頂面所測量的寬度W1、在輪廓調整層 135的頂面所測量的寬度W2、及在蝕刻停止層115的 頂面所測量的寬度W3。W1大於W2。在一實例中， W1約為0.28微米及W3約為0.16微米。 在一實例中，W2等於W3及角度”b”為介於約87° 及不大於90°之間。在一實例中，W2大於W3，但角 度” b”小於角度” a”。再者，輪廓調整層135的存在因 為光阻層150的侵蝕受到控制而允許開口 155D在上 方區域160中於第四介電層140的頂面變寬，並促進 在下方區域165中形成直線或侧壁。若沒有輪廓調整 層135,不是開口 155D在頂部會顯得太窄而不能在金 屬填充中未併入大空隙的情形下用金屬填充，就是 W1的值必須大上許多才能維持在輪廓調整層的存在 200924058 下所得的W3相同值。 在圖1G中，使用氧氣灰化 移除光阻層150及ARC 145(；見^ 2电漿钱刻） 可在圖1H *所示的製程後^于圖)。^者，此步驟 ^層115保留完整的情況下執行光阻移; =靖罐路1G5Am錢路⑽包 在圖1Η中，使用蝕刻停止層115比第一、第一 =π:125Γ° 快的RIE(即，對“ 1 、弟二及第三介電層12G、125及 3〇、至屬線路1〇5及視情況第四介電層M〇具有選 〇 性的RIE)移除在®1G的開σ 1551)中暴露之侧停止 層115的區域，以在開口咖的底部中暴露金屬線路 的區域。對蝕刻停止層115進行蝕刻的實例RIE 製程包括用混合的CtVCHFVAr/O2氣體衍生電漿來蝕 刻。區域160在與基板1〇〇中線路1〇5之頂面垂直的 方向中，具有從第四介電層140之頂面至輪廓調整層 135之頂面所測量的高度H1。區域165在與基板ι〇〇 中線路105之頂面垂直的方向中，具有從輪廓調整層 135之頂面至基板1〇〇中線路1〇5之頂面所測量的高 度H2。在一實例中’對介於約！ 4微米及約2 〇微米 的總開口深度（即，Η 1 +H2)，Η 1約為〇·4微米，及H2 -20- 200924058 為介於約1微米及約1.6微米。在W3(見圖IF)的值約 0.16微米的情況下，開口 155E之深度與寬度的比率 為介於約1.4/0.16=約8.75及約2.0/0.16=約12.5。在 一實例中，H1+H2等於或大於約1微米。在一實例中， H1+H2等於或大於約2微米。在一實例中， (H1+H2)/W1大於或等於5。在一實例中，（H1+H2)/W1 大於或等於8。 在圖II中，執行選擇性直流(DC)清洗(如，用惰 性氣體的濺鍍清洗），其後在開口 155E的側壁及第四 介電層140的頂面上形成導電襯墊170，其後用導電 芯導體175填滿開口 155E。在一實例中，導電襯墊170 按沈積順序包含一層TaN、一層Ta、及一層Cu，及芯 導體175包含電鍍銅。 在圖1J中，執行化學機械拋光(CMP)以從第四介 電層140上方移除襯墊170及芯導體175，以形成從 第四介電層之頂面185延伸至線路105之頂面（與線路 105電接觸）的導電介層180。在CMP後，介層180的 頂面190與第四介電層140的頂面185共面。 應明白，按照最簡單的形式，本發明的具體實施 例可在介電質堆疊上實施，在該堆疊中，用單一的介 電層取代圖丨的第一、第二及第三介電層丨20、125 200924058 及130。在其他具體貫施例中，堆疊中可以有由圖1 的第一、第二及第三介電層12〇、125及13〇所代表的 二個介電層，不過此三層應全部為相似的材料(如，氧 化矽）或對用以蝕刻停止及輪廓調整層的RIE具有相 似的選擇性。 圖2A至2C為根據本發明之具體實施例之第一示 |巳性二維積體電路之製造的橫截面。在圖2A中，上 方半導體基板200包括：氧化矽接合層2〇5、在接合 層上的BOX層210、半導體層215(包括在半導體層; 形成的半導體區域220及STI 225)、在半導體層 之頂部上的輪廓調整層230、及在輪廓調整層上的 電層说。包含在半導體區域220中形成之源 (S/D)及在S/D之間在矽區域上方形成之閘極的示範性 場效電晶體(FET)240係在基板2〇〇中形成。半導體岸 215 包含如 Si、SiGe、Ge、GaAs 或 lnp 〇 " 蝕刻停止層亦可用作銅的擴散障壁層及/或用作 基板300包括：半導體基底層3〇5、在基底矽屌 上的BOX層310、包括在矽層中形成之半導體區域3 9 及STI 325的半導體層315、包括接點335的層間介: 質（丨L D)線路組3 3 0及在IL D線路組3 3 〇之介泰s笔 兔增355 -22 - 200924058 之相應介電層中形成的線路340及350。半導體基底 層305包含如Si、SiGe、Ge、GaAs或InP。半導體層 315 包含如 Si、SiGe、Ge、GaAs 或 InP。 ILD線路層包含嵌埋其中的介電層及一或多個線 路、介層或接點。顯示ILD線路組330具有三個ILD 線路層。ILD線路組330可包括更多或更少的ILD層 (減少到含有接點335的一層），或可包含積體電路設 計所需的許多層。舉例而言，ILD線路組330的ILD 線路層為利用鑲嵌及雙鑲嵌製程形成的鑲嵌及雙鑲嵌 ILD 層。 鑲嵌程序如下：其中在介電層中形成線路溝渠或 介層開口，在介電質的頂面上沈積填充溝渠之足夠厚 度的導電體，及執行化學機械拋光(CMP)程序以移除 多餘導體，及使導體表面與介電層表面共面以形成鑲 嵌線路（或鑲欲介層）。僅形成一溝渠及一線路（或一介 層開口及介層）時，將此程序稱為「單鑲嵌」。 雙鑲嵌程序如下：其中形成穿過介電層整個厚度 的介層開口，接著形成部分穿過任何給定橫截面圖中 介電層的溝渠。所有介層開口均與上方的整合線路溝 渠及下方的線路溝渠相交，但並非所有溝渠必須與介 層開口相交。在介電質的頂面上沈積填充溝渠及介層 -23 - 200924058 開口之足夠厚度的導電體，然後執行CMP程序 ，以使 溝渠中的導體表面與介電層表面共面，以形成雙鑲嵌 線路及具有整合雙鑲嵌介層的雙鑲嵌線路。 回到圖2A’示範性場效電晶體(FET)345包含在 半導體區域320中形成的源極/汲極(S/D)及在基板3〇〇 中形成的S/D之間在矽區域上方形成的閘極。接點335 及線路340電連接FET 345至電路或電路的部分。基 板300另外包括在ILD線路組355之頂部上的姓刻停 止層360及在蝕刻停止層上的氧化矽接合層365。接 合層205及365將基板200及300接合為單一的結構。 接合製程包括使接合層205及365在室溫以上但在例 如350 C以下的溫度下接觸。 在一實例中’介電層235、355及STI 225係分別 從由以下項目組成的群組中選出：熱氧化物、HDP氧 化物、PECVD氧化物、UDP氧化物、te〇S氧化物、 及旋塗氧化物’且接合層205及365為LTO。在一實 例中，輪廓調整層230及儀刻停止層360係分別從由 以下項目組成的群組中選出：氮化石夕、碳化石夕、氧氮 化石夕、或氧破化石夕。在一第二實例中，介電層235、 355及STI 225及接合層205及365有利的是第一相似 材料（如’氧化發）’且#刻停止層3 60及輪廓調整層 2 3 0有利的疋弟二相似材料（如’ I化石夕），其中第一及 -24 - 200924058 第一材料可相對於彼此加以選擇性電漿餘刻。在一實 例中電層235為介於約2500 A及約7500 A厚。 在只例中，輪廓調整層230為介於約250人及約1000 f f。在—實例中，STI 225為介於約1500 A及約2500 么厚。在一實例中，BOX層210為介於約15〇〇 A及 ^ 2500 A厚。在—實例中，接合層210為介於約2500 及約3500 A厚。在一實例中，接合層365為介於約 2500 A及約3500 A厚。在一實例中，蝕刻停止層360 為介於約250·Α及約1000 A厚。 可藉由在形成FET 240後，移除在BOX層210 之下的半導體（如矽）基底層，其後沈積一層 LTO以在 B〇X層225上形成接合層205，從SOI基板形成基板 200。可完全用ILD線路組330從SOI基板形成基板 3〇〇，其後沈積蝕刻停止層36〇及沈積一層LT〇以形 成接合層365。 在圖2A中’光阻層4〇〇在介電層上形成及圖案 化以在光阻層中以與上述在圖1B中在光阻150中形 成開口 155相似的方式形成開口 405。雖然圖2A中未 顯不ARC(TARC或BARC)，但可使用ARC(TARC及/ 或 BARC)。 在圖2B中’形成開口 4丨〇穿過介電層235、輪廓 -25 - 200924058 Ο Ο 調整層230、STI層225、BOX層210、接合層2〇5及 365、及蝕刻停止層360，以暴露線路350的頂面。然 後移除光阻層400(見圖2Α)。其方法相似於上述關於 在圖1Η中形成開口 155Ε的方法。首先，當介電層235 為氧化發及輪廊§周整層2 3 0為氮化砍時，使用例如、、尸 合的CO/qFVAr氣體衍生電漿對介電層235進行對钤 廓調整層230具有選擇性的RIE。此化學作用（在適^ 的偏壓、正向及反向功率、壓力及氣流下）可蝕刻=二 矽比氮化矽快約25倍。第二，當介電層235及srn 2乃 為二氧㈣及輪廓調整層為氮化㈣，使Μ如混么 的CHF3/CF4/Ar氣體衍生電漿對輪廊 口一 對介電層235…5具有選擇二= 作用（在適當的偏壓、正向及反向功率、壓 ^In FIG. 1D, the etched fourth dielectric layer 14 is used to align the fourth dielectric layer 140 with a profile: RIE) is removed from the region of the opening layer 140 of FIG. ic to the region of the opening 155B . Note that the photoresist layer 15 is etched by the RIE etching of the layer 140. An open example RIE process in which three ports are larger than the bottom surface of the photoresist layer includes etching with a mixed slurry. This chemistry (under appropriate pressure, gas flow) etches oxides. 200924058 矽 is about 25 times faster than tantalum nitride. In FIG. 1E, the RIE that is faster than the third dielectric layer 130 using the etch profile adjustment layer 135 (ie, the RIE that is selective to the third dielectric layer 130 to the contour adjustment layer 135) is removed at the opening of FIG. 1D. The area of the contouring layer 135 exposed in 155B exposes the area of the third dielectric layer in the bottom of the opening 155C. An example RIE process for etching the profile adjustment layer involves etching with a mixed CHF3/CF4/Ar gas-derived plasma. This chemistry (under appropriate bias, forward and reverse power, pressure, and gas flow) etches tantalum nitride about four times faster than yttrium oxide. It is advantageous to keep the profile adjustment layer 135 (and the etch stop layer 115) as thin as possible. In FIG. 1F, the RIE that etches the third, second, and first dielectric layers 130, 125, and 120 faster than the etch stop layer 115 and the contour adjustment layer 135 is used (ie, the third dielectric layer 130 is etched to stop). Layer 115 and contouring layer 135 have selective RIE) removal of the region of third dielectric layer 130 exposed in opening 155C of FIG. 1E along with second and first dielectrics aligned under opening 155C of FIG. 1E The regions of layers 125 and 120 are regions that expose the etch stop layer in the bottom of opening 155D. An example RIE process for etching the third, second, and first dielectric layers 130, 125, and 120 includes engraving with a mixed CO/C4F8/Ar gas-derived plasma. Please note that the photoresist layer 150 and the ARC 145 are further etched by the RIE etching of the third dielectric layer 130, the second dielectric layer 25, and the first dielectric layer 120 200924058. This etch is not selective to the fourth dielectric layer 140, and in combination with the further erosion of the photoresist layer 150 and the ARC 145, the inverted tapered shape of the opening 155D is formed in the region forming the opening 155D through the fourth dielectric layer 140. Upper area 160. The sidewalls of the opening 155D in the region 160 are tapered at an angle "an measured between the sidewall and a plane parallel to the top surface 110 of the substrate 100. A lower region 165 of the opening 155D is formed through the contouring layer 135 and the third, second, and first dielectric layers 130, 125, and 120. The sidewalls of opening 155D in region 165 exhibit an angle V' measured between the sidewalls and a plane parallel to top surface 110 of substrate 100. The opening 155D has a width W1 measured on the top surface of the fourth dielectric layer 140, a width W2 measured on the top surface of the contour adjustment layer 135, and a width W3 measured on the top surface of the etch stop layer 115. W1 is greater than W2. In one example, W1 is about 0.28 microns and W3 is about 0.16 microns. In one example, W2 is equal to W3 and angle "b" is between about 87° and no more than 90°. In one example, W2 is greater than W3, but the angle "b" is less than the angle "a". Moreover, the presence of the contour adjustment layer 135 allows the opening 155D to widen in the upper region 160 on the top surface of the fourth dielectric layer 140 because the erosion of the photoresist layer 150 is controlled, and promotes the formation of a straight line in the lower region 165 or Side wall. Without the contour adjustment layer 135, instead of the opening 155D being too narrow at the top to be filled with metal in the case where the metal fill does not incorporate a large gap, the value of W1 must be much larger to maintain the presence of the contour adjustment layer. The same value of W3 obtained under 200924058. In Fig. 1G, the photoresist layer 150 and the ARC 145 are removed using oxygen ashing (see Fig. 1H*) after the process shown in Fig. 1H*. ^, this step ^ layer 115 remains intact to perform the photoresist shift; = Jingkang Road 1G5Am money road (10) package in Figure 1Η, using the etch stop layer 115 faster than the first, first = π: 125 Γ ° RIE (ie, RIE with selective selectivity for "1, 2nd and 3rd dielectric layers 12G, 125 and 3〇, to line 1〇5 and optionally fourth dielectric layer M") The area of the side stop layer 115 exposed in the open σ 1551) of 1G to expose the area of the metal line in the bottom of the opening coffee. Example of etching the etch stop layer 115 The RIE process includes deriving electricity with a mixed CtVCHFVAr/O2 gas The etch is etched. The region 160 has a height H1 measured from the top surface of the fourth dielectric layer 140 to the top surface of the contour adjustment layer 135 in a direction perpendicular to the top surface of the wiring 1〇5 in the substrate 1〇〇. The region 165 has a height H2 measured from the top surface of the contour adjustment layer 135 to the top surface of the wiring 1〇5 in the substrate 1 in a direction perpendicular to the top surface of the wiring 105 in the substrate ι. The middle 'pair is about 4 microns and the total opening depth of about 2 〇 microns (ie, Η 1 +H2), Η 1 is about 〇·4 microns And H2 -20- 200924058 is between about 1 micron and about 1.6 microns. In the case of W3 (see Figure IF) having a value of about 0.16 microns, the ratio of depth to width of opening 155E is between about 1.4/0.16 = About 8.75 and about 2.0/0.16 = about 12.5. In one example, H1 + H2 is equal to or greater than about 1 micron. In one example, H1 + H2 is equal to or greater than about 2 microns. In one example, (H1 + H2) /W1 is greater than or equal to 5. In one example, (H1+H2)/W1 is greater than or equal to 8. In Figure II, selective direct current (DC) cleaning (eg, cleaning with inert gas sputtering) is performed, Thereafter, a conductive pad 170 is formed on the sidewall of the opening 155E and the top surface of the fourth dielectric layer 140, and thereafter the opening 155E is filled with the conductive core conductor 175. In an example, the conductive pad 170 includes a layer in the deposition order. TaN, a layer of Ta, and a layer of Cu, and core conductor 175 comprise electroplated copper. In FIG. 1J, chemical mechanical polishing (CMP) is performed to remove liner 170 and core conductor 175 from above fourth dielectric layer 140 to form Conductive via 180 extending from top surface 185 of the fourth dielectric layer to the top surface of line 105 (in electrical contact with line 105). After CMP, via 18 The top surface 190 of 0 is coplanar with the top surface 185 of the fourth dielectric layer 140. It will be appreciated that in its simplest form, embodiments of the present invention may be implemented on a dielectric stack in which a single The dielectric layer replaces the first, second and third dielectric layers 20, 125 200924058 and 130 of the figure. In other specific embodiments, the stack may have the first, second and The three dielectric layers of the three dielectric layers 12, 125, and 13 ,, but the three layers should all be similar materials (eg, hafnium oxide) or similar to the RIE used for the etch stop and contour adjustment layers. The selectivity. 2A through 2C are cross sections of the manufacture of a first two-dimensional integrated circuit in accordance with a specific embodiment of the present invention. In FIG. 2A, the upper semiconductor substrate 200 includes a yttrium oxide bonding layer 2〇5, a BOX layer 210 on the bonding layer, a semiconductor layer 215 (included in the semiconductor layer; the formed semiconductor region 220 and the STI 225), and a semiconductor layer. The contour adjustment layer 230 on the top and the electrical layer on the contour adjustment layer. An exemplary field effect transistor (FET) 240 including a source (S/D) formed in the semiconductor region 220 and a gate formed over the germanium region between the S/Ds is formed in the substrate 2A. The semiconductor bank 215 includes a diffusion barrier layer such as Si, SiGe, Ge, GaAs or lnp, which can also be used as a diffusion barrier layer for copper and/or as a substrate 300 comprising: a semiconductor substrate layer 3〇5 on the substrate The BOX layer 310, the semiconductor layer 319 including the semiconductor region 319 and the STI 325 formed in the 矽 layer, the interlayer dielectric including the contact 335: the 丨 (LD) line group 3 3 0 and the IL D line group 3 3 Lines 340 and 350 formed in the corresponding dielectric layers of 〇之介泰s pen rabbits 355 -22 - 200924058. The semiconductor substrate layer 305 contains, for example, Si, SiGe, Ge, GaAs or InP. The semiconductor layer 315 contains, for example, Si, SiGe, Ge, GaAs or InP. The ILD circuit layer includes a dielectric layer embedded therein and one or more lines, vias, or contacts. The display ILD line group 330 has three ILD line layers. The ILD line set 330 can include more or fewer ILD layers (reduced to a layer containing contacts 335), or can include many layers required for integrated circuit design. For example, the ILD line layer of the ILD line set 330 is a mosaic and dual damascene ILD layer formed using damascene and dual damascene processes. The damascene procedure is as follows: a line trench or via opening is formed in the dielectric layer, a sufficient thickness of the electrical conductor filling the trench is deposited on the top surface of the dielectric, and a chemical mechanical polishing (CMP) process is performed to remove the excess conductor And causing the surface of the conductor to be coplanar with the surface of the dielectric layer to form a damascene line (or intercalation layer). This procedure is referred to as "single inlay" when only one trench and one line (or a via opening and via) are formed. The dual damascene procedure is as follows: where a via opening is formed through the entire thickness of the dielectric layer, followed by a trench that partially passes through the dielectric layer in any given cross-sectional view. All of the via openings intersect the upper integrated trench and the underlying trench, but not all trenches must intersect the via opening. Depositing a sufficient thickness of the gap filling the trench and the via -23 - 200924058 on the top surface of the dielectric, and then performing a CMP process to make the surface of the conductor in the trench coplanar with the surface of the dielectric layer to form a dual damascene Lines and dual damascene lines with integrated dual damascene layers. Returning to FIG. 2A', an exemplary field effect transistor (FET) 345 includes a source/drain (S/D) formed in the semiconductor region 320 and an S/D formed in the substrate 3A in the germanium region. The gate formed above. Contact 335 and line 340 electrically connect FET 345 to the portion of the circuit or circuit. The substrate 300 additionally includes a surname stop layer 360 on top of the ILD line set 355 and a yttrium oxide bond layer 365 on the etch stop layer. Bonding layers 205 and 365 join substrates 200 and 300 into a single structure. The bonding process includes contacting the bonding layers 205 and 365 above room temperature but at a temperature below, for example, 350 C. In one example, dielectric layers 235, 355, and STI 225 are each selected from the group consisting of thermal oxides, HDP oxides, PECVD oxides, UDP oxides, te〇S oxides, and Spin-on oxide' and bonding layers 205 and 365 are LTO. In one example, the contouring layer 230 and the inscription stop layer 360 are each selected from the group consisting of: nitrite, carbon carbide, oxynitride, or oxygen decarburization. In a second example, dielectric layers 235, 355 and STI 225 and bonding layers 205 and 365 are advantageously first similar materials (eg, 'oxidized hair'' and #刻止层3 60 and contouring layer 2 3 0 A favorable similar material (such as 'I fossil eve), wherein the first and -24 - 200924058 first materials can be selectively plasma-replaced relative to each other. In one embodiment, the electrical layer 235 is between about 2500 A and about 7500 A thick. In the example, the contouring layer 230 is between about 250 and about 1000 ff. In an example, STI 225 is between about 1500 A and about 2500 thick. In one example, the BOX layer 210 is between about 15 A and 252 500 thick. In an example, the bonding layer 210 is between about 2500 and about 3500 A thick. In one example, the bonding layer 365 is between about 2500 A and about 3500 A thick. In one example, the etch stop layer 360 is between about 250 Å and about 1000 Å thick. After the FET 240 is formed, the semiconductor (eg, germanium) underlying layer under the BOX layer 210 is removed, followed by deposition of a layer of LTO to form a bonding layer 205 on the B〇X layer 225, and the substrate 200 is formed from the SOI substrate. . The substrate 3 can be formed from the SOI substrate entirely using the ILD line group 330, after which the etch stop layer 36 is deposited and a layer of LT is deposited to form the bonding layer 365. The photoresist layer 4 is formed and patterned on the dielectric layer in Fig. 2A to form openings 405 in the photoresist layer in a manner similar to that described above for forming openings 155 in photoresist 150 in Fig. 1B. Although ARC (TARC or BARC) is not shown in Figure 2A, ARC (TARC and / or BARC) can be used. In FIG. 2B, 'the opening 4 is formed through the dielectric layer 235, the outline-25 - 200924058 Ο Ο the adjustment layer 230, the STI layer 225, the BOX layer 210, the bonding layers 2〇5 and 365, and the etch stop layer 360, To expose the top surface of line 350. The photoresist layer 400 is then removed (see Figure 2). The method is similar to the above method for forming the opening 155 在 in Fig. 1 . First, when the dielectric layer 235 is an oxidized hair and the turret is circumscribed, the whole layer of 203 is nitrided, and the dielectric layer 235 is adjusted by using, for example, a CO/qFVAr gas-derived plasma. Layer 230 has a selective RIE. This chemistry (under appropriate bias, forward and reverse power, pressure, and gas flow) can be etched = two turns about 25 times faster than tantalum nitride. Second, when the dielectric layers 235 and srn 2 are dioxins (four) and the profile adjustment layer is nitrided (four), the CHF3/CF4/Ar gas-derived plasma is mixed with a pair of dielectric layers 235 of the porch. ...5 has the choice of two = action (at the appropriate bias, forward and reverse power, pressure ^

可餘刻氮化石夕比氧化石夕快約4倍。 /；'L 整層230(及蝕刻停止層36〇)保持 越：將：廓。周 當stI 235、box層210、接合層;^第三’ 且輪廓調整層230及_停止層 5為氧化石夕 用例如混合的CO/C4F8/Ar氣體衍雷將虱化矽時，使 丽層210、接合層2〇5及祕進行=對如235、 及蝕刻停止層360具有選擇性的R 廓調整層23〇 對介電層235不具有選擇性，因此 弟三腿製程 的存在，開口 410在介電層235中且炎輪廓調整層230 在STT 225、BOX 2丨〇、及9接合層有匈錐形縱斷面、 上平直或些許倒錐形縱斷面（盥I+及365中呈大體 、包滑235中之開口 200924058 410的錐形相比）。第四，使用氧氣灰化製程移除光阻 層400(見圖2A)。第五，當蝕刻停止層360及輪廓調 整層230為氮化矽且介電層210、ST1 225、BOX層225 及接合層205及365為氧化矽時，使用例如混合的 CF4/CHF3/Ar/02氣體衍生電漿對蝕刻停止層360進行 對介電層235、STI 225、BOX層210及接合層205及 365具有選擇性的RIE。第六，執行使用％及H2的選 擇性DC清洗（即，混合的N2/H2氣體衍生電漿蝕刻）。 在圖2C中，用與線路350電接觸之導電介層420 的導電體填充開口 410(見圖2B)。在一實例中，藉由 在開口 410的側壁上（見圖2B)及介電層235的頂面上 沈積導電概整5其後用導電怎導體填滿開口 ^形成介 層420。在一實例中，導電襯墊按沈積順序包含一層 TaN、一層Ta、及一層Cu，及芯導體包含電鍍銅。在 填充開口後，執行CMP以從介電層235上方移除襯墊 及芯導體，以形成從介電層235之頂面425延伸至線 路350之頂面的介層420。在CMP後，介層420的頂 面430與介電層235的頂面425共面。因此，介層420 為镶敌介層。 可使導電接點（未顯示）穿過介電層235到達FET 240的S/D及閘極。或者，可在形成光阻層400(見圖 2 A)之前，形成接點。含有線路的附加層間介電層可在 -27 - 200924058 介電層235的頂部上形成，其中線路將介 接至FET 24〇及將FET 345電連接 :^迷 3。 明翏見圖The remaining nitrite is about 4 times faster than the oxidized stone. /; 'L full layer 230 (and etch stop layer 36 〇) keep the more: will: profile. Week as stI 235, box layer 210, bonding layer; ^ third ' and contour adjustment layer 230 and _ stop layer 5 are oxidized stone, such as mixed CO / C4F8 / Ar gas derivation will be 虱 ,, The layer 210, the bonding layer 2〇5 and the secret layer=the R-profile adjustment layer 23 which is selective for the 235 and the etch stop layer 360 are not selective to the dielectric layer 235, so the presence of the three-leg process is open. 410 in the dielectric layer 235 and the swell profile adjustment layer 230 has a Hungarian tapered profile, a straight upper or a slightly inverted tapered profile at the STT 225, BOX 2, and 9 bonding layers (盥I+ and 365) The middle is generally larger than the taper of the opening 200924058 410 in the package 235). Fourth, the photoresist layer 400 is removed using an oxygen ashing process (see Figure 2A). Fifth, when the etch stop layer 360 and the contour adjustment layer 230 are tantalum nitride and the dielectric layer 210, the ST1 225, the BOX layer 225, and the bonding layers 205 and 365 are tantalum oxide, for example, mixed CF4/CHF3/Ar/ is used. 02 The gas-derived plasma etches the etch stop layer 360 to the dielectric layer 235, the STI 225, the BOX layer 210, and the bonding layers 205 and 365. Sixth, selective DC cleaning using % and H2 (i.e., mixed N2/H2 gas-derived plasma etching) is performed. In Figure 2C, the opening 410 is filled with an electrical conductor of a conductive via 420 in electrical contact with line 350 (see Figure 2B). In one example, the dielectric layer 420 is formed by depositing a conductive outline 5 on the sidewall of the opening 410 (see Fig. 2B) and the top surface of the dielectric layer 235, and then filling the opening with a conductive conductor. In one example, the conductive pads comprise a layer of TaN, a layer of Ta, and a layer of Cu in a deposition order, and the core conductor comprises electroplated copper. After filling the openings, CMP is performed to remove the pads and core conductors from above the dielectric layer 235 to form a via 420 that extends from the top surface 425 of the dielectric layer 235 to the top surface of the line 350. After CMP, top surface 430 of via 420 is coplanar with top surface 425 of dielectric layer 235. Therefore, the dielectric layer 420 is an enemies. Conductive contacts (not shown) may be passed through dielectric layer 235 to the S/D and gates of FET 240. Alternatively, a contact may be formed before the photoresist layer 400 (see Fig. 2A) is formed. An additional interlayer dielectric layer containing circuitry can be formed on top of -27 - 200924058 dielectric layer 235, where the circuitry will interface to FET 24 and electrically connect FET 345. See the picture

圃3為根據本發明之具體實施例之二 之製造中附加製造步驟的橫截面。在圖3 _貝飞路 FET 240之一的導電接點44〇,及在介電層；二至 ILD線路組445。助線路層组445 ^ 形成 端塾奶。顯示ILD線路組445 ^路4 0及終 仰線路層組445可包括更多或更有;^=路層。 含有線路/終端墊455的一#)，二土D層(減少到 計所需的許多層。舉例而言，IL二線二3積體電路設圃3 is a cross section of an additional manufacturing step in the manufacture of a second embodiment of the present invention. In Fig. 3, the conductive contact 44〇 of one of the feifei FETs 240, and the dielectric layer; and the second to the ILD line group 445. The auxiliary circuit layer group 445 ^ forms the end milk. The display ILD line group 445 ^way 40 and the terminal line layer group 445 may include more or more; ^ = road layer. One #), two earth D layer containing line/terminal pad 455 (reducing many layers required for metering. For example, IL two-wire two-three integrated circuit design

線路層為利用鑲嵌及雙鑲嵌製程开/成二445的1LD ILD μ 〇 440 /成的鑲嵌及雙鑲嵌 广滑雜點44〇顯示為鎮嵌接點。 將接點440連接至介層42()。因此 ^線路450 及 FET 345 的三 FET240 可在圖2C的介電層235上方形成 非SOI基板。 方基板錢㈣基板，而The circuit layer is a 1LD ILD μ 440 440 / intolaid and dual damascene wide-spotted 44 利用 using the inlay and dual damascene process open / 445. Contact 440 is connected to via 42(). Thus, the three FETs 240 of line 450 and FET 345 can form a non-SOI substrate over dielectric layer 235 of FIGURE 2C. Square substrate money (four) substrate, and

圖2A至2C及圖3的兩個實例中 BOX 2U)為⑽基板，切層3 二J 板。應明白，可用塊狀石夕基板取代基板細為基 -28- 200924058 因此，各具體實施例提供使用深介層結構之深介 層及半導體裝置的製程方法，該深介層結構具有比較 不會受到金屬填充問題之影響的縱斷面。 上述本發明具體實施例的說明是為了暸解本發 明。應明白，本發明不限於本文所述的特定具體實施 例，而是在不脫離本發明範疇下，能夠進行各種修改、 重新配置及替換，正如本技術人士所明白的。因此， 以下申請專利範圍是用來涵蓋此種在本發明精神及範 售之内的修改及變更。 【圖式簡單說明】 本發明的特色如隨附的申請專利範圍所述。然 而，要完全瞭解本發明本身，請在連同附圖一起閱讀 時，參考解說性實施例的詳細說明，圖式中： 圖1A至1J為根據本發明之具體實施例之示範性 導電介層之製造的橫截面； 圖2A至2C為根據本發明之具體實施例之第一示 範性三維積體電路之製造的橫截面；及 圖3為根據本發明之具體實施例之三維積體電路 之製造中附加製造步驟的橫截面。 -29 - 200924058 【主要元件符號說明】 100 、 200 105 110、185、190、425 115 、 360 120 125 130 135 > 230 140 145 150 、 400 155、155A、155B、155C 160 165 170 175 180 > 420 205 、 365 210、310 215 、 315 220、320 225 ' 325 235 ' 355 半導體基板 金屬線路 頂面 飯刻停止層 第一介電層 第二介電層 第三介電層 輪廓調整層 第四介電層 選擇性抗反射塗層(ARC) 光阻層 、155D、155E、405、410 開口 倒錐形上方區域 下方區域 導電襯墊 導電芯導體 介層 氧化矽接合層 BOX層 半導體層 半導體區域 淺溝渠隔離(ST1) 介電層 -30 - 200924058 240 > 345 場效電晶體(FET) 300 基板 305 半導體基底層 330、445 層間介電質(ILD)線路組 335 ' 440 接點 340、350、450 線路 455 終端墊 S/D 源極/没極In the two examples of Figures 2A to 2C and Figure 3, BOX 2U) is a (10) substrate, a sliced layer 3 and a J-plate. It should be understood that the substrate can be replaced by a bulk-like substrate. -28-200924058 Accordingly, various embodiments provide a method for processing a deep via layer and a semiconductor device using a deep via structure, which is relatively inferior. Longitudinal section affected by metal filling problems. The above description of specific embodiments of the invention has been presented for purposes of understanding the invention. It is to be understood that the invention is not limited to the specific embodiments described herein, and that various modifications, modifications and substitutions are possible without departing from the scope of the invention. Therefore, the following claims are intended to cover such modifications and variations within the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS The features of the present invention are as set forth in the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS The detailed description of the illustrative embodiments, in which reference is made in conjunction with the accompanying drawings, in which: FIG. 1A to 1J are exemplary conductive layers in accordance with an embodiment of the present invention. 2A to 2C are cross sections of the manufacture of a first exemplary three-dimensional integrated circuit in accordance with an embodiment of the present invention; and FIG. 3 is a fabrication of a three-dimensional integrated circuit in accordance with an embodiment of the present invention. A cross section of the additional manufacturing step. -29 - 200924058 [Description of main component symbols] 100, 200 105 110, 185, 190, 425 115, 360 120 125 130 135 > 230 140 145 150 , 400 155 , 155A , 155B , 155C 160 165 170 175 180 > 420 205 , 365 210 , 310 215 , 315 220 , 320 225 ' 325 235 ' 355 semiconductor substrate metal line top surface rice stop layer first dielectric layer second dielectric layer third dielectric layer contour adjustment layer fourth Electrical layer selective anti-reflective coating (ARC) photoresist layer, 155D, 155E, 405, 410 open area under the upper region of the inverted cone. Conductive gasket conductive core conductor interlayer yttrium oxide bonding layer BOX layer semiconductor layer semiconductor region shallow trench Isolation (ST1) Dielectric Layer -30 - 200924058 240 > 345 Field Effect Transistor (FET) 300 Substrate 305 Semiconductor Substrate 330, 445 Interlayer Dielectric (ILD) Line Group 335 ' 440 Contact 340, 350, 450 Line 455 terminal pad S/D source / no pole

Claims (1)

200924058 十、申請專利範圍： 積體f路中製造超深介叙方法，其包含: 土板之一頂面上形成一蝕刻停止層； J該蝕刻停止層之—頂面上形成一第二介 在該第一介電層之—頂面 曰’ 在該輪㈣答成一輪廓調整層； =;第2之一頂面上形成-第二介電層； ,,〜 "電層之一頂面上形成一成傻Μ (photo-imaging layer)； 成像層 3成像層中形成一開口，該第 的一區域暴露於該開口的-底部中；層之该頂面 以一對該輪廓調整層具有 作用對該第二介電層進行反^擇^的弟一钱刻化學 過該第二介電層的開口；應[生雄子韻刻，以形成一穿 刻化輪具有選擇性的第二餘 該開口延伸穿賴輪廓^層伙應性料㈣，以使 層具= S = f有選擇性及對糊停止 心评ί王的弟二蝕刻化學 f 刻，—= 刻化學作用對該敍刻^止層n具有選擇性的第四！虫 該開口延伸穿過該_停I層；τ /性離子糊，以使 /成像層，在該移除該成像層後，該開口從該 -•32- 200924058 第二介電層之該頂面延伸穿 廓調整層、穿過該第一介I “ 一μ電層、穿過該輪 達該基板之該=及穿職_停止層到 2.如請求項1之方法，复中 第二介電層不具有選擇性、。〜弟三_化學作用對該 學作 用係相同的二::法’其中該第-及第三蝕刻化 4用係其中該第二及第四_化學作 5-如請求項1之方牛，甘士 該第一介電層進行’ 〃該移除該成像層係在該對 層進行反純離子以朗祕刻停止 6. 如請求項1之方法，1 層包含氧切，及該；介電層及第二介電 化石夕。 项。周整層及祕刻停止層包含氡 7. 如請t項1之方法，其中： 在该第二介雷Μ 該頂面平行之第_二之°亥頂面處在與該第二介電層之 方向中所測量之該開口的一第—寬 200924058 度大於在該輪靡調整 測量之該開口的一頂面處在該第-方向中所 處在該第一方6由—曰兑又且大於在該基板之該頂面 二寬度大於或等於該第三寬度；及弟—見度5亥弟 處在二Ι;ίί : = 面至該基板的該頂面 口的一深戶盥…的弟—方向中所測量之該開 度與寬度的—比率等於或大於五。 Ο 8’如明求項1之方法，其進一步包括： 在/移除韻像層後’用該導電體填充該開口。 9 包含如請求項8之方法，其中該用—導電體填充該開口 二，口之側壁及一底部上方沈積一氮化纽層； 在5亥鼠化麵層上沈積一组層； 在該钽層上沈積一種子銅層； 填充ΐί種t銅層上電鍍—電鍍銅層，該電_層完全 兄5亥開口中的剩餘空間；及 上方^：；化學機械拋光，以從該第二介電層之該頂面 銅t除錢她層、馳層、該種子㈣、及該電鍛 請求項1之方法’其_該成像層包括—在該第一 I曰之邊頂面上之—抗反射塗層上方的光阻層，及該 -34 - 200924058 ^成像層t形成該開Π包含透過—圖案化光罩曝光 该光阻層於光化輕射，顯影該曝光的光阻層，及用_初 純刻化學作”純反射塗層進行反應性離子钮 刻，其中該抗反射塗層未受該光阻層保護。 11.,如明求項1G之方法，其中該初始射彳化學作用 =光阻2及該第—介電層具有選擇性，及其_該初始、 第二及第四蝕刻化學作用係相同的化學作用。 ° 12. —種製造三維積體電路之方法，其包含： 形成一第一基板，該第一基板包括： 電連接至一組線路層的第一電晶體，每一線路芦 一相應介電層中包括導電線路； 日 一在該組線路層之離該基板最遠之—最上方線路 層之一頂面上的钕刻停止層，該钱刻停止層與 1 線路層之一線路接觸；及 -在該_停止層之—頂面上的第—介電接合層； 形成一第二基板，該第二基板包括： a， 一第二介電接合層； 在該第二介電接合層之一頂面上的 化物層； 嫩乳 一在該埋藏氧化物層之一頂面上的半 層，該半導體層包括在該石夕層中以介電質隔離而= 相電絕緣的第二電晶體： -35 -200924058 X. Patent application scope: The ultra-deep introduction method in the integrated body f road includes: forming an etch stop layer on one of the top surfaces of the earth plate; J forming a second dielectric layer on the top surface of the etch stop layer The top surface 曰' of the first dielectric layer is formed as a contour adjustment layer in the wheel (4); =; the second dielectric layer is formed on the top surface of the second surface; ,, " Forming a photo-imaging layer thereon; forming an opening in the imaging layer of the imaging layer 3, the first region being exposed in the bottom of the opening; the top surface of the layer having a pair of the contour adjustment layer The role of the second dielectric layer is reversed to control the opening of the second dielectric layer; the [small male rhyme engraving to form a second pass of the engraved wheel is selective The opening extends through the contour layer of the layer (4), so that the layer = S = f is selective and the paste is stopped. The king's second etching chemistry is engraved, -= the chemical action on the scribe ^ Stop layer n has a selective fourth! The opening of the insect extends through the _ stop I layer; τ / ionic paste, to / imaging layer, after the removal of the imaging layer, the opening from the top of the -•32-200924058 second dielectric layer The surface extends through the adjustment layer, passes through the first dielectric layer, and the second and second layers of the substrate are passed through the substrate, and the device is replaced by the method. The dielectric layer is not selective, and the third chemistry is the same as the second:: method 'where the first and third etching 4 are the second and fourth chemistry 5 - as in the case of claim 1, the first dielectric layer is performed. 〃 The removal of the imaging layer is performed on the pair of layers to perform anti-pure ions to stop. 6. As in the method of claim 1, 1 The layer comprises oxygen cut, and the dielectric layer and the second dielectric fossil layer. The whole layer and the secret stop layer comprise 氡 7. If the method of item 1 is selected, wherein: The top surface of the second parallel surface of the second parallel surface of the second dielectric layer measured in the direction of the second dielectric layer is greater than a width of 200924058 degrees greater than The entire measurement of a top surface of the opening in the first direction is at the first side 6 by - 又 and greater than the width of the top surface of the substrate is greater than or equal to the third width; - The degree 5 is in the second place; ίί : = the ratio of the opening to the width measured in the direction of the deeper face of the top surface of the substrate is equal to or greater than five. The method of claim 1, wherein the method further comprises: filling the opening with the conductor after the image layer is removed/removed. 9. The method of claim 8, wherein the opening is filled with a conductor 2. depositing a nitride layer on the sidewall of the port and a bottom; depositing a layer on the surface layer of the 5th layer; depositing a layer of copper on the layer of the layer; plating on the layer of copper a copper layer, the remaining space in the opening of the electric layer; and the upper ^:; chemical mechanical polishing to remove the layer, the layer, the seed from the top surface of the second dielectric layer (d), and the method of the electric forging claim 1 'the imaging layer includes - on the top surface of the first I a photoresist layer over the anti-reflective coating, and the image forming layer t forming the opening comprises exposing the photoresist layer to a photochemical light beam through a patterned mask to develop the exposed photoresist layer, And a reactive ion button is performed with a purely reflective coating, wherein the anti-reflective coating is not protected by the photoresist layer. 11. The method of claim 1, wherein the initial priming chemistry = photoresist 2 and the first dielectric layer are selective, and wherein the initial, second, and fourth etch chemistries are the same Chemical action. 12. A method of manufacturing a three-dimensional integrated circuit, comprising: forming a first substrate, the first substrate comprising: a first transistor electrically connected to a set of circuit layers, each line a corresponding dielectric layer Included in the conductive line; on the top of the set of circuit layers that are furthest from the substrate - the top of the uppermost circuit layer, the stop layer, the stop layer and one of the circuit layers; and a first dielectric bonding layer on the top surface of the _stop layer; a second substrate comprising: a, a second dielectric bonding layer; and a second dielectric bonding layer a chemical layer on a top surface; a half layer on the top surface of one of the buried oxide layers, the semiconductor layer including a second dielectric electrically insulated in the layer Crystal: -35 - 以 200924058 -頂面整：及上及在該介電質隔離之 將兮廓調整層之—頂面上的第—介電層； 一 / "电接合層的—頂面與該第二介電接人 L!: Γί合，該第一及第二介電接合層、該埋藏i 化物層、及該介電質隔離包含—多層第二介電層臧乳 在該第一介電層之一頂面上形成一 在該成像層令形成一開口，_帛， 的-區域暴露於該開口的二部中弟，，電層娜^ 以一對該輪廓調整層具有選擇性的第一姓刻 作用對該第-介電層進行反應性離子_，以 過該第一介電層的開口； 战穿 以-對該第一及第二介電層具有選擇性的第 刻化學作㈣該輪賴㈣進行反應性離子侧 該開口延伸穿過該輪廓調整層； 對战糨鄺調整層具有選擇性及對該蝕刻停止 層具有選擇性的第三㈣化學作用對該第二介電 仃反應性離子_，以使該開口延伸穿過該第二& 層； 电 以—對該第一及第二介電層以及該線路具有選擇 子蝕刻，以使該開口延伸穿過該蝕刻停止層； …移除該成像層，在該移除該成像層後，該開口從該 第一介電層之该頂面延伸穿過該輪廓調整層、穿過該第 -36- 200924058 =介電層、及穿過軸刻停止層到達該線路之—頂面 觸。用一導電趙填充該開口，該導電體與該線路電接 該第-介電衫性射該第三軸彳化學作用對 法，其中該第-—學 :二:=2學：法，該第二及第-刻化學 16·如請求項12之方法， 對該第二介f層進槪應性層係在該 止層進行反触料射彳之間執行。A f忒蝕刻停 17.如請求項12之方法，其令該第__ 層、該埋藏氧化物層、及該第:仏= 矽及5玄輪廓調整層及該飯刻停止層包含氮化石夕。羊 18.如請求項12之方法，其令·· 電層之 在4第—介電層之該頂面處在與該第二介 -37-With 200924058 - top surface: and the first dielectric layer on the top surface of the dielectric layer which is separated from the dielectric layer; a / " top surface of the electrical bonding layer and the second dielectric layer The first and second dielectric bonding layers, the buried dielectric layer, and the dielectric isolation comprise a plurality of second dielectric layers in the first dielectric layer a top surface is formed on the top surface of the image forming layer to form an opening, and the - region is exposed to the opening portion, and the electric layer is a pair of the first surname having the selectivity of the contour adjusting layer Engaging the first dielectric layer with a reactive ion _ to pass through the opening of the first dielectric layer; traversing the first chemistry of the first and second dielectric layers (4) Revolving (4) performing a reactive ion side of the opening extending through the contour adjustment layer; having a selectivity to the trench adjustment layer and a third (four) chemical reaction selective to the etch stop layer to react to the second dielectric enthalpy Ion _ to extend the opening through the second &layer; An electrical layer and the line having a selective etch to extend the opening through the etch stop layer; removing the imaging layer, the opening from the top of the first dielectric layer after the removing the imaging layer The face extends through the contour adjustment layer, through the first -36-200924058 = dielectric layer, and through the axis stop layer to reach the top surface of the line. Filling the opening with a conductive Zhao, the electrical conductor is electrically connected to the line, and the first dielectric shirt is subjected to the third axis 彳 chemical interaction method, wherein the first-study: two:=2: method, the Second and first-order chemistry 16. The method of claim 12, wherein the second layer of the accommodating layer is performed between the stop layer and the counter-contact shot. A f etch stop 17. The method of claim 12, wherein the __ layer, the buried oxide layer, and the first: 仏 = 矽 and 5 mysterious contour layers and the rice stop layer comprise nitride Xi. Sheep 18. The method of claim 12, wherein the electrical layer is at the top surface of the 4th dielectric layer and the second dielectric layer is -37- 19.如請求項 口包含： 200924058 該頂面平行 度大於在該斤測量之該開口的-第 測量之該開口：二；：$5玄頂面處在該第-方向中戶/ 處在該第一方見度且大於在該基板之一頂运 處在的該頂面至該基板的該頂面 口的-深度二η直的第二方向中所測量之該開 /、该弟一寬度的一比率等於或大於五。 12之方法，其中該用一導電體填充該開 口之側壁及一底部上方沈積一氮化鈕層； 在5亥氮化鈕層上沈積一鈕層； 在該鈕層上沈積一種子銅層； 按亡A /種子銅層上電鍍—電鑛銅層，該電鑛銅層完全 真充該開口中的剩餘空間；及 執行一化學機械拋光，以從該第二介電層之該頂面 上方移除該氮化组層、馳層、該種子銅層、及該電鑛 銅層。 一0人t請求項12之方法，其中該成像層包括—在該第 一介電層之該頂面上之一抗反射塗層上方的光阻層，及 該在該成像層中形成該開口包含透過一圖案化光罩曝 光4光阻層於光化輪射，顯影該曝光的光阻層，及用一 -38- 200924058 初始關化學作用對該抗反射塗層進行反應性離子钱 刻，其中該抗反射塗層未受該光阻層保護。 21·如請求項2G之方法’其㈣初始則化學作 J光阻2及該第-介電層具有選擇性，及其㈣初始、 第一及第四蝕刻化學作用係相同的化學作用。 π㉔水項12之方法，其進一步包括： 形成-穿過該第一介電層至該第二基板 —電晶體之一電晶體的導電接點；及 ， 广成一在該第一介電層之該頂面上 層’该附加組線路t的線拉脾兮叫^ 、、且線路 接至穿過料-㈣料體電連 23. 二，在積體f路中的超深介層之結構，其包含 一基板 一在该基板之—頂面上 在該第—介電層之1面二1層_ 在該第二介電層之一頂面二層 在該第三介電層之一頂:m;層 -從該第四介電層的―:上四介電層； 面的開口； θ 、、面延伸至該基板之言J 該頂面平行之第-方向 在該第四介電層之該頂面處 面平行之第—方…一…亥弟四介電層 第 -39 ^ 200924058 度大於在該第三介電層層之該頂面處在該第一方向中 所測量之該開口的一第二寬度且大於在該基板之一頂 面處在該第一方向中所測量之該開口的一第三寬度，該 第二寬度大於或等於該第三寬度； 從該弟四介電層的該頂面至該基板的該頂面處在 一與該第一方向垂直的第二方向中所測量之該開口的 一深度與該第三寬度的一比率等於或大於五；及 一填充該開口的導電體。 24. 如請求項23之結構，其中： 該第一及第三介電層包含氮化石夕；及 該第二及第四介電層包含一氧化石夕。 25. 如請求項23之結構，其中： 該第一介電層及該第三介電層各自分別具有相應 厚度比該第二介電層的一厚度或該第四介電層的一厚 度小至少五倍；及 該第一、第二、第三、及第四介電層之一總厚度大 於或等於約1微米。 26. 如請求項23之結構，其進一步包括： 一嵌埋於該第四介電層中的第一石夕層，一在該第一 矽層中的第一電晶體，一在該第四介電層中的導電接 點，該接點電接觸該第一電晶體； -40- 200924058 一在第四介電層之一頂面上的第一組線路層，在該 第一組線路層中的一線路或多個線路將該接點電連接 至該開口中的該導電體；及 該基板包括一接觸該第一介電層之一底面的第二 組線路層，在該第二組線路層中的一線路或多個線路將 該開口中的該導電體電連接至形成於一第二矽層中與 該第二組線路層之一底面接觸的一第二電晶體。 27. 如請求項23之結構，其中： 該第一及第三介電層分別包含一選自由以下項目 組成之群組的材料.低溫乳化物、南密度電漿_氧化物、 電漿增強化學氣相沈積氧化物、超高密度電漿氧化物、 四乙氧基矽烷氧化物、旋塗氧化物及其之多個層。 28. 如請求項23之結構，其中： 該第二及第四介電層分別包含一選自由以下項目 組成之群組的材料.氮化碎、碳化碎、乳氣化砍、氧碳 化矽及 Nblock(SiCNH)。 29. 如請求項23之結構，其中該導電體包含： 一在該開口之側壁及一底部上方的I化组層； 一在該氮化组層上的组層； 一在該组層上的種子銅層；及 一在該種子銅層上的電鍍銅層，該電鍍銅層完全填 -41 - 200924058 充該開口中的剩餘空間。 3〇.如請求項23之結構，盆中談第_ 介電層。 ’、μ弟—；丨电層包含多個 丄如明求項23之結構’其中該第三介電人 公、、及第七介電層，該第五介電層鄰C五、 層，該第六介電層在該第五及第七介電層之°間弟1電 32·如請求項31之結構，其中： 底面及 該第33電層延伸穿過在第二介電層之 、"電日之一頂面間之一矽層的區域。 33.—種三維積體電路的結構，其包含： 二第-基板’該第—基板包括： ^接至-組線路層的第一電晶體 —相應介電層中包括導電線路； '^線路層在 —在該組線路層之離該基 „ 層之—頂面上的蝕—取上方線路 線路層之-線=^止層’祕料止層與該最上方 層;Γ㈣停止層之-頂面上的-第-介電接合 頂面=7介電接合層之—底面與該韻刻停止層之- •42 - 200924058 一第二基板’該第二基板包括： —弟一介電接合層； 在該第二介電接合層之一頂面上的—埋 化物層； 一在該埋藏氧化物層之一頂面上的矽層，該矽 層包括在該矽層中以介電質隔離而互相電絕 第二電晶體； ' :在該矽層之一頂部上及在該介電質隔離之 頂面上的輪扉調整層；及 在該輪廓調整層之一頂面上的一介電層. 接合至該埋藏氧化物之一底面 層的一頂面； /乐"電接合 介電層之該頂面延伸穿過該輪_整#、穿 過该介電質㈣、穿㈣埋絲化物層、穿過曰—穿 ::::接Γ及穿蝴刻停止層至梅之二： 填充該開口的導雷辦 觸 电體该導電體與該線路電接 34.如請求項33之結構，其中 # 層、該埋藏氧化物層、及誃八=及弟—介電接合 廓調整層及該蝕刻停止層氮;二含氧化矽，及I亥輪 35_如請求項33之結構，其令· ' 43， 200924058 ,在該介電層之該頂面處在與該介電層之該頂面平 t第一方向$所測量之該開口的—第―寬度大於在 =輪廓調整層之該頂面處在該第—方向中所測量之該 :口的-第二寬度且大於在該基板之__頂面處在該第 2向中所測量之該開口的—第三寬度，該第二寬度大 於或等於該第三寬度；及 其中從該介電層的該頂面至該基板的該頂面處在 ?、該第-方向垂直的第二方向中所測量之該開口的 一沬度與該第一寬度的一比率等於或大於五。 6.如明求項33之結構，其中該導電體包含： -在該開口之側壁及一底部上方的氮化钽層； 一在該氮化鉅層上的鈕層； 一在該钽層上的種子銅層；及 -在該種子銅層上的電_層，該電鑛銅層完 充该開口中的剩餘空間。 々 37.如請求項33之結構，其進一步包括： 電晶 一穿過該介電層至該第二基板之該等第 之一電晶體的導電接點；及 在。亥w %層之该頂面上的附加組線路 =路中的線路將該開口中的該導電體電連接至S 該介電層的該接點。 牙過 -44 - 200924058 * 38. 如請求項33之結構，其中： 該介電層包含一選自由以下項目組成之群組的材 料：高密度電漿氧化物、電漿增強化學氣相沈積氧化 物、超高密度電漿氧化物、四乙氧基矽烷氧化物、旋塗 氧化物及其之多個層。 39. 如請求項33之結構，其中： 該輪廓調整層及該蝕刻停止層分別包含一選自由 〇 以下項目組成之群組的材料：氮化矽、碳化矽、氧氮化 矽、氧碳化矽、及Nblock(SiCNH)。 40. 如請求項33之結構，其中： 該第一及第二介電接合層包含低溫氧化物。19. If the request entry includes: 200924058 the top parallelism is greater than the opening of the opening measured by the kilogram - the first measurement of the opening: two;: $5 the top surface is in the first direction of the household / at the first One side is greater than the width measured in the second direction from the top surface of the top surface of the substrate to the top surface of the substrate A ratio is equal to or greater than five. The method of 12, wherein a sidewall is filled with a conductive body and a nitride button layer is deposited on a bottom; a button layer is deposited on the nitride layer; and a copper layer is deposited on the button layer; Electroplating-electro-copper layer on the dead A/seed copper layer, the electro-mineral copper layer completely filling the remaining space in the opening; and performing a chemical mechanical polishing to be above the top surface of the second dielectric layer The nitrided layer, the chisel layer, the seed copper layer, and the electroderaline layer are removed. The method of claim 12, wherein the imaging layer comprises a photoresist layer over the anti-reflective coating on the top surface of the first dielectric layer, and the opening is formed in the imaging layer The method comprises: exposing a photoresist layer through a patterned reticle to an actinic wheel, developing the exposed photoresist layer, and performing reactive ion etching on the anti-reflective coating with an initial chemical chemistry of -38-200924058, Wherein the anti-reflective coating is not protected by the photoresist layer. 21. The method of claim 2, wherein (iv) initially chemically acts as J photoresist 2 and the first dielectric layer is selective, and (iv) the initial, first and fourth etch chemistries are the same chemical action. The method of π24 water item 12, further comprising: forming a conductive contact through the first dielectric layer to the second substrate-transistor crystal; and, forming the first dielectric layer The top layer 'the line of the additional group line t pulls the spleen and squeaks ^, and the line is connected to the through-material-(four) material body connection 23. Second, the structure of the ultra-deep interlayer in the integrated body f road, The substrate comprises a substrate on the top surface of the substrate on one side of the first dielectric layer and two layers _ on the top surface of one of the second dielectric layers on top of one of the third dielectric layers: m; layer-from: the fourth dielectric layer of the fourth dielectric layer; the opening of the surface; θ, the surface extending to the substrate J, the top surface parallel to the first direction in the fourth dielectric layer The top surface of the top surface is parallel to the ... - ... Haidi four dielectric layer -39 ^ 200924058 degrees greater than the measured in the first direction at the top surface of the third dielectric layer a second width of the opening and greater than a third width of the opening measured in the first direction at a top surface of the substrate, the second width being greater than or equal to a third width; a depth of the opening and a third width measured in a second direction perpendicular to the first direction from the top surface of the four dielectric layers to the top surface of the substrate A ratio equal to or greater than five; and an electrical conductor filling the opening. 24. The structure of claim 23, wherein: the first and third dielectric layers comprise nitride nitride; and the second and fourth dielectric layers comprise a oxidized stone. 25. The structure of claim 23, wherein: the first dielectric layer and the third dielectric layer each have a respective thickness that is less than a thickness of the second dielectric layer or a thickness of the fourth dielectric layer At least five times; and one of the first, second, third, and fourth dielectric layers has a total thickness greater than or equal to about 1 micron. 26. The structure of claim 23, further comprising: a first layer embedded in the fourth dielectric layer, a first transistor in the first layer, and a fourth a conductive contact in the dielectric layer, the contact electrically contacting the first transistor; -40- 200924058 a first set of circuit layers on a top surface of one of the fourth dielectric layers, in the first set of circuit layers One or more of the wires electrically connect the contact to the electrical conductor in the opening; and the substrate includes a second set of circuit layers contacting a bottom surface of the first dielectric layer, in the second set A line or lines in the circuit layer electrically connect the electrical conductor in the opening to a second transistor formed in a second germanium layer in contact with a bottom surface of the second set of wiring layers. 27. The structure of claim 23, wherein: the first and third dielectric layers each comprise a material selected from the group consisting of low temperature emulsions, south density plasmas, oxides, plasma enhanced chemistry Vapor deposited oxide, ultra high density plasma oxide, tetraethoxy decane oxide, spin-on oxide, and layers thereof. 28. The structure of claim 23, wherein: the second and fourth dielectric layers respectively comprise a material selected from the group consisting of nitriding, carbonized mash, milk gas cracking, oxycarbonized bismuth and Nblock (SiCNH). 29. The structure of claim 23, wherein the electrical conductor comprises: an I-group layer on a sidewall of the opening and a bottom; a group layer on the nitride layer; and a layer on the layer a seed copper layer; and an electroplated copper layer on the seed copper layer, the electroplated copper layer is completely filled with -41 - 200924058 to fill the remaining space in the opening. 3〇. As in the structure of claim 23, the _ dielectric layer is discussed in the basin. ',μ弟—; the electric layer contains a plurality of structures such as the structure of the present invention, wherein the third dielectric layer and the seventh dielectric layer are adjacent to the fifth layer and the fifth layer. The sixth dielectric layer is between the fifth and seventh dielectric layers. The structure of claim 31, wherein: the bottom surface and the 33rd electrical layer extend through the second dielectric layer. , " an area of the top layer of one of the top days of the electricity day. 33. The structure of a three-dimensional integrated circuit, comprising: a second substrate-substrate comprising: a first transistor connected to the group of wiring layers - a corresponding dielectric layer comprising a conductive line; The layer is—the eclipse on the top surface of the set of circuit layers from the base layer—takes the upper line circuit layer-line=^stop layer' secret stop layer and the uppermost layer; Γ(4) stop layer- The top surface of the first-dielectric junction top surface = 7 the dielectric bonding layer - the bottom surface and the rhyme stop layer - 42 - 200924058 a second substrate 'the second substrate includes: - a dielectric junction a layer on the top surface of one of the second dielectric bonding layers; a germanium layer on a top surface of the buried oxide layer, the germanium layer including a dielectric layer in the germanium layer Isolating and electrically disconnecting the second transistor; ': a rim adjustment layer on top of one of the enamel layers and on the top surface of the dielectric isolation; and a top surface on one of the contour adjustment layers a dielectric layer. a top surface bonded to a bottom layer of the buried oxide; the top surface of the electrical bonding dielectric layer is extended Through the wheel _ whole #, through the dielectric (four), through (four) buried silk layer, through the 曰 - wear :::: Γ and wear the butterfly to stop the layer to the second: the mine that fills the opening The electric conductor is electrically connected to the electric line 34. The structure of claim 33, wherein the #层, the buried oxide layer, and the 誃八=和弟-dielectric junction adjustment layer and the etch stop layer nitrogen And a structure comprising the structure of claim 33, wherein '43, 200924058, at the top surface of the dielectric layer is at the top of the dielectric layer The first width of the opening measured in one direction $ is greater than the second width measured in the first direction at the top surface of the contour adjustment layer: the second width of the opening and greater than the top of the substrate a third width of the opening measured in the second direction, the second width being greater than or equal to the third width; and wherein the top surface of the dielectric layer is from the top surface of the substrate a ratio of a degree of the opening measured in the second direction perpendicular to the first direction to the first width is equal to or greater than five. The structure of item 33, wherein the electrical conductor comprises: - a tantalum nitride layer on a sidewall of the opening and a bottom; a button layer on the nitrided giant layer; a seed copper layer on the germanium layer; And an electric layer on the seed copper layer, the electric copper layer filling the remaining space in the opening. 々37. The structure of claim 33, further comprising: electroforming a dielectric layer through the dielectric layer a conductive contact to the first one of the second substrates; and an additional set of lines on the top surface of the second layer = the line in the path electrically connects the conductor in the opening to S. The contact of the dielectric layer. 牙过-44 - 200924058 * 38. The structure of claim 33, wherein: the dielectric layer comprises a material selected from the group consisting of high density plasma oxidation , plasma enhanced chemical vapor deposited oxide, ultra high density plasma oxide, tetraethoxy decane oxide, spin-on oxide and multiple layers thereof. 39. The structure of claim 33, wherein: the contour adjustment layer and the etch stop layer respectively comprise a material selected from the group consisting of: tantalum nitride, tantalum carbide, niobium oxynitride, niobium oxycarbonate And Nblock (SiCNH). 40. The structure of claim 33, wherein: the first and second dielectric bonding layers comprise a low temperature oxide.
TW097126073A 2007-09-11 2008-07-10 Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias TW200924058A (en)

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