200921906 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種影像感測元件(image sensor)，特別是有 關於一種可降低暗電流強度之互補式金氧半導體電晶體 (complementary metal-oxide semiconductor，CMOS)影像感測元件。 【先前技術】 互補式金氧半導體電晶體影像感測元件(CMOS image sensor， CIS)常見於各式的影像感測裝置，其所包含之感光二極體可感測 光學訊5虎而產生電荷’再藉由CMOS影像感測元件所包含之電晶 體結構把產生的電荷轉換為電信訊號。由於CMOS影像感測元件 是以傳統的半導體製程製作，因此具有製作成本較低以及元件尺 寸較小的優點。此外，CMOS影像感測元件還具有高量子效率 (quantum efficiency)以及低雜訊(read-out noise)等優勢，因此已廣泛 應用在照相手機(camera phone)以及數位相機(digital camera)等電 子產品上。 傳統CMOS影像感測元件的像素單元包括有一感光二極體， 例如一 PN二極體’其係由一 N型摻雜區以及p型接雜井所構成。 另外，CMOS影像感測元件亦包含有一轉移閘極(transfer gate)，設 置於感光·一極體旁，用來把在感光二極體内所產生的電荷移轉至 一浮置節點(floating node)。浮置節點可以進一步與一源極隨耦器 電晶體(source follower transistor)的閘極耦合，藉以從源極隨耦器 5 200921906 電晶體提供-輪出訊號至―列存取電晶體(酶*咖咖 恤si㈣。此外’CM0S影像感測元件更包含有一重置電晶體㈣技 transistor)，用來重設(reset)浮置節點的電位。 請參考第1圖，其綠示的是一傳統CM〇s影像感測元件之結 構示意圖。如第1圖所示，CM〇s影像感測元件3〇包含有一半導 體基底ίο ’且半導縣底1G絲設有概鑛細離(shaii〇w trench isolation ’ STI)結構14。淺溝隔離結構14可定義出複數個像 素單元12。各像素單元12包含有複數個電晶體結構(未示於圖 中）’其中各像素單元12係利用一感光二極體2〇作為一電晶體的 源極，藉以把在感光二極體2〇内所產生的電荷移轉至浮置節點(未 示於圖中）。感光二極體20分別包含一 n型掺雜區16與一 P型摻 雜井18，作為感測外來光源強度的元件。此外，半導體基底 表面設有複數層介電層與多重金屬内連線(multilevel interconnects)’例如一層間介電層(interievel dielectric layer) % 與二 層金屬間介電層(intermetal dielectric layer，IMD)22、24，而金屬 間介電層22、24間另設置有複數個金屬導線23、25。 CMOS影像感測元件係藉由電晶體結構所產生之電流來處理 訊號資料，例如感光二極體於受光狀態所感應而產生的電流稱為 光電流(light current)，代表電路之訊號(signal)，而感光二極體於 不受光狀態所產生的電流稱為暗電流(dark current)，代表電路之雜 訊(noise)。因此，CMOS影像感測元件即利用訊號與雜訊之比值 200921906 • (slgna〗/nolse)的大小來偵測光線的強弱程度。倘若CMOS影像感測 元件於不受光狀ϋ時職生的暗電流過大，訊號無訊之比值就 會大幅降低’進巾嚴魏影_彳cmos影像制元件對於光線的 感測靈敏度。有鑑於此，為了提升CM〇s影像感測元件之感測靈 敏度與性能，如何減少暗電流之產生仍為此技術領域之一大課題。 【發明内容】 ( 因此，本發明係於此提供一種CMOS影像感測元件及其製作 方法，用以降低CMOS影像感測元件於不受光狀態時所產生的暗 電流，進而提升CMOS影像感測元件對於光學訊號的感測能力。 根據本發明之一較佳實施例，本發明提供一種製作CM〇s影 像感測元件的方法。首先提供一基底，基底包含有至少一光感測 區與至少一電晶體區。之後，於電晶體區内之基底表面形成至少 一閘極結構。接著，對基底進行一離子佈植製程，離子佈植製程 〇 穿透’結構而於電晶體d内之基底巾形成-第-導電型摻雜 井。其中，該第一導電型摻雜井包含有至少一第一井區與至少一 第二井區。 根據本發明之另一較佳實施例，本發明另提供一種CM〇s影 像感測元件’包含有-基底、至少—感光二極體、至少—鬧極結 構、至少一第二導電型摻雜區以及至少一第一導電型摻雜井。感 光二極體設置於基底中，而閘極結構設置於感光二極體旁之基底 7 200921906 表面上。第二導電型摻雜區設置於基底中，且位於閘極結構旁相 對於感光二極體之一側。第一導電型摻雜井也位於基底中，其包 含有至少-第-井區與至少―第二井區。第一井區係位於閘極結 構下方，而第二井區則位於第二導電型摻雜區下方。其中，第二 井區的佈植深度比第一井區的佈植深度更深。 為讓本發明之上述目的、特徵、和優點能更明顯易懂，下文 特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如 下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明 加以限制者。 【實施方式】 請參考第2圖至第5圖，第2圖至第5圖為本發明之第一較佳 實施例製作CMOS影像感測元件的方法示意圖。如第2圖所示， 首先提供一基底40，基底40可以包含有一 p型磊晶層(p_epi layer)、—矽基底或者是石夕覆絕緣(silic〇n_〇ninsulat〇rS〇i)基底， 其上定義有至少一光感測區41與至少一電晶體區43，且光感測區 41係位於電晶體區43之左方。基底4〇内另可包含至少一淺溝隔 離結構42、至少一 P型場區(P_fleld)72與至少一 N型摻雜區％。 其形成方式為習知該項技藝者及具通常知識者所熟知之技術，例 如可先於基底40内形成至少一溝渠(未示於圖中），再於基底4〇表 面全面覆蓋—絶緣層(未示於圖中)並填滿溝渠，然後利用化學機械 研磨製程除去多餘之絶緣層’以於基底4〇中形成淺溝隔離結構 200921906 內Γ型場區72與N㈣雜區74的形成_是分別於基底 40内植人P型摻質與N型师。淺溝_ 彼- ==娜咖梅她，細 亦可利用其他如魏蝴舰)等絕緣結構來替代。 如第3圖所示，接著於基底4G表面形成—介竭未示於圖 ΙΙ’ΓΓ層可以為熱氧化法所形成之魏化合物，或者是以其200921906 IX. Description of the Invention: [Technical Field] The present invention relates to an image sensor, and more particularly to a complementary metal-oxide semiconductor (sublement metal) capable of reducing dark current intensity (complementary metal- Oxide semiconductor, CMOS) image sensing element. [Prior Art] A complementary MOS image sensor (CMOS image sensor, CIS) is commonly used in various image sensing devices, and the photosensitive diode included therein can sense optical signals and generate charges. The electrical charge generated by the CMOS image sensing element converts the generated charge into a telecommunication signal. Since the CMOS image sensing element is fabricated in a conventional semiconductor process, it has the advantages of lower fabrication cost and smaller component size. In addition, CMOS image sensing devices have advantages such as high quantum efficiency and low-read noise, and are widely used in electronic products such as camera phones and digital cameras. on. The pixel unit of the conventional CMOS image sensing element includes a photodiode, such as a PN diode, which is composed of an N-type doped region and a p-type well. In addition, the CMOS image sensing device also includes a transfer gate disposed adjacent to the photosensitive body to transfer the charge generated in the photodiode to a floating node (floating node) ). The floating node can be further coupled to the gate of a source follower transistor to provide a turn-off signal from the source follower 5 200921906 transistor to the column access transistor (enzyme*) The coffee café si (four). In addition, the 'CM0S image sensing element further includes a reset transistor (four) technology transistor) for resetting the potential of the floating node. Please refer to Fig. 1, which shows a schematic diagram of the structure of a conventional CM〇s image sensing element. As shown in Fig. 1, the CM 〇 image sensing element 3 〇 includes a half of the conductor substrate ίο ' and the semiconducting bottom 1G wire is provided with a shaii 〇 w trench isolation ' STI structure 14 . The shallow trench isolation structure 14 defines a plurality of pixel units 12. Each of the pixel units 12 includes a plurality of transistor structures (not shown). Each of the pixel units 12 utilizes a photodiode 2 as a source of a transistor, whereby the photodiode is placed in the photodiode. The charge generated inside is transferred to the floating node (not shown). The photodiode 20 includes an n-type doped region 16 and a p-type doped well 18, respectively, as elements for sensing the intensity of the external light source. In addition, the surface of the semiconductor substrate is provided with a plurality of dielectric layers and multiple metal interconnects, such as an interievel dielectric layer and an intermetal dielectric layer (IMD). 22, 24, and a plurality of metal wires 23, 25 are disposed between the inter-metal dielectric layers 22, 24. The CMOS image sensing component processes the signal data by the current generated by the transistor structure. For example, the current generated by the photosensitive diode in the light receiving state is called a light current, and represents a signal of the circuit. The current generated by the photodiode in an unopposed state is called a dark current and represents the noise of the circuit. Therefore, the CMOS image sensing component uses the ratio of signal to noise ratio 200921906 • (slgna/nolse) to detect the intensity of light. If the dark current of the CMOS image sensing element is not too high, the ratio of the signal to the signal will be greatly reduced. The sensing sensitivity of the light-sensitive imaging device is light. In view of this, in order to improve the sensing sensitivity and performance of the CM〇s image sensing element, how to reduce the generation of dark current is still a major issue in the technical field. SUMMARY OF THE INVENTION Accordingly, the present invention is directed to a CMOS image sensing device and a method for fabricating the same, which are used to reduce a dark current generated by a CMOS image sensing device in an unoptical state, thereby improving a CMOS image sensing device. Sensing Capability for Optical Signals According to a preferred embodiment of the present invention, the present invention provides a method of fabricating a CM〇s image sensing device. First, a substrate is provided, the substrate including at least one photo sensing region and at least one a transistor region. Thereafter, at least one gate structure is formed on the surface of the substrate in the transistor region. Then, an ion implantation process is performed on the substrate, and the ion implantation process penetrates the substrate to form the substrate in the transistor d. Forming a first-conducting type doping well, wherein the first conductive type doping well comprises at least one first well region and at least one second well region. According to another preferred embodiment of the present invention, the present invention further Providing a CM 〇 s image sensing element s including a substrate, at least a photodiode, at least a nuisance structure, at least one second conductivity type doping region, and at least one first conductivity type doping The photosensitive diode is disposed in the substrate, and the gate structure is disposed on the surface of the substrate 7 200921906 adjacent to the photosensitive diode. The second conductive type doped region is disposed in the substrate and is located adjacent to the gate structure One side of the polar body. The first conductive type doping well is also located in the substrate, and includes at least a first well region and at least a second well region. The first well region is located below the gate structure, and the second well The region is located below the second conductivity type doping region, wherein the implantation depth of the second well region is deeper than the implantation depth of the first well region. The above objects, features, and advantages of the present invention can be more clearly understood. The following is a detailed description of the preferred embodiments of the invention. Please refer to FIG. 2 to FIG. 5 , and FIG. 2 to FIG. 5 are schematic diagrams showing a method for fabricating a CMOS image sensing device according to a first preferred embodiment of the present invention. As shown in FIG. 2 , a substrate 40 is first provided. The substrate 40 can include a p-type a p_epi layer, a germanium substrate or a silic〇n_〇ninsulat〇rS〇i substrate having at least one photo sensing region 41 and at least one transistor region 43 defined thereon, and The light sensing region 41 is located to the left of the transistor region 43. The substrate 4 can further include at least one shallow trench isolation structure 42, at least one P-type field region (P_fleld) 72 and at least one N-type doping region %. It is formed by a person skilled in the art and a technique well known to those skilled in the art. For example, at least one trench (not shown) may be formed in the substrate 40, and then the entire surface of the substrate 4 is covered. (not shown in the figure) and filling the trench, and then removing the excess insulating layer by a chemical mechanical polishing process to form a shallow trench isolation structure in the substrate 4〇 200921906 formation of the intrinsic field region 72 and the N (four) impurity region 74 P-type dopants and N-type divisions are implanted in the substrate 40, respectively. Shallow trench _ 彼 - = = Naca Mei she, fine can also use other insulation structures such as Wei Hu ship) instead. As shown in Fig. 3, it is then formed on the surface of the substrate 4G. The layer which is not shown in Fig. ΓΓ can be formed by the thermal oxidation method, or
導電㈣械之各式介電材料’隨後再於介電層上形成一 2層(未示於圖中），且此導電層可包含多晶韻、金屬魏物、 層與介電層進行—微影暨細製程，以於基底40上形 、各電晶體所需之閘極，例如第3 _示之轉移閘極私與重置閉 ㈣’轉移閑極44與重置間極5〇皆包含有一間極介電層你和一 5又置於閘極介電層46上之導電體48。 隨後如第4圖所示，於基底奶上形成-佈植遮罩7〇，再對基 -進行料佈植製程，離子佈植製程穿透轉移祕糾與重 置間極50而於電晶體區43内之基底4()中形成—p型摻雜井％。 ^。佈植遮罩7〇可覆蓋於光感測區Μ上，用以隔絕離子佈植 '避免把離子摻雜至佈植遮罩7〇下方之基底40中。佈植遮 〇的材料可以為—般相之正、貞光阻，*其厚度可根據離子 純製㈣強度_整。叫有半導體製細言，聽子佈植製 耘時所使㈣佈概制切f於9G代刊鱗㈣齡 9 200921906 子穿，閘極44與重置_而_。中形 〜井52，當離子佈植製程的強 ^遮罩料嶋询繼。嫩，嶋=== ;=:罩7。來阻絕所有離子佈植，只要使離子佈植製 22Γ48朗極介電層46所制之私結構，科會; 可。...70、導電體48與間極介電層46所構成之叠合結構即 Γ 未被轉_極44與重朗極％所賴之基底則 極44與咖極5崎遮蔽之基錢的佈植深妓 冰。因此’Ρ型摻料52會包含有二第—賴54與—第 %，第-井區54位於轉移間極糾與重置閘極如下方，第: 56位於轉移閘極44魅置閘極5()之_基底 ％ 製程的佈植方向係與 斜佈植。因此，笫一非卩q«7Ί貝 Mtwm^nr ” 置並非恰好對應至轉移閘極44 區^ ，轉移間極44以及重置閘極5〇係與第一井 °° 1重$ ’而二第-井區54的位置會 置問極50的位置更加遠離光感測區41。 44从及重 「亍一活 如第5圖所示，其後先去除佈植遮罩％，對基底奶進+ 10 200921906 f程’再_多道_化製麵多道離子佈植製料 感測區41中完成感光二極體58，並於電晶體區43中之从4〇 内形成所需之N型摻雜區62。舉例來說，可先把雜 感測區41之基底40中形成—表面，之後 量離子饰植把剛咖__)摻人電晶_3之芙= 中^成-N型摻雜區62，作為—浮置節點。習者 可理解’ _活化製_，P歸_ 52之摻魏度私 改變’耻本發_式崎示之各摻純婦料侧以表達出 主要的摻質分布區域’並不表示摻雜區與摻雜井沒有任何換 質。此外，摻祕與摻雜相實際形狀也會根據製程參數的不同 與元件配置糾同而改變。隨後，本發明可根據產品設計而再於 基底4〇上軸概層介·、Μ金助連線與絲透鏡等元件 (未不中）’以完成CM〇s影像感測元件之製作。另外，習知 該項技藝者錢可轉，本發明各獅區與雜井之N型導電型 式與P型導電型式皆可以互換，無須受上述實施例所舰。 由於本發明之離子魅製程健透_導㈣48而把離子植 入，晶體的通域，因此可具有下觸個優點。錢，習知技 術疋對裸路的基底表面直接進行高能量的離子佈·程，因此習 ^技術在植人過財，將不可魏的讀财區_晶格造成損 害’因而使不受光狀態所產生的暗電流上升，嚴重影響感測度。 相反地本發明之製程可簡單地利用已形成之閘極導電體仙來調 整P型摻雜井52的佈植位置與佈植深度。離子佈植製程的能量可 200921906 受到閘極結構的緩衝， 能量在程即可以避免離子佈植的 結構 的通顧域產生軸，料會損傷到電晶體之間極 植二…白知洋置節點^型摻雜區係直接被p型換雜井所環 ⑶，因此不受树較容祕CM0Sf彡像❹抗狀_處產生暗 電流而流入浮置節點，而本發明則可利用間極結構進行自對準的 離子佈植製程，使第-實施财位於N型摻雜區㈤下方p型的第 了井區56之佈植深度較深，如此—來，❹二極體％所產生之 電机主要會㈣錄娜縣44正下方之通道區麵流人N型換 雜區62,使CM0S影像感測元件較不易產生暗電流流^型捧雜 區62 ’也可以避免N型摻雜區62與p型換雜井52之間產生漏電 流(floating node leakage)。再者，傾斜佈植之離子佈植製程可使N 型摻雜區74的一端不必延伸至通道區域的第一井區％之中，同 樣可避免暗電麵人N师肺62 _持趣_奴。有鑑於 此’本發明可以使CMOS影像感測元件具有更好的摻雜佈局，進 而減少暗電流的產生。 再者，當基底40包含有P型磊晶層時，第一實施例光感測區 41之N型摻雜區74下方可直接與p型磊晶層接觸，有助於增加 感光二極體58之接面空乏區寬度(junction depletion width)，進而 增加感光二極體58感測光學能量的能力。 12 200921906 根據實驗數據結果可知，相較於習知技術直接對裸露的基底 全面進行高能量的離子佈植製程，本發明之CM〇s影像感測元件 約可降低百分之八十(80%)的暗電流值，例如第一較佳實施例 CMOS衫像感測元件之暗電流值低於5微微安培(5χι〇-ι2 amperes) ’有效地提升CM〇s影像感測元件對於光學訊號的感測 能力。 於前述實施例中，形成P型擦雜井52之離子佈植製程的佈植 方向係與基底40表面之法線方向之間具有而離子佈植製 程係從左上方往右下方進行傾斜佈植。於本發明之其他實施例 中，形成P麵雜井52之軒输製程的舰方向可峨右上方 往左下錢行爾雜，或者舰純也仰大致上與基底表Each of the conductive (four) mechanical dielectric materials 'subsequently forms a two layer on the dielectric layer (not shown), and the conductive layer may comprise polycrystalline rhyme, metal material, layer and dielectric layer - The lithography and fine process are used to form the upper surface of the substrate 40 and the gates required for the respective transistors, for example, the transfer gate of the third and the reset (four) 'transfer idle pole 44 and the reset between the poles An electrical conductor 48 comprising a very dielectric layer and a 5 on the gate dielectric layer 46 is included. Then, as shown in Fig. 4, a substrate mask is formed on the base milk, and then the substrate is subjected to a material coating process. The ion implantation process penetrates the transfer and corrects the interpole 50 and the transistor. The p-type doping well % is formed in the substrate 4 () in the region 43. ^. The implant mask 7〇 can be overlaid on the photo-sensing zone 隔绝 to isolate the ion implants' to avoid ion doping into the substrate 40 below the implant mask 7〇. The material of the implant concealer can be the positive phase of the normal phase, the photoresist of the 贞, and the thickness can be based on the purity of the ion (four) intensity _ whole. It is said that there is a semiconductor system, when the listener is planted, the ( 使 ( 四 四 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于Medium shape ~ well 52, when the ion implantation process is strong, the mask material is inquired. Tender, 嶋 === ;=: cover 7. To block all ion implantation, as long as the ion implants a private structure made of 22Γ48 朗极电层46, the association will; ... 70, the superposed structure of the electric conductor 48 and the inter-electrode dielectric layer 46 is not converted to the base of the base 44 and the pole of the coffee. Planting deep ice. Therefore, the 'Ρ-type admixture 52 will contain two first-Lai 54 and - the first, the first-well area 54 is located between the transfer pole and the reset gate is as follows, the first: 56 is located at the transfer gate 44 charm gate 5 () _ substrate % process of planting direction and oblique cloth planting. Therefore, the non-卩q«7 mussel Mtwm^nr ” is not exactly corresponding to the transfer gate 44 area ^, the transfer interpole 44 and the reset gate 5 与 system and the first well ° ° 1 weight $ ' and two The position of the first well region 54 will position the pole 50 farther away from the light sensing region 41. 44 The weight of the well is as shown in Fig. 5, and then the implant mask is removed first, and the base milk is removed. Into the + 10 200921906 f process 're-_ multi-channel _ chemical surface multi-channel ion implantation material sensing area 41 completes the photodiode 58 and forms the desired layer from the 4 电 in the transistor region 43 The N-type doped region 62. For example, the surface of the dummy sensing region 41 may be formed into a surface first, and then the ion-implanted gingival __) is incorporated into the electro-crystal _3 芙 = 中^成- N-doped region 62, as a floating node. The learner can understand ' _ activation system _, P _ 52 mixed Wei degree private change 'shame hair _ akizaki show each mixed pure side to express The main doping distribution region does not mean that the doping region and the doping well do not have any quality change. In addition, the actual shape of the doping and doping phase will also change according to the difference of the process parameters and the component configuration. According to the product design, the CM〇s image sensing component can be completed by using the components of the substrate 4, the upper layer, the sheet metal lens and the wire lens (not included). It is known that the skilled person can turn the money, and the N-type conductivity type and the P-type conductivity type of the various lion areas and the mixed wells of the present invention can be interchanged without being subjected to the ship of the above embodiment. Since the ion charm process of the present invention is _ Guide (4) 48 and implant the ions, the crystal domain, so it can have the advantage of the next touch. Money, the conventional technology 直接 directly on the surface of the bare surface of the high-energy ion cloth, so the technology is implanted If you make a fortune, you will not be able to read the financial area _ lattice damage, thus increasing the dark current caused by the light state, seriously affecting the sensitivity. Conversely, the process of the present invention can simply use the formed gate conductor Xianlai adjusts the implantation position and implantation depth of the P-type doping well 52. The energy of the ion implantation process can be buffered by the gate structure in 200921906, and the energy can be used to avoid the generation of the axis of the structure of the ion implantation. , it will damage the crystal Between the body and the second plant... The Baizhiyang node is not directly connected to the well by the p-type (3), so it is not subject to the darker current of the CM0Sf image. Node, and the present invention can utilize the inter-electrode structure for self-aligned ion implantation process, so that the first implementation is located deeper in the p-type well region 56 below the N-type doped region (5), so - Come, the motor produced by the ❹ diode is mainly used. (4) The N-type miscellaneous area 62 of the channel area below the recording area of the Na Na County 44 makes the CM0S image sensing component less prone to dark current flow. The miscellaneous region 62' can also avoid floating node leakage between the N-doped region 62 and the p-type well 52. Furthermore, the ion implantation process of the oblique implant can make one end of the N-type doping region 74 not necessarily extend to the first well region of the channel region, and can also avoid the dark electricity surface N. slave. In view of the present invention, the CMOS image sensing element can have a better doping layout, thereby reducing the generation of dark current. Furthermore, when the substrate 40 includes a P-type epitaxial layer, the underside of the N-type doped region 74 of the photo-sensing region 41 of the first embodiment can directly contact the p-type epitaxial layer, which helps to increase the photodiode. The junction depletion width of the junction of 58 increases the ability of the photodiode 58 to sense optical energy. 12 200921906 According to the experimental data, it can be seen that the CM〇s image sensing component of the present invention can be reduced by about 80% (80%) compared with the conventional technique for directly performing a high-energy ion implantation process on the bare substrate. The dark current value, for example, the dark current value of the CMOS image sensing element of the first preferred embodiment is less than 5 picoamperes (5 χι〇-ι2 amperes) 'effectively increasing the CM 〇 image sensing element for optical signals Sensing ability. In the foregoing embodiment, the implantation direction of the ion implantation process for forming the P-type well 52 is between the normal direction of the surface of the substrate 40 and the ion implantation process is obliquely implanted from the upper left to the lower right. . In other embodiments of the present invention, the direction of the ship forming the P-side well 52 can be 峨 峨 right upper left to the left, or the ship purely
面之法線方向平行。請參考第6圖與第7圖，第6圖與第7圖分 別為本發明m較佳實施㈣作CM〇s影佩測元件的 示〜圖如第6圖所示’為了形成p型摻雜井，離子佈植 製程係朝向基底40並且從電晶體區43的方向偏向光感測區Μ的 方向進仃傾斜佈植，因此二第一井區54的位置會比轉移閑極私 ^及重置閘極5〇的位置更加接近光感測區4ι。或者如第7圖所 p型摻雜井52 ’離子佈植製程的佈植方向大致上係 ^=4()表面之树方辭行，因此二第—輕54的位置恰好 ^應至轉移閘極私與重置閘極5〇正下方。如前所述，由於本 子:植製程係穿透閘極導電體48而把離子植入電晶體的 、域’因綱轉電體48可簡錄子佈_能量在電晶體 13 200921906 的通道區域產生缺陷，進而降低暗電流值。另需注音的曰，1述 _ 第6圖與第7圖主要係用以說明本發明第二與第三較佳^施二形 成P型摻雜井52之離子佈植製程，因此光感剛區#内之元件並 未全數繪示於圖中。實際上，光感測區41之、;《溝隔離結構42斑 各換雜區域等結構可㈣製作電晶體區43内之各式閘極結構與推 雜區域之前、之後或同時形成。 此外’本發明離子倾製程的佈植方向與佈植遮罩7〇的實際 位置皆可根據製程需要與產品設計而調整，錢侷限於前述實施 例。請參考第8圖至第K) _，第8圖至第1()圖分職本發明之 第四至第六較佳實關製作CM〇s影縣測元件的方法示意圖。 如第8圖與第9圖所示，佈植遮罩7()可以覆蓋至部分之轉移問極 44。如第10圖所示，適當地調整傾斜佈植的角度，佈植遮罩％ 也可以完全不接觸轉移閘極44。 另一方面’本發明也可以先形成P型摻雜井52 ,再形成轉移 閘極44與重置酿5〇等閘極結構。請參考第u圖至第b圖， 第11圖至第15圖為本發明之第七較佳實施例製作C順影像感 測元件的方法示意圖。如第u圖所示，首先提供—基底秦並上 定義有至少-柿躯41與至少—f晶魏43，絲感測區Μ 係位於電晶體區43之左方。麵4()㈣可包含至少—淺溝隔離 結構42、至少—P型場區72與至少-N型摻雜區74。 14 200921906 接著如第!2圖所示’於基底4〇表面形成 = 146上形成-導電請，於導電層㈣^ 7，心後再於_化絲176上形成—雜鮮i7Q。斗 ’或者疋以其他沉積等製程卿成之各式介電材料，導電層⑽ ^包含多綱’獅、終合蝴如其他稱 ^程所形成之各式導電材料。圖案化光阻176與佈植遮罩17〇的 财以為―般常狀正、負光阻，而其厚度皆可根據離子佈植 製程的強度_整’此外，也可賤用半透雄aif_t_)光罩來直 接形成具階梯圖案的光阻遮罩。 後如第13 _示’對基底4G進行—離子佈植製程，離子佈 植製程穿透圖案化光阻176、導電層148與介電層146祕電晶體 區43内之基底40中形成- P型捧雜井52。佈植遮罩17〇可用以 隔絕離子佈植製程，避免把離子摻雜至佈植遮罩i7G下方之基底 40令。這裡離子佈植製程時所使用的佈植能量甚至可大於9〇 KeV，使離子可穿透圖案化光阻176、導電層148與介電層146所 構成之叠合結構，而不會穿透佈植遮罩m、圖案化光阻Μ、導 電層148與介電層146所構成之疊合結構。 15 200921906 的佈植深度會比被圖案 '深。因此，P型摻雜井 56，第—井區54位於未 下方，第二井區56位於 未被圖案化光阻176所遮蔽之基底4〇的々 化光阻176所遮蔽之基底4〇的佈植深度更深 52會包含有二第一井區54與一第二井區％， 被佈植遮罩170所遮蔽之圖案化光阻176 未被圖案化光阻m所遮蔽之導電層⑽下方，且第二井區允的 佈植深度比第一井區54的佈植深疳争、:这The normal direction of the face is parallel. Please refer to FIG. 6 and FIG. 7 . FIG. 6 and FIG. 7 respectively show a preferred embodiment of the present invention. FIG. 4 shows a CM 〇 影 佩 佩 〜 〜 图 图 图 图 图 为了 为了 为了 为了 为了 为了 为了 为了 为了 为了 为了 为了In the well, the ion implantation process is oriented toward the substrate 40 and obliquely inclined from the direction of the transistor region 43 toward the direction of the light sensing region, so that the position of the second first well region 54 is different from that of the transfer. The position of the reset gate 5〇 is closer to the light sensing area 4ι. Or, as shown in Fig. 7, the implantation direction of the p-type doping well 52' ion implantation process is roughly the same as the tree surface of the ^=4() surface, so the position of the second-light 54 is just to the transfer gate. Private and reset gates are just below 5〇. As described above, since the sub-process: the implant process penetrates the gate conductor 48 and implants ions into the transistor, the domain 'synchronous electrotransformer 48 can be simply recorded as a sub-energy in the channel region of the transistor 13 200921906. Defects are generated, which in turn reduces dark current values. Another need for phonetic 曰, 1 _ 6 and 7 are mainly used to illustrate the second and third preferred embodiments of the present invention to form a P-type doping 52 ion implantation process, so the light sense just The components in Zone # are not fully shown in the figure. In fact, the structure of the light sensing region 41; the structure of the trench isolation structure 42 and the replacement region can be formed (4) before, after or simultaneously with the various gate structures and the dummy regions in the transistor region 43. Further, the implantation direction of the ion tilting process of the present invention and the actual position of the implant mask 7 can be adjusted according to the process requirements and product design, and the money is limited to the foregoing embodiment. Please refer to Fig. 8 to K). _, Fig. 8 to Fig. 1() are diagrams showing the method of making the CM〇s shadow county measuring component according to the fourth to sixth preferred embodiments of the present invention. As shown in Figures 8 and 9, the implant mask 7() can cover a portion of the transfer pole 44. As shown in Fig. 10, the angle of the oblique implant is appropriately adjusted, and the implant mask % can also be completely out of contact with the transfer gate 44. On the other hand, the present invention can also form a P-type doping well 52 first, and then form a gate structure such as a transfer gate 44 and a reset brewing. Referring to Figures u through b, Figs. 11 through 15 are schematic views showing a method of fabricating a C-sequence sensing element according to a seventh preferred embodiment of the present invention. As shown in Fig. u, firstly, at least - persimmon body 41 and at least - f crystal Wei 43 are defined, and the silk sensing region is located to the left of the crystal region 43. Face 4()(4) may comprise at least a shallow trench isolation structure 42, at least a P-type field region 72 and at least an -N type doped region 74. 14 200921906 Then as shown in Fig. 2, 'formed on the surface of the substrate 4 = = 146 - conductive, in the conductive layer (four) ^ 7, after the heart is formed on the _ filament 176 - hybrid i7Q.斗 ' or 疋 疋 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他The patterned photoresist 176 and the implant mask 17〇 are considered to be “normally positive and negative photoresist”, and the thickness can be based on the intensity of the ion implantation process. In addition, the semi-transparent aif_t_ can also be used. The reticle directly forms a photoresist mask with a step pattern. After the ion implantation process is performed on the substrate 4G, the ion implantation process penetrates the patterned photoresist 176, and the conductive layer 148 and the dielectric layer 146 are formed in the substrate 40 in the crystal region 43. The type is mixed with 52. The implant mask 17 can be used to isolate the ion implant process and avoid ion doping to the substrate under the implant mask i7G. Here, the implantation energy used in the ion implantation process can be even greater than 9 〇 KeV, so that the ions can penetrate the patterned photoresist 176, the conductive layer 148 and the dielectric layer 146 to form a superposed structure without penetrating. The implant mask m, the patterned photoresist, the conductive layer 148 and the dielectric layer 146 are stacked. 15 200921906 The depth of the planting will be deeper than the pattern. Therefore, the P-type doping well 56, the first well region 54 is not below, and the second well region 56 is located on the substrate 4 遮蔽 shielded by the electrochemical photoresist 176 of the substrate 4 that is not shielded by the patterned photoresist 176. The deeper depth 52 will include two first well regions 54 and a second well region %, and the patterned photoresist 176 shielded by the implant mask 170 is not shielded by the patterned photoresist m (10). And the second planting area allows the planting depth to be deeper than that of the first well area 54:
β亦可”基底40表面之法線方向之間具有一夾角。 然後如第14圖所示，先去除佈植遮罩17〇與圖案化光阻H 再對基底40進行-活化製程，接著再於導電層148上另形成一圖 案化光阻(未示於圖中），以對導電層U8與介電層146進行一微影 暨侧製程’藉以於基底4G_L形成各電晶體所需之閘極，例如第 Η圖所示之轉移閘極44與重置閘極5〇。於此實施例巾，轉移問 極44與重置閘極50的形成位置與大小可以不受到ρ型摻雜井％ 的影響，而可根據產品需要而設置。 然後如第15圖所示，利用多道圖案化製程和多道離子佈植製 程等步驟於光感測區41中形成感光二極體58，並於電晶體區汜 中之基底40内形成所需之Ν型摻雜區62。例如先把ρ型摻質摻 入光感測區41之基底40中形成一表面ρ型摻雜區6〇，之後再以 咼能$離子佈植把Ν型摻質植入電晶體區43之基底4〇中，形成 16 200921906 —N型摻祕62 ’作為—浮置節點。隨後’本發明可根據產品設 計而再於基底40上形颜制介騎、多重金仙連線與光學透 鏡等元件(未示於财），以完成CMOS影像_元件之製作。 如前所述’本發明離子佈植製程的佈植方向與佈植遮罩170 的位置實際上皆可根據製程需要與產品設計而調整。請參考第Μ 圖與第Π圖，第圖與第17圖分別為本發明之第八與第九較佳 '實施例製作復⑶影像感測元件的方法示意圖。如第16圖所示， 佈植遮罩Π0可以覆蓋至部分之轉移閉極44。如第17圖所示，進 行離子佈植製程時，佈植遮罩170也可以暴露出轉移間極44與重 置閘極50預定區域以外之圖案化光阻176。需注意的是，前述第 16圖與第17圖主要係用以說明本發明第八與第九較佳實施例形 成Ρ型摻雜井52之離子佈植製程，因此光感測區41内之元件並 未全數繪示於圖中。 、值得注意的是’本發明製作CM〇s影像感測元件的流程順序 、、'不侷限於則述實施例之步驟。本發明可同時於光感測區Μ與電 。體區43内刀別形成所需的感光二極體％與各式電晶體結構。 或者’本發明可先製作光感測區41之感光二極體58，再製作電晶 體區43内之各式閘極結構與摻雜區域。亦或，本發明可先製作電 =體區43内之各式閘極結構與摻㈣域’再製作光制區41之 感光一極體58。另一方面，本發明亦可於光感測區41内之基底 形成P型摻雜井，此光感測區41之P型摻雜井可與電晶 17 200921906 體區43之P型摻雜井幻於 也可以於電晶體區43之？刑離子佈㈣程中同時佈植形成， 垔摻雜井52形成之前或之後製作。 請參考第18圖至第2η ® 之第十至第忙難實施_118圖至第2()圖分別為本發明 圖。如第心^T0S影像感測元件的方法示意 覆蓋部分位於之轉移_ 44==二=17_僅 暴露出位於光_ 41之圖=置上方的圖案化光阻176 ’而 一、 之圖案化光阻176。或者如第19圖與第 2〇圖所不，進彳了離子佈植製程時，域藥μ與電晶體區犯也 可以不設置佈_罩。如此—來，本發明之第十至第十二較佳實 施例即可彻形成!>歸雜井52之同—離子佈植製程來於光感測 區41中佈植形成一 p型摻雜井152。 綜上所述’本發明之製程可簡單地利用之閘極導電層來調整p 型摻雜井的佈植強度與錄深度，既可⑽鱗子佈_能量在 電晶體的通道區域產生缺陷，還可减CMC)S影像制元件具有 更好的#雜佈局，進而減少暗電流的產生。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖繪示的是一傳統CMOS影像感測元件之結構示意圖。 200921906 第2圖至第5圖為本發明之第-較佳實施例製作CMOS影像感測 元件的方法示意圖。 第6圖與第7圖分別為本發明之第二與第三較佳實施例製作 CMOS影像感測元件的方法示意圖。 第8圖至第10圖分別為本發明之第四至第六較佳實施例製作 CMOS影像感測元件的方法示意圖。 第11圖至第15圖為本發明之第七較佳實施例製作CM〇s影像感 、 測元件的方法示意圖。 “ 第16圖與第17圖分別為本發明之第八與第九較佳實施例製作 CMOS影像感測元件的方法示意圖。 第18圖至第20圖分別為本發明之第十至第十二較佳實施例製作 CMOS影像感測元件的方法示意圖。 【主要元件符號說明】 10 半導體基底 12 像素單元 14 淺溝隔離結構 16 N型摻雜區 18 p型摻雜井 20 感光二極體 22 金屬間介電層 23 金屬導線 24 金屬間介電層 25 金屬導線 26 層間介電層 40 基底 41 光感測區 42 淺溝隔離結構 43 電晶體區 44 轉移閘極 46 閘極介電層 48 導電體 19 200921906 50 重置閘極 52 P型摻雜井 54 第一井區 56 第二井區 58 感光二極體 60 表面P型摻雜區 62 N型摻雜區 70 佈植遮罩 72 P型場區 74 N型摻雜區 146 介電層 148 導電層 152 P型摻雜井 170 佈植遮罩 176 圖案化光阻 20β can also have an angle between the normal directions of the surface of the substrate 40. Then, as shown in Fig. 14, the implant mask 17〇 and the patterned photoresist H are removed first, and then the substrate 40 is subjected to an activation process, and then A patterned photoresist (not shown) is further formed on the conductive layer 148 to perform a lithography and side process on the conductive layer U8 and the dielectric layer 146 to form a gate required for forming the respective transistors on the substrate 4G_L. The pole, for example, the transfer gate 44 and the reset gate 5〇 shown in the figure. In this embodiment, the transfer pole 44 and the reset gate 50 are formed in a position and size that is not affected by the p-type doping well. The influence of % can be set according to the needs of the product. Then, as shown in Fig. 15, the photodiode 58 is formed in the photo sensing region 41 by using a multi-pass patterning process and a multi-pass ion implantation process, and A desired doped region 62 is formed in the substrate 40 in the transistor region. For example, a p-type dopant is first doped into the substrate 40 of the photo sensing region 41 to form a surface p-doped region 6〇. Then, the erbium type dopant is implanted into the substrate 4〇 of the transistor region 43 by the ionic energy ion implantation to form 16 200921906 — N Incorporating the secret 62' as a floating node. Subsequently, the present invention can be formed on the substrate 40 according to the product design, such as a medium riding, a multi-golden connection and an optical lens (not shown) to complete the CMOS. Image_component fabrication. As mentioned above, the implantation direction of the ion implantation process of the present invention and the position of the implant mask 170 can be adjusted according to the process requirements and product design. Please refer to page 与 and Π Figure, Figure and Figure 17 are schematic views respectively showing a method of fabricating a complex (3) image sensing element according to the eighth and ninth preferred embodiments of the present invention. As shown in Figure 16, the implant mask Π0 can cover part of The transfer closed end 44. As shown in Fig. 17, when the ion implantation process is performed, the implant mask 170 can also expose the patterned photoresist 176 outside the predetermined area of the transfer interpole 44 and the reset gate 50. It is to be noted that the foregoing FIGS. 16 and 17 are mainly for explaining the ion implantation process for forming the erbium doping well 52 of the eighth and ninth preferred embodiments of the present invention, and therefore the components in the photo sensing region 41. Not all of them are shown in the figure. It is worth noting that 'the invention The flow sequence of the CM〇s image sensing element is 'not limited to the steps of the embodiment. The present invention can simultaneously and electrically connect the light sensing region. The desired photosensitive diode is formed in the body region 43. % and various types of transistor structures. Or 'The present invention can first fabricate the photodiode 58 of the photo-sensing region 41, and then fabricate various gate structures and doped regions in the transistor region 43. Alternatively, this The invention can firstly fabricate various gate structures in the electric body region 43 and the photosensitive electrode body 58 of the doped (four) domain 'reproduction optical region 41. On the other hand, the present invention can also be used in the light sensing region 41. The substrate forms a P-type doping well, and the P-type doping well of the photo-sensing region 41 can be combined with the P-type doping well of the electro-crystal 17 200921906 body region 43 or the transistor region 43. Simultaneously implanted in the ion cloth (4), and the yttrium doping well 52 is formed before or after the formation. Please refer to Fig. 18 to Fig. 2n to the tenth to the first to the hard to implement _118 to 2(), respectively. For example, the method of the first heart ^T0S image sensing element indicates that the cover portion is located at the transition _ 44 == two = 17_ only exposes the patterned photoresist 176 ′ above the image of the light _ 41 = patterned Photoresist 176. Or, as shown in Fig. 19 and Fig. 2, when the ion implantation process is carried out, the domain drug μ and the transistor region may not be provided with a cloth cover. As such, the tenth to twelfth preferred embodiments of the present invention can be formed in a well-formed well 52-ion implantation process to implant a p-type doping in the photo-sensing region 41. Miscellaneous 152. In summary, the process of the present invention can simply utilize the gate conductive layer to adjust the implantation strength and recording depth of the p-type doping well, and the (10) scale cloth _ energy can cause defects in the channel region of the transistor. It is also possible to reduce the CMC) S-image components to have a better #杂 layout, thereby reducing the generation of dark current. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. [Simple Description of the Drawing] FIG. 1 is a schematic structural view of a conventional CMOS image sensing element. 200921906 Figures 2 through 5 are schematic views of a method of fabricating a CMOS image sensing device in accordance with a first preferred embodiment of the present invention. 6 and 7 are schematic views respectively showing a method of fabricating a CMOS image sensing element according to the second and third preferred embodiments of the present invention. 8 to 10 are schematic views respectively showing a method of fabricating a CMOS image sensing element according to fourth to sixth preferred embodiments of the present invention. 11 to 15 are schematic views showing a method of fabricating a CM〇s image sensing and measuring element according to a seventh preferred embodiment of the present invention. Fig. 16 and Fig. 17 are respectively schematic views showing a method of fabricating a CMOS image sensing element according to the eighth and ninth preferred embodiments of the present invention. Figs. 18 to 20 are respectively the tenth to twelfthth aspects of the present invention. A schematic diagram of a method for fabricating a CMOS image sensing device. [Description of main component symbols] 10 semiconductor substrate 12 pixel unit 14 shallow trench isolation structure 16 N-type doping region 18 p-type doping well 20 photodiode 22 metal Dielectric layer 23 metal wire 24 intermetal dielectric layer 25 metal wire 26 interlayer dielectric layer 40 substrate 41 photo sensing region 42 shallow trench isolation structure 43 transistor region 44 transfer gate 46 gate dielectric layer 48 electrical conductor 19 200921906 50 Reset gate 52 P-type doping well 54 First well region 56 Second well region 58 Photodiode 60 Surface P-doped region 62 N-doped region 70 Implanted mask 72 P-type field Region 74 N-doped region 146 Dielectric layer 148 Conductive layer 152 P-type doping well 170 Implant mask 176 Patterned photoresist 20