200921888 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種靜電放電避免電路及相關靜電放電防護 電路，尤指一種使用靜電放電偵測器於一反饋回路之靜電放電避 免電路及相關靜電放電防護電路。 【先前技術】 k 奢互補式金氧半場效（Complementary Metal-Oxide '200921888 IX. Description of the Invention: [Technical Field] The present invention relates to an electrostatic discharge avoidance circuit and an associated electrostatic discharge protection circuit, and more particularly to an electrostatic discharge avoidance circuit using an electrostatic discharge detector in a feedback loop and Related electrostatic discharge protection circuit. [Prior Art] k Luxury Complementary Metal-Oxide
Semiconductor，CMOS)製程技術發展至深次微米及奈米階段，積 體電路效能也跟著不斷地提升，因此現今已有很多積體電路係以 CMOS導入量產。在更先進製程技術中，可使所生產的積體電路 之元件尺寸更縮小、閘極氧化層（Gate_〇xide)更薄、以及汲極/ 源極（Drain/Source)深度更淺等，用以提高密集度與改善元件特 性。然而這些先進製程技術，卻嚴重降低積體電路對靜電放電 (Electro-static discharge，ESD)的耐受度，使得靜電放電更容易成 為量產積體電路中的良率瓶頸所在。 請參考第1圖，第1圖為習知積體電路1〇〇輸入端的靜 電放電防護電路之示意圖。積體電路100包含一連接墊 101、一輸入電阻108、一内部電路12〇、一電源箝制電路 (powerclampcirCUit)130、一輸入端 ESD 防護電路 1〇5、及 一輸入端反相器110。輸入端ESD防護電路1〇5包含一 N 型金氧半場效(metal oxide semiconductor，MOS)電晶體 200921888 與一 P型金氧半場效電晶體107，以分別於連接墊101與 電源端190之間以及連接墊101與接地端195之間形成 ESD防護，電源端190可為一電源繞線，而接地端195則 可為一接地繞線。 電源箝制電路130係為電源端190與接地端195之間 的ESD防護電路。輸入端反相器110包含一 N型金氧半場 效電晶體111與一 P型金氧半場效電晶體112，耦接於輸 入電阻108與内部電路120之間，用以配合輸入電阻108， 提供内部電路120更一步的靜電放電防護功能。積體電路 100輸入端的靜電放電防護電路之工作原理，係利用疏浚 靜電電流方式，保護内部電路120，其中N型金氧半場效 電晶體106、P型金氧半場效電晶體107、及電源箝制電路 130，即用以當靜電放電事件發生於連接墊101、電源端 190、或接地端195時，提供靜電電流疏浚通道。 當内部電路包含有可程式電路(programmable circuit)，而燒錄訊號之電壓又要經由連接墊101提供至可 程式電路，以執行燒錄操作時，則第1圖所示之積體電路 100輸入端的靜電放電防護電路，無法執行燒錄操作，因P 型金氧半場效電晶體107之汲極與通道摻雜井所形成的二極 體，會將燒錄訊號之電壓箝位於電源端190之電源電壓 Vdd。請參考第2圖，第2圖係顯示習知具可程式功能之積 200921888 體電路200輪入端的靜電放電防護電路之示意圖。具可程 式功能之積體電路200係為將積體電路1〇〇之p型金氧半 場效電晶體1G7移除後之電路，而p型金氧半場效電晶體 1〇7之防護功能係由N型金氧半場效電晶體1〇6之寄生電 晶體，配合電源箝制電路130而提供的防護功能所取代。 在第1圖及第2圖所示的靜電放電防護電路，均係利 用疏溲靜電電流方式’以避免後級f路受到損害，但若瞬 間静電放電累積的電荷量太大時，可能就無法即時地疏漫 瞬間累積的電荷量，導至靜電累積電荷傳輸至後級電路= 造成損害。 【發明内容】 依據本發明之實施例，其揭露一種使用靜電放電偵測器於一 反饋回路之靜電放電避免電路(ESD avoiding circuit)，用以當—連 接墊感應-靜電放電頓時，_靜電放電電壓以贼 p損害’此靜電放電避免電路包含有—第—電晶體及一 電::糊合於連接塾之一源極，合於内: 合於第-電晶體，; 據控制訊號可控制第―電Γ體^ 電日日體之間極，根 乐—冤日日體及一第四電晶體。第二+ 有轉合於連触之-源極，合於其源極之—通道穆雜^體具 '开’麵合 200921888 ==:’::合於第一電晶體之_ 一 的-狀。/舰，及祕於第—電晶體之閘極 極之-通道體具妨合於接地端之1極，合於其源 晶體之===極Mm端之—間極，及搞合於第一電 -反實施例’其另揭露一種使用靜電放賴測器於 一内部電路2放細電第D P™Gn ―)，用以保護 損宝，包含有連接墊所感應之—靜電放電電壓之影響而 第一電晶體具有輕合於連接墊之靜^電動]减一弟五電晶體。 極，於連接墊之一源極’轉合於内部電路之一汲 娜田 通道摻雜井。靜電放電偵測器轉合於第-電曰 脰’用以提供一控制訊號至第一電晶體之間極: 控制第-電晶體之開關狀態，靜電放電偵測器包含 f電日鳴及—相電晶體。第二電晶體 塾,一源極，合於其源極之—通道摻雜井，私電= ::極，合於第-電晶體之•之-汲極。第三電:體:： 源極’:合於其源極之-通道摻雜井，耦合 四電晶體具嫩於沒極。第 -，第五電晶體具有柄合於接地端之一源極二： 200921888 之一通道摻雜井，耦合於其源标夕 丹愿枉之―閘極，及耦合於連接墊之一 沒極。 【實施方式】 為讓本發明之目的、特徵和優點更顯而紐，下文依本發明 之使用靜電放電_11於—反饋回路之靜電放電避免電路及靜電 放電防護電路，特舉實施例配合所附圖式作詳細說明，但所提供 之實施例並不用以限制本發明所涵蓋的技術範圍。 ^ w考第3圖第3圖係、顯示依本發明之積體電路細輸 電放電避免電路之—第—實施例的電路示意圖。 積體電路300包含一連接墊3〇1 ^ ^ όΌΙ —第—電晶體305、一靜 電放電偵測器370及一内部雷改够， 〜 Ρ電路38〇°第3圖之靜電放電避旁雷 路包含第一電晶體3〇5及靜雷占' 哭3 電放電偵測器370。靜電放電偵測 第三電晶體315、一第四 „„ 370包含一第二電晶體31〇、 電晶體320及一電阻321。 第一電晶體305具有耗合於連接塾 部電路380之一糾i人 ^01之一源極，耦合於内 靜電放電偵測器370之—閘極，及 通机雜井，第-電晶體3〇5之通 或轉合於-電舰於其源極， t料39()1 —電晶體地係為—p型 曰曰體’而其通道摻雜井即為-N型換雜井。靜 琢效電 可偵測來自連接墊3〇1之電偵冽器370 之一靜電放電電屋，並可提供-控制訊號 10 200921888 2制第-電晶體305的導通/截止狀態，也就是說，第— 电曰日體305的功此基本上就是受靜電放電偵測器控制之 —開關電晶體（pass transist〇r)。 第二電晶體310具有轉合於連接塾3〇1之一源極，搞合於其 2極之-通這摻雜井’耗合於内部電路則之一閘極，及轉合於 f =晶體3〇5之閘極的一汲極，第二電晶體3H)係為-p型金 礼半场效電晶體。第三電晶體315具有耦合於 合於其源極之-通道推雜井，搞合於内部電路勘之一 —電晶體3〇5之間極的一沒極，第三電晶體阳 井。· +場效電晶體，而其通道摻雜井即為—ρ型推雜 第四電曰日體320具有耦合於一接地端395之 其源極之-it轉料，Μ = ’ ^於 一電晶體305之門_1 閉極’及輕合於第 半場效電晶體Γ 四電晶體320係為—ν型金氧 的間極之間Γ在軸合於電源端與第四電晶體挪 氧化層之—金氧半場效電晶 ?第_=化 電晶體係為具相極氧化層之金氧半場效電紅及第三 作時= 端的靜電放㈣免電路，在正常工 电1件發生時，電路工作原理分別敘述如 200921888 下。在電路正常工作時，雷艰 ^電源纟而390供應電源電壓vdd， 而接地端395則耗接？咕 要至接地電位，第四電晶體320因其閘 虽耦合於電源端390之電源電壓Vdd而導通，所以第二電 晶體305之閘極所接收之控制訊號係為一接地電位訊號， 因而使第一電晶體305導通。 當輸入一低電位訊號至連接墊3〇1時，低電位訊號可 經由第-電晶體3〇5傳輸至内部電路38〇，此低電位訊號 亦同時被反馈至第二電晶體31G及第三電晶體315之問 極’、因而使第二電晶體310導通和使第三電晶體315截止， 所以第-電晶體3 0 5之閘極也可經由第二電晶體3 i 〇輛合 低^位afL f虎目此’控制訊號可以是經由第四電晶體 饋入之接地電位訊號，也可以是經由第二電晶體饋入 之低電位訊號。 當輪入一高電位訊號至連接墊3〇1時，高電位訊號可 經由第一電晶體3〇5傳輸至内部電路38〇，此高電位訊號 亦同日τ被反饋至第一電晶體310及第三電晶體315之閘 極因而使第二電晶體31 〇截止和使第三電晶體3丨5導通， 所以第—電晶體305之閘極也可經由第三電晶體315耦合 至接地電位。請特別注意，此高電位訊號之電壓可以是高 於電源端390之電源電壓Vdd的一燒錄訊號之電壓，換句 活5兒，此高電位訊號之電壓並不會被箝位於電源電壓 J2 200921888Semiconductor, CMOS) process technology has evolved to the deep micron and nano phase, and the performance of integrated circuits has been continuously improved. Therefore, many integrated circuits are now mass-produced in CMOS. In more advanced process technology, the component size of the integrated circuit produced can be further reduced, the gate oxide layer (Gate_〇xide) is thinner, and the drain/source (Drain/Source) depth is shallower. Used to increase density and improve component characteristics. However, these advanced process technologies have severely reduced the tolerance of integrated circuits to Electro-static discharge (ESD), making electrostatic discharges more likely to be the yield bottleneck in mass-produced circuits. Please refer to Fig. 1. Fig. 1 is a schematic diagram of the electrostatic discharge protection circuit at the input end of the conventional integrated circuit. The integrated circuit 100 includes a connection pad 101, an input resistor 108, an internal circuit 12A, a power clamp circuit 130, an input ESD protection circuit 1〇5, and an input inverter 110. The input ESD protection circuit 1〇5 includes an N-type metal oxide semiconductor (MOS) transistor 200921888 and a P-type MOS field-effect transistor 107 to be respectively connected between the connection pad 101 and the power supply terminal 190. The ESD protection is formed between the connection pad 101 and the grounding end 195. The power supply end 190 can be a power supply winding, and the ground end 195 can be a grounding winding. The power clamp circuit 130 is an ESD protection circuit between the power terminal 190 and the ground terminal 195. The input inverter 110 includes an N-type MOS field oxide transistor 111 and a P-type MOS field-effect transistor 112 coupled between the input resistor 108 and the internal circuit 120 for mating with the input resistor 108. The internal circuit 120 has a further electrostatic discharge protection function. The working principle of the electrostatic discharge protection circuit at the input end of the integrated circuit 100 protects the internal circuit 120 by using a dredging electrostatic current mode, wherein the N-type gold-oxygen half-field effect transistor 106, the P-type gold-oxygen half-field effect transistor 107, and the power supply clamp The circuit 130 is configured to provide an electrostatic current dredging channel when an electrostatic discharge event occurs at the connection pad 101, the power terminal 190, or the ground terminal 195. When the internal circuit includes a programmable circuit, and the voltage of the programming signal is supplied to the programmable circuit via the connection pad 101 to perform the programming operation, the integrated circuit 100 shown in FIG. 1 is input. The electrostatic discharge protection circuit of the terminal cannot perform the programming operation. The diode formed by the drain of the P-type metal oxide half field effect transistor 107 and the channel doping well clamps the voltage of the programming signal to the power terminal 190. Power supply voltage Vdd. Please refer to Fig. 2, which shows a schematic diagram of a conventional program with the programmable function. 200921888 The circuit of the 200-input electrostatic discharge protection circuit. The integrated circuit 200 with programmable function is a circuit for removing the p-type gold-oxygen half field effect transistor 1G7 of the integrated circuit 1 , and the protection function of the p-type gold oxygen half field effect transistor 1〇7 The parasitic transistor of the N-type MOS field-effect transistor 1 〇 6 is replaced by a protective function provided by the power supply clamping circuit 130. The electrostatic discharge protection circuits shown in Fig. 1 and Fig. 2 both use the dredging electrostatic current method to avoid damage to the rear stage f. However, if the amount of charge accumulated by the instantaneous electrostatic discharge is too large, it may be It is impossible to instantly dissipate the amount of charge accumulated in an instant, leading to the accumulation of static charge to the subsequent stage circuit = causing damage. SUMMARY OF THE INVENTION According to an embodiment of the present invention, an ESD avoiding circuit using an ESD detector in a feedback loop is disclosed for when the connection pad is inductively-electrostatic discharge, _electrostatic discharge The voltage is damaged by the thief. 'This electrostatic discharge avoidance circuit contains - the first transistor and the other: the paste is connected to one of the sources of the connection, and is integrated with: the first transistor; the control signal can be controlled The first - electric body ^ electric day between the Japanese body, the root music - the Japanese body and a fourth transistor. The second + has a turn-to-touch-source, which is combined with its source-channel mu-mat ^ body with 'open' face 200921888 ==: ':: combined with the first transistor _ one - shape. / ship, and secret - the gate of the transistor - the channel body can be tied to the ground of the pole, combined with the source crystal === pole Mm end - the pole, and fit the first The electro-reverse embodiment discloses a method of using an electrostatic discharge detector to discharge a fine PDPMGn ― in an internal circuit 2 for protecting the damage, including the influence of the electrostatic discharge voltage induced by the connection pad. The first transistor has a lightly coupled to the connection pad, and the second transistor is reduced. The pole is connected to one of the internal circuits of one of the connection pads 汲 Natian channel doping well. The ESD detector is coupled to the first electrode to provide a control signal to the first transistor: controlling the switching state of the first transistor, and the electrostatic discharge detector includes the f-day and the Phase transistor. The second transistor, 源, a source, is coupled to its source - the channel doping well, the private power = :: pole, and the - transistor of the first - transistor. The third electricity: body:: source': the channel-doped well that is combined with its source, the coupling of the four transistors is tender and infinite. The first-, fifth-electrode has a shank that is coupled to one of the ground terminals. Source: 200921888 One channel-doped well coupled to its source 夕 丹 枉 ― ― 闸 ,, and coupled to one of the connection pads . [Embodiment] In order to make the objects, features and advantages of the present invention more obvious, the electrostatic discharge avoidance circuit and the electrostatic discharge protection circuit using the electrostatic discharge_11-feedback loop according to the present invention, the specific embodiment cooperates with the present invention. The drawings are described in detail, but the embodiments provided are not intended to limit the technical scope of the invention. ^W. Fig. 3, Fig. 3 is a circuit diagram showing the first embodiment of the integrated circuit of the integrated circuit of the present invention. The integrated circuit 300 includes a connection pad 3〇1 ^ ^ όΌΙ - the first transistor 305, an electrostatic discharge detector 370 and an internal lightning correction, ~ Ρ circuit 38 〇 ° Figure 3 of the electrostatic discharge avoidance The road includes a first transistor 3〇5 and a static mine occupies a 'cry 3 electric discharge detector 370. Electrostatic Discharge Detection The third transistor 315, a fourth „ 370 includes a second transistor 31 , a transistor 320 , and a resistor 321 . The first transistor 305 has a source that is coupled to one of the connection circuit 380, is coupled to the gate of the internal electrostatic discharge detector 370, and is connected to the well, the first transistor. 3〇5通或转合-Electric ship at its source, t material 39()1—the crystal field is a p-type 曰曰 body' and its channel doping well is a -N type well . The static electricity can detect an electrostatic discharge electric house from the electrical detector 370 of the connection pad 3〇1, and can provide the on/off state of the control transistor 10 200921888 2 - transistor 305, that is, The first function of the electric body 305 is basically controlled by an electrostatic discharge detector - a pass transistor (pass transist〇r). The second transistor 310 has a source that is coupled to the connection 塾3〇1, and is coupled to the two poles thereof. The doping well is consuming one of the gates of the internal circuit, and is coupled to f = A drain of the gate of the crystal 3〇5, the second transistor 3H) is a -p type Jinli half field effect transistor. The third transistor 315 has a channel-inducing well coupled to its source, which is integrated into a pole of the internal circuit, a pole between the transistors 3〇5, and a third transistor. + field effect transistor, and its channel doping well is -p type pusher fourth electric cell 320 has a source coupled to a ground terminal 395 -it reversal, Μ = ' ^ in one The gate _1 of the transistor 305 is closed-closed and lightly coupled to the first half field effect transistor Γ. The four-transistor 320 series is between the inter-electrode of the -ν-type gold oxide, and is coupled to the power supply terminal and the fourth transistor. The layer--the gold-oxygen half-field effect transistor? The _=------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- When the circuit works, it is described separately under 200921888. When the circuit is working normally, it is difficult to supply the power supply voltage vdd, and the ground terminal 395 is consumed. The fourth transistor 320 is turned on because the gate is coupled to the power supply voltage Vdd of the power supply terminal 390. Therefore, the control signal received by the gate of the second transistor 305 is a ground potential signal, thereby The first transistor 305 is turned on. When a low potential signal is input to the connection pad 3〇1, the low potential signal can be transmitted to the internal circuit 38〇 via the first transistor 3〇5, and the low potential signal is also fed back to the second transistor 31G and the third. The gate of the transistor 315, thus turning on the second transistor 310 and turning off the third transistor 315, so that the gate of the first transistor 305 can also be turned down via the second transistor 3 i. The 'af control signal' may be a ground potential signal fed through the fourth transistor or a low potential signal fed through the second transistor. When a high-potential signal is input to the connection pad 3〇1, the high-potential signal can be transmitted to the internal circuit 38〇 via the first transistor 3〇5, and the high-potential signal is also fed back to the first transistor 310 at the same day τ and The gate of the third transistor 315 thus turns off the second transistor 31 and turns on the third transistor 3丨5, so that the gate of the first transistor 305 can also be coupled to the ground potential via the third transistor 315. Please pay special attention to the fact that the voltage of the high-potential signal can be a voltage higher than the power-on signal of the power supply terminal 390 of the power supply terminal 390. In other words, the voltage of the high-potential signal is not clamped to the power supply voltage J2. 200921888
Vdd，所以，連接墊301不但可以作為一般邏輯訊號的輸入 塑·，也可以作為燒錄訊號的輸入塾。因此，第3圖所示之 靜電放電避免電路可相容於具可程式功能之積體電路，而連 接墊301可兼具接收燒錄訊號與接收邏輯訊號的功能。 在靜電放電事件發生時，連接墊3〇1、電源端39〇及 接地端395均係在浮接狀態，即為沒有接地的浮接端，而 浮接端貫質上係易於I馬接至零電位(接地電位），所以第一 至第四電晶體305、310、315及320在不受靜電放電事件 影響時’均處於截止狀態。當相對於接地端395之一靜電 放電正電壓發生於連接墊301，並傳至第二電晶體31〇之 源極時’會使第二電晶體310因浮接端而導通，靜電放電 正電壓就被傳送至第一電晶體305之閘極，當作控制訊號 使第一電晶體305保持在截止狀態，所以靜電放電正電壓 就被第一電晶體305隔絕以避免傳送至内部電路380造成 損害。當相對於接地端395之一靜電放電負電壓發生於連 接螯301，並傳至第一電晶體305之源極時，第一電晶體 305仍會保持在截止狀態，所以靜電放電負電璧就被第一 電晶體305隔絕以避免傳送至内部電路380造成損害。此 外’當靜電放電電壓發生於電源端390時，則被第四電晶 體320及第一電晶體305的閘極氧化層隔絕而無法影響到 内部電路380 ’當靜電放電電壓發生於接地端395時，則 藉由第一電晶體3〇5及第二電晶體310的隔絕作用，所以 13 200921888 靜電放電電壓也不可能影響到内部電路38〇。 請參考第4圖’第4圖係顯示依本發明之積體電路_輸 入端的靜電放電避免電路之—第二實施例的電路示意圖。 積體電路400包含一連接墊3(H、一第—電晶體3〇5、一靜 電放電偵測器370、-第五電晶體425、—電阻426及一内部 電路380。第4圖之靜電放電避免電路包含第—電晶體3〇5、 第五電晶體425、電阻426及靜電放電制器37〇。靜電放電 偵測器370包含一第二電晶體31〇、-第三電晶體315、一 第四電晶體320及-電阻32卜第一電晶體3〇5具有輕合於連 接墊301之一源極，耦合於内部電路38〇之—汲極，一閘極，及 輕合於電源端390之一通道換雜井。 第五電晶體425具有轉合於連接塾3〇1之一源極，搞合於内 部電路380之-沒極，搞合於電阻伽之一間極，及轉合於接地 端395之-通道摻雜井’第五電晶體奶係為具厚閉極氧化層之 - N型金乳半場效電晶體。第五電晶體奶之功能係在電路正常 工作時，提供連接墊301與内部電路彻之間更高速度與更低電 阻的訊號傳輸路徑，因N型錄半場效電晶_通道導通傳輸速 度及電阻均優於P型金氧半場效電晶體。電阻426係轉合於電源 端與第五電晶體425的閑極之間。積體電路_輸入端之 靜電放電避免電路的其餘電路元件之搞接關係同第3圖之 積體電路300 ’所以不再贊述。 14 200921888 積體電路400輸入端的靜電放電避免電路，在正常工 作時及在靜電放電事件發生時，電路工作原理分別敘述如 下。在電路正常工作時，電源端390供應電源電壓Vdd， 而接地端395則耦接至接地電位，所以第四電晶體320因 其閘極耦合於電源端390之電源電壓Vdd而導通，第一電 晶體305因其閘極經由第四電晶體320耦合至接地電位而 導通，第五電晶體425則因其閘極耦接至電源電壓Vdd且 通道摻雜井耦接至接地電位而導通，如前所述，第五電晶體425 導通時，可輔助第一電晶體305提供更高速度及更低電阻 的傳輸路徑。 當輸入一低電位訊號至連接墊301時，低電位訊號可 經由第一電晶體305或第五電晶體425傳輸至内部電路 380,此低電位訊號亦同時被反饋至第二電晶體310及第三 電晶體315之閘極，因而使第二電晶體310導通和使第三 電晶體315截止，所以第一電晶體305之閘極也可經由第 二電晶體310耦合至低電位訊號。 當輸入一高電位訊號至連接墊301時，高電位訊號可 經由第一電晶體305或第五電晶體425傳輸至内部電路 380,此高電位訊號亦同時被反饋至第二電晶體310及第三 電晶體315之閘極，因而使第二電晶體310截止和使第三 電晶體315導通，所以第一電晶體305之閘極也可經由第 15 200921888 三電晶體315耦合至接地電位。同理，此高電位訊號之電 壓可以是高於電源端390之電源電壓Vdd的一燒錄訊號之 電壓，所以，連接墊301不但可以作為一般邏輯訊號的輸 入墊，也可以作為燒錄訊號的輸入墊，因此，第4圖所示 之靜電放電避免電路也可相容於具可程式功能之積體電路。 同前所述，在靜電放電事件發生時，連接墊301、電 源端390及接地端395均係在浮接狀態，即為沒有接地的 浮接端，而浮接端實質上係易於耦接至零電位（接地電 位），所以第一至第五電晶體305、310、315、320及425 在不受靜電放電事件影響時，均處於截止狀態。當相對於 接地端395之一靜電放電正電壓發生於連接墊301，並傳 至第二電晶體310之源極時，會使第二電晶體310因浮接 端而導通，靜電放電正電壓就被傳送至第一電晶體305之 閘極，因而保持第一電晶體305在截止狀態，同時當靜電 放電正電壓傳至第五電晶體425之源極時，也會使第五電 晶體425因電源端390的浮接狀態而保持在截止狀態，所 以靜電放電正電壓就被第一電晶體305及第五電晶體425 隔絕以避免傳送至内部電路380造成損害。當相對於接地 端395之一靜電放電負電壓發生於連接墊301，並傳至第 一電晶體305之源極及第五電晶體425之源極時，第一電 晶體305及第五電晶體425仍會保持在截止狀態，所以靜 電放電負電壓就被第一電晶體305及第五電晶體425隔絕 16 200921888 以避免傳送至内部電路勘造成損害。此外，1電放電 電壓發生於電源端或接地端395日夺，對靜&電電壓 的隔絕原理類似對第3圖之靜電放電避免電路所說明的隔 絕原理，所以不再贅述。 。 ^ 請參考第5圖，第5圖係顯示依本發明之積體電路5〇〇輸 入端的靜電放電防護電路之一第一實施例的電路示意圖。 積體電路500包含-連接勢5(H、一第一電晶體5〇5、一靜 電放電侦測器570、-第五電晶體525及__内部電路獨。靜 電放電偵測器570包含一第二電晶體51〇、一第三電晶體 515、一第四電晶體52〇及一電阻521。第5圖之靜電放電 防護電路包含第一電晶體5〇5、第五電晶體525及靜電放電 偵測器570。第一電晶體5〇5至第四電晶體52〇、連接墊5〇1、 隻阻521及内部電路58〇之間的耦接關係同第3圖之積體電路 3〇〇，所以不再贅述。 第五電晶體525具有耦合於連接墊501之一汲極，耦合於 接地端595之一源極，耦合其源極之一閘極，及耦合於其源極之 一通這摻雜井’第五電晶體525係為具厚閘極氧化層之一 N型金 氧半場效電晶體。第五電晶體525之功能係在靜電放電事件發生 時’提供一靜電放電電流之疏浚路徑。 積體電路500輸入端的靜電放電防護電路，在正常工 17 200921888 作時及在靜電放電事件發生時，電路工作原理分別敘述如 下。在電路正常工作時，電源端590供應電源電壓Vdd， 而接地端595則耦接至接地電位，第一電晶體505至第四 電晶體520的工作原理同於第3圖之第一電晶體305至第 四電晶體320的工作原理，所以不再贅述。當輸入低電位 訊號或高電位訊號至連接墊501時，第五電晶體525均處 於戴止狀態，使所輸入之低電位訊號或高電位訊號均經由 第一電晶體505傳輸至内部電路580。當有一負電壓脈波 發生於連接墊50】時，此負電壓脈波可經由第五電晶體525 之一寄生二極體而導通至接地端595，也就是說，第五電 晶體525可於正常工作時，將發生於連接墊501之負電壓 脈波疏浚至接地端595，使負電壓脈波不會被傳輸至内部 電路580。請特別注意，上述之高電位訊號的電壓也可以 是高於電源端590之電源電壓Vdd的一燒錄訊號之電壓。 所以，連接墊501不但可以作為一般邏輯訊號的輸入墊， 也可以作為燒錄訊號的輸入墊，因此，第5圖所示之靜電 放電防護電路可相容於具可程式功能之積體電路。 同前所述，在靜電放電事件發生時，連接墊501、電 源端590及接地端595均係在浮接狀態，即為沒有接地的 浮接端，而浮接端實質上係易於耦接至零電位（接地電 位），所以第一至第五電晶體在不受靜電放電事件影響時， 均處於截止狀態。當相對於接地端595之一靜電放電負電 18 200921888 壓發生於連接墊501時，在連接墊501所累積之靜電電荷， 可經由第五電晶體525之汲極N型摻雜區及P型摻雜井所 形成的寄生二極體，而疏浚至接地端595，或者當第五電晶 體525無法及時疏浚靜電電荷時，靜電放電負電壓會被傳 送至第一電晶體505之源極，使第一電晶體505保持在截 止狀態，所以靜電放電負電壓就被第一電晶體505隔絕以 避免傳送至内部電路580造成損害。 當相對於連接墊501之一靜電放電正電壓發生於接地 端595，並經由第二電晶體510(P型金氧半場效電晶體)而傳 送至第一電晶體505之閘極時，可保持第一電晶體505在 截止狀態，所以靜電放電正電壓就被第一電晶體505隔絕 以避免傳送至内部電路580造成損害。至於當一靜電放電 電壓發生於電源端590或接地端595時，第一至第四電晶 體對靜電放電電壓的隔絕原理類似對第3圖之靜電放電避 免電路所說明的隔絕原理，所以不再贅述。由上述可知， 第5圖所示之靜電放電防護電路，不但可相容於具可程式功 能之積體電路，而且兼具隔絕靜電放電電壓與疏浚靜電放電電 流的功能，所以可提供晶片内部積體電路更可靠的靜電放電保護 機制。 請參考第6圖，第6圖係顯示依本發明之積體電路600輸 入端的靜電放電防護電路之一第二實施例的電路示意圖。 19 200921888 積體電路60〇包含一連接墊601、一第一電晶體605、一靜 電放電偵測器670、-第五電晶體625、—第六電晶體63〇、 —第七電晶體635、一第八電晶體64〇、一第九電晶體645、 —内部電路680、一電源箝制電路685及一電阻636。第6 圖之靜電放電防護電路包含第一電晶體6〇5、第五電晶體 625、第六電晶體63〇、第七電晶體635、第八電晶體64〇、 第九電晶體645、電阻636、電源箝制電路685及靜電放電 偵測器670。靜電放電偵測器67〇包含一第二電晶體61〇、一第 三電晶體615、一第四電晶體62〇及一電阻621。電源箝制 電路685係耦合於電源端69〇與接地端695之間。 第八電晶體640具有耦合於電源端69〇之一源極，耦合於其 ’原極之一通道摻雜井，轉合於内部電路680之-沒極，及-閘極， 第八電晶體640係為-Ρ型金氧半場效電晶體。第九電晶體⑷ 具有柄合於接地端695之-源極，轉合於其源極之一通道摻雜井， 轉合於内部電路680之-汲極，及搞合於第八電晶體_之閘極 的閘極，第九電晶體645係為一㈣金氧半場效電晶體。 第-電晶體605具有轉合於連接墊碰之一源極，柄合於第 電曰曰體640之間極的一沒極，耦合於靜電放電偵測器㈣之一 =，及轉合於電源端_之—通道摻雜井，第—電晶體6〇5係 ‘ ：、’、Ρ型金乳半場效電晶體。第七電晶體635具有轉合於連接墊 _之-源極’ Μ合於第人電晶體_之閘極的—汲極，合於電 20 200921888 阻636之—間極，及柄合於接地端695之-通道摻雜和第 晶體635係為-N型金氧半場效電晶體。電阻636 _合於電源 端690與第七電晶體635的閘極之間。 第二電晶體610具有轉合於連接墊6〇1之一源極，搞合於其 源極之-通道摻雜井，柄合於第八電晶體_之閘極的一;極了 及轉合於第-電晶體605之間極的一汲極，第二電晶體副係為 - p型金氧半場效電晶體。第三615具抽合於一接地端 695之-源極,合於其源極之一通道摻雜井，搞合於第八電晶體 =〇之閘極的-閘極’及耗合於第一電晶體6〇5之閉極的一汲極， 第二電晶體615係為一 N型金氧半場效電晶體。 第四電晶體620具有轉合於一接地端695之一源極，耗合於 .、源極之if道摻雜井，耗合於電阻之一間極，及辆合於第 電晶體605之閘極的一汲極，第四電晶體62〇係為—N型金氧 半場效電晶體。電阻621係耦合於電源端690與第四電晶體62〇 的閘極之間。在一較佳實施例中’第四電晶體620係為具薄閘極 氧化層或厚難氧化層之—金氧半場效電晶體，而其餘電晶體係 為具厚閘極氧化層之金氧半場效電晶體。 第五電晶體625具有耦合於連接墊601之一汲極，耦合於 接地端695之一源極’耦合其源極之一閘極，及耦合於其源極之 —通道摻雜井，第五電晶體625係為一 N型金氧半場效電晶體。 21 200921888 第六電晶體63〇具有耦合於連接墊601之一汲極，耦合 69〇之一源極，耦合其源 _ 、电#5而 雜井，第六電日日日體閘極’核合於其源極之一通道摻 :晶體 、' p型金氧半場效電| 積體電路600輪入立山 刑八端的靜電放電 作時及在靜電放電事件發生時，。 濩電路，在正常工 下。在電路正常：ϋ作時，f t冑路卫作原理分別敎述 了電源端690供痛干 而接地端095則耦接至接 · 一、愿電源電壓Vdd， 電晶體625及第七電晶辦 玉日日體605至第五 电曰日體635的工作原掙闩 乐五 4圖之第五電晶體425 電晶體505至第五電曰 、同於第5圖之第 的工作原理’所以不再寶 ,, 日日體525及第4阍夕结τι ^ 述 當輸入低電位訊衆或古 五電晶體625及第六電晶：二&墊叫 入之低電位訊號或高電位訊號均可_=狀態，使所輸 第七電晶體635傳輸至内部電路_」右—電晶體605或 發生於連接塾601時’此正電壓脈波可：有-正電壓脈波 之-寄生二極體而導通至電源端咖二由第^電晶體㈣ 連接塾，之正電麼脈波可被疏:=，發生於 壓脈波不會被傳輸至内部電路68〇。电愿端69〇,使正電 同前所述，可被第五電曰曰 至於負電壓脈波，則 曰曰體625之一卑^ _ 接地端695。第八電晶體 ^生二極體而疏浚至 相器電路。 與第九電晶體⑷形成—反 22 200921888 在靜電放電事件發生時，連接墊601、電源端690及 接地端695均係在浮接狀態，所以第一至第九電晶體在不 受靜電放電事件影響時，均處於截止狀態。第一電晶體605 至第五電晶體625及第七電晶體635的工作原理同於第5 圖之第一電晶體505至第五電晶體525及第4圖之第五電 晶體425的工作原理，所以不再贅述。 此外，當第六電晶體630無法及時疏溲靜電電荷時， 靜電放電正電壓會被傳送至第一電晶體605之閘極，當作 控制訊號使第一電晶體605保持在戴止狀態，所以靜電放 電正電壓就被第一電晶體605隔絕以避免傳送至内部電路 680造成損害，而第八電晶體640與第九電晶體645之閘 極氧化層也可避免内部電路680受靜電電荷直接影響而損 害。電源箝制電路685係為習知用以提供電源端690與接 地端695之間的靜電放電電流疏浚功能。 由上述可知，第6圖所示之靜電放電防護電路，提供 多重的靜電放電保護機制，若省略第六電晶體630、第八 電晶體640及第九電晶體645，將第一電晶體605之汲極 直接耦合至内部電路680，及將第一電晶體605之源極直 接耦合至連接墊601，則第6圖之靜電放電防護電路也可 相容於具可程式功能之積體電路。 23 200921888 請參考第7圖’第7圖為第6圖之電源箝制電路之一第一實 化例的電路示意圖。如弟7圖所示，電源箝制電路7〇〇包含一電 晶體710、一電阻720及一電容73〇。電阻72〇及電容73〇係以串 接方式轉合於電源端690與接地端695之間，電容可為一金 氧半導體電容(MOS capacitor)或一金屬-絕緣體_金屬 (metal-insulator_metal，MIM)電容。電晶體71〇具有耦合於接地端 695之一汲極’耦合於電源端69〇之一源極，耦合於其源極之一通 道摻雜井，及轉合於電阻720與電容73〇之連接節點的一問極， 電晶體710係為-P型金氧半場效電晶體。電源箝制電路係 為習知技藝，所以不再贅述其工作原理。 請參考第8圖，第8圖為第6圖之電源箝制電路之一第二實 施例的電路示意圖。如第8圖所示，電源箝制電路_包含Γ第 -電晶體810、-第二電晶體82◦、一第三電晶體請、一電阻_ 及-電容850。電阻840及電容85〇係以串接方式轉合於電源端 _與接地端695之間，電容8料為—金氧半導體電容或一金屬 .體，電容。第三電晶體㈣具綠合於電源端_之一汲 極，輕合於接地端695之-源極，搞合於其源極之一通道摻雜井， 及一閘極’第三電晶體83〇係為一 N型金氧半場效電晶體。第一 =:〇具有_源端㈣之一源極，合於第三電晶體 阻ΓΓΓΓ祕，私於其源極之—通道摻雜井，及耗合於電 ^入^⑥谷850之連接節點的一閘極，第—電晶體⑽係為-P 孟礼丰％效電晶體。第二電晶體伽具有輕合於接地端奶之 24 200921888 -源極傭第三電晶體謂之間極的一汲極，執 之=通道摻雜井，及耗合於第一電晶體仙之間極的___，第 -電曰曰體820係為-N型金氧半場效電晶體。第—電晶體 ^刪820形成-反向器，合於電阻_與電容咖的連 接即點糾二電晶體83〇的閑極之間。電源籍制電路_為 習知技藝，所以不再贅述其工作原理。 ’、马 由上述可知，依本發明之使用靜電放電偵測器於一反饋回 路的静電《贼辑，料隔婦較電電_舰，而 相容於具可程式魏之積體電路。而依本發明之制靜電放 電偵測器於-反饋回路的靜電放電防護電路，則兼具隔絕 電電壓與錢靜f放電電流的魏，細可提供晶片内部積， 路更可靠的靜電放電保護機制。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之鱗變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖顯示習知積體電路輸人端的靜電放電防護電路之示 意圖。 第2圖顯tf白知具可程式功能之積體電路輸人端的靜電放 電防遵電路之示意圖。 第3圖顯示依本發明之積體電路輸人端的靜電放電避免電路 25 200921888 ,之一第—實施例的電路示意圖。 第4圖顯不依本發明之 之-第-實以電路輸入端的靜電放電避免電路 ^ _ 實％例的電路示意圖。 第5圖顯示依本發明之 路 具體電路輸入端的靜電放電防謹雷 之-第-實施例的電路示意圖。 第6圖顯示依本發明之籍 路 卜 知體琶路輸入端的靜電放電防護 斤之一々第二實施例的電路示意圖。 f 6圖之電源箝制電路之―第一實施例的電路示意圖。 第8圖顯示第6圖之電源箝制電路之一第二實施例的電路示意圖。 【主要元件符號說明】 100、200、300、積體電路 500 ' 600 101 105 106 107 108 110 301 > 501 111 112 601連接墊 輸入端ESD防護電路 N型金氧半場效電晶體 P型金氧半場效電晶體 輸入電阻 輸入端反相器 120、380、580、680 内部電路 130、685、700、800電源箝制電路 190、390、59Q、690 電源端 195、395、595、695 接地端 26 200921888 305、 505、 605、 810 第 _— 電 晶 體 310、 510、 610、 820 第 二 電 晶 體 315、 515、 615、 830 第 三 電 晶 體 320、 520 、620 第 四 電 晶 體 321 > 426 、521 電 阻 621 ' 636、 720、 840 425 ' 525 、625 第 五 電 晶 體 630 第 六 電 晶 體 635 第 七 電 晶 體 640 第 八 電 晶 體 645 第 九 電 晶 體 710 電 晶 體 730 電容 Vdd 電源電壓 27Vdd, therefore, the connection pad 301 can be used not only as an input for general logic signals, but also as an input port for programming signals. Therefore, the ESD avoidance circuit shown in FIG. 3 can be compatible with a programmable circuit with a programmable function, and the connection pad 301 can function as both a reception signal and a reception logic signal. When an electrostatic discharge event occurs, the connection pad 3〇1, the power terminal 39〇, and the ground terminal 395 are all in a floating state, that is, a floating end that is not grounded, and the floating end is easily connected to the ground. Zero potential (ground potential), so the first to fourth transistors 305, 310, 315, and 320 are both in an off state when they are not affected by an electrostatic discharge event. When an electrostatic discharge positive voltage is generated on the connection pad 301 with respect to one of the ground terminals 395 and is transmitted to the source of the second transistor 31〇, the second transistor 310 is turned on by the floating terminal, and the electrostatic discharge positive voltage is The gate electrode is transferred to the gate of the first transistor 305 as a control signal to maintain the first transistor 305 in an off state, so that the positive discharge positive voltage is isolated by the first transistor 305 to prevent damage to the internal circuit 380. . When an electrostatic discharge negative voltage occurs with respect to one of the ground terminals 395 and is transmitted to the source of the first transistor 305, the first transistor 305 remains in the off state, so the electrostatic discharge negative voltage is The first transistor 305 is isolated to avoid damage to the internal circuitry 380. In addition, when the electrostatic discharge voltage occurs at the power supply terminal 390, it is isolated by the gate oxide layer of the fourth transistor 320 and the first transistor 305, and cannot affect the internal circuit 380' when the electrostatic discharge voltage occurs at the ground terminal 395. By the isolation of the first transistor 3〇5 and the second transistor 310, the electrostatic discharge voltage of 13 200921888 is also unlikely to affect the internal circuit 38〇. Referring to Fig. 4', Fig. 4 is a circuit diagram showing a second embodiment of the electrostatic discharge avoiding circuit of the integrated circuit _ input terminal according to the present invention. The integrated circuit 400 includes a connection pad 3 (H, a first transistor 3〇5, an electrostatic discharge detector 370, a fifth transistor 425, a resistor 426, and an internal circuit 380. The static electricity of FIG. The discharge avoidance circuit includes a first transistor 3〇5, a fifth transistor 425, a resistor 426, and an electrostatic discharge device 37. The electrostatic discharge detector 370 includes a second transistor 31〇, a third transistor 315, A fourth transistor 320 and a resistor 32 have a light source coupled to a source of the connection pad 301, coupled to the internal circuit 38 - a drain, a gate, and a light source One of the ends of the terminal 390 is replaced with a well. The fifth transistor 425 has a source that is coupled to the connection 塾3〇1, which is integrated into the internal circuit 380, and is integrated with the resistance gamma, and The fifth transistor milk system is connected to the grounding terminal 395. The fifth transistor milk system is a thick-closed oxide layer-type N-type gold emulsion half-field effect transistor. The function of the fifth transistor milk is when the circuit is working normally. Providing a higher speed and lower resistance signal transmission path between the connection pad 301 and the internal circuit, due to the N-type recording half field effect transistor _ The channel conduction transmission speed and resistance are better than the P-type gold-oxygen half-field effect transistor. The resistor 426 is coupled between the power supply terminal and the idle electrode of the fifth transistor 425. The integrated circuit _ input terminal electrostatic discharge avoidance circuit The connection relationship of the remaining circuit components is the same as that of the integrated circuit 300' of FIG. 3. Therefore, the electrostatic discharge avoidance circuit at the input end of the integrated circuit 400 is operated during normal operation and during an electrostatic discharge event. The principle is described as follows. When the circuit is working normally, the power terminal 390 supplies the power voltage Vdd, and the ground terminal 395 is coupled to the ground potential, so the fourth transistor 320 is coupled to the power supply voltage Vdd of the power terminal 390 due to its gate. Turning on, the first transistor 305 is turned on because its gate is coupled to the ground potential via the fourth transistor 320. The fifth transistor 425 is coupled to the power supply voltage Vdd due to its gate and the channel doping well is coupled to the ground potential. Turning on, as described above, when the fifth transistor 425 is turned on, it can assist the first transistor 305 to provide a higher speed and lower resistance transmission path. When inputting a low potential signal to the company In the case of the pad 301, the low potential signal can be transmitted to the internal circuit 380 via the first transistor 305 or the fifth transistor 425, and the low potential signal is also fed back to the gates of the second transistor 310 and the third transistor 315. Therefore, the second transistor 310 is turned on and the third transistor 315 is turned off, so the gate of the first transistor 305 can also be coupled to the low potential signal via the second transistor 310. When a high potential signal is input to the connection pad 301 The high potential signal can be transmitted to the internal circuit 380 via the first transistor 305 or the fifth transistor 425, and the high potential signal is also fed back to the gates of the second transistor 310 and the third transistor 315 at the same time, thereby The second transistor 310 is turned off and the third transistor 315 is turned on, so the gate of the first transistor 305 can also be coupled to the ground potential via the 15th 200921888 triple transistor 315. Similarly, the voltage of the high-potential signal may be a voltage higher than a power-on signal of the power supply terminal V390 of the power supply terminal 390. Therefore, the connection pad 301 can be used not only as an input pad of a general logic signal but also as a signal for burning signals. The input pad, therefore, the electrostatic discharge avoidance circuit shown in Fig. 4 can also be compatible with the integrated circuit with programmable function. As described above, when an electrostatic discharge event occurs, the connection pad 301, the power supply terminal 390, and the ground terminal 395 are all in a floating state, that is, a floating end without a ground, and the floating end is substantially easily coupled to The zero potential (ground potential), so the first to fifth transistors 305, 310, 315, 320, and 425 are all in an off state when they are not affected by the electrostatic discharge event. When an electrostatic discharge positive voltage is generated on the connection pad 301 with respect to one of the ground terminals 395 and is transmitted to the source of the second transistor 310, the second transistor 310 is turned on by the floating terminal, and the electrostatic discharge positive voltage is The gate is transferred to the gate of the first transistor 305, thereby keeping the first transistor 305 in an off state, and when the positive voltage of the electrostatic discharge is transmitted to the source of the fifth transistor 425, the fifth transistor 425 is also caused The floating state of the power supply terminal 390 is maintained in an off state, so that the electrostatic discharge positive voltage is isolated by the first transistor 305 and the fifth transistor 425 to prevent damage to the internal circuit 380. When an electrostatic discharge negative voltage is generated on the connection pad 301 with respect to one of the ground terminals 395 and is transmitted to the source of the first transistor 305 and the source of the fifth transistor 425, the first transistor 305 and the fifth transistor 425 will remain in the off state, so the electrostatic discharge negative voltage is isolated by the first transistor 305 and the fifth transistor 425 16 200921888 to avoid transmission to the internal circuitry for damage. In addition, the 1 electric discharge voltage occurs at the power supply terminal or the ground terminal for 395 days. The isolation principle for the static and electric voltage is similar to the isolation principle described in the electrostatic discharge avoidance circuit of Fig. 3, and therefore will not be described again. . ^ Refer to Fig. 5, which is a circuit diagram showing a first embodiment of an electrostatic discharge protection circuit according to the input terminal of the integrated circuit of the present invention. The integrated circuit 500 includes a connection potential 5 (H, a first transistor 5〇5, an electrostatic discharge detector 570, a fifth transistor 525, and an internal circuit. The electrostatic discharge detector 570 includes a a second transistor 51A, a third transistor 515, a fourth transistor 52A, and a resistor 521. The electrostatic discharge protection circuit of FIG. 5 includes a first transistor 5〇5, a fifth transistor 525, and an electrostatic The discharge detector 570. The coupling relationship between the first transistor 5〇5 to the fourth transistor 52〇, the connection pad 5〇1, only the resistor 521 and the internal circuit 58〇 is the same as that of the integrated circuit 3 of FIG. The fifth transistor 525 has a drain coupled to one of the connection pads 501, a source coupled to the ground terminal 595, a gate coupled to the source, and a source coupled to the source. The fifth transistor 525 of the doped well is an N-type gold-oxygen half field effect transistor with a thick gate oxide layer. The function of the fifth transistor 525 is to provide an electrostatic discharge current when an electrostatic discharge event occurs. The dredging path of the electrostatic discharge protection circuit at the input end of the integrated circuit 500, during normal operation 17 200921888 When the electrostatic discharge event occurs, the circuit operation principle is respectively described as follows. When the circuit is in normal operation, the power supply terminal 590 supplies the power supply voltage Vdd, and the ground terminal 595 is coupled to the ground potential, the first transistor 505 to the fourth transistor 520. The working principle is the same as that of the first transistor 305 to the fourth transistor 320 of FIG. 3, so it will not be described again. When the low potential signal or the high potential signal is input to the connection pad 501, the fifth transistor 525 is In the wearing state, the input low potential signal or high potential signal is transmitted to the internal circuit 580 via the first transistor 505. When a negative voltage pulse occurs in the connection pad 50, the negative voltage pulse can be The fifth transistor 525 is parasitic diode and is connected to the ground terminal 595. That is, the fifth transistor 525 can dredge the negative voltage pulse generated on the connection pad 501 to the ground terminal 595 during normal operation. The negative voltage pulse wave is not transmitted to the internal circuit 580. It is particularly noted that the voltage of the high potential signal described above may also be a voltage of a programming signal higher than the power supply voltage Vdd of the power supply terminal 590. Therefore, the connection pad 501 can be used not only as an input pad for general logic signals, but also as an input pad for programming signals. Therefore, the ESD protection circuit shown in FIG. 5 can be compatible with an integrated circuit having a programmable function. As described above, when an electrostatic discharge event occurs, the connection pad 501, the power supply terminal 590, and the ground terminal 595 are in a floating state, that is, a floating terminal having no ground, and the floating terminal is substantially easily coupled to Zero potential (ground potential), so the first to fifth transistors are in an off state when they are not affected by the electrostatic discharge event. When one of the electrostatic discharges 18200921888 is generated on the connection pad 501 with respect to one of the ground terminals 595, The electrostatic charge accumulated in the connection pad 501 can be dredged to the ground terminal 595 via the parasitic diode formed by the drain N-type doping region and the P-type doping well of the fifth transistor 525, or when the fifth When the transistor 525 is unable to dredge the electrostatic charge in time, the electrostatic discharge negative voltage is transmitted to the source of the first transistor 505, so that the first transistor 505 is kept in the off state, so the electrostatic discharge negative voltage is first Crystal 505 is transmitted to the isolation in order to avoid damage to the internal circuit 580. When a positive discharge positive voltage with respect to one of the connection pads 501 occurs at the ground terminal 595 and is transmitted to the gate of the first transistor 505 via the second transistor 510 (P-type MOS field-effect transistor), it can be maintained. The first transistor 505 is in an off state, so the positive discharge positive voltage is isolated by the first transistor 505 to avoid transmission to the internal circuit 580 causing damage. As for when an electrostatic discharge voltage occurs at the power supply terminal 590 or the ground terminal 595, the isolation principle of the first to fourth transistors to the electrostatic discharge voltage is similar to the isolation principle explained in the electrostatic discharge avoidance circuit of FIG. 3, so Narration. It can be seen from the above that the electrostatic discharge protection circuit shown in FIG. 5 can not only be compatible with the integrated circuit with programmable function, but also has the function of isolating the electrostatic discharge voltage and dredging the electrostatic discharge current, so that the internal product of the chip can be provided. A more reliable electrostatic discharge protection mechanism for the body circuit. Please refer to FIG. 6. FIG. 6 is a circuit diagram showing a second embodiment of an ESD protection circuit at the input end of the integrated circuit 600 according to the present invention. 19 200921888 The integrated circuit 60A includes a connection pad 601, a first transistor 605, an electrostatic discharge detector 670, a fifth transistor 625, a sixth transistor 63A, a seventh transistor 635, An eighth transistor 64A, a ninth transistor 645, an internal circuit 680, a power clamping circuit 685, and a resistor 636. The electrostatic discharge protection circuit of FIG. 6 includes a first transistor 6〇5, a fifth transistor 625, a sixth transistor 63〇, a seventh transistor 635, an eighth transistor 64〇, a ninth transistor 645, and a resistor. 636, a power clamp circuit 685 and an electrostatic discharge detector 670. The ESD detector 67A includes a second transistor 61A, a third transistor 615, a fourth transistor 62A, and a resistor 621. A power clamp circuit 685 is coupled between the power supply terminal 69A and the ground terminal 695. The eighth transistor 640 has a source coupled to the power supply terminal 69, coupled to one of its 'primary-channel doped wells, coupled to the internal circuit 680--no-pole, and-gate, eighth transistor The 640 series is a - Ρ type gold oxide half field effect transistor. The ninth transistor (4) has a source coupled to the ground terminal 695, is coupled to one of its source channel doping wells, is coupled to the internal circuit 680-dip, and is adapted to the eighth transistor _ The gate of the gate, the ninth transistor 645 is a (four) gold oxide half field effect transistor. The first transistor 605 has a source that is coupled to one of the source pads of the connection pad, and is coupled to the pole between the first body 640, coupled to one of the electrostatic discharge detectors (4), and is coupled to Power terminal _ - channel doping well, first - transistor 6 〇 5 series ':, ', Ρ type gold emulsion half field effect transistor. The seventh transistor 635 has a drain connected to the gate of the connection pad _ the source is coupled to the gate of the first transistor, and is coupled to the ground of the resistor 20, 200921888, and the handle is grounded. The channel doping and the second crystal 635 of the terminal 695 are -N type gold oxide half field effect transistors. The resistor 636 is coupled between the power supply terminal 690 and the gate of the seventh transistor 635. The second transistor 610 has a source that is coupled to one of the connection pads 〇1, a channel-doped well that is coupled to its source, and a shank that is coupled to the gate of the eighth transistor. A dipole that is coupled to the pole between the first and second transistors 605, and the second transistor pair is a p-type gold-oxygen half field effect transistor. The third 615 is drawn to the source of a grounding terminal 695, and is integrated with one of the source channel doping wells, and is engaged with the eighth transistor = the gate of the gate of the gate - and is consumed by the first A closed pole of a transistor 6〇5, and a second transistor 615 is an N-type metal oxide half field effect transistor. The fourth transistor 620 has a source coupled to a ground terminal 695, is immersed in the source of the if-doped well, is consumed by one of the resistors, and is coupled to the first transistor 605. A drain of the gate, the fourth transistor 62 is an N-type gold oxide half field effect transistor. A resistor 621 is coupled between the power supply terminal 690 and the gate of the fourth transistor 62A. In a preferred embodiment, the fourth transistor 620 is a gold oxide half field effect transistor with a thin gate oxide layer or a thick hard oxide layer, and the remaining transistor system is a gold oxide with a thick gate oxide layer. Half field effect transistor. The fifth transistor 625 has a drain coupled to one of the connection pads 601, a source coupled to the ground terminal 695 'couples one of its source gates, and a channel-doped well coupled to its source, a fifth The transistor 625 is an N-type gold oxide half field effect transistor. 21 200921888 The sixth transistor 63〇 has a drain coupled to one of the connection pads 601, a source of 69〇, coupled with its source _, electricity #5 and a well, the sixth electric day and day body gate 'nucleus Incorporating one of its sources, the channel is doped: crystal, 'p-type gold-oxygen half-field effect electricity| The integrated circuit 600 is inserted into the eight-end electrostatic discharge of the mountain and when the electrostatic discharge event occurs.濩 Circuit, under normal work. When the circuit is normal: when it is used, the principle of ft胄路卫卫 respectively describes the power supply terminal 690 for the pain and the ground terminal 095 is coupled to the connection. First, the power supply voltage Vdd, the transistor 625 and the seventh crystal The work of the Jade Japanese body 605 to the fifth electric 曰 635 is the fifth working circuit of the fifth crystal 425 transistor 505 to the fifth electric cymbal, the same as the working principle of the fifth figure. Re-bao, the Japanese body 525 and the fourth 阍 结 τ τ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ The _= state can be used to transmit the seventh transistor 635 to the internal circuit _"right-transistor 605 or when it is connected to 塾601". This positive voltage pulse can be: - positive voltage pulse - parasitic diode When the body is connected to the power supply terminal, the second transistor is connected to the second transistor (4), and the positive pulse wave can be thinned out: =, the pressure pulse wave is not transmitted to the internal circuit 68. The electric terminal is 69 〇, so that the positive electric power can be used as the fifth electric cymbal. As for the negative voltage pulse wave, one of the corpses 625 is _ ground 695. The eighth transistor is dilute to the phase circuit. Formed with the ninth transistor (4) - anti 22 200921888 In the event of an electrostatic discharge event, the connection pad 601, the power terminal 690 and the ground terminal 695 are in a floating state, so the first to ninth transistors are not subject to electrostatic discharge events. When it is affected, it is in the cutoff state. The working principle of the first transistor 605 to the fifth transistor 625 and the seventh transistor 635 is the same as that of the first transistor 505 to the fifth transistor 525 of FIG. 5 and the fifth transistor 425 of FIG. So I won't go into details. In addition, when the sixth transistor 630 is unable to dredge the electrostatic charge in time, the electrostatic discharge positive voltage is transmitted to the gate of the first transistor 605, and the control signal is used to keep the first transistor 605 in the wearing state, so The electrostatic discharge positive voltage is isolated by the first transistor 605 to avoid damage to the internal circuit 680, and the gate oxide layer of the eighth transistor 640 and the ninth transistor 645 can also prevent the internal circuit 680 from being directly affected by the electrostatic charge. And damage. The power clamp circuit 685 is conventionally used to provide electrostatic discharge current dredging between the power terminal 690 and the ground terminal 695. As can be seen from the above, the electrostatic discharge protection circuit shown in FIG. 6 provides multiple electrostatic discharge protection mechanisms. If the sixth transistor 630, the eighth transistor 640, and the ninth transistor 645 are omitted, the first transistor 605 is The drain is directly coupled to the internal circuit 680, and the source of the first transistor 605 is directly coupled to the connection pad 601. The ESD protection circuit of FIG. 6 is also compatible with the integrated circuit having a programmable function. 23 200921888 Please refer to Fig. 7'. Fig. 7 is a circuit diagram showing a first embodiment of the power supply clamp circuit of Fig. 6. As shown in Figure 7, the power supply clamping circuit 7A includes a transistor 710, a resistor 720, and a capacitor 73. The resistor 72〇 and the capacitor 73 are connected in series between the power terminal 690 and the ground terminal 695. The capacitor can be a MOS capacitor or a metal-insulator_metal (MIM). )capacitance. The transistor 71A has one of the drains coupled to the grounding end 695' coupled to one of the source terminals of the power supply terminal 69, coupled to one of the source doping wells of the source, and coupled to the connection of the resistor 720 and the capacitor 73〇. At the end of the node, the transistor 710 is a -P type MOS field effect transistor. The power clamp circuit is a well-known technique, so its working principle will not be described again. Please refer to Fig. 8. Fig. 8 is a circuit diagram showing a second embodiment of the power supply clamp circuit of Fig. 6. As shown in FIG. 8, the power supply clamp circuit _ includes a first transistor 810, a second transistor 82A, a third transistor, a resistor _, and a capacitor 850. The resistor 840 and the capacitor 85 are connected in series between the power terminal _ and the ground terminal 695, and the capacitor 8 is a MOS capacitor or a metal body. The third transistor (4) has a green junction at the power terminal _ one of the drains, is lightly coupled to the source of the ground terminal 695, is adapted to one of the source channel doping wells, and a gate 'third transistor The 83 〇 system is an N-type gold oxygen half field effect transistor. The first =: 〇 has one source of the _ source terminal (four), which is combined with the third transistor, the channel is doped, and the channel is doped, and the connection is limited to the connection of the 650 A gate of the node, the first transistor (10) is a -P Meng Lifeng% effect transistor. The second transistor gamma has a light junction with the grounding end of the milk. 200921888 - The source of the third transistor is a pole between the poles, the = channel doping well, and the first transistor is used The inter-electrode ___, the first electro-hydraulic body 820 is a -N-type metal oxide half field effect transistor. The first-transistor 820 is formed as an inverter, which is connected between the resistor _ and the capacitor coffee, that is, between the idle poles of the transistor 83 点. The power system circuit _ is a well-known technique, so its working principle will not be described again. As can be seen from the above, according to the present invention, an electrostatic discharge detector is used in a feedback circuit of the electrostatic "thief series, which is more compatible with the electric power_ship, and is compatible with the programmable circuit." According to the electrostatic discharge protection circuit of the ESD detector of the present invention, the ESD protection circuit can provide the internal product of the chip and the circuit with more reliable electrostatic discharge protection. mechanism. The above description is only the preferred embodiment of the present invention, and all scale changes and modifications made in accordance with the scope of the present invention should be covered by the present invention. [Simple description of the drawing] Fig. 1 shows the schematic diagram of the electrostatic discharge protection circuit of the input end of the conventional integrated circuit. Figure 2 shows a schematic diagram of the electrostatic discharge prevention circuit of the input terminal of the integrated circuit with programmable function. Figure 3 is a circuit diagram showing an electrostatic discharge avoidance circuit of an input terminal of an integrated circuit according to the present invention. Fig. 4 is a circuit diagram showing an example of an electrostatic discharge avoidance circuit of the circuit input terminal of the present invention. Fig. 5 is a circuit diagram showing the electrostatic discharge anti-ramming-first embodiment of the circuit specific circuit input terminal according to the present invention. Fig. 6 is a circuit diagram showing a second embodiment of the electrostatic discharge protection according to the input terminal of the invention. Fig. 6 is a circuit diagram of the first embodiment of the power supply clamp circuit of Fig. 6. Fig. 8 is a circuit diagram showing a second embodiment of a power supply clamp circuit of Fig. 6. [Main component symbol description] 100, 200, 300, integrated circuit 500 ' 600 101 105 106 107 108 110 301 > 501 111 112 601 connection pad input ESD protection circuit N-type gold oxygen half field effect transistor P-type gold oxygen Half field effect transistor input resistance input inverter 120, 380, 580, 680 internal circuit 130, 685, 700, 800 power clamping circuit 190, 390, 59Q, 690 power terminal 195, 395, 595, 695 ground terminal 26 200921888 305, 505, 605, 810 __ transistor 310, 510, 610, 820 second transistor 315, 515, 615, 830 third transistor 320, 520, 620 fourth transistor 321 > 426, 521 resistance 621 ' 636, 720, 840 425 ' 525 , 625 fifth transistor 630 sixth transistor 635 seventh transistor 640 eighth transistor 645 ninth transistor 710 transistor 730 capacitor Vdd power supply voltage 27