200919668 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種晶粒重新配置之封裝方法’特別是有關於藉由基 板上的網狀結構來進行晶粒重新配置之封裝方法。 【先前技術】 半導體的技術已經發展的相當的迅速，因此微型化的半導體晶粒(Diee) 必須具有多樣化的功能的需求，使得半導體晶粒必須要在很小的區域中配 置更多的輸入/輸出墊(I/O pads)，因而使得金屬接腳(pins)的密度也快速的 提高了。因此，早期的導線架封裝技術已經不適合高密度之金屬接腳；故 發展出一種球陣列(Ball Grid Array: BGA)的封裝技術，球陣列封裝除了有比 導線架封裝更高密度之優點外，其錫球也比較不容易損害與變形。 隨著3C產品的流行，例如：行動電話(Cell Phone)、個人數位助理(pda) 或是iPod等’都必須要將許多複雜的系統晶片放入一個非常小的空間中， 因此為解決此一問題，一種稱為「晶圓級封裝（waferlevelpackage;wu>)」 之封裝技術已經發展出來，其可以在切割晶圓成為一顆顆的晶粒之前，就 先對晶圓進行封裝。美國第5,323,051號專利即揭露了這種「晶圓級封裝」 技術。然而，這種「晶圓級封裝」技術隨著晶粒主動面上的焊墊①ads)數目 的增加，使得焊墊(pads)之間距過小，除了會導致訊號辆合或訊號干擾的問 題外，也會因為焊墊間距過小而造成封裝之可靠度降低等問題。因此，當 曰曰粒再更進一步的縮小後’使得前述的封裝技術都無法滿足。 為解決此一問題，美國第7，196,408號專利已揭露了一種將完成半導體 製程之晶圓，經過測試及切割後，將測試結果為良好的晶粒（g〇〇ddie)重 新放置於另一個基板之上，然後再進行封裝製程，如此，使得這些被重新 放置的晶粒間具有較寬關距’故可以將晶粒上的焊墊適當的分配，例如 使用橫向延伸（fanout)技術’因此可以有效解決關距過小，除了會導致 200919668 訊號搞合或訊號干擾的問題。 然而’為使半導體晶片能夠有較小及較薄的封裝結構，在進行晶圓切 割别’會先對晶圓進行薄化處理，例如以背磨（backsidei卿方式將晶 圓薄化至2 20rm卜然後再切割成一顆顆的晶粒。此一經過薄化處理之晶 粒’經過重新配置在另一基板上，再以注模方式將複數個晶粒形成一封裝 體，由於阳粒很薄，使得封裝體也是非常的薄，故當封賴脫離基板之後， 封膠體本身的應力會使得封膠體產生翹曲，增加後續進行切割製程的困難。 另外，在晶圓切割之後，要將晶粒重新配置在另一個尺寸較原來基板 ( 的尺寸還大基板時，由於需要經由取放裝置（pick & place)將晶粒吸起， 然後將晶粒翻轉後’以覆晶方式將錄之主動祕附於基板上，而在取放 裝置將晶粒翻轉的過程中，容易會產生傾斜⑽）而造成位移，例如：傾 斜超過5微米，故會使得晶粒無法對準，進而使得後續植球製程中也無法 對準，而造成封裝結構的可靠度降低。 為此，本發明除了提供一種藉由基板上配置的網狀結構並且不需將晶 粒翻轉之封裝方法’其可使每一顆要進行重新配置之晶粒能夠放置在一較 適當之範圍内，以增加封裝之精確性。 【發明内容】 有鑒於發明背景中所述之晶粒無法對準問題，本發明提供一種在基板 上預先配置網狀結構之晶粒重新配置之封裝結構及其方法，其主要目的在 提供一種可以在晶粒重新配置的過程中，藉由基板上配置的網狀結構來對 準之封裝結構及其方法，可有效提高製造之良率及可靠度。 本發明之另一主要目的在提供一種晶粒重新配置之封裝方法中，係將 晶粒之主動面朝上，故不需要將晶粒翻轉，其除了可以提高晶粒重新配置 之精確性外，還可以使用較便宜的取放設備，故還可降低製造之成本。 6 200919668 本發明之另-主要目的在提供一種晶粒重新配置之封裝方法，其可以 將12片晶圓所切割出來的晶粒重新配置於8时晶圓之基板上，如此可以有 六，用8 f日日圓之即有之封裝設備而無需重新設立12时晶圓之封裝設 備’可以降低12时晶圓之封裝成本。 …本發明之還有—主要目的在提供—種晶粒重新配置之封裝方法，使得 進行封裝的θ日片都是，，已知是功能正常之晶片，，g。。^此），可以節 省封裝材料，故也可以降低製程之成本。 根據以上所述，本發明揭露一種晶粒重新配置之封裝方法，包括:提供 第-基板’在第—基板上配置—峨結構；提供複數個晶粒，每—晶粒具 有一主動Φ及-下表面，且於絲面±配置#複數個雜；取放複數個晶 粒，第-基板上，係將每—晶粒之下表面配置於峨結構之每—區塊中， 且每-晶=與每—區塊之間具有—間隔；貼附第二基板，於第二基板上配 置有-黏著層’係將第二基板上之黏著層貼附在第—基板上之複數個晶粒 之主動面上；脫離第—基板及網狀結構，以曝露出每—晶粒之下表面；形 成一高分t材料層’㈣包覆每—晶粒且填滿於每—晶粒與每—區塊之間 隔中；覆蓋-模具袭置’用以平坦化高分子材料層，使得高分子材料層充 滿在複數個晶粒之間，且包覆每脫賴具裝置，用鱗露出高分 子材料層之表面，然剝除第二基板及黏著層’以曝露出每一晶粒之主動 面^每-晶粒上之複數卿墊’以形成—封膠體；形成複數條扇出之金屬 線段:其中複數條金屬線段之—端與複數個焊墊電性連接；形成一保護層， 以覆蓋每-晶粒之絲面及每-金屬線段，並曝露出每—金屬線段^另一 端之-表面；形紐數織性連接元件，翁複數個紐連接元件盘已曝 露之複數條金屬線段的另一端電性連接；及切割封膠體，以形成複數個各 自獨立之完成封裝之晶粒’其中每—晶粒之五個面均由封膠體所包覆。 本發明還提供-種晶粒重新配置之封裝結構，包括晶粒，具有一主 動面及-下表面’於主動面上配置有複數個焊塾；—封膠體，用以包覆晶 200919668 _ #/且曝露出晶粒之主動面上之複數個详墊；複數條扇出之金屬 線段，其母-金屬線段之-端與複數個焊墊電性連接；—保護層 晶粒之主動面及複數條金屬線段，並曝露出複數條金屬線段之另—端之一 上表面；及複數個電性連接元件與複數條金屬線段之另-端電性連接。一 有關本發明的特徵與實作，合圖示作最佳實施例詳細說明如下。 j為使對本發·目的、構造、特徵 '及其魏有進—步的瞭解，兹配合 實施例詳細說明如下。） -σ 【實施方式】 本發明在此所探討的方向為—種晶粒重新配置之封裝方法，將複數個 晶粒重聽置㈣-基板上’紐進行縣财法。為了能職地瞭解本 發明’將在下列的描述中提出詳盡的步驟及其組成。齡地，本發明的施 行並未限定晶片堆疊的方式之技藝者所熟習的特殊細節。另—方面，眾所 周知的晶片軸方式以及晶>{薄化等後段製程之詳細步觀未描述於細節 中，，避免造成本發明不必要之限制。然而，對於本發明的較佳實施例， 則會詳細描述如下’錢除了這些詳細描述之外，本發明還可以廣泛地施 行在其他的實施射，且本發·觸衫蚊，細錢的專利範圍為 準。 在現代的半導體封裝製程中，均是將一個已經完成前段製程（加故咖 Process) (wafer) ^4¾ (Thinning Process)， 的厚度研磨至2〜20 mil之間；然後，進行晶p_ss) & 形成-顆顆的晶粒；織，使用取放裝置（piekandplaee)將—顆顆的晶粒 逐-放置於另-個基板1GG上’如第i圖所示。很明顯地，基板上的晶粒 間隔區域比晶粒110大，因此’可以使得這些被重新放置的晶粒nG間具有 較寬的間距，故可崎晶粒11G上的焊㈣當的分配。此外，本實施例所使 用的封裝方法’可以將12忖晶圓所切割出來的晶粒11〇重新配置於8叶晶 200919668 圓之基板1GG上，如此可以有效 8 4晶圓之即有之封裳設備，而無需 重新没立12忖晶圓之封裝設備，可以降低12对晶圓之封裝成本'然後要 強漏是’本發明之實施例並未限定使用8忖晶圓大小之基板，其只要能 提供承載的穩者’例如：玻璃、石英、喊、電路域金朗板（㈣ 等’均可作為本實糊之基板，@此基板_狀也未加以限制。 參考第2A圊，係表示在基板上配置有網狀結構之俯視圖以及第2B圖 係表示根據第2A圖之AA線段剖面之剖面示意圖。如第2A圖所示，係提 供-第-基板1GA，在第-基板1GA上形成—網狀結構2()，此網狀結構2〇 ( 係絲將第-基板1GA區分成複數個同樣大小之區塊21()，如第二B圖所 不，以便藉由網狀結構20的相對位置來提高晶粒重新配置時的準確性。 接著，如第3圖所示，當晶圓被切割成複數顆晶粒31〇後，並將每一 顆晶粒310的主動面朝上；接著，使用取放裝置（未於圖中顯示）由主動 面將每-顆晶粒310吸起並放置於第—基板赢上；由於，每—顆晶粒3〇 的主動面上均配置有複數個焊墊32〇，因此，取放裝置可以直接辨識出每一 顆晶粒310其主動面上的焊墊32〇位置；當取放裝置要將晶粒31〇放置於 第-基板lOAJi時’可以再藉由第一基板1〇A上的參考點（未於圖中顯示） I 以及網狀結構2G的相對位置’將晶粒31G精媒地放置於第-基板1()A上由 網狀結構20所形成之複數個區塊210内，而每一晶粒31〇與網狀結構2〇 之間具有-間隔130，其間隔可以選擇小於1〇密爾(mil)(即25〇微米），如 第3圖所示。因此，當複數個晶粒31〇重新配置在第一基板i〇a上時，就 可以將晶粒210準碎地放置於第一基板1〇A上。在本具體實施例中，網狀 結構20可以由膠帶(tape)或是p〇lyimide所構成。 接著，請參考第4圖，係提供一第二基板1〇B且於第二基板1〇B上配 置有-黏著層30 ’在此黏著層3〇之材料為具有彈性之黏著材料，其可自下 列族群中選钆梦橡膠（siHe(me mbber)、梦樹脂（sm_ ）、彈性即、 多孔PU、丙烯酸橡膠（aciylic mbber)及晶粒切割滕。接著，係將第二基 9 200919668 板10B之具有黏著層30之表面與第一基板上之複數個晶粒3i〇之主動 面貼合，如第5圖所示。贿，脫離[基板嫩與網狀結構2G，以曝露 出複數個晶粒310之下表面，其中可將第二基板1〇拉起，且貼附於黏著層 30上之複數個晶粒31〇會由第一基板1〇A上之網狀結構2〇之間脫離而曝露 出複數個晶粒310之下表面，如第6圖所示。 接下來，請參考第7圖，係於第二基板1〇B及部份晶粒si〇之主動面 上塗佈-高分子材料層6〇,並且使用一模具裝置則將高分子材料層的壓 + ’賤得高分子㈣層6G形成—平坦化的表面，且將使得高分子材料層 Γ 60包覆每-顆晶粒31〇並填滿於每一顆晶粒310之間，如第8圖所示。而 在本實施例中，高分子材料層60可以是石夕膠、環氧樹脂、丙烯酸（aoylic)、 及苯環丁烯（BCB)等材料。 一接著，可以選擇性地對平坦化的高分子材料層6〇進行一烘烤程序，使 同/刀子材料層60固化。再接著，進行脫模程序，將模具裝置5〇〇與固化後 的高分子材料層60分離，以裸露出平坦之高分子材料層60之表面，如第9 圖所示。然後’可以選擇性地使用切割刀(未在圖中表示），在高分子材料層 的表面上形成複數條切割道6〇2，其中每一條切割道6〇2絲度為Μ— ( 密爾(mil)，而切割道602的寬度則為5至25微米。在一較佳實施例中，切 割道可以是相互垂直交錯，並且可以作為實際切#丨晶粒時的參考線。 緊接著，將高分子材料層60與黏著層3〇分離，例如將高分子材料層 60與第二基板10B 一起放入去離子水的槽(未在圖中表示)中，可以使高分 子材料層60與黏著層30分離，以形成一個封膠體，如第1〇圖所示。此封 膠體包覆每-顆晶粒遍的五個面，且曝露出每一顆晶粒si〇的主動面上 之複數個焊φ 320。由於封膠體之相對於晶粒sl〇之主動面的表面上有複數 條切割道602，因此’當高分子材料層6〇與第二基板1〇B剝離後，封膠體 上的應力會藉由這些切割道6〇2所形成的區域所抵消，故可有效地解決封 膠體趣曲的問題。 200919668 接著，請繼續參考如第11圖至第η圖，係表示在娜體之每-晶粒 31〇的複數個焊塾32〇上形成扇出（加⑽）之金屬線段％之步驟示音圖。 如第U圖所示，利用半導體製程，在每一晶粒31〇之主動面上形成一具有 圖案化U護層40，其步驟包括洗形成—層第_保護層⑼在每一晶 粒3U)之絲面及娜體之—表面上；軸—圖案化之絲層(未在圖中表 不)在第-保護層40上以移除部份第一保護層4〇以曝露出每一晶粒 31〇之複數個焊塾32〇，如第u圖所示。接著，在確定每一晶粒·的複數 個焊塾320位置後，接著，即可使用傳統的重佈線製程（Re-Layer ; RDL) 於晶粒 310 的複數個焊塾 32〇 上形成複數個扇 出之金屬線段 5〇，,其中每一金屬線段50之一端與焊塾320電性連接，如帛12圖所示， 其形成步驟包括洗形成-金屬層(未在圖中表示)在第 所曝露之焊塾咖形成-瞧化之光阻層(未在圖中表示)在金屬層上真= 刻以移除部份金屬層’以形成複數個扇出之金屬線段％。接著，以半導體 製程於金屬線段5G上形成-第二保護層42，如第13騎示，並於每一個 金屬線段50之另-端上形成複數個開口（〇pening)，如第14圖所示。最後， 再於每-開π上形成複數料電猶7G，以便作為晶粒3ω對外電性連接 之接點，其中，此導電元件7〇可以是金屬凸塊扣祕ump)或是錫麵施 ^)。然後，即可對封膠體進行最後的切割，以形成—顆顆完成封裝製程之 晶粒’如第15A圖所示。在此要強調的是，產生扇出結構之金屬線段％並 非僅限辦傳統的重祕餘，其只魏藉由轉體製郷 方法，均為本發明之實施方式；同時，制半導體製_成扇出賴之方 法已為習知技術’故本發明不加以詳細敘述，崎免產生不必要之限制。 …在上述實關巾，舰平坦化的高分子制層⑼的枝可以選擇使用 注模方式(molding process)來形成。此時，將一模具裝置5〇〇先覆蓋至第二 基板10B上，此時，可以使模具裝置5〇〇與晶粒31〇之間保持一处間，: 後再進行賴製程，將高好材料層⑼，例如環_職封材^啊 11 200919668BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of packaging a crystal grain re-arrangement, particularly to a packaging method for grain re-arrangement by a mesh structure on a substrate. [Prior Art] The technology of semiconductors has been developed quite rapidly, so the miniaturized semiconductor die (Diee) must have a variety of functional requirements, so that the semiconductor die must be configured with more inputs in a small area. / Output pads (I/O pads), thus increasing the density of metal pins. Therefore, the early lead frame packaging technology is not suitable for high-density metal pins; therefore, a ball grid array (BGA) packaging technology has been developed. In addition to the higher density than the lead frame package, the ball array package has the advantages of higher density than the lead frame package. Its tin ball is also less susceptible to damage and deformation. With the popularity of 3C products, such as: Cell Phone, personal digital assistant (PDA) or iPod, you have to put many complicated system chips into a very small space, so to solve this one The problem, a packaging technology called wafer level package (wafer level package; wu >), has been developed to package wafers before they are diced into individual dies. This "wafer level packaging" technology is disclosed in U.S. Patent No. 5,323,051. However, this "wafer-level packaging" technology increases the number of pads (pads) on the active surface of the die, so that the distance between the pads is too small, in addition to the problem of signal integration or signal interference. There is also a problem that the reliability of the package is lowered because the pitch of the pads is too small. Therefore, when the granules are further reduced, the aforementioned packaging techniques are unsatisfactory. In order to solve this problem, U.S. Patent No. 7,196,408 discloses a wafer that will complete a semiconductor process. After testing and cutting, the test result is a good grain (g〇〇ddie) placed in another Above the substrate, the encapsulation process is then performed so that the repositioned dies have a wider separation distance so that the pads on the dies can be properly dispensed, for example using a fanout technique. It can effectively solve the problem that the distance is too small, except that it will cause the 200919668 signal to be engaged or signal interference. However, in order to enable semiconductor wafers to have smaller and thinner package structures, wafers can be thinned first, such as back grinding, which is thinned to 2 20 rm. Then, it is cut into individual crystal grains. The thinned crystal grains are reconfigured on another substrate, and then a plurality of crystal grains are formed into a package by injection molding, because the positive particles are thin. Therefore, the package is also very thin, so after sealing off the substrate, the stress of the sealant itself causes warpage of the sealant, which increases the difficulty of subsequent cutting process. In addition, after the wafer is cut, the die is to be processed. Re-arranged in another size larger than the original substrate (the size of the substrate is larger, due to the need to pick up the die via the pick & place, then flip the die, then the flip-chip will be recorded actively The secret is attached to the substrate, and during the process of flipping the die to the pick-and-place device, the tilt (10) is liable to cause displacement, for example, the tilt is more than 5 micrometers, so that the crystal grains cannot be aligned, thereby In the subsequent ball processing process, the alignment cannot be aligned, and the reliability of the package structure is reduced. To this end, the present invention provides a packaging method by using a mesh structure disposed on a substrate without flipping the die. Each of the dies to be reconfigured can be placed in a more appropriate range to increase the accuracy of the package. SUMMARY OF THE INVENTION In view of the problem of grain misalignment described in the background of the invention, the present invention provides a A package structure and a method for pre-configuring a mesh structure of a mesh structure on a substrate, the main purpose of which is to provide a package that can be aligned by a mesh structure disposed on a substrate during die rearrangement. The structure and the method thereof can effectively improve the yield and reliability of the manufacturing. Another main object of the present invention is to provide a method for encapsulating a crystal grain in which the active side of the crystal grain faces upward, so that the crystal is not required. In addition to improving the accuracy of grain reconfiguration, it can also use cheaper pick and place equipment, which can also reduce the cost of manufacturing. 6 20091966 8 Another object of the present invention is to provide a method for packaging a die re-arrangement, which can reconfigure the die cut by 12 wafers on the substrate of the 8 o'clock wafer, so that there are six, 8 F-days of the packaged equipment without the need to re-establish the 12-hour wafer packaging equipment' can reduce the packaging cost of the 12-hour wafer. ... The present invention is also - the main purpose is to provide a package for chip reconfiguration The method is such that the θ-day film for packaging is, and is known to be a functioning wafer, g..), the packaging material can be saved, and the cost of the process can also be reduced. According to the above, the present invention discloses a method for packaging a die re-arrangement, comprising: providing a first substrate 'on the first substrate--a structure; providing a plurality of crystal grains, each of the crystal grains having an active Φ and - The lower surface, and the surface of the wire ± configuration # a plurality of impurities; pick and place a plurality of grains, on the first substrate, the surface of each of the grains is arranged in each block of the structure, and each crystal Between the block and the block, the second substrate is attached, and the adhesive layer is disposed on the second substrate, and the adhesive layer on the second substrate is attached to the plurality of crystal grains on the first substrate. The active surface; the first substrate and the mesh structure are removed to expose the lower surface of each of the grains; a high-division t material layer is formed '(4) to coat each of the grains and fill each of the grains and each - the interval between the blocks; the cover-mold attack' is used to planarize the polymer material layer so that the polymer material layer is filled between the plurality of crystal grains, and each of the detaching device is coated, and the polymer is exposed by the scale The surface of the material layer is stripped of the second substrate and the adhesive layer to expose each of the grains The moving surface ^each of the plurality of crystal pads on the die to form a sealant; forming a plurality of fan-out metal segments: wherein the ends of the plurality of metal segments are electrically connected to the plurality of pads; forming a protective layer, Covering the surface of each of the grains and each of the metal segments, and exposing the surface of each of the other ends of the metal segments; the shape of the number of the woven connecting elements, the plurality of metal elements of the plurality of connecting elements The other end of the line segment is electrically connected; and the encapsulant is cut to form a plurality of separate independent finished crystal grains, wherein each of the five faces of the die is covered by the sealant. The present invention also provides a package structure for grain reconfiguration, comprising a die having an active surface and a lower surface configured with a plurality of solder fillets on the active surface; a sealant for coating the crystal 200919668 _# And exposing a plurality of detailed pads on the active surface of the die; a plurality of fan-out metal segments, the ends of the mother-metal segments are electrically connected to the plurality of pads; the active surface of the protective layer die a plurality of metal segments and exposing an upper surface of the other end of the plurality of metal segments; and the plurality of electrical connecting members are electrically connected to the other ends of the plurality of metal segments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The features and implementations of the present invention are described in detail as a preferred embodiment. j is a detailed description of the present invention, the purpose, the structure, the characteristics, and the Wei, and the following examples. - σ [Embodiment] The present invention is directed to a method of encapsulating a crystal grain re-arrangement, in which a plurality of crystal grains are re-listed on a (four)-substrate on a substrate. In order to be able to understand the present invention, detailed steps and their compositions will be set forth in the following description. Age, the implementation of the present invention does not define the specific details familiar to those skilled in the art of wafer stacking. On the other hand, the well-known wafer axis mode and the detailed steps of the thinning process, such as thinning, are not described in detail to avoid unnecessary limitations of the present invention. However, for the preferred embodiment of the present invention, the following description will be described in detail. In addition to the detailed description, the present invention can be widely applied to other implementations, and the patent of the hair, the mosquito, and the fine money. The scope shall prevail. In the modern semiconductor packaging process, the thickness of a completed front-end process (wafer) ^43⁄4 (Thinning Process) is ground to 2~20 mil; then, the crystal p_ss) & Forming-grained grains; weaving, using a piekandplaee to place the grains of the particles one by one on the other substrate 1GG' as shown in Fig. i. It is apparent that the grain spacer regions on the substrate are larger than the crystal grains 110, so that a wider pitch between the repositioned crystal grains nG can be made, so that the solder (4) on the chip 11G can be distributed. In addition, the packaging method used in the present embodiment can reconfigure the die 11 切割 cut by the 12-inch wafer on the substrate 1GG of the 8-leaf 200919668 circle, so that the wafer can be effectively sealed. It is possible to reduce the packaging cost of 12 pairs of wafers without having to re-package the 12-inch wafer packaging device. Then, the embodiment of the present invention does not limit the use of a substrate having an 8-inch wafer size. As long as it can provide the stability of the load, for example: glass, quartz, shouting, circuit domain Jinlang board ((4), etc. can be used as the substrate of the real paste, @this substrate_ shape is also not limited. Refer to Section 2A, A plan view showing a mesh structure on a substrate, and a second block view showing a cross-sectional view of a cross section taken along line AA of FIG. 2A. As shown in FIG. 2A, a first substrate 1GA is provided on the first substrate 1GA. Forming a mesh structure 2(), the mesh structure 2〇 (the wire divides the first substrate 1GA into a plurality of blocks 21 of the same size, as shown in the second B, so as to be by the mesh structure The relative position of 20 to improve the accuracy of the die reconfiguration. As shown in FIG. 3, after the wafer is cut into a plurality of crystal grains 31, and the active surface of each of the crystal grains 310 faces upward; then, using a pick and place device (not shown) The active surface sucks up and deposits each of the crystal grains 310 on the first substrate; since each of the active surfaces of the three crystal grains is provided with a plurality of pads 32 〇, the pick-and-place device can directly The position of the pad 32 主动 on the active surface of each die 310 is recognized; when the pick-and-place device is to place the die 31 于 on the first substrate 10AJi, the reference on the first substrate 1A can be used again. Point (not shown in the figure) I and the relative position of the mesh structure 2G' are placed in the plurality of blocks 210 formed by the mesh structure 20 on the first substrate 1 (A). And each of the 31 〇 and the mesh 2 〇 has a spacing 130, the interval of which may be selected to be less than 1 mil (ie 25 μm), as shown in Fig. 3. Therefore, when plural When the die 31 is reconfigured on the first substrate i〇a, the die 210 can be placed on the first substrate 1A in a quasi-fragment manner. The mesh structure 20 may be composed of a tape or a p〇lyimide. Next, referring to FIG. 4, a second substrate 1B is provided and an adhesive layer is disposed on the second substrate 1B. 30 'The material of the adhesive layer 3 is an elastic adhesive material, which can be selected from the following groups: siHe (me mbber), dream resin (sm_), elastic, porous PU, acrylic rubber (aciylic) Mbber) and die-cutting. Next, the surface of the second substrate 9 200919668 plate 10B having the adhesive layer 30 is bonded to the active faces of the plurality of crystal grains 3i on the first substrate, as shown in FIG. . Bribe, detached from the [substrate and mesh structure 2G] to expose the lower surface of the plurality of crystal grains 310, wherein the second substrate 1〇 can be pulled up, and the plurality of crystal grains 31 attached to the adhesive layer 30〇 The lower surface of the plurality of crystal grains 310 is exposed by being separated from the mesh structure 2A on the first substrate 1A, as shown in FIG. Next, please refer to FIG. 7 to apply a polymer material layer 6〇 on the active surface of the second substrate 1〇B and a part of the die si〇, and use a mold device to laminate the polymer material layer. The pressure + '贱 polymer (4) layer 6G forms a flattened surface, and will cause the polymer material layer Γ 60 to coat each of the crystal grains 31〇 and fill each of the crystal grains 310, as in the first Figure 8 shows. In the present embodiment, the polymer material layer 60 may be a material such as Shiqi gum, epoxy resin, aoylic, and benzocyclobutene (BCB). Thereafter, the planarized polymer material layer 6 can be selectively subjected to a baking process to cure the same/knife material layer 60. Next, a mold release process is performed to separate the mold unit 5 from the cured polymer material layer 60 to expose the surface of the flat polymer material layer 60 as shown in Fig. 9. Then, a cutting blade (not shown) can be selectively used to form a plurality of dicing streets 6 〇 2 on the surface of the polymer material layer, wherein each scribe line has a filament of 6 〇 2 (Mil (mil), and the width of the scribe line 602 is 5 to 25 microns. In a preferred embodiment, the scribe lines may be vertically staggered with each other and may serve as a reference line when the dies are actually cut. The polymer material layer 60 is separated from the adhesive layer 3, for example, the polymer material layer 60 and the second substrate 10B are placed together in a bath (not shown) of deionized water, so that the polymer material layer 60 can be The adhesive layer 30 is separated to form an encapsulant, as shown in Fig. 1. The encapsulant covers the five faces of each of the crystal grains and exposes the active surface of each of the crystal grains si〇 a plurality of welds φ 320. Since the sealant has a plurality of dicing streets 602 on the surface of the active surface relative to the die sl〇, the sealant is removed after the polymer material layer 6〇 and the second substrate 1〇B are peeled off. The upper stress is offset by the area formed by these scribe lines 6〇2, so it is effective Solve the problem of the sealant fun. 200919668 Next, please continue to refer to the 11th to the ηth figure, which means that a fan-out (plus (10)) is formed on each of the 32-inch multiple dies 32〇 of the crystal body. Step-by-step diagram of the metal segment %. As shown in FIG. U, a patterned U-layer 40 is formed on the active surface of each die 31 by a semiconductor process, the steps of which include a wash-layer _ protective layer (9) on the surface of each of the 3U) filaments and the surface of the body; the axis-patterned silk layer (not shown in the figure) on the first protective layer 40 to remove parts A protective layer 4〇 exposes a plurality of solder bumps 32〇 of each of the crystal grains 31〇, as shown in FIG. Then, after determining the positions of the plurality of pads 320 for each die, a plurality of pads 32 〇 of the die 310 can be formed using a conventional rewiring process (RDL). a fan-out metal wire segment 5〇, wherein one end of each metal wire segment 50 is electrically connected to the solder bump 320, as shown in FIG. 12, the forming step of which comprises forming a metal layer (not shown) The exposed solder enamel-formed photoresist layer (not shown) is stamped on the metal layer to remove portions of the metal layer to form a plurality of fan-out metal segments. Next, a second protective layer 42 is formed on the metal line segment 5G by a semiconductor process, as shown in FIG. 13, and a plurality of openings are formed on the other end of each metal line segment 50, as shown in FIG. Show. Finally, a plurality of materials 7G are formed on each of the openings π to serve as a contact for the external connection of the die 3ω, wherein the conductive member 7〇 can be a metal bump buckle or a tin surface. ^). Then, the final dicing of the encapsulant can be performed to form a granule that completes the encapsulation process as shown in Fig. 15A. It should be emphasized here that the % of the metal segment that produces the fan-out structure is not limited to the traditional secrets. It is only the embodiment of the present invention by means of the transfer system. At the same time, the semiconductor system is formed. The method of fanning out is already a well-known technique. Therefore, the present invention will not be described in detail, and the exemption imposes unnecessary restrictions. ... In the above-mentioned solid towel, the branch of the polymer layer (9) in which the ship is flattened can be formed by using a molding process. At this time, a mold device 5 is firstly covered on the second substrate 10B. At this time, the mold device 5〇〇 and the die 31〇 can be kept in one place, and then the process is performed, which is high. Good material layer (9), such as ring _ job sealing material ^ ah 11 200919668
Molding Compound; EMC)注入模具裝置500與晶粒310的空間中，使得高 分子材料層60形成一平坦化的表面，以使高分子材料層6〇包覆每一顆晶 粒310並填滿於晶粒31〇之間。由於，使用注模方式之後的製造過程與前 述方式相同，故不再贅述之。 此外，在本發明之實施例中，為了增加整個封裝結構之散熱效率，可 以進一步地在晶粒310的背面再係形成一散熱裝置9〇，如散熱鰭片（『in)， 特別要強調的是，本實施例中的每—晶粒之背面雖被高分子材料所包覆， ，其背面可以控制在非常薄的厚度，例如：小於inim ;甚至可以將模具與 晶粒的背面接觸在—起，使得每—晶粒之f面曝露。_，盖論每一 曰署曰^之背面是碰高分子材料包覆，本發明均可在晶粒3G㈣面i散孰裝 置〇之間是經由-導電膠80來將散熱裝置90固接在晶粒3〇的背面上。 明，樹施例揭露如上，繼非用以限定本發 之更動細ιΓ 视縣發明讀神域_，當可作些許 範圍所界:者為Ϊ此本發明之專利保護範圍須視本說明書所附之申請專利 【圖式簡單說明】 第1圖係表錢前技術之示意圖； 第2Α圖’係表不在第—基板上具有—網狀結構之俯視圖； 第2Β圖係表示根據第2Α圖之ΑΑ線段剖面之截面示意圖； 圖第3圖至第14辭嫌據本發明之晶《新配置之難触之各步驟示 第Μ圖係根據本發明之完成封裝之晶粒上之示意圖；及 第15B圖係根據本發明 疋成封裝之晶粒上形絲熱裝置之示意圖。 12 200919668 【主要元件符號說明】 10A 第一基板 10B 第二基板 20 網狀結構 210 區塊 30 黏著層 310 晶粒 320 焊墊 40 第一保護層 42 第二保護層 50 金屬線段 60 高分子材料層 602 切割道 70 導電元件 80 導電膠 90 散熱裝置 100 晶圓 110 晶粒 200 黏著層 500 模具裝置 13Molding Compound; EMC) is injected into the space of the mold device 500 and the die 310, so that the polymer material layer 60 forms a planarized surface, so that the polymer material layer 6 is coated with each of the crystal grains 310 and filled up. Between the 31 〇 grains. Since the manufacturing process after the injection molding method is the same as that described above, it will not be described again. In addition, in the embodiment of the present invention, in order to increase the heat dissipation efficiency of the entire package structure, a heat dissipating device 9 such as a heat dissipating fin ("in)) may be further formed on the back surface of the die 310, in particular, Therefore, in the embodiment, the back surface of each of the crystal grains is covered by the polymer material, and the back surface thereof can be controlled to a very thin thickness, for example, less than inim; or even the mold can be in contact with the back surface of the crystal grain - As a result, the surface of each of the grains is exposed. _, cover the back of each 曰 ^ is covered with polymer material coating, the present invention can be between the die 3G (four) surface 孰 孰 device is through the - conductive adhesive 80 to fix the heat sink 90 The die 3 is on the back side. Ming, the tree example reveals the above, and is not used to limit the movement of the hair. Depending on the scope of the invention, the scope of the patent protection is subject to the scope of this patent. Patent application [simplified description of the drawings] Figure 1 is a schematic diagram of the pre-money technology; the second diagram is not a top view of the network structure on the first substrate; the second diagram is based on the second diagram. A cross-sectional view of a section of a line segment; Figure 3 to Figure 14 of the present invention, "the steps of the new configuration are shown in the drawings, which are schematic diagrams of the completed package according to the present invention; and 15B BRIEF DESCRIPTION OF THE DRAWINGS The Figure is a schematic illustration of a die-shaped filament heat device packaged in accordance with the present invention. 12 200919668 [Description of main components] 10A First substrate 10B Second substrate 20 Mesh structure 210 Block 30 Adhesive layer 310 Grain 320 Pad 40 First protective layer 42 Second protective layer 50 Metal segment 60 Polymer layer 602 cutting channel 70 conductive element 80 conductive adhesive 90 heat sink 100 wafer 110 die 200 adhesive layer 500 mold device 13