TW200915565A - Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure - Google Patents
Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure Download PDFInfo
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200915565 九、發明說明： 【發明所屬之技術領域】 本發明大體上有關於鰭式場效電晶體，更明確而言， 是有關於一種具有藉由一導體（例如金屬石夕化物）來合併多 個鰭片的鰭式場效電晶體。 【先前技術】 電晶體的設計持續地改良與革新，不斷創造出多種不 同型式的電晶體。已研發出多閘極式的非平面金屬氧化物 半導體場效電晶體，包括雙閘極鰭式與三閘極鰭式場效電 晶體，以提供比平面式電晶體具有更快驅動電流及較小短 通道效應的裝置。 雙閘極鰭式場效電晶體是一種通道區位在半導體鰭片 中央處内的場效電晶體（F E T)。源極區與〉及極區則分別位在 通道區兩側上的鰭片相反兩端中。閘極通常形成在與通道 區對應的薄半導體鰭片各側上。「鰭式電晶體（finFET)」通 常是指雙閘極鰭式電晶體（dual-gate fin-type FET)，在此種 電晶體中，鰭片因為太薄而造成完全空乏。鰭片的高度決 定有效的鰭片寬度，例如粗短型鰭片（short wide fin)可能 造成通道部分空乏。對於鰭式電晶體，鰭片厚度約為四分 之一閘極長度（或更小）可確保壓制住有害的短通道效應， 例如臨界電壓變異性以及過大的汲極漏電電流。在授與Hu 等人的美國專利64 1 3 802號中揭露了數種FinFET，其引用 於本文中以供參考。 200915565 三閘極鰭式場效電晶體的結構類似於雙閘極鰭式電晶 體，但其鰭片寬度與高度則大致相同，因此可以在通道區 的三個面上形成閘極，包括頂面和相反兩側壁。高度與寬 度的比值通常介於3 :2至2 :3之間，使得通道區將保持完 全空乏（fully depleted)，並且三閘極式電晶體的三方向場 效應將會提供比平面式電晶體更大的驅動電流以及改善的 短通道特性。200915565 IX. INSTRUCTIONS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to fin field effect transistors, and more specifically to a combination of a plurality of conductors (e.g., metal lithium) Fin fin field effect transistor. [Prior Art] The design of the transistor has been continuously improved and innovated, and various types of transistors have been continuously created. Multi-gate non-planar metal-oxide-semiconductor field-effect transistors, including dual-gate and three-gate fin field-effect transistors, have been developed to provide faster drive currents and smaller than planar transistors Device for short channel effects. A double-gate fin field effect transistor is a field effect transistor (F E T) with a channel location in the center of the semiconductor fin. The source region and the > and polar regions are located in opposite ends of the fins on both sides of the channel region. Gates are typically formed on each side of the thin semiconductor fins corresponding to the channel regions. "FinFET" is generally referred to as a dual-gate fin-type FET in which the fins are too thin to cause complete depletion. The height of the fins determines the effective fin width, for example, a short wide fin may cause a portion of the channel to be depleted. For fin transistors, a fin thickness of about a quarter of the gate length (or smaller) ensures that harmful short channel effects, such as threshold voltage variability and excessive drain leakage current, are suppressed. A number of FinFETs are disclosed in U.S. Pat. 200915565 The structure of a three-gate fin field effect transistor is similar to that of a double gate fin transistor, but its fin width and height are approximately the same, so that gates can be formed on three sides of the channel region, including the top surface and Opposite the two side walls. The ratio of height to width is usually between 3:2 and 2:3, so that the channel region will remain fully depleted, and the three-direction field effect of the three-gate transistor will provide a planar transistor Larger drive current and improved short channel characteristics.
可在場效電晶體結構中納入多個鰭片來進一步增加雙 閘極與三閘極鰭式電晶體的有效通道寬度。然而，當此類 場效電晶體的尺寸縮小時，驅動電流將會受到串聯電阻的 限制。 【發明内容】 有鑒於上述情形，本文中揭露一種多鰭式場效電晶體 (即，多鰭式雙閘或三閘場效電晶體）的數個實施例，在此 種電晶體中，利用高導體材料，例如金屬矽化物，將多個 鰭片部分或完全合併（merged)。合併鰭片能夠減小串聯電 阻，並且僅增加些許閘極和源/汲極區之間的寄生電容.（若 有的話）。合併半導體鰭片還允許利用單一個接觸孔 (contact via)來接觸該些合併的源/沒極區，並且提供更彈 性化的接觸孔配置方式。 更明確而言，本文揭示一種多鰭式場效電晶體的數個 實施例，例如多鰭式雙閘極場效電晶體或多鰭式三閘極場 效電晶體。 6 200915565 F E T可包含多個位在一基板上的半導體鰭片，例如至 少兩個半導體鰭片，更明確而言，是位在基板的絕緣層上。 該些半導體鰭片各自包含一頂面、相反兩側壁、兩相反端 區（即是，源極區和汲·極區）以及介在兩相反端區之間的中 央區（即，通道區）。該些半導體鰭片更可定位成彼此互相 平行且相隔一間距。此外，在每個，鰭片之端區（end regions) 的頂面和側壁上具有磊晶矽層。但是這些磊晶矽層的厚度 不會使該些鰭片合併在一起。Multiple fins can be incorporated into the field effect transistor structure to further increase the effective channel width of the dual gate and triple gate fin transistors. However, when the size of such field effect transistors is reduced, the drive current will be limited by the series resistance. SUMMARY OF THE INVENTION In view of the above circumstances, several embodiments of a multi-fin field effect transistor (ie, a multi-fin double gate or a triple gate field effect transistor) are disclosed herein, in which the utilization of the transistor is high. A conductor material, such as a metal halide, partially or completely merges the plurality of fins. Combining the fins reduces the series resistance and only increases the parasitic capacitance between the gate and the source/drain regions (if any). The merging of the semiconductor fins also allows for the contact of the combined source/no-polar regions with a single contact via and provides a more resilient contact hole configuration. More specifically, various embodiments of a multi-fin field effect transistor are disclosed herein, such as a multi-fin double gate field effect transistor or a multi-fin three gate field effect transistor. 6 200915565 F E T may comprise a plurality of semiconductor fins on a substrate, such as at least two semiconductor fins, more specifically on an insulating layer of the substrate. The semiconductor fins each include a top surface, opposite side walls, opposite end regions (i.e., source regions and germanium regions) and a central region (i.e., channel region) interposed between the opposite end regions. The semiconductor fins are more preferably positioned parallel to each other and spaced apart from each other. In addition, an epitaxial layer is provided on each of the top and side walls of the end regions of the fins. However, the thickness of these epitaxial layers does not cause the fins to merge together.
依據該場效電晶體是雙閘極場效電晶體或三閘極場效 電晶體，來改變位於中央區（即是，通道區）處之鰭片的高 寬比。例如，若是雙閘極FET，每個鰭片在通道區的高寬 比可約為4: 1或更大；若是三閘極FET，則每個鰭片在通 道區的高寬比則介於3 : 2至2 : 3之間。 閘極設置成與每個半導體鰭片位在相反兩端（源極區 和汲極區）之間的中央區（即，通道區）鄰接。同樣地，依據 該場效電晶體是雙閘極場效電晶體或二閘極場效電晶體^ 來改變閘極相對於鰭片的位置。例如，若是雙閘極FET， 閘極可設置成鄰接每個鰭片在通道區處的側壁，但是可利 用例如鰭片覆蓋層（fin cap)而與每個鰭片在通道區處的頂 面電性絕緣。若是三閘極F E T，則閘極可設置成與每個鰭 片在通道區處的側壁和頂面相鄰接。 一導體在一端上橫越且合併該些半導體鰭片，也就是 在閘極的其中一側上橫越且合併每個鰭片的源/汲極區。該 導體包括位在每個鰭片頂面上且位在相鄰鰭片間之間距中 7The aspect ratio of the fins located in the central region (i.e., the channel region) is varied depending on whether the field effect transistor is a double gate field effect transistor or a triple gate field effect transistor. For example, in the case of a dual-gate FET, the aspect ratio of each fin in the channel region can be about 4:1 or greater; in the case of a three-gate FET, the aspect ratio of each fin in the channel region is between 3: 2 to 2: 3 between. The gate is disposed adjacent to a central region (i.e., a channel region) between opposite ends (source region and drain region) of each semiconductor fin. Similarly, depending on whether the field effect transistor is a double gate field effect transistor or a two gate field effect transistor ^, the position of the gate relative to the fin is changed. For example, in the case of a dual gate FET, the gate can be placed adjacent to the sidewall of each fin at the channel region, but can be utilized, for example, with a fin cap and a top surface of each fin at the channel region. Electrical insulation. In the case of a three-gate F E T , the gate can be placed adjacent to the sidewall and top surface of each fin at the channel region. A conductor traverses on one end and merges the semiconductor fins, i.e., traverses on one side of the gate and merges the source/drain regions of each fin. The conductor is placed on the top surface of each fin and is located between the adjacent fins.
200915565 的高導體材料（例如金屬矽化物）。位在間距中的導體 可延伸達到介於一鰭片側壁和相鄰鰭片側壁之間的間 度，以合併該些鰭片。需了解到，若該些鰭片的頂面 壁上具有蟲晶碎層’則導電材料會形成在該些韓片頂 磊晶矽層上，並且延伸在介於相鄰鰭片側壁上之磊晶 之間的間距中。 相鄰鰭片之間的間距可以導體材料完全填滿，也 導體材料延伸在從基板到頂面的相鄰鰭片側壁之間， 小串聯電阻；或者也可利用導體材料來部分填充相鄰 之間的間距，也就是導體材料延伸在相鄰鰭片側壁之 但是沒有延伸至從基板到頂面的鰭片全長，以選擇性 整串聯電阻。 FET亦可包含一類似結構的導體（即是，第二導ί 該第二導體橫越且合併位在閘極相反兩側上之鰭片的 /汲極區。其可調整串聯電阻，特別是可相對於閘極另 地調整閘極一側上的電阻。因此，可推知FET結構可 對稱。 鄰接半導體鰭片的介電間隙壁可將導體與閘極電 緣開來。 文中還揭露數個形成上述多縛式雙閘極或三閘極 電晶體之方法的實施例。該些方法實施例包括提供 材，並且形成多個半導體鰭片（例如，矽鰭片）在基材 該些鰭片可更各自具有一頂面、兩相反側壁、兩相反 以及一介於兩相反端的中央區。用於雙閘極F Ε Τ時， 材料 距寬 與側 面的 矽層 就是 以減 籍片 間， 地調 ί )， 源極 一側 能不 性絕 場效 一基 上。 端區 每個High conductor material (eg metal telluride) of 200915565. The conductors in the spacing may extend to a distance between the sidewalls of a fin and the sidewalls of adjacent fins to merge the fins. It should be understood that if there are wormhole layers on the top wall of the fins, conductive materials will be formed on the top-layer epitaxial layers of the Korean fins and extended on the sidewalls of the adjacent fins. Between the spaces. The spacing between adjacent fins may be completely filled with the conductor material, and the conductor material may extend between the adjacent fin sidewalls from the substrate to the top surface, with a small series resistance; or a conductor material may be used to partially fill the adjacent regions. The spacing, that is, the conductor material extending over the sidewalls of adjacent fins but not extending to the full length of the fins from the substrate to the top surface, selectively selects the series resistance. The FET may also comprise a conductor of similar structure (ie, the second conductor traverses and merges the fin/drain region of the fin on opposite sides of the gate. The adjustable series resistance, in particular The resistance on the gate side can be adjusted separately with respect to the gate. Therefore, it can be inferred that the FET structure can be symmetrical. The dielectric spacer adjacent to the semiconductor fin can electrically connect the conductor to the gate. An embodiment of a method of forming the multi-junction double gate or triple gate transistor described above. The method embodiments include providing a material and forming a plurality of semiconductor fins (eg, fin fins) on the substrate. Each of the two can have a top surface, two opposite side walls, two opposite sides, and a central portion at the opposite ends. For the double gate F Ε , the material width and the side layer of the layer are used to reduce the size of the sheet. ί ), the source side can be ineffective. End zone
200915565 半導體鰭片之通道區部份的高寬比可約為4:1或更 於三閘極F E T時，每個半導體鰭片之通道區部份的 約介於3 :2至2 : 3之間。 形成的閘極可與每個鰭片的中央區鄰接。對於 FET，閘極可鄰接每個鰭片中央區的側壁，並且可 如一覆蓋層（cap layer)而與每個鰭片中央區的頂面 緣。用於三閘極FET時，閘極可鄰接每個半導體鰭 區的側壁和頂面。 形成與閘極鄰接的介電間隙壁，以使後續形成 與該閘極電性絕緣。可在每個鰭片兩端區的側壁和 形成磊晶矽層，但不會合併該些鰭片。因此，即使 磊晶矽層之後，仍在相鄰鰭片之間保留部分的間距 執行佈植製程，以在鰭片的相反端區中形成源極區 區。 形成源/汲極區之後，可形成一導體（即是，第· 橫越每個半導體鰭片的一端區（即是，第一端區）， 於閘極一側上的源/汲極區合併起來。此導體的形成 在每個鰭片第一端區的側壁和頂面上形成一高導體 使得導體材料位在間距中並且延伸在相鄰鰭片之間 寬度，因而讓此導體材料延伸在這些相鄰半導體鰭 之間。在形成導體的步驟中，導體材料可以完全填 鰭片之間的間距（也就是，導體材料延伸在介於相鄰 壁之間的間距寬度，並且延伸達到從鰭片頂面到基 個間距長度）以使串聯電阻減至最小；或者，導體材 大；用 高寬比 雙閘極 藉著例 電性絕 片中央 的導體 頂面上 在形成 之後， 與汲極 -導體） 以將位 可藉著 材料， 的間距 片側壁 滿相鄰 鰭片側 材的整 料可以 9 200915565 部分填充相鄰鰭片之間的間距（也就是，導體材料延伸在介 於相鄰鰭片側壁之間的間距寬度，但是不會延伸至從鰭片 頂面到基材的整個間距長度）以調整串聯電阻。 可用來形成該導體的範例技術包括執行自我對準矽化 物形成製程（即是，矽化反應製程），以在每個半導體鰭片 端區的側壁和頂面上形成金屬矽化物層。可持續執行自我 對準矽化物形成製程，直到相鄰半導體鰭片側壁上的金屬 石夕化物層合併在一起。 亦形成另一相似配置方式的導體（即是，第二導體）， 使其橫越且合併每個半導體鰭片的相反端區。形成第一與 第二導體使FET結構具有對稱性，而使閘極兩側上的串聯 電阻大致相等。然而，電晶體設計者還發現到，相較於位 在閘極相反側上的汲極來說，必須選擇性地改變位在閘極 一側上之源極中的串聯電阻。因此，可預期到，這些方法 實施例可能不會產生對稱性的FET結構。 參照下列敘述内容與附圖可更佳地了解本發明所述和 其他實施例態樣，同時本發明所顯示的實施例和各種特定 細節僅作為示範之用，並非用來限制本發明。在不偏離本 發明精神的情況下，本發明範圍還包含所有實施例的修飾 態樣。 【實施方式】 參照繪於附圖中的非限制性實施例和下述詳細内容來 說明本發明的多個實施例及其各種特徵與優點。需注意 10 200915565 到，圖中所示的特徵無須按比例繪製。並且省略對公 件與處理技術的描述，以避免讓本發明實施例變得晦 懂。文中所舉範例僅幫助了解如何實施本發明實施例 該領域中熟悉該項技術者能夠實施本發明實施例。因 該些範例不應用來限制本發明實施例的範圍。 如上所述，可藉著在場效電晶體（FET)結構中納入 鰭片來增加雙閘極與三閘極之鰭式場效電晶體的有效 寬度。然而，按比例配置FET的尺寸時，驅動電流會 串聯電阻的限制。串聯電阻主要來自矽化物與矽的接 阻。藉著增加鰭片之源/汲極區中矽化物和矽的界面面 可降低矽化物和矽之接觸電阻的影響。 參閱第1圖，藉著提高矽化物與矽之界面面積1: 降低多鰭式FET 100中之串聯電阻的技術包括在鰭片 上磊晶成長矽1 2 0直到該些鰭片合併在一起（也就是， 磊晶成長矽1 20來電性連接該些鰭片），並且隨後在頂 形成矽化物（見矽化物 160)。此技術的優點在於因為 些鰭片和矽化物1 60合併在一起，因此僅需要分別提 個接觸孔（c ο n t a c t v i a)給閘極 1 7 0兩側上的源極區和 區1 7 5。此外，接觸孔的配置更靈活。然而此技術有 缺點。其一，由於矽化物與矽的界面面積1 1 0有限， 矽化物1 6 0和通道區（即，與閘極1 7 0鄰接的鰭片中j 之間的距離相對較長，因此串聯電阻仍然相對較高。月 此技術會在閘極1 7 〇和源/汲極區1 7 5中的矽1 2 0之間 相對較高的寄生電容。 知部 澀難 而使 此， 多個 通道 受到 觸電 積， ί 0來 150 利用 面上 將該 供一 汲極 數個 並且 4區） .者’ 產生 11 200915565 參閱第2圖，藉著提高矽化物與矽之界面面積1 降低多鰭式F E T 2 0 0中之串聯電阻的另一技術還包括 片250上蟲晶成長梦220。然而’此技術並不合併該 片250，而是利用磊晶成長矽220來提高鰭片250的 和高度。在鰭片250之磊晶矽220的側壁表面和頂面 成矽化物 2 6 0，並且在每個具有矽化物的鰭片之間留 間距 2 2 1。相較於上述技術，此技術的優點在於可增 化物和矽的界面面積2 1 0，且減少矽化物2 6 0與通道 的距離，以及減少閘極2 7 0與源/汲極區2 7 5之間的寄 容。然而，此技術無法僅在閘極2 7 0的各側上僅分別 單一個接觸孔。即是，需為每個鰭片250設置各自的指 基於上述情形，本文揭露多鰭式場效電晶體（多鰭 閘極或三閘極場效電晶體）的數種實施例，在該些實 中，利用一高導體材料（例如，金屬矽化物）來合併該 鰭片。合併鰭片可以降低串聯電阻，並且僅小幅升高 和源/汲極區之間的寄生電容（若有的話）。合併半導體 還允許只利用單一個接觸孔就可接觸每個源/汲極區， 提供更彈性靈活的接觸孔配置方式。 更明確而言，參閱第3至5圖，本文揭示多鰭式 電晶體（FET)3 00的數個實施例。例如，參閱第3圖的 實施例3 0 0 a、第4圖的F E T實施例3 0 0 b，以及第5 場效電晶體3 0 0的剖面圖。 場效電晶體3 0 0可包含多個半導體鰭片3 5 0 (例如 兩個半導體鰭片），該些半導體鰭片3 5 0位在基材3 0 1 L0來 在鰭 些鰭 寬度 上形 下一 加矽 之間 生電 士η· 要 δ又直 卜觸。 式雙 施例 多個 閘極 .鰭片 並且 場效 FET 圖之 至少 上， 12 200915565 且更明確而言是位在基材3 0 1的絕緣層上。例如 鰭片3 5 0可以是位在絕緣層上的矽鰭片，例如位 上覆矽（SOI)晶圓的包埋氧化層上。該些半導體鰭 分別呈矩形，且一鄰接基材301的底面（也就是與 緣層相鄰接）、一頂面3 5 2、相反側壁3 5 3、相反 掺雜源/汲極區375a和375b)以及介於該相反端ϋ 375b之間的一中央區。該些半導體鰭片350更可 此大致平行並且以一間距3 2 1分隔開來。 依據該場效電晶體3 00是雙閘極FET或是三 來改變鰭片中央區（即，通道區）處的高寬比。舉 用於雙閘極FET時，每個鰭片之通道區376的高 為4:1或更大，參閱第6圖。或者，用於三閘極 每個鰭片的通道區376的高寬比介於約3:2至2 參閱第7圖。 此外，如上所述，基本鰭片結構3 5 0可能包 片。然而，FET結構3 00可能在每個鰭片3 50之 端區或兩個端區375a、375b的側壁和頂面上更包 矽層3 2 0。因此，每個鰭片之端區（也就是源/汲4 和375b)的總高度及/或寬度與中央區3 76(也就； 的Τ§3度和寬度不相同。 閘極3 7 0 (即，閘介電層和閘導體）設置成與 體鰭片3 5 0介於相反端區3 7 5 (也就是介於源/汲；| 的中央區 3 7 6 (即通道區）相鄰接。同樣地，根據 晶體300是雙閘極FET或三閘極FET來改變閘極 ，半導體 在絕緣層 片3 50可 基材的絕 端區（即， I 375a 和 設置成彼 閘極FET 例而言， 寬比大致 FET 時， :3之間， 含一 ί夕鰭 其中一個 含一蟲晶 憂區 375a I：通道區） 每個半導 S區）之間 該場效電 相對於每 13 200915565 個鰭片3 50的位置。更明確而言，用於雙閘極FET時，閘 極370可橫越每個鰭片350，且設置成鄰接每個半導體鰭 片3 5 0之通道區3 7 6的多個側壁3 5 3，但是卻可藉由鰭片 覆蓋層而與頂面3 75電性絕緣開來，參閱第6圖的剖面圖。 或者，用於三閘極FET時，閘極370可設置成與每個半導 體鰭片3 5 0之通道區3 7 6的多個側壁3 5 3和頂面3 5 2相鄰 接，參閱第7圖的剖面圖。200915565 The aspect ratio of the channel region of a semiconductor fin can be about 4:1 or more, and the channel portion of each semiconductor fin is about 3:2 to 2:3. between. The formed gate can be contiguous with the central region of each fin. For FETs, the gate can abut the sidewall of the central region of each fin and can be a cap layer with the top edge of the central region of each fin. For a three-gate FET, the gate can abut the sidewalls and top surface of each semiconductor fin region. A dielectric spacer adjacent to the gate is formed to electrically insulate subsequent formation from the gate. An epitaxial layer can be formed on the sidewalls of both end regions of each fin, but the fins are not combined. Therefore, even after the epitaxial layer, the spacing of the remaining portions between the adjacent fins is performed to perform the implantation process to form the source regions in the opposite end regions of the fins. After forming the source/drain regions, a conductor can be formed (ie, the first end region of each semiconductor fin (ie, the first end region), and the source/drain region on the gate side). The conductors are formed such that a high conductor is formed on the sidewalls and the top surface of the first end region of each fin such that the conductor material is in the pitch and extends between adjacent fins, thereby allowing the conductor material to extend. Between these adjacent semiconductor fins, in the step of forming the conductor, the conductor material may completely fill the spacing between the fins (ie, the conductor material extends over the pitch width between adjacent walls and extends to The top surface of the fin to the base pitch length) to minimize the series resistance; or, the conductor material is large; the aspect ratio of the double gate is used to form the top surface of the conductor after the formation of the upper surface of the conductor, Pole-conductor) The material between the spacers and the sidewalls of the adjacent fins can be filled by the material, and the spacing between adjacent fins can be partially filled (ie, the conductor material extends between adjacent Fin side wall The pitch between the widths, but does not extend to the entire pitch length from the top surface of the fins to the substrate) to adjust the series resistance. An exemplary technique that can be used to form the conductor includes performing a self-aligned vapor formation process (i.e., a deuteration process) to form a metal telluride layer on the sidewalls and top surface of each semiconductor fin end region. The self-alignment of the telluride formation process can be continued until the metallurgical layers on the sidewalls of adjacent semiconductor fins are combined. Another conductor of similar configuration (i.e., the second conductor) is formed such that it traverses and merges the opposite end regions of each of the semiconductor fins. Forming the first and second conductors provides symmetry to the FET structure while causing the series resistances on both sides of the gate to be substantially equal. However, the crystal designer has also discovered that the series resistance in the source on the gate side must be selectively changed as compared to the drain on the opposite side of the gate. Therefore, it is contemplated that these method embodiments may not produce symmetrical FET structures. The invention and other embodiments of the present invention will be better understood by the following description and the appended claims. The scope of the present invention is intended to include modifications of all embodiments without departing from the spirit of the invention. Embodiments of the present invention and various features and advantages thereof will be described with reference to the non-limiting embodiments shown in the accompanying drawings and the detailed description below. Note that the features shown in the figures are not necessarily drawn to scale. Descriptions of the components and processing techniques are omitted to avoid obscuring the embodiments of the present invention. The examples used herein are only to assist in understanding how to implement the embodiments of the invention. Those skilled in the art can implement the embodiments of the invention. The examples are not intended to limit the scope of the embodiments of the invention. As described above, the effective width of the double gate and triple gate fin field effect transistors can be increased by incorporating fins in the field effect transistor (FET) structure. However, when the FET size is scaled, the drive current is limited by the series resistance. The series resistance is mainly derived from the resistance of the telluride to germanium. The effect of the contact resistance of the telluride and tantalum can be reduced by increasing the interface between the telluride and tantalum in the source/drain region of the fin. Referring to Figure 1, by increasing the interface area between the telluride and germanium 1: the technique of reducing the series resistance in the multi-fin FET 100 includes epitaxial growth on the fins 矽1 2 0 until the fins are merged together (also That is, the epitaxial growth 矽1 20 electrically connects the fins) and then forms a telluride at the top (see telluride 160). The advantage of this technique is that since the fins and the telluride 1 60 are combined, it is only necessary to separately provide a contact hole (c ο n t a c t v i a) to the source region and region 175 on both sides of the gate 170. In addition, the configuration of the contact holes is more flexible. However, this technique has drawbacks. First, since the interface area of the telluride and germanium is limited to 1 0 0, the distance between the germanide 1 60 and the channel region (ie, the fin adjacent to the gate 1 70 is relatively long, so the series resistance It is still relatively high. This technique will have a relatively high parasitic capacitance between the gate 1 7 〇 and the 矽 1 2 0 in the source/drain region 1 7.5. The Ministry knows how to make this, multiple channels Subject to electric shock, ί 0 to 150 will be used for a number of poles and 4 zones). Produce 11 200915565 Refer to Figure 2 to reduce the multi-fin FET by increasing the interface area between the telluride and germanium. Another technique for series resistance in 200 also includes the worm growth dream 220 on the sheet 250. However, this technique does not incorporate the sheet 250, but instead uses epitaxial growth 矽220 to increase the height and height of the fins 250. The sidewalls and the top surface of the epitaxial germanium 220 of the fin 250 are formed into a telluride 250, and a space of 2 2 1 is left between each fin having a germanide. Compared with the above technology, the advantage of this technique is that the interface area of the polymerizable and germanium can be 2 1 0, and the distance between the germanide 2 60 and the channel is reduced, and the gate 2 70 and the source/drain region are reduced. 5 between the host. However, this technique cannot only have a single contact hole on each side of the gate 210. That is, each fin 250 needs to be provided with a respective finger. Based on the above situation, several embodiments of a multi-fin field effect transistor (multi-fin gate or triple-gate field effect transistor) are disclosed herein. The high fin material (eg, metal telluride) is used to merge the fins. Combining the fins reduces the series resistance and only slightly increases the parasitic capacitance (if any) between the source/drain regions. The combined semiconductors also allow access to each source/drain region with a single contact hole, providing a more flexible and flexible contact hole configuration. More specifically, referring to Figures 3 through 5, several embodiments of a multi-fin transistor (FET) 300 are disclosed herein. For example, refer to the embodiment 300 of FIG. 3, the F E T embodiment of FIG. 4, and the cross-sectional view of the fifth field effect transistor 300. The field effect transistor 300 may include a plurality of semiconductor fins 350 (e.g., two semiconductor fins), the semiconductor fins 3 50 at the substrate 3 0 1 L0 to form a fin width The next coronation between the electrician η· wants δ and direct touch. The dual embodiment of the plurality of gates. The fins and the field effect FET pattern are at least, 12 200915565 and more specifically on the insulating layer of the substrate 310. For example, the fins 350 can be fin fins on the insulating layer, such as an embedded oxide layer on a topography (SOI) wafer. The semiconductor fins are respectively rectangular, and a bottom surface of the adjacent substrate 301 (ie, adjacent to the edge layer), a top surface 3 5 2, an opposite sidewall 3 53 , an opposite doping source/drain region 375a, and 375b) and a central zone between the opposite end 375 375b. The semiconductor fins 350 can be substantially parallel and separated by a spacing of 3 2 1 . The aspect ratio at the central region of the fin (i.e., the channel region) is varied depending on whether the field effect transistor 300 is a double gate FET or three. For dual gate FETs, the channel area 376 of each fin is 4:1 or greater, see Figure 6. Alternatively, the channel area 376 for each of the three gates has an aspect ratio of between about 3:2 and 2 (see Figure 7). Furthermore, as described above, the basic fin structure 350 may be packaged. However, the FET structure 300 may further include a germanium layer 300 in the end regions of each of the fins 350 or the sidewalls and top surfaces of the two end regions 375a, 375b. Thus, the total height and/or width of the end regions of each fin (i.e., source/汲4 and 375b) is different from the central region 3 76 (i.e., Τ3 degrees and width). Gate 3 7 0 (ie, the gate dielectric layer and the gate conductor) are disposed in opposite end regions 3 7 5 from the body fins 350 (ie, in the central region 3 7 6 (ie, the channel region) of the source/汲;| Similarly, the gate is changed according to whether the crystal 300 is a double gate FET or a triple gate FET, and the semiconductor is in the insulating region of the insulating layer 3 50 substrate (ie, I 375a and is set to be the gate FET). For example, when the width ratio is roughly FET, between: 3, including one 夕 鳍 其中 其中 其中 含 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 375 13 200915565 The position of the fins 3 50. More specifically, for a dual gate FET, the gate 370 can traverse each fin 350 and is disposed adjacent to the channel region of each of the semiconductor fins 350 3 7 6 of the plurality of side walls 3 5 3, but can be electrically insulated from the top surface 3 75 by the fin cover layer, see the cross-sectional view of Fig. 6. Or, for the three gate FET, Electrode 370 may be provided to each of the plurality of sidewalls and the semiconductor fins 350 of the channel region 376 of top surface 353 and the abutment 352, see FIG. 7 is a sectional view.
同樣參閱第3至5圖，導體3 6 0a(第一導體）可橫越且 合併每個半導體鰭片350的其中一端375a，也就是橫越且 合併位在閘極 3 7 0其中一側上之鰭片 3 5 0的源/汲極區 375a。此導體360a可包含高導體材料，該高導體材料位於 每個鰭片3 5 0的頂面上，並且更位在兩相鄰鰭片3 5 0之間 的間距3 2 1中。明確而言，位在相鄰鰭片3 5 0間之間距3 2 1 中的該導體材料可延伸達到介於一鰭片3 5 0之側壁3 5 3和 相鄰鰭片3 5 0之側壁3 5 3之間的間距寬度，而將該些鰭片 合併在一起。需了解到，若每個鰭片350在其頂面352和 側壁3 5 3上包含一磊晶矽層3 2 0，該導體材料則必須位在 每個鰭片3 5 0頂面的磊晶矽層3 2 0上，並且更延伸達到介 於相鄰鰭片側壁3 5 3之磊晶矽層3 2 0之間的間距寬度。導 體3 6 0可能包含高導體材料。例如，導體材料可包括金屬 石夕化物，如石夕化鎳（N i S i)、石夕化钻（C 〇 S i 2)、石夕化鈦（T i S i 2) 等等。 更明確而言，可如第3圖所示般，使用導體材料完全 填滿介於相鄰鰭片之間的間距3 2 1。也就是，導體材料延 14 200915565 伸達到介於相鄰鰭片側壁之間的間距寬度，並且延伸達到 從鰭片頂面下至基板的間距長度。此種結構可增加矽化物 和石夕的界面面積 3 1 0，從而減小源/没極區 3 7 5 a中的串聯 電阻。或者，可如第4圖所示般，使用導體材料來部分填 滿相鄰鰭片之間的間距 3 2 1。也就是，導體材料延伸達到 介於相鄰鰭片側壁之間的間距寬度，並且從鰭片頂面向下 延伸達一預定距離的間距長度，但小於從鰭片頂面到基材 的長度。此種結構可供設計者選擇性地調整源/汲極區3 7 5 a 中的串聯電阻。 場效電晶體3 0 0可更包含另一個類似配置方式的導體 360b(第二導體），該導體360b橫越且合併每個半導體鰭片 350的該相反端區375b，也就是橫越且合併該些鰭片350 位於閘極3 7 0之反側上的源/汲極區 3 7 5 b。因此，該場效 電晶體結構可為對稱的，並且在閘極3 7 0兩側上之源/汲極 區375a和375b中的串聯電阻大致相同。 然而，建議電晶體設計者可相較於汲極（位於閘極的另 一相反側上）中的串聯電阻來選擇性地改變源極（位於閘極 的一側上）中的串聯電阻。因此，可推知該場效電晶體結構 3 0 0在閘極3 7 0的兩側處可能不對稱。 舉例而言，導體可以只合併閘極3 70其中一側上的該 些鰭片。或者，可使位在閘極其中一側上之相鄰鰭片350 之間的間距3 2 1完全填滿導體材料，但位在閘極另一相反 側處的間距3 2 1則僅部份填充導體材料。該領域中的習知 技藝者將可了解到上述的不對稱結構是作為示範之用，依 15 200915565 據本發明可推知其他的非對稱性結構。 與半導體鰭片3 5 0和閘極3 7 0相鄰的介電間隙壁3 8 0 能把閘極3 7 0和導體3 6 0 a - b電性絕緣開來。此外，可分別 使用單個接觸孔來個別接觸已合併的源/汲極區3 7 5 a及/或 3 75b °Referring also to Figures 3 through 5, the conductor 360a (first conductor) can traverse and merge one end 375a of each of the semiconductor fins 350, i.e., traverse and merge on one side of the gate 307. The source/drain region 375a of the fins 350. This conductor 360a may comprise a high conductor material on the top surface of each fin 350 and more in the spacing 3 2 1 between two adjacent fins 350. Specifically, the conductor material located between the adjacent fins 350 to 3 2 1 can extend to the side wall 3 5 3 of one fin 350 and the side wall of the adjacent fin 350 The width of the gap between 3 5 3, and the fins are merged together. It should be understood that if each fin 350 includes an epitaxial layer 3 2 0 on its top surface 352 and sidewalls 35, the conductor material must be epitaxial on the top surface of each fin 350. The germanium layer 3 2 0 and extends further to a pitch width between the epitaxial germanium layers 3 2 0 of the adjacent fin sidewalls 3 5 3 . The conductor 360 may contain a high conductor material. For example, the conductor material may include a metal lithium compound such as Nisic Nickel (N i S i ), Shi Xi Hua Diamond (C 〇 S i 2), Titanium Titanium (T i S i 2), and the like. More specifically, as shown in Fig. 3, the conductor material is used to completely fill the gap 3 2 1 between adjacent fins. That is, the conductor material extends to a pitch width between the sidewalls of adjacent fins and extends to a pitch length from the top surface of the fin to the substrate. This structure increases the interfacial area of the telluride and the shovel 3 1 0, thereby reducing the series resistance in the source/nothing region 3 7 5 a. Alternatively, a conductor material may be used to partially fill the spacing 3 2 1 between adjacent fins as shown in FIG. That is, the conductor material extends to a pitch width between the adjacent fin sidewalls and extends from the top of the fins downward for a predetermined distance, but less than the length from the top surface of the fin to the substrate. This configuration allows the designer to selectively adjust the series resistance in the source/drain region 3 7 5 a. The field effect transistor 300 may further comprise another conductor 360b (second conductor) of similar configuration, the conductor 360b traversing and merging the opposite end region 375b of each semiconductor fin 350, that is, traversing and merging The fins 350 are located on the source/drain region 3 7 5 b on the opposite side of the gate 307. Therefore, the field effect transistor structure can be symmetrical, and the series resistances in the source/drain regions 375a and 375b on both sides of the gate 310 are substantially the same. However, it is recommended that the transistor designer selectively vary the series resistance in the source (on one side of the gate) compared to the series resistance in the drain (on the other opposite side of the gate). Therefore, it can be inferred that the field effect transistor structure 300 may be asymmetrical at both sides of the gate 310. For example, the conductors may only incorporate the fins on one side of the gate 3 70. Alternatively, the spacing 3 2 1 between adjacent fins 350 on one side of the gate can be completely filled with the conductor material, but the spacing 3 2 1 at the other opposite side of the gate is only partially Fill the conductor material. Those skilled in the art will appreciate that the asymmetric structure described above is exemplary, and other asymmetric structures are inferred from the present invention in accordance with the present invention. The dielectric spacers 380 adjacent to the semiconductor fins 305 and the gates 370 can electrically insulate the gates 370 and the conductors 610a-b. In addition, a single contact hole can be used to individually contact the combined source/drain regions 3 7 5 a and/or 3 75b °
參閱第8圖，本文還揭露數種用來形成上述多缝式雙 閘極或三閘極場效電晶體3 0 0的方法實施例。該些方法實 施例包括提供晶圓（步驟 8 0 2)。此晶圓包括，例如具有一 覆蓋層902的絕緣層上覆矽（SOI)晶圓。參閱第9圖，使用 習知處理技術在絕緣層上的矽層中形成多個半導體鰭片 (步驟804)。舉例而言，在絕緣層上覆矽（SOI)晶圓的矽層 中圖案化且蝕刻出至少兩個半導體鰭片 350。可執行圖案 化與蝕刻製程，以形成多個彼此大致平行且彼此之間以一 間距3 2 1分隔開來的半導體鰭片3 5 0。更可執行圖案化和 蝕刻製程，使得每個半導體鰭片為矩形，並且具有一鄰接 絕緣層3 01的底面、一頂面、相反的側壁3 5 3、相反端區 375a和375b，以及一介於該些相反端區375a-b之間的中 央區376 。 根據欲形成的場效電晶體類型，可改變鰭片中央區 3 7 6的高寬比，鰭片中央區將相當於場效電晶體的通道 區。如第6圖所示，若是形成雙閘極FET，每個半導體鰭 片之通道區376的高寬比可約為4:1;又如第7圖所示， 若形成三閘極FET，每個半導體鰭片之通道區的高寬比則 介於約3 : 2至2 : 3之間。 16Referring to Figure 8, a number of embodiments of the method for forming the multi-slot double gate or triple gate field effect transistor 300 are also disclosed herein. Embodiments of the method include providing a wafer (step 802). The wafer includes, for example, an overlying silicon dioxide (SOI) wafer having a cap layer 902. Referring to Figure 9, a plurality of semiconductor fins are formed in the germanium layer on the insulating layer using conventional processing techniques (step 804). For example, at least two semiconductor fins 350 are patterned and etched into the germanium layer of a blanket overlying (SOI) wafer. A patterning and etching process may be performed to form a plurality of semiconductor fins 350 that are substantially parallel to each other and spaced apart from one another by a spacing of 31. The patterning and etching processes can be further performed such that each of the semiconductor fins has a rectangular shape and has a bottom surface adjacent to the insulating layer 310, a top surface, opposite side walls 353, opposite end regions 375a and 375b, and an The central zone 376 between the opposite end regions 375a-b. According to the type of field effect transistor to be formed, the aspect ratio of the central region of the fin can be changed, and the central region of the fin will be equivalent to the channel region of the field effect transistor. As shown in Fig. 6, if a double gate FET is formed, the aspect ratio of the channel region 376 of each semiconductor fin can be about 4:1; and as shown in Fig. 7, if a three gate FET is formed, each The aspect ratio of the channel region of the semiconductor fins is between about 3:2 and 2:3. 16
200915565 例如第9圖所示，雙閘極場效電晶體的製造可始 驟8 0 2的提供一絕緣層上覆矽晶圓，該絕緣層上覆矽 具有 4 0奈米厚之矽層以及厚度約 2 0奈米的鰭片覆 902(例如氧化物層）。圖案化且蝕刻貫穿該鰭片覆蓋層 和矽層9 0 1，而形成多個厚度約1 5奈米且間距約8 0 的鰭片。 在步驟804中形成多個半導體鰭片之後，若該多 FET是三閘極FET，則可選擇性地從鰭片頂面上移除 化物覆蓋層902，使得隨後形成的閘即3 70不會與該 片之通道區的頂面電性絕緣開來（未顯示）。 參閱第10圖，接著可形成閘極370，其鄰接每個 的中央區（步驟 8 0 6)。可使用習知處理技術來形成 3 7 0。舉例而言，可利用沉積與圖案化來形成閘極堆疊 極堆疊包括一閘介電層、一閘導體層1 0 0 3以及一閘覆 1 0 0 1。同樣地，根據所欲形成的 F E T種類（也就是三 FET或雙閘極FET)，閘極370可與每個半導體鰭片之 區的頂面電性絕緣。也就是，如第6圖所示，若形成 式雙閘極電晶體，閘極3 7 0可鄰接每個鰭片之中央區 的側壁3 5 3，但是可藉由例如氧化物覆蓋層3 5 1而與 鰭片中央區3 7 6的頂面3 5 2電性絕緣。或者，如第7 示，若形成多鰭式三閘極電晶體，閘極3 7 0則可與每 導體鰭片之中央區3 7 6的側壁3 5 3和頂面3 5 2相鄰接 例如第1 0圖所示，在步驟8 0 6中，所沉積的閘極 層1 0 0 3可包含厚度約8 0奈米的多晶矽層1 0 0 3，並且 於步 晶圓 蓋層 902 奈米 籍式 該氧 些鰭 鶴片 閘極 ，閘 蓋層 閘極 中央 多鰭 376 每個 圖所 個半 〇 導體 所沉 17 200915565 積的閘覆蓋層1 004可包含厚度約60奈米的氮化物覆蓋 層。隨後可圖案化該閘極堆疊，使得閘極長度約2 8奈米， 並且露出端區375a和375b。 在步驟8 0 6中形成閘極3 7 0之後，可使用習知的間隙 壁形成技術來形成介電間隙壁 3 8 0 (例如，氧化物間隙壁） 與閘極3 70相鄰接，以使後續形成的導體3 60a-b與閘極 3 7 0電性絕緣開來，參閱第1 1圖。該些間隙壁3 8 0的厚度 可例如約2 5奈米。 接著，若鰭片上有覆蓋層902的話，可從鰭片露出來 的部分上移除覆蓋層 9 0 2。隨後，在每個半導體鰭片350 之端區3 7 5 a-b的側壁3 5 3和頂面3 5 2上形成一磊晶矽層 320，但不合併該些鰭片350(步驟810，參閱第13圖）。因 此，即便在形成磊晶矽層3 2 0之後，相鄰鰭片之間仍保留 一部分的間距3 2 1。可使用習知的磊晶成長製程來達成此 步驟。形成此磊晶矽層允許執行後續步驟8 1 2的自我對準 矽化製程，而不會損耗任何的原始矽鰭片3 5 0。 舉例而言，在步驟8 1 0，位於鰭片3 5 0之側壁以及頂 面上的磊晶矽層320可具有約20奈米的厚度。因此，對於 雙閘極FET而言，若間距約為80奈米，且鰭片厚度約為 1 5奈米時，介於相鄰鰭片3 5 0側壁上之磊晶矽層3 2 0之間 的殘留間距則約為2 5奈米。 接著，在該些鰭片350的相反端區375a和375b中形 成源/汲極區（步驟8 1 2)。可利用習知的摻雜技術，例如佈 植製程，使用適當的η型或p型摻雜物沿著閘極多晶矽3 7 0 18 200915565 來摻閘該些含有磊晶矽層之半導體鰭片的端區，而達成此 步驟。也就是說，對於η型FET而言，可使用例如磷（P)、 銻（Sb)或砷（As)來佈植源/汲極區3 75a與3 75b。或者，對 於p型FET，可使用例如硼（B)來佈植源/汲極區3 75a與 3 75b °200915565 For example, as shown in FIG. 9, the manufacture of a double gate field effect transistor can be performed by initially providing an insulating layer overlying a germanium wafer having a layer of 40 nm thick and a layer of germanium thereon. A fin cover 902 (eg, an oxide layer) having a thickness of about 20 nm. A plurality of fins having a thickness of about 15 nm and a pitch of about 80 are formed by patterning and etching through the fin cover layer and the germanium layer 910. After forming a plurality of semiconductor fins in step 804, if the multi-FET is a three-gate FET, the material cap layer 902 can be selectively removed from the top surface of the fin, so that the subsequently formed gate is 3 70 It is electrically insulated from the top surface of the channel region of the sheet (not shown). Referring to Fig. 10, a gate 370 can then be formed which abuts the central region of each (step 806). Conventional processing techniques can be used to form 370. For example, deposition and patterning can be used to form a gate stack. The pole stack includes a gate dielectric layer, a gate conductor layer 1 0 0 3 , and a gate cover 1 0 0 1 . Similarly, gate 370 can be electrically isolated from the top surface of each semiconductor fin region depending on the type of F E T to be formed (i.e., a triple FET or a dual gate FET). That is, as shown in Fig. 6, if a double gate transistor is formed, the gate 307 may abut the side wall 353 of the central region of each fin, but may be covered by, for example, an oxide layer 3 5 1 is electrically insulated from the top surface 3 5 2 of the fin central region 376. Alternatively, as shown in FIG. 7, if a multi-fin three-gate transistor is formed, the gate 307 may be adjacent to the sidewall 353 and the top surface 325 of the central region of each conductor fin. For example, as shown in FIG. 10, in step 060, the deposited gate layer 1 0 0 3 may comprise a polysilicon layer 1 0 0 3 having a thickness of about 80 nm, and the wafer cap layer 902 奈The m-type of the oxygen fins of the gates, the gates of the gates and the multi-fins of the gates of the gates 376 of each of the layers of the conductors of each of the figures. 200915565 The gate cover of the product 1 004 can contain nitrides with a thickness of about 60 nm. Cover layer. The gate stack can then be patterned such that the gate length is about 28 nm and the end regions 375a and 375b are exposed. After the gate 307 is formed in step 806, a conventional spacer formation technique can be used to form a dielectric spacer 380 (eg, an oxide spacer) adjacent to the gate 3 70 to The subsequently formed conductors 3 60a-b are electrically insulated from the gates 370, see Fig. 11. The thickness of the spacers 380 may be, for example, about 25 nm. Next, if there is a cover layer 902 on the fin, the cover layer 902 can be removed from the exposed portion of the fin. Subsequently, an epitaxial layer 320 is formed on the sidewalls 3 5 3 and the top surface 325 of the end regions 3 7 5 ab of each of the semiconductor fins 350, but the fins 350 are not combined (step 810, see 13 picture). Therefore, even after the formation of the epitaxial layer 3 2 0, a portion of the pitch 3 2 1 remains between adjacent fins. This step can be achieved using a conventional epitaxial growth process. Forming this epitaxial layer allows the self-alignment process of the subsequent step 8 1 2 to be performed without loss of any of the original fin fins 350. For example, in step 810, the epitaxial layer 320 on the sidewalls and top surface of the fins 350 may have a thickness of about 20 nanometers. Therefore, for a dual gate FET, if the pitch is about 80 nm and the fin thickness is about 15 nm, the epitaxial layer 3 2 0 on the sidewall of the adjacent fin 350 The residual spacing between them is about 25 nm. Next, source/drain regions are formed in opposite end regions 375a and 375b of the fins 350 (step 8 1 2). Conventional doping techniques, such as implantation processes, can be used to bond the semiconductor fins containing epitaxial germanium layers along the gate polysilicon 矽 3 7 0 18 200915565 using appropriate n-type or p-type dopants. End zone, and reach this step. That is, for the n-type FET, source/drain regions 3 75a and 3 75b can be implanted using, for example, phosphorus (P), antimony (Sb), or arsenic (As). Alternatively, for p-type FETs, for example, boron (B) can be used to implant source/drain regions 3 75a and 3 75b °
接續形成源/汲極的步驟 8 1 2之後，可形成一導體 360a(第一導體）而橫越每個半導體鰭片 350 的一端區 3 7 5 a(第一端區），進而將位在閘極3 7 0 —側上之每個鰭片 的源/汲極區375a合併在一起。可藉著在每個鰭片350之 端區3 7 5 a的側壁和頂面上形成高導體材料，使得導體材料 位在介於相鄰半導體鰭片3 5 0之間的間距3 2 1中，並且延 伸達到介於相鄰半導體鰭片3 5 0之側壁3 5 3之間的間距寬 度，而形成導體3 60a。 在形成導體的步驟中，可如第3圖所示般，導體材料 可能完全填滿相鄰鰭片3 5 0之間的間距3 2 1 (也就是導體材 料形成在間距内而延伸達到從相鄰鰭片之側壁到側壁之間 的間距寬度，且導體材料延伸達到從鰭片頂面向下至基材 的間距長度），以減小串聯電阻。或者，如第4圖所示，導 體材料可部分填充間距3 2 1 (也就是導體材料形成在間距 内而延伸達到從相鄰鰭片之側壁到側壁之間的間距寬度， 但是導體材料未達到從鰭片頂面向下至基材的間距全長長 度），以調整串聯電阻。需了解到若該些鰭片 3 5 0的側壁 3 5 3和頂面3 5 2上具有磊晶矽層3 2 0，則導體材料必須位在 每個鰭片3 5 0頂面上之磊晶矽層3 2 0上，並且將延伸達到 19 200915565 在間距3 2 1中介於側壁3 5 3上之磊晶矽層3 2 0之間的 寬度。 可用來形成導體 3 6 0 a的示範技術包括執行一自 準矽化製程（也就是金屬矽化製程），以在每個半導體 3 5 0之端區3 7 5 a的側壁和頂面上形成金屬矽化物層。 對準矽化製程會將諸如鎳、鈷或鈦等高導體金屬引導 在鰭片3 5 0之側壁3 5 3和頂面3 5 2上的暴露磊晶矽層 可使用習知的矽化技術來達成此矽化步驟。也就是， 所選的金屬（例如鎮、姑、鈦）沉積在露出的蟲晶石夕上 積之後，可執行一熱退火製程，以產生金屬與矽的化名 例如矽化鎳（NiSi)、矽化鈷（CoSi2)、矽化鈦（TiSi2)等 自我對準矽化製程可持續，直到相鄰半導體鰭片側壁 金屬矽化物層360合併在一起為止，參閱第3圖。 如上所述，串聯電阻與矽化物-矽界面3 1 0有關。 是說，增加矽化物和矽的界面3 1 0可減小串聯電阻。g 為了減小串聯電阻，可在間距3 2 1中形成金屬矽化物 使得間距3 2 1完全填滿（也就是使金屬矽化物延伸達 於相鄰鰭片側壁上之磊晶矽層之間的間距寬度，並且 達到從鰭片頂面至基材的間距長度），如第 3圖所示 者，建議可調整串聯電阻，而不將串聯電阻減至最小 此，在執行金屬矽化製程之前，可把鰭片3 5 0的一預 分遮蔽住，以調整後續形成的矽化物與矽的介面 3 1 C 而調整串聯電阻（步驟 8 1 5)。例如，可沉積且選擇性 介電層 3 9 0 (例如氮化層），以暴露出將被矽化的鰭片 間距 我對 鰭片 自我 至位 上。 可將 。沉 ‘物， 等。 上的 也就 1此， 360 > 到介 延伸 。或 。因 定部 丨，進 回# 區域 20After the step 8 1 2 of forming the source/drain, a conductor 360a (first conductor) may be formed to traverse the end region 3 7 5 a (first end region) of each of the semiconductor fins 350, and then The source/drain regions 375a of each of the fins on the side of the gate 3 70 are merged together. A high conductor material can be formed on the sidewalls and the top surface of the end regions 3 7 5 a of each of the fins 350 such that the conductor material is positioned in a spacing 3 2 1 between adjacent semiconductor fins 350 And extending to a pitch width between the side walls 3 5 3 of the adjacent semiconductor fins 350, to form a conductor 3 60a. In the step of forming the conductor, as shown in Fig. 3, the conductor material may completely fill the gap 3 2 1 between the adjacent fins 350 (that is, the conductor material is formed within the pitch and extends to the phase The width of the spacing between the sidewalls of the adjacent fins to the sidewalls, and the conductor material extending to the length of the pitch from the top of the fins down to the substrate to reduce the series resistance. Alternatively, as shown in Fig. 4, the conductor material may be partially filled with a pitch of 3 2 1 (that is, the conductor material is formed within the pitch and extends to a pitch width from the sidewall of the adjacent fin to the sidewall, but the conductor material does not reach The length of the entire length of the substrate is adjusted from the top of the fin to the bottom to adjust the series resistance. It should be understood that if the sidewalls 3 5 3 and the top surface 3 5 2 of the fins 350 have an epitaxial layer 3 2 0, the conductor material must be placed on the top surface of each fin 350. The germanium layer is on the surface of the germanium layer 3 2 0 and will extend to a width of 19 200915565 between the epitaxial germanium layers 3 2 0 on the sidewalls 3 5 3 in the pitch 3 2 1 . An exemplary technique that can be used to form conductors 360a includes performing a self-alignment process (ie, a metallization process) to form metal germanium on the sidewalls and top surfaces of the end regions of each semiconductor 350. Layer of matter. Alignment of the high-conductor metal such as nickel, cobalt or titanium on the sidewalls 3 5 3 and the top surface 35 of the fins 350 can be achieved using conventional deuteration techniques. This purification step. That is, after the selected metal (eg, town, uranium, titanium) is deposited on the exposed smectite, a thermal annealing process can be performed to generate a chemical name of metal and lanthanum such as nickel hydride (NiSi) or cobalt hydride. Self-aligned deuteration processes such as (CoSi2) and titanium telluride (TiSi2) may continue until the adjacent metal fin sidewall metallization layers 360 are merged together, see Figure 3. As mentioned above, the series resistance is related to the telluride-germanium interface 310. That is to say, increasing the interface of germanium and germanium 3 10 can reduce the series resistance. g In order to reduce the series resistance, a metal telluride can be formed in the spacing 3 2 1 such that the spacing 3 2 1 is completely filled (that is, the metal telluride extends between the epitaxial layers on the sidewalls of the adjacent fins) The width of the pitch, and the length of the pitch from the top surface of the fin to the substrate), as shown in Figure 3, it is recommended to adjust the series resistance without minimizing the series resistance. Before performing the metal smelting process, A pre-fraction of the fins 350 is masked to adjust the subsequently formed germanium and germanium interface 3 1 C to adjust the series resistance (step 8 15). For example, a dielectric layer 390 (e.g., a nitride layer) can be deposited and selectively exposed to expose the fin spacing that will be deuterated. I am self-aligning the fins. Can be. Shen ‘thing, etc. On the first one, 360 > to the extension. Or . According to the 丨 丨, go back to the # area 20
200915565 (參閱第14圖）。因此，在矽化過程中，會形成 3 6 0，而只會部分填充相鄰鰭片之間的間距，也 化物延伸達到介於相鄰鰭片側壁3 5 3上之磊晶 間的間距寬度，但是僅延伸在介於從鰭片3 5 0 下至高於基材頂面一預定高度的部分間距長度 所示。 除了在步驟814形成導體360a以外，步驟 形成另一個類似結構的導體3 60b(第二導體）， 併每個半導體鰭片350的該相反端區375b，也 合併位於閘極 3 7 0反側上之該些鰭片 3 5 0 U 375b。這些導體360a和36 0b可以是對稱的， 側上的串聯電阻大致相等。然而，電晶體設計 現到，相較於没極（位於閘極的該相反側上）的 必須選擇性地改變源極（位在閘極的一側上） 阻。因此，舉例而言，可預期到該方法實施例 對稱的場效電晶體結構。 例如，步驟8 1 4可能只會在閘極3 7 0的其 生合併的矽化物鰭片。或者，閘極3 7 0其中一 鰭片3 5 0之間的間距3 2 1可被導體材料完全填 導體材料部份填充位在閘極該相反側上的間距 域中的習知技藝者可理解到，上述的非對稱性 為示範說明之用，亦可推知其他的非對稱性結4 在形成導體的步驟814之後，完成場效電 (步驟8 1 6)。例如，可沉積毯覆介電層、形成接 金屬石夕化物 就是金屬石夕 矽層320之 之頂面3 5 2 ，如第4圖 814可包括 其橫越且合 就是檢越且 3源/ >及極區 因此閘極兩 者可能也發 串聯電阻， 中的串聯電 可能產生不 中一側上產 側上之相鄰 滿；而使用 3 2 1。該領 結構僅是作 f冓。 晶體的處理 觸孔等等。 21 200915565 如上所述，如上述方法合併該些鰭片 350 的額外優點在 於，每個已合併的源/汲極區375a及/或375b僅各自需要 單一個接觸孔。200915565 (see Figure 14). Therefore, in the deuteration process, 3 60 is formed, and only the spacing between adjacent fins is partially filled, and the extension of the compound reaches the pitch width between the epitinoids on the adjacent fin sidewalls 3 5 3 . However, it extends only as shown by the length of the partial pitch from the fin 350 to a predetermined height above the top surface of the substrate. In addition to forming the conductor 360a in step 814, the step forms another similarly structured conductor 3 60b (second conductor), and the opposite end region 375b of each semiconductor fin 350 is also merged on the opposite side of the gate 307 The fins are 3 5 0 U 375b. These conductors 360a and 306b may be symmetrical, with series resistance on the sides being substantially equal. However, the transistor design now has to selectively change the source (on one side of the gate) resistance compared to the gate (on the opposite side of the gate). Thus, for example, a symmetric field effect transistor structure of the method embodiment is contemplated. For example, step 8 1 4 may only be combined with the germanide fins at the gate 3 70. Alternatively, the pitch 3 2 1 between the gates 390 and one of the fins 350 can be filled by the conductor material completely filling the conductor material portion in the pitch field on the opposite side of the gate. It is understood that the above-described asymmetry is used for exemplary purposes, and it is also inferred that the other asymmetrical junction 4 completes the field effect power after the step 814 of forming the conductor (step 8 16). For example, a blanket dielectric layer can be deposited, and a metallization can be formed to be the top surface of the metal slab layer 320. As shown in FIG. 4, the 814 can include the traverse and the combination is the detection and the 3 source/ > and the polar region, therefore, both of the gates may also have series resistance, and the series power in the middle may produce the adjacent full side on the upper side; instead, 3 2 1 is used. The collar structure is only for f冓. Processing of crystals, etc. 21 200915565 As mentioned above, an additional advantage of incorporating the fins 350 as described above is that each of the merged source/drain regions 375a and/or 375b requires only a single contact hole.
因此，以上揭不的數種多，轉式場效電晶體實施例（即 是，多鰭式雙閘極或三閘極場效電晶體），利用一高導體材 料（例如金屬矽化物）將多個鰭片完全或部分合併在一起。 合併多個鰭片可減小串聯電阻，並且僅會提升些許閘極與 源/汲極區之間的寄生電容。合併多個半導體鰭片還允許利 用單一個接觸孔來接觸每個源/汲極區，並且提供更靈活的 接觸孔配置。 第1 5圖顯示設計流程範例1 5 0 0的方塊圖。設計流程 1 5 0 0可根據欲設計的積體電路（IC)類型而改變。例如，用 來建構一特定用途IC (ASIC)的設計流程1 500與用來設計 標準留件的設計流程1 500不相同。設計結構1 520較佳是 鍵入設計程序1510的輸入值，並且可來自於IP提供者、 核心研發人員、其他設計公司、設計流程操作員所產生或 來自其他來源。設計結構1 520包含概要圖或HDL、硬體 描述語言（如 Verilog、VHDL、C語言等）形式的第1至7 圖以及第9至1 4圖之電路。設計結構1 5 2 0可存錄在一或 多個機械可讀取媒體上。例如，設計結構 1 5 2 0可能是第 1_7與7-14圖之電路的文字檔或圖形檔。設計程序1510 較佳可將第 1-7 和 9-14 圖的電路合成為一網絡表 (netlist) 1 5 80，網絡表1 5 8 0可例如是線路、電晶體、邏輯 閘、控制電路、I/O、模組等用來描述積體電路設計中之其 22 200915565 他元件與電路連接關係的列表，並且紀錄在至少其中一種 機器可讀取媒體上。此可為一種互動程序（interactive process)，根據電路的設計規格和參數，可以重複一或多 次地合成出該網絡表1 5 8 0。 設計程序1 5 1 0可包括使用各種輸入，例如來自庫源件 1530(library elements)、設計規格 1540、特徵資料 1550、 驗證資料1 5 6 0、設計規則1 5 7 0以及測試資料檔1 5 8 5 (可包 含測試模式與其他測試資訊）的輸入，庫元件1 5 3 0可包含 一組用於指定製造技術（例如3 2奈米、4 5奈米、9 0奈米等 不同技術節點）的常用元件、電路與裝置，包括模組、佈局 與代表符號。設計程序1 5 1 0可更包含，例如標準電路設計 製程，例如時序分析、驗證、設計規則檢查、操作的設置 與路線安排等等。積體電路設計領域中具有通常知識者能 在不偏離本發明精神與範圍的情況下理解可用於設計程序 1 5 1 0中的電子設計自動化工具和應用。本發明的設計結構 受限於任何特定的設計流程。 如第1 5圖所示，設計程序1 5 1 0較佳可將本發明實施 例以及任何額外的積體電路設計或資料（若可實施的話）轉 譯成第二設計結構1 5 9 0。設計結構1 5 9 0以可用於交換積 體電路佈局資料的資料格式，例如以GDSII(GDS2)、GL1、 Ο A SIS或其他適合儲存此類設計結構的格式，存錄在一儲 存媒體上。設計結構1 5 9 0可能包含多種資訊，例如測試資 料檔、設計内容檔、製造資料、佈局參數、線路、金屬層、 介層孔、形狀、製程線的動線資料，以及半導體製造業者 23 200915565 製造本發明實施例所需要的任何其他資料，如第1 5圖所 示。設計結構1 5 9 0隨後可進行至階段1 5 9 5，例如設計結 構1590可進行試產（tape-out)、釋出進行生產製造、釋出 給光罩製作廠（Mask House)、送至其他設計廠、送回給客 戶等等。Therefore, the above-mentioned several kinds of multi-turn, field-effect transistor embodiments (ie, multi-fin double gate or triple gate field effect transistors) use a high conductor material (such as metal telluride) to be more The fins are completely or partially combined. Combining multiple fins reduces the series resistance and only increases the parasitic capacitance between the gate and the source/drain regions. Combining multiple semiconductor fins also allows for a single contact hole to contact each source/drain region and provides a more flexible contact hole configuration. Figure 15 shows a block diagram of the design flow example 1 500. The design flow 1 500 can be changed depending on the type of integrated circuit (IC) to be designed. For example, the design flow 1500 used to construct an application specific IC (ASIC) is not the same as the design flow 1500 used to design standard spare parts. Design Structure 1 520 is preferably entered into the input value of design program 1510 and may be generated by an IP provider, a core developer, other design company, a design process operator, or from other sources. Design Structure 1 520 includes schematics or circuits in Figures 1 through 7 and 9 through 14 in the form of HDL, hardware description languages (such as Verilog, VHDL, C, etc.). The design structure 1 5 2 0 can be recorded on one or more mechanically readable media. For example, the design structure 1 5 2 0 may be a text file or a graphic file of the circuits of the first and seventh steps 7-14. The design program 1510 preferably combines the circuits of Figures 1-7 and 9-14 into a netlist 1 5 80. The network table 1 5 8 0 can be, for example, a line, a transistor, a logic gate, a control circuit, I/O, modules, etc. are used to describe the list of their components and circuit connections in the integrated circuit design, and are recorded on at least one of the machine readable media. This can be an interactive process. The network table 1 580 can be synthesized one or more times according to the design specifications and parameters of the circuit. The design program 1 5 1 0 may include the use of various inputs, such as from library source 1530, design specifications 1540, profile 1550, verification data 1 5 6 0, design rules 1 5 7 0, and test data files 1 5 8 5 (can include test mode and other test information) input, library component 1 5 3 0 can contain a set of different manufacturing techniques for specifying manufacturing technologies (eg 3 2 nm, 45 nm, 90 nm, etc.) Common components, circuits and devices, including modules, layout and representative symbols. The design program 1 5 1 0 can include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, operation setting and routing, and the like. Those skilled in the art of integrated circuit design can understand the electronic design automation tools and applications that can be used in the design process 1 5 1 0 without departing from the spirit and scope of the present invention. The design structure of the present invention is limited to any particular design flow. As shown in Fig. 15, the design program 105 can preferably translate the embodiment of the invention and any additional integrated circuit design or material (if applicable) into a second design structure 1 590. The design structure 1 5 9 0 is stored on a storage medium in a data format that can be used to exchange integrated circuit layout data, such as GDSII (GDS2), GL1, Ο A SIS, or other format suitable for storing such design structures. Design Structure 1 5 9 0 may contain a variety of information, such as test data files, design content files, manufacturing materials, layout parameters, wiring, metal layers, vias, shapes, process lines, and semiconductor manufacturers 23 200915565 Any other information required to make an embodiment of the invention is shown in Figure 15. The design structure 1 5 9 0 can then proceed to stage 1 5 9 5, for example, the design structure 1590 can be tape-out, released for production, released to the Mask House, sent to Other design factories, return to customers, etc.
以上揭露内容是有關於多鰭式場效電晶體（多鰭式雙 閘極或三閘極場效電晶體）的數個實施例，該些實施例中， 利用一高導體材料（例如金屬矽化物）將多個鰭片完全或部 分地合併在一起。合併該些鰭片允許降低串聯電阻，並且 僅微量增加閘極與源/汲極區之間的寄生電容。合併該些半 導體鰭片還允許可利用單一個接觸孔就可接觸每個源/汲 汲區，並且使接觸孔的配置更加靈活。 以上特定實施例的描述内容可完整呈現本發明的大體 本質，並且可藉著應用當前知識在不偏離本發明的整體概 念下，依據不同用途來修飾及/或變化這些特定實施例。因 此，此類修飾與變化態樣應屬於文中揭露實施例之均等物 的範圍。又需了解到，文中所使用的專業術語和用詞僅是 作為說明之用，而非用來限制本發明。因此，該領域中熟 悉此項技術者將明白可在不偏離後附申請專利範圍與精神 下對本發明實施例做出各種修飾變化。 【圖式簡單說明】 參照所附圖式來閱讀以上詳細說明將可更佳地了解本 發明實施例，該些附圖為： 苐1圖顯不一多轉式場效電晶體的不意圖， 24 200915565 第2圖顯示另一種多鰭式場效電晶體的示意圖； 第3圖顯示本發明之多鰭式場效電晶體實施例的示意 圖； 第4圖顯示本發明之之多鰭式場效電晶體另一實施例 的示意圖； 第5圖顯示本發明場效電晶體貫施例的不範剖面圖； 第6圖顯示本發明場效電晶體實施例的示範剖面圖； 第7圖顯示本發明場效電晶體實施例的另一個示範剖 面圖； 第8圖顯示形成第3與4圖場效電晶體之方法實施例 的流程圖； 第9圖顯示部分完成之多鰭式場效電晶體的示意圖； 第1 0圖顯示部分完成之多鰭式場效電晶體的示意 圖； 第11圖顯示部分完成之多鰭式場效電晶體的示意 圖； 第1 2圖顯示部分完成之多鰭式場效電晶體的示意 圖； 第1 3圖顯示部分完成之多鰭式場效電晶體的示意 圖； 第14圖顯示部分完成之多鰭式場效電晶體的示意 圖；以及 第1 5圖是用於半導體設計、製造及/或測試的設計程 序流程圖。 25 200915565 【主要元件符號說明】 100 、 200 ' 300a 、 300b 場效電晶體 1 1 0、2 1 0、3 1 0矽化物和矽的界面 12 0、220、3 2 0 磊晶矽 150、250、350半導體鰭片 16 0、2 6 0矽化物 1 75、275、3 75a-b 源 / 汲極區 221 ' 321 間距 35 1覆蓋層 3 5 3側壁 3 76通道區/中央區 3 9 0介電層 812、 814、 815、 816 步驟 902覆蓋層 10 04閘覆蓋層 1 5 1 0設計程序 1 5 3 0庫元件 1 5 5 0特徵資料 1 5 7 0設計規則 1 5 9 0最終設計結構 1 5 9 5階段 170、 270、 370 閘極 301基材 3 5 2頂面 360a導體 3 8 0介電間隙壁 802 、 804 、 806 ' 808 、 810 9 0 1矽層 1 0 0 3閘導體層 1 5 0 0設計流程 1 5 2 0設計結構 1 5 4 0設計規格 1 5 6 0驗證資料 1 5 8 0網絡表 1 5 8 5測試資料 26The above disclosure relates to several embodiments of multi-fin field effect transistors (multi-fin double gate or triple gate field effect transistors), in which a high conductor material (eg, metal telluride) is utilized. The plurality of fins are combined completely or partially together. Combining the fins allows the series resistance to be reduced and only slightly increases the parasitic capacitance between the gate and the source/drain regions. The combination of the semiconductor fins also allows access to each of the source/germanium regions with a single contact hole and makes the configuration of the contact holes more flexible. The above description of the specific embodiments may be presented to the full scope of the present invention, and the specific embodiments may be modified and/or varied depending on the application, without departing from the present invention. Therefore, such modifications and variations are intended to fall within the scope of the equivalents of the embodiments disclosed herein. It is also to be understood that the terminology and terminology used herein are for the purpose of description Therefore, it will be apparent to those skilled in the art that various modifications may be made to the embodiments of the present invention without departing from the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The embodiments of the present invention will be better understood by reading the above detailed description with reference to the accompanying drawings, which are: FIG. 1 is not intended to be a multi-turn field effect transistor, 24 200915565 Figure 2 shows a schematic diagram of another multi-fin field effect transistor; Figure 3 shows a schematic diagram of an embodiment of the multi-fin field effect transistor of the present invention; Figure 4 shows another multi-fin field effect transistor of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5 is a cross-sectional view showing an embodiment of a field effect transistor of the present invention; FIG. 6 is a cross-sectional view showing an embodiment of the field effect transistor of the present invention; and FIG. 7 is a view showing a field effect of the field effect transistor of the present invention. Another exemplary cross-sectional view of a crystal embodiment; FIG. 8 is a flow chart showing an embodiment of a method of forming a field effect transistor of FIGS. 3 and 4; and FIG. 9 is a schematic view showing a partially completed multi-fin field effect transistor; Figure 0 shows a schematic diagram of a partially completed multi-fin field effect transistor; Figure 11 shows a schematic view of a partially completed multi-fin field effect transistor; Figure 12 shows a schematic view of a partially completed multi-fin field effect transistor; Figure 3 shows a schematic diagram of a partially completed multi-fin field effect transistor; Figure 14 shows a schematic view of a partially completed multi-fin field effect transistor; and Figure 15 shows a design procedure for semiconductor design, fabrication and/or testing. flow chart. 25 200915565 [Explanation of main component symbols] 100, 200 ' 300a, 300b field effect transistor 1 1 0, 2 1 0, 3 1 0 interface of germanium and germanium 12 0, 220, 3 2 0 epitaxy 150, 250 , 350 semiconductor fins 16 0, 2 6 0 germanide 1 75, 275, 3 75a-b source / drain region 221 '321 spacing 35 1 cover layer 3 5 3 sidewall 3 76 channel area / central area 3 9 0 Electrical layer 812, 814, 815, 816 Step 902 Cover layer 10 04 Gate cover layer 1 5 1 0 Design procedure 1 5 3 0 Library element 1 5 5 0 Characteristic data 1 5 7 0 Design rule 1 5 9 0 Final design structure 1 5 9 5 stage 170, 270, 370 gate 301 substrate 3 5 2 top surface 360a conductor 3 8 0 dielectric spacer 802, 804, 806 '808, 810 9 0 1 layer 1 0 0 3 gate conductor layer 1 5 0 0 Design flow 1 5 2 0 Design structure 1 5 4 0 Design specification 1 5 6 0 Verification data 1 5 8 0 Network table 1 5 8 5 Test data 26
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| US11/873,521 US7851865B2 (en) | 2007-10-17 | 2007-10-17 | Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8557692B2 (en) | 2010-01-12 | 2013-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET LDD and source drain implant technique |
| CN104576643A (en) * | 2013-10-14 | 2015-04-29 | 格罗方德半导体公司 | Three-dimensional transistor with improved channel mobility |
| TWI496287B (en) * | 2009-09-17 | 2015-08-11 | Ibm | Dual dielectric tri-gate field effect transistor |
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| US10164108B2 (en) | 2014-10-17 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (FinFET) device and method for forming the same |
| US9922975B2 (en) | 2015-10-05 | 2018-03-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit having field-effect trasistors with dielectric fin sidewall structures and manufacturing method thereof |
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| KR100555518B1 (en) * | 2003-09-16 | 2006-03-03 | 삼성전자주식회사 | Double gate field effect transistor and manufacturing method for the same |
| US7042009B2 (en) * | 2004-06-30 | 2006-05-09 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
| US20060220120A1 (en) * | 2005-03-31 | 2006-10-05 | Impinj, Inc. | High voltage LDMOS device with counter doping |
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| TWI496287B (en) * | 2009-09-17 | 2015-08-11 | Ibm | Dual dielectric tri-gate field effect transistor |
| US8557692B2 (en) | 2010-01-12 | 2013-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET LDD and source drain implant technique |
| CN104576643A (en) * | 2013-10-14 | 2015-04-29 | 格罗方德半导体公司 | Three-dimensional transistor with improved channel mobility |
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