TW200915439A - Method for fabricating recess gate in semiconductor device - Google Patents

Method for fabricating recess gate in semiconductor device Download PDF

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Publication number
TW200915439A
TW200915439A TW097137008A TW97137008A TW200915439A TW 200915439 A TW200915439 A TW 200915439A TW 097137008 A TW097137008 A TW 097137008A TW 97137008 A TW97137008 A TW 97137008A TW 200915439 A TW200915439 A TW 200915439A
Authority
TW
Taiwan
Prior art keywords
etching
layer
region
amorphous carbon
recessed
Prior art date
Application number
TW097137008A
Other languages
Chinese (zh)
Other versions
TWI425578B (en
Inventor
Yong-Tae Cho
Eun-Mi Kim
Original Assignee
Hynix Semiconductor Inc
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Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200915439A publication Critical patent/TW200915439A/en
Application granted granted Critical
Publication of TWI425578B publication Critical patent/TWI425578B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Drying Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method for fabricating a recess gate in a semiconductor device includes etching a silicon substrate to form a trench that defines an active region, forming a device isolation layer that gap-fills the trench, forming a hard mask layer over the silicon substrate, the hard mask layer comprising a stack of an oxide layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the active region, and forming a recess region with a dual profile by first etching and second etching the channel target region using the hard mask layer as an etch barrier, wherein the second etching is performed after removing the amorphous carbon layer.

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200915439 九、發明說明： 【發明所屬之技術領域】 本發明主張於2007年9月28日申請之韓國專利申請案 號2007-0098221之優先權，將其全文以參考的方式倂入本 文。 本發明關於半導體元件製造，尤其是關於一種製造半導 體元件之凹陷閘極之方法。 【先前技術】 在半導體元件之製造中，使用形成平面閘極之方法來於 平面主動區上形成閘極。然而，因圖案尺寸縮減而造成的 通道長度減少及因基板之離子佈植掺雜濃度增加而造成的 電場增加，因而造成接面漏電流（junction leakage )。這 會使其難以獲得元件之更新特性。 爲了解決上述限制，已提出一種三維凹陷閘極製程作爲 替代的形成閘極的方法，其在蝕刻主動區後形成閘極。凹 陷閘極製程使其可以增加通道長度並減少離子佈植掺雜濃 度，因而改善元件之更新特性。 第1A至1C圖說明根據先前技術的製造半導體元件之凹 陷閘極之方法。在此，每一圖式的右邊部分爲沿著I - Γ線 之剖面圖。 參照第1 A圖，蝕刻矽基板1 1之元件隔離區而形成溝槽 1 2，及將元件隔離層1 3形成於溝槽1 2中。此製程稱爲矽 溝槽隔離（STI)製程。 將非晶質碳層14形成在結果結構（resulting structure ) 200915439 上並在非晶質碳層14上實施用以形成凹陷區之^ (mask process)，藉以形成光阻圖案15。 使用光阻圖案1 5作爲蝕刻阻障而蝕刻非晶質碳 參照第1 B圖，使用非晶質碳層14作爲蝕刻阻 矽基板11而形成作爲電晶體通道之凹陷區1 6。G 亦稱爲凹陷通道。 參照第1C圖，在含有凹陷區16之矽基板11上 絕緣層1 7。將導電層沉積於閘極絕緣層1 7上直到 區16，及蝕刻沉積的導電層而形成閘極18。 然而，於半導體元件之超微細圖案化製程期間 成三維凹陷閘極之凹陷區的尺寸減少，而在電漿 中使凹陷閘極1 6的底部輪廓形成V型輪廓。此造 應（horneffect)，其中矽（Si)殘渣（參照如牛 於與元件隔離層1 3相鄰之上區中。矽殘渣係由聚 生’其中聚合物則由非晶質碳層之碳的再沉積所 第2圖說明顯示根據先前技術之牛角的掃瞄式 鏡（S EM )照片。能由第2圖觀察到牛角位於與 層相鄰之上區中。 牛角Η造成閘極絕緣層17劣化。牛角η係應 並成爲漏電流的來源，因而降低元件生產良率及價 難以製造。 寥照第3圖’牛角η係在以約90。以下之角度 1 2側壁時所形成的凹陷區1 6之V型輪廓所造成 1罩製程 層1 4。 障，餽刻 ：Π陷區1 6 形成閘極 塡滿凹陷 ，因能形 蝕刻製程 成牛角效 角Η)位 合物所產 製得。 電子顯微 元件隔離 力集中點 if# DRAM 形成溝槽 ，其中溝 200915439 槽1 2係以元件隔離層1 3予以間隙塡充。 第3圖說明顯示根據先前技術之以元件隔離層予以間隙 塡充的溝槽之側壁角度之S EM照片。能由第3圖觀察到溝 槽係以約90°以下之角度形成。 【發明內容】 本發明實施例係針對提供一種製造半導體元件之凹陷閘 極之方法，其能在形成凹陷閘極製程期間抑制凹陷區之蝕 刻製程中牛角的產生。 本發明實施例亦針對提供一種形成半導體元件之凹陷通 道之方法’其能進一步增加通道長度同時減少凹陷通道的 線寬。 根據本發明之一態樣，提供一種製造半導體元件之凹陷 閘極之方法。該方法包括：蝕刻矽基板而形成界定主動區 之溝槽；形成間隙塡充溝槽之元件隔離層；於矽基板上形 成硬遮罩層’硬遮罩層包含氧化層及非晶質碳層之堆疊， 其中硬遮罩層暴露主動區之通道目標區；及藉由使用硬遮 罩層作爲蝕刻咀障而將通道目標區進行第一蝕刻及第二蝕 刻以形成具有雙重輪廓之凹陷區，其中在移除非晶質碳層 後實施第二蝕刻。 根據本發明之另一態樣，提供一種形成半導體元件之凹 陷通道之方法。該方法包括：於半導體基板上形成硬遮罩 層’硬遮罩層包括鈍化層（passivation layer)及非晶質碳 層之堆疊’其中硬遮罩層暴露半導體基板之通道目標區； 200915439 使用非晶質碳層作爲蝕刻阻障而蝕刻通 —凹陷區；移除非晶質碳層；及使用鈍 而餓刻第一凹陷區底部以形成第二凹陷 根據本發明之另一態樣，提供一種製 陷閘極之方法。該方法包括：蝕刻矽基 區之溝槽；於溝槽中形成元件隔離層； 遮罩層’硬遮罩層包含氧化層及非晶質 層暴露主動區之通道目標區；使用非晶 障而將通道目標區實施第一蝕刻以形成 非晶質碳層；使用氧化層作爲蝕刻阻障 部實施第二蝕刻以形成第二凹陷區，其 一凹陷區寬。 根據本發明之另一態樣，提供一種形 陷通道之方法。該方法包括：於半導體 層’硬遮罩層包括鈍化層及非晶質碳層 露半導體基板之通道目標區；使用非晶 障而蝕刻通道目標區以形成第一凹陷 層·，及使用鈍化層作爲蝕刻阻障而蝕刻 形成第二凹陷區，其中第二凹陷區比第 【實施方式】 以下，將參照隨附圖式詳細敘述根據 體元件之凹陷閘極之方法。 請注意本文中當指示如層、薄膜、圖 道目標區以形成第 化層作爲蝕刻阻障 區。 造半導體元件之凹 板而形成界定主動 於矽基板上形成硬 碳層，其中硬遮罩 質碳層作爲蝕刻阻 第一凹陷區；移除 而將第一凹陷區底 中第二凹陷區比第 成半導體元件之凹 基板上形成硬遮罩 ’其中硬遮罩層暴 質碳層作爲蝕刻阻 區；移除非晶質碳 第一凹陷區底部以 一凹陷區寬。 本發明之製造半導 案及區域之元件爲 200915439 於（在）另一元件上/於（在）另一元件下時，其可能爲直 接於（在）另一元件上/於（在）另一元件下，及可能存在 一個以上介於其間之元件。 本發明實施例中，在用以形成凹陷區或凹陷通道之凹陷 蝕刻製程中使用具有鈍化層（例如氧化層）及非晶質碳層 之堆疊的硬遮罩層作爲飩刻阻障。凹陷蝕刻製程包括使用 非晶質碳層作爲蝕刻阻障之第一凹陷蝕刻製程及使用鈍化 層作爲蝕刻阻障之第二凹陷蝕刻製程。使用相同的蝕刻氣 體、相同的壓力、相同的來源功率（source power)及相同 的偏壓功率（b i a s ρ 〇 w e r )來實施第一凹陷蝕刻製程及第二 凹陷蝕刻製程，且在實施第二凹陷蝕刻製程前預先移除非 晶質碳層。換言之，係於非晶質碳層不存在的情況下實施 第二凹陷蝕刻製程。在此情況下，第二凹陷蝕刻製程中所 產生之聚合物量小於第一凹陷蝕刻製程中所產生者。因 此’可形成較寬的凹陷區並可防止在與元件隔離層相鄰的 區域中產生牛角。 第4A至4F圖說明根據本發明實施例的製造半導體元件 之凹陷閘極之方法。在此，每一圖式的右邊部分爲沿著Π -Π ’線之剖面圖。 參照第4A圖’使用淺溝槽隔離（STI )製程來形成元件 隔離層23而塡充矽基板21之溝槽22。由溝槽22界定主動 區，及可以約90。以下的角度形成溝槽22。 於矽基板21上形成硬遮罩層24。硬遮罩層24可包含氧 200915439 化層或非晶質碳層。較佳爲硬遮罩層24可含有氧化層24A 及非晶質碳層24B之堆疊。氧化層24A亦作爲保護矽基板 2 1表面的鈍化層。 於硬遮罩層24上形成抗反射塗布（ARC)層25，並在結 果結構上實施用於形成凹陷區之遮罩製程，以形成光阻圖 案26。ARC層25可爲有機底部抗反射塗布（OBARC)層。 參照第4B圖，使用光阻圖案26作爲鈾刻阻障來蝕刻ARC 層25及硬遮罩層24。可使用如電容式偶合電漿（C CP )型 或磁場強化反應性離子蝕刻（MERIE )型之電漿源來實施 這些蝕刻製程。使用含有％氣體及〇2氣體之混合物，以 及同時施加來源功率及偏壓功率來蝕刻A R C層2 5及非晶 質碳層24B。使用氧化層24A作爲蝕刻中止層來蝕刻非晶 質碳層24B。之後，使用含有〇2氣體、及CFx (例如CF4 ) 氣體與CHFx (例如CHF3 )氣體之一的混合物來蝕刻氧化層 24A。 參照第4C圖，移除光阻圖案26及殘留的ARC層25’。 使用殘留的非晶質碳層24B’作爲蝕刻阻障，實施第一凹陷 蝕刻製程而將矽基板2 1蝕刻至預定深度。藉由第一凹陷蝕 刻製程形成第一凹陷區27。使用變壓式偶合電漿（TCP ) 或感應偶合電漿（ICP )作爲電漿源及使用氯系氣體及溴系 氣體之混合物實施第一凹陷蝕刻製程。例如，較佳爲使用 HBr: Cl:之流量比約爲5: 1，施加約5 mtorr至約20mtorr 之壓力、約500W至約1500W之來源功率及約100V至約 -10- 200915439 300 V之偏壓功率來實施第一凹陷蝕刻製程。 藉由上述的第一凹陷餓刻製程’第一凹陷區27具有垂直 輪廓及具有約200A至約500人之深度。於另一實施例中， 可在用於触刻非晶質碳層24B之腔中原位實施第一凹陷蝕 刻製程。 參照第4D圖’在用於實施第一凹陷蝕刻製程之蝕刻設備 中原位移除殘留的非晶質碳層24B’ 。爲此目的，使用約 200 seem至約1〇〇〇 sccin之〇2電漿及施加來源功率而不施 加偏壓功率。 參照第4 E圖，使用殘留的氧化層2 4 A ’作爲蝕刻阻障， 實施第二凹陷蝕刻製程來蝕刻第一凹陷區27底部，藉以形 成第二凹陷區2 8。在此，在用於實施第一凹陷蝕刻製程及 移除殘留的非晶質碳層24B’之蝕刻設備中原位實施第二 凹陷蝕刻製程。例如，可在使用氯系氣體及溴系氣體之混 合物的TCP或ICP型電漿源之條件下實施第二凹陷蝕刻製 程。例如，較佳爲藉由施加約1 0 m t 〇 r r至約3 0 m t 〇 r r之壓 力、約500 W至約1500 W之來源功率及約100 V至約300 V 之偏壓功率來實施第二凹陷蝕刻製程。特別是，若分別使 用HBr及Ch作爲溴系氣體及氯系氣體，則較佳地HBr : Cl2 之流量比爲約5 : 1。藉由在上述蝕刻條件下蝕刻第一凹陷 區27底部所形成之第二凹陷區28具有隨著第二凹陷區28 深度增加而逐漸變寬的輪廓。較佳爲將第二凹陷區28形成 得比第一凹陷區27深，例如，至約700 A至約1 000A之厚 -11 - 200915439 度。 根據上述多個製程，第一凹陷區27及第二凹陷區28構 成具有雙重輪廓之凹陷區1〇〇,其中雙重輪廓具有不同的頂 部及底部輪廊。 第一凹陷區27及第二凹陷區28因下列原因而具有不同 輪廓。 因爲使用殘留的非晶質碳層24B’作爲蝕刻阻障而蝕刻 第一凹陷區27，由殘留的非晶質碳層24B’之碳產生大量 的聚合物。所產生的聚合物被再沉積使得鈾刻輪廓具有垂 直輪廓。 另一方面，在移除殘留的非晶質碳層24B’後形成第二 凹陷區28，而由碳產生相對小量的聚合物。如此，因爲沒 有來自碳聚合物之蝕刻障礙，所以第二凹陷區28比第一凹 陷區27寬。 即，第二凹陷區28被蝕刻多於第一凹陷區27。如此，能 抑制牛角發生於與元件隔離層23相鄰之區域中，且即使產 生牛角，其高度能被明顯地降低。 具有雙重輪廓之凹陷區丨〇〇具有加寬的輪廓，其中底部 寬度大於傳統的凹陷區約數十奈米。因而’不像先前技術， 其可形成具有縮小化牛角的凹陷區。參照第4E圖，元件符 號P 1代表傳統的輪廓而元件符號P2代表根據本發明實施 例的輪廓。可由第4E圖觀察到與傳統的輪廓相比，根據本 發明實施例之輪廓具有相當低的牛角。 -12- 200915439 在用於形成加寬的第二凹陷區28之第二凹陷鈾刻條件 之中，壓力、功率及氣體比率非常重要。較佳爲藉由施加 約lOmtorr至約30mtorr之壓力、約500 W至約1500 W之 來源功率及約100 V至約300 V之偏壓功率來實施第二凹 陷鈾刻製程。 在另一實施例中，在形成第二凹陷區2 8後，可額外地實 施第三凹陷蝕刻製程來進一步加寬第二凹陷區 2 8的寬 度。第三凹陷蝕刻製程係原位實施。例如，可使用TCP或 ICP作爲電漿源，及藉由使用HBr/Ch氣體與小量的SF6/〇2 氣體之混合物來實施第三凹陷蝕刻製程。較佳爲藉由施加 約20 mtorr至約100 mtorr之壓力、約500 W至約1500 W 之來源功率及約5 0 W以下之偏壓功率來實施第三凹陷蝕 刻製程。使用氯系氣體及氟系氣體之混合物、與小量的氧 氣體及氟系氣體之混合物來實施第三凹陷蝕刻製程。氟系 氣體可爲氟化氮（NFx )氣體或氟化碳（CFx )氣體，以及 如SFs氣體之氟化硫氣體。氟化氮氣體可爲NF3氣體，而氟 化碳氣體可爲CF4氣體。使用氟系氣體及氧氣體來引發等 向性蝕刻，且因此，能藉由第三凹陷蝕刻製程進一步加寬 第二凹陷區28。 當在上述蝕刻條件下實施第三凹陷蝕刻製程時，能進一 步將第二凹陷區2 8加寬例如約1 〇 n m至約1 5 n m。當實施 第三凹陷蝕刻製程，能進一步減少牛角高度。 利用使用TCP或ICP作爲電漿源之高密度蝕刻設備來實 -13- 200915439 施根據上述實施例之第一凹陷蝕刻製程及第二凹陷蝕刻製 程。在另一實施例中，可在安裝有法拉第屏蔽之ICP型蝕 刻設備中實施第一凹陷蝕刻製程及第二凹陷蝕刻製程。同 樣地，可在使用微波下降流（MDS )、電子迴旋共振（ECR ) 及螺旋型（Helical)之一作爲電漿源的飩刻設備中實施第 一凹陷蝕刻製程及第二凹陷蝕刻製程。 參照第4F圖，移除殘留的氧化層24A’及在含有凹陷區 100的矽基板21上形成閘極絕緣層29。之後，將導電層沉 積於閘極絕緣層29上直到凹陷區1 〇〇被塡滿，及蝕刻結果 結構而形成閘極30。因此，在閘極下之凹陷區1〇〇成爲電 晶體的凹陷通道。 第5圖說明顯示根據本發明實施例之牛角及凹陷區輪廓 的SEM照片。 參照第5圖，能觀察到相較於傳統的牛角，根據本發明 之牛角係相當低。同樣地，能觀察到凹陷區1 〇〇具有雙重 輪廓而非尖頭輪廓（pointed profile)。因此，即使當以約 9 0°以下之角度形成塡有元件隔離層之溝槽時，亦能減少牛 角的尺寸。因爲藉由第二凹陷蝕刻製程加寬第二凹陷區， 所以即使當將第一凹陷區形成爲具有較小線寬時，本發明 亦能增加通道長度。當縮減第一凹陷區之線寬時，能防止 與聞極之未封準（misalignment with a gate electrode)。提 供參考，當先前技術將凹陷區線寬形成爲約3 9 nm時，本 發明能將凹陷區線寬縮減至爲約3 1 nm。 -14- 200915439 結果’將牛角極小化，抑制漏電流’而改善元件之更牵斤 特性。因此，能改善元件製造良率及減少製造成本。 能藉由實驗設計（DOE )來達成用以減少牛角高度之最 適化蝕刻條件。 根據上述實施例，即使當在S TI製程中以約9 0。以下之角 度形成溝槽時，亦可將凹陷區的牛角減到最少。 同樣地，可藉由形成具有雙重輪廓之凹陷區而進一步增 加通道長度。 亦可將通過閘極（passing gate)區域的場氧化物損失 (f i e 1 d ο X i d e 1 〇 s s )減到最少同時減少牛角。通過閘極係與 相鄰於主動區端部的元件隔離層頂部交叉之閘極。因爲相 對於由氧化層所形成的元件隔離層，第二蝕刻具有高選擇 性，所以能防止場氧化物損失。 如上述’即使當在S TI製程中以約9 0。以下之角度形成溝 槽時，本發明亦能將凹陷區的牛角減到最少。因此，本發 明能防止閘極絕緣層之特性劣化及由於閘極絕緣層之特性 劣化所引起之應力集中。 本發明實施例能藉由形成具有雙重輪廓之凹陷區而進一 步增加通道長度。 本發明實施例亦能將通過閘極區域的場氧化物損失減到 最少同時減少牛角。因此，本發明實施例能改善半導體元 件特性。 雖然藉由參照特定實施例描述本發明，但對本領域之具 200915439 有通常知識者而言，在不悖離下述申請專利範圍所界定的 本發明之精神及範圍的情況下，可輕易進行各種變更及替 代。 【圖式簡單說明】 第1A至1C圖說明根據先前技術的製造半導體元件之凹 陷閘極之方法。 第2圖說明顯示根據先前技術之牛角的SEM照片。 第3圖說明顯示根據先前技術之以元件隔離層予以間隙 塡充的溝槽之側壁角度之SEM照片。 第4A至4F圖說明根據本發明實施例的製造半導體元件 之凹陷閘極之方法。 第5圖說明顯示根據本發明實施例之牛角及凹陷區輪廓 的SEM照片。 【主要元件符號說明】 1 1 > 21 矽 基 板 12、 22 溝 槽 13、 23 元 件 隔 離 層 14、 24B 非 晶 質 碳 層 15、 26 光 阻 圖 案 16 凹 陷 區 17、 .29 閘 極 絕 緣 層 18 、 .30 閘 極 24 硬 遮 罩 層 -16- 200915439 24A 氧 化 層 24A’ 殘 留 的 氧 化 層 24B’ 殘 留 的 非 晶 質碳層 25 抗 反 射 塗 布 (ARC)層 25， 殘 留 的 ARC 層 27 第 一 凹 陷 區 28 第 二 凹 陷 區 100 凹 陷 區 Η 牛 角 PI 傳 統 的 輪 廓 Ρ2 根 據 本 發 明 實施例的輪廓 -17-。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 This invention relates to the fabrication of semiconductor devices, and more particularly to a method of fabricating recessed gates for semiconductor components. [Prior Art] In the fabrication of a semiconductor device, a method of forming a planar gate is used to form a gate on a planar active region. However, the reduction in the channel length due to the reduction in the pattern size and the increase in the electric field due to the increase in the ion implantation doping concentration of the substrate cause junction leakage. This makes it difficult to obtain the updated characteristics of the component. In order to solve the above limitations, a three-dimensional recess gate process has been proposed as an alternative method of forming a gate which forms a gate after etching the active region. The recessed gate process allows for increased channel length and reduced ion implantation doping concentration, thereby improving the renewed characteristics of the device. Figs. 1A to 1C illustrate a method of manufacturing a depressed gate of a semiconductor element according to the prior art. Here, the right part of each figure is a cross-sectional view along the I - Γ line. Referring to Fig. 1A, the trench isolation region of the germanium substrate 11 is etched to form the trench 12, and the element isolation layer 13 is formed in the trench 12. This process is called a trench trench isolation (STI) process. The amorphous carbon layer 14 is formed on the resultant structure 200915439 and a mask process for forming a recessed region is performed on the amorphous carbon layer 14, whereby the photoresist pattern 15 is formed. Etching of amorphous carbon using the photoresist pattern 15 as an etching barrier Referring to Fig. 1B, a recessed region 16 as a transistor channel is formed using the amorphous carbon layer 14 as an etching stopper substrate 11. G is also known as a recessed channel. Referring to Fig. 1C, an insulating layer 17 is formed on the germanium substrate 11 including the recessed regions 16. A conductive layer is deposited on the gate insulating layer 17 until the region 16, and the deposited conductive layer is etched to form the gate 18. However, the size of the recessed region which becomes a three-dimensional recessed gate during the ultra-fine patterning process of the semiconductor element is reduced, and the bottom profile of the recessed gate 16 is formed into a V-shaped profile in the plasma. This horn effect, in which the cerium (Si) residue (see, for example, the cow is in the upper region adjacent to the element isolation layer 13), the ruthenium residue is formed by the accumulation of the polymer, and the polymer is composed of the carbon of the amorphous carbon layer. Figure 2 shows a scanning mirror (S EM ) photograph showing a horn according to the prior art. It can be observed from Fig. 2 that the horn is located in the upper region adjacent to the layer. The horns cause the gate insulation. 17 deterioration. The horn η system should be a source of leakage current, thus reducing the production yield and price of the component. It is difficult to manufacture. Referring to Fig. 3, the horn is formed by the horn angle η at an angle of about 90 degrees. Zone 1 6 V-shaped profile caused by a cover process layer 1 4. Barrier, feed engraving: Envelope zone 1 6 Forming a gate full-filled depression, due to the ability to form a etch process into a horn effect Η) Got it. Electron microscopy element isolation force concentration point if# DRAM forms trenches, where trenches 200915439 trenches 1 2 are interstitially filled with component isolation layers 13. Figure 3 illustrates an S EM photograph showing the sidewall angle of a trench filled with a gap by an element isolation layer according to the prior art. It can be observed from Fig. 3 that the groove system is formed at an angle of about 90 or less. SUMMARY OF THE INVENTION Embodiments of the present invention are directed to a method of fabricating a recessed gate of a semiconductor device capable of suppressing generation of horns in an etching process of a recessed region during formation of a recessed gate process. Embodiments of the present invention are also directed to a method of forming a recessed via for a semiconductor device which can further increase the length of the channel while reducing the line width of the recessed via. According to an aspect of the present invention, a method of fabricating a recessed gate of a semiconductor device is provided. The method comprises: etching a germanium substrate to form a trench defining an active region; forming an element isolation layer of the gap filling trench; forming a hard mask layer on the germanium substrate, the hard mask layer comprising an oxide layer and an amorphous carbon layer a stack, wherein the hard mask layer exposes the channel target region of the active region; and the first target etching and the second etching are performed by using the hard mask layer as an etch barrier to form a recessed region having a double contour, Wherein the second etching is performed after removing the amorphous carbon layer. According to another aspect of the present invention, a method of forming a recessed via of a semiconductor component is provided. The method includes: forming a hard mask layer on a semiconductor substrate, the hard mask layer comprising a passivation layer and a stack of amorphous carbon layers, wherein the hard mask layer exposes a channel target region of the semiconductor substrate; 200915439 The crystalline carbon layer etches the via-recessed region as an etch barrier; removes the amorphous carbon layer; and uses the blunt and hungry first recessed region bottom to form the second recess. According to another aspect of the present invention, a The method of trapping the gate. The method includes: etching a trench of the germanium base region; forming an element isolation layer in the trench; the mask layer 'hard mask layer includes an oxide layer and the amorphous layer exposing the active region of the channel target region; using an amorphous barrier The channel target region is subjected to a first etching to form an amorphous carbon layer; the second etching is performed using the oxide layer as an etch barrier to form a second recessed region having a recessed region wide. According to another aspect of the invention, a method of forming a recessed channel is provided. The method includes: in a semiconductor layer, a hard mask layer includes a passivation layer and a channel target region of an amorphous carbon layer exposed semiconductor substrate; etching a channel target region to form a first recess layer using an amorphous barrier, and using a passivation layer The second recessed region is etched as an etch barrier, wherein the second recessed region is compared to the first embodiment. Hereinafter, a method according to the recessed gate of the bulk element will be described in detail with reference to the accompanying drawings. Please note that the layers, film, and target regions are indicated herein to form a morphing layer as an etch barrier. Forming a concave plate of the semiconductor component to form a hard carbon layer formed on the substrate, wherein the hard mask carbon layer serves as a first recessed region of the etching resist; and removing the second recessed region in the bottom of the first recessed region A hard mask is formed on the concave substrate of the semiconductor element, wherein the hard mask layer of the hard mask layer serves as an etch stop region; and the bottom portion of the first recessed region of the amorphous carbon is removed to have a recessed region width. The elements of the manufacturing semi-guide and region of the present invention are 200915439 on or under another component, which may be directly on (in) another component/on (in) another component Under one component, there may be more than one component in between. In an embodiment of the invention, a hard mask layer having a passivation layer (e.g., an oxide layer) and a stack of amorphous carbon layers is used as a etch barrier in a recess etch process for forming recessed regions or recessed vias. The recess etch process includes a first recess etch process using an amorphous carbon layer as an etch barrier and a second recess etch process using a passivation layer as an etch barrier. Performing the first recess etching process and the second recess etching process using the same etching gas, the same pressure, the same source power, and the same bias power (bias ρ 〇wer ), and implementing the second recess The amorphous carbon layer is previously removed before the etching process. In other words, the second recess etching process is performed in the absence of the amorphous carbon layer. In this case, the amount of polymer produced in the second recess etching process is smaller than that produced in the first recess etching process. Therefore, a wider depressed area can be formed and horns can be prevented from occurring in a region adjacent to the element isolation layer. 4A through 4F illustrate a method of fabricating a recessed gate of a semiconductor device in accordance with an embodiment of the present invention. Here, the right part of each figure is a cross-sectional view along the line Π - Π '. The trench isolation layer 23 is formed by using a shallow trench isolation (STI) process to fill the trench 22 of the substrate 21 with reference to FIG. 4A. The active region is defined by trenches 22 and may be about 90. The grooves 22 are formed at the following angles. A hard mask layer 24 is formed on the germanium substrate 21. The hard mask layer 24 may comprise an oxygen layer of 200915439 or an amorphous carbon layer. Preferably, the hard mask layer 24 can comprise a stack of an oxide layer 24A and an amorphous carbon layer 24B. The oxide layer 24A also serves as a passivation layer for protecting the surface of the crucible substrate 21. An anti-reflective coating (ARC) layer 25 is formed on the hard mask layer 24, and a masking process for forming recessed regions is performed on the resultant structure to form a photoresist pattern 26. The ARC layer 25 can be an organic bottom anti-reflective coating (OBARC) layer. Referring to FIG. 4B, the ARC layer 25 and the hard mask layer 24 are etched using the photoresist pattern 26 as a uranium barrier. These etching processes can be performed using a plasma source such as a capacitively coupled plasma (C CP ) type or a magnetic field enhanced reactive ion etching (MERIE ) type. The A R C layer 25 and the amorphous carbon layer 24B are etched using a mixture containing % gas and 〇 2 gas, and simultaneously applying source power and bias power. The amorphous carbon layer 24B is etched using the oxide layer 24A as an etch stop layer. Thereafter, the oxide layer 24A is etched using a mixture containing ruthenium dioxide gas and one of CFx (e.g., CF4) gas and one of CHFx (e.g., CHF3) gases. Referring to Fig. 4C, the photoresist pattern 26 and the remaining ARC layer 25' are removed. Using the residual amorphous carbon layer 24B' as an etch barrier, a first recess etching process is performed to etch the germanium substrate 2 1 to a predetermined depth. The first recessed region 27 is formed by a first recess etching process. The first recess etching process is performed using a transformer-coupled plasma (TCP) or an inductively coupled plasma (ICP) as a plasma source and a mixture of a chlorine-based gas and a bromine-based gas. For example, it is preferred to use a flow ratio of HBr:Cl: of about 5:1, a pressure of about 5 mtorr to about 20 mtorr, a source power of about 500 W to about 1500 W, and a bias of about 100 V to about -10-200915439 300 V. The first recess etching process is performed by compressing power. The first recessed region 27 has a vertical profile and has a depth of from about 200 A to about 500 by the first recessed process described above. In another embodiment, the first etch process can be performed in situ in a cavity for etching the amorphous carbon layer 24B. The residual amorphous carbon layer 24B' is removed in situ in the etching apparatus for performing the first recess etching process with reference to Fig. 4D. For this purpose, a plasma of about 200 seem to about 1 〇〇〇 sccin is used and source power is applied without applying bias power. Referring to Fig. 4E, a second recess etching process is performed to etch the bottom of the first recessed region 27, using the residual oxide layer 2 4 A ' as an etch barrier, thereby forming a second recessed region 28. Here, the second recess etching process is performed in-situ in an etching apparatus for performing the first recess etching process and removing the residual amorphous carbon layer 24B'. For example, the second recess etching process can be carried out under the conditions of a TCP or ICP type plasma source using a mixture of a chlorine-based gas and a bromine-based gas. For example, it is preferred to implement the second by applying a pressure of about 10 mt rrrr to about 30 mt rrrr, a source power of about 500 W to about 1500 W, and a bias power of about 100 V to about 300 V. The recess etching process. In particular, when HBr and Ch are used as the bromine-based gas and the chlorine-based gas, respectively, the flow ratio of HBr:Cl2 is preferably about 5:1. The second recessed region 28 formed by etching the bottom of the first recessed region 27 under the above etching conditions has a profile which gradually widens as the depth of the second recessed region 28 increases. Preferably, the second recessed region 28 is formed deeper than the first recessed region 27, for example, to a thickness of from about 700 A to about 1 000 Å - 200915439 degrees. According to the plurality of processes described above, the first recessed area 27 and the second recessed area 28 constitute a recessed area 1 具有 having a double contour, wherein the double outline has different top and bottom lands. The first recessed area 27 and the second recessed area 28 have different profiles for the following reasons. Since the first recessed region 27 is etched using the residual amorphous carbon layer 24B' as an etching barrier, a large amount of polymer is generated from the carbon of the residual amorphous carbon layer 24B'. The resulting polymer is redeposited such that the uranium engraved profile has a vertical profile. On the other hand, the second recessed region 28 is formed after the residual amorphous carbon layer 24B' is removed, and a relatively small amount of polymer is produced from carbon. Thus, the second recessed region 28 is wider than the first recessed region 27 because there is no etching barrier from the carbon polymer. That is, the second recessed region 28 is etched more than the first recessed region 27. Thus, it is possible to suppress the occurrence of horns in the region adjacent to the element isolation layer 23, and the height can be remarkably lowered even if a horn is produced. The recessed region having a double contour has a widened profile in which the bottom width is greater than a conventional recessed area of about several tens of nanometers. Thus, unlike the prior art, it is possible to form a recessed area having a reduced horn. Referring to Fig. 4E, the component symbol P 1 represents a conventional outline and the component symbol P2 represents an outline according to an embodiment of the present invention. It can be observed from Fig. 4E that the outline according to an embodiment of the present invention has a relatively low horn compared to the conventional outline. -12- 200915439 Among the second recessed uranium engraving conditions for forming the widened second recessed region 28, pressure, power and gas ratios are very important. Preferably, the second recessed uranium engraving process is carried out by applying a pressure of from about 10 mtorr to about 30 mtorr, a source power of from about 500 W to about 1500 W, and a bias power of from about 100 V to about 300 V. In another embodiment, after the second recess region 28 is formed, a third recess etching process may be additionally performed to further widen the width of the second recess region 28. The third recess etch process is performed in situ. For example, TCP or ICP can be used as the plasma source, and the third recess etching process can be performed by using a mixture of HBr/Ch gas and a small amount of SF6/〇2 gas. Preferably, the third recess etching process is carried out by applying a pressure of about 20 mtorr to about 100 mtorr, a source power of about 500 W to about 1500 W, and a bias power of about 50 W or less. The third recess etching process is performed using a mixture of a chlorine-based gas and a fluorine-based gas and a mixture of a small amount of oxygen gas and a fluorine-based gas. The fluorine-based gas may be a nitrogen fluoride (NFx) gas or a carbon fluoride (CFx) gas, and a sulfur fluoride gas such as an SFs gas. The fluorinated nitrogen gas may be NF3 gas, and the fluorinated carbon gas may be CF4 gas. The fluorine-based gas and the oxygen gas are used to initiate the isotropic etching, and therefore, the second recessed region 28 can be further widened by the third recess etching process. When the third recess etching process is performed under the above etching conditions, the second recessed region 28 can be further widened by, for example, about 1 〇 n m to about 15 n m. When the third recess etching process is implemented, the height of the horn can be further reduced. The first recess etching process and the second recess etching process according to the above embodiment are applied by using a high-density etching apparatus using TCP or ICP as a plasma source. In another embodiment, the first recess etch process and the second recess etch process can be performed in an ICP type etch device equipped with a Faraday shield. Similarly, the first recess etching process and the second recess etching process can be performed in an etching apparatus using one of microwave descending flow (MDS), electron cyclotron resonance (ECR), and spiral (Helical) as a plasma source. Referring to Fig. 4F, the residual oxide layer 24A' is removed and a gate insulating layer 29 is formed on the germanium substrate 21 having the recessed regions 100. Thereafter, a conductive layer is deposited on the gate insulating layer 29 until the recessed region 1 is filled, and the resulting structure is etched to form the gate 30. Therefore, the recessed region 1 under the gate becomes a recessed channel of the transistor. Figure 5 illustrates an SEM photograph showing the outline of the horns and depressions in accordance with an embodiment of the present invention. Referring to Figure 5, it can be observed that the horns according to the present invention are relatively low compared to conventional horns. Similarly, it can be observed that the recessed area 1 〇〇 has a double profile rather than a pointed profile. Therefore, even when the groove having the element isolation layer is formed at an angle of about 90 ° or less, the size of the horn can be reduced. Since the second recessed region is widened by the second recess etching process, the present invention can increase the channel length even when the first recessed region is formed to have a small line width. When the line width of the first recessed region is reduced, misalignment with a gate electrode can be prevented. To provide a reference, the present invention can reduce the width of the recessed region to about 31 nm when the prior art forms the line width of the recessed region to about 39 nm. -14- 200915439 The result 'improves the horn angle and suppresses the leakage current' to improve the more attractive characteristics of the component. Therefore, component manufacturing yield and manufacturing cost can be improved. The optimum etching conditions for reducing the height of the horn can be achieved by experimental design (DOE). According to the above embodiment, even when it is in the S TI process, it is about 90. When the following angles form a groove, the horn of the recessed area can also be minimized. Similarly, the channel length can be further increased by forming a recessed region having a double profile. It is also possible to minimize the field oxide loss (f i e 1 d ο X i d e 1 〇 s s ) through the passing gate region while reducing the horn. The gate crossing the gate with the top of the element isolation layer adjacent to the end of the active region. Since the second etching has high selectivity with respect to the element isolation layer formed of the oxide layer, field oxide loss can be prevented. As described above' even when it is about 90 in the S TI process. The present invention also minimizes the horn of the recessed area when the following angles form the groove. Therefore, the present invention can prevent deterioration of characteristics of the gate insulating layer and stress concentration due to deterioration of characteristics of the gate insulating layer. Embodiments of the present invention can further increase the length of the channel by forming a recessed region having a double contour. Embodiments of the present invention can also minimize field oxide loss through the gate region while reducing horns. Therefore, the embodiment of the present invention can improve the characteristics of semiconductor elements. Although the present invention has been described with reference to the specific embodiments of the present invention, it is possible to carry out various embodiments without departing from the spirit and scope of the invention as defined by the following claims. Changes and substitutions. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A to 1C illustrate a method of manufacturing a depressed gate of a semiconductor element according to the prior art. Figure 2 illustrates an SEM photograph showing the horn of the prior art. Figure 3 illustrates an SEM photograph showing the sidewall angle of a trench filled with a gap by an element isolation layer according to the prior art. 4A through 4F illustrate a method of fabricating a recessed gate of a semiconductor device in accordance with an embodiment of the present invention. Figure 5 illustrates an SEM photograph showing the outline of the horns and depressions in accordance with an embodiment of the present invention. [Main component symbol description] 1 1 > 21 矽 substrate 12, 22 trench 13, 23 element isolation layer 14, 24B amorphous carbon layer 15, 26 photoresist pattern 16 recessed region 17, . 29 gate insulating layer 18 , .30 gate 24 hard mask layer-16- 200915439 24A oxide layer 24A' residual oxide layer 24B' residual amorphous carbon layer 25 anti-reflective coating (ARC) layer 25, residual ARC layer 27 first depression Zone 28 second recessed zone 100 recessed zone 牛 horn PI conventional contour Ρ 2 contour -17- according to an embodiment of the invention

Claims (1)

200915439 十、申請專利範圍： 1. 一種製造半導體元件之凹陷閘極之方法，該方法包β : 蝕刻矽基板而形成界定主動區之溝槽； 形成間隙塡充（gap-fill )該溝槽之元件隔離層； 於該矽基板上形成硬遮罩層，該硬遮罩層包含氧化胃 及非晶質碳層之堆疊，其中該硬遮罩層暴露該主動區之 通道目標區；及 藉由使用該硬遮罩層作爲蝕刻阻障而將該通道目標區 進行第一蝕刻及第二蝕刻以形成具有雙重輪廓之凹陷 區， 其中在移除該非晶質碳層後實施該第二蝕刻。 2·如申請專利範圍第1項之方法，其中進一步包括在該第 二蝕刻後，實施原位第三蝕刻以增加該凹陷區之寬度。 3 ·如申請專利範圍第1項之方法，其中形成該凹陷區包括： 使用該非晶質碳層作爲蝕刻阻障而實施該第一蝕刻以 形成第一凹陷區； 移除該非晶質碳層；及 使用該氧化層作爲蝕刻阻障而實施該第二蝕刻以形成 第二凹陷區，其中該第二凹陷區比該第一凹陷區寬。 4 ·如申請專利範圍第3項之方法，其中在電漿蝕刻設備中 原位實施該第一蝕刻、該非晶質碳層之移除、及該第二 蝕刻。 5 .如申請專利範圍第4項之方法，其中使用氯系氣體及溴 -18- 200915439 系热體之混合物實施該弟一餓刻及該第二餓刻。 6.如申請專利範圍第5項之方法，其中以η B r : C12爲約5 : 1之流量比、施加約5 mtorr至約20 mtorr之壓力、約500 W至約1500 W之來源功率（source p〇wer)、及約1〇〇 V 至約300 V之偏壓功率（bias power)來實施該第一餓刻 及該第二蝕刻。 7 .如申請專利範圍第4項之方法，其中使用流量爲約2 0 0 seem至約1000 seem之〇2電漿及藉由施加來源功率而不 施加偏壓功率來移除該非晶質碳層。 8. 如申請專利範圍第2項之方法，其中藉由將氟系氣體及 氧氣體之混合物添加至氯系氣體及溴系氣體之混合物中 來實施該第三蝕刻。 9. 如申請專利範圍第8項之方法，其中該氟系氣體包括氟 化硫氣體、氟化氮氣體、及氟化碳氣體之一者。 10·如申請專利範圍第8項之方法，其中藉由施加約20 mtorr 至約100 mtorr之壓力、約500 W至約1500 W之來源功 率、及約5 0 W以下之偏壓功率來實施該第三鈾刻。 11.如申請專利範圍第8項之方法，其中該溴系氣體爲HBr 及該氯系氣體爲Cl2。 1 2.如申請專利範圍第4項之方法，其中該電漿飩刻設備使 用磁場強化反應性離子蝕刻（MERIE )、變壓式偶合電 漿（TCP)、感應偶合電漿（ICP) '微波下降流（MDS )、 電子迴旋共振（ECR)、及螺旋型（Helical)之一者作 200915439 爲電漿源。 13.—種形成半導體元件之凹陷通道之方法，該方法包括： 於半導體基板上形成硬遮罩層，該硬遮罩層包括鈍化 層（passivation layer)及非晶質碳層之堆疊，其中該硬 遮罩層暴露該半導體基板之通道目標區； 使用該非晶質碳層作爲蝕刻阻障而蝕刻該通道目標 區以形成第一凹陷區： 移除該非晶質碳層；及 使用該鈍化層作爲蝕刻阻障而蝕刻該第一凹陷區底 部以形成第二凹陷區。 1 4 .如申請專利範圍第1 3項之方法，其中在電漿蝕刻設備 中原位實施該蝕刻通道目標區、該移除非晶質碳層、及 該蝕刻第一凹陷區底部。 1 5 .如申請專利範圍第1 4項之方法，其中使用相同的蝕刻 氣體、相同的壓力、相同的來源功率、及相同的偏壓功 率來實施該蝕刻通道目標區及該蝕刻第一凹陷區底部° 1 6 .如申請專利範圍第1 4項之方法，其中使用〇2電槳及藉 由施加來源功率而不施加偏壓功率來移除該非晶質碳 層。 1 7 .如申請專利範圍第1 4項之方法，其中該電辕餓刻5又備 使用磁場強化反應性離子蝕刻（MERIE )、變壓式偶合 電漿（TCP )、感應偶合電漿（ICP )、微波下降流（MDS )、 電子迴旋共振（ECR)、及螺旋型（Helical)之一者作 -2〇 - 200915439 爲電漿源。 1 8 .如申請專利範圍第1 3項之方法，其中該半導體基板包 括矽基板及該鈍化層包括氧化層。 1 9 ·如申請專利範圍第1 3項之方法，其中進一步包括在蝕 刻該第一凹陷區底部後，實施原位蝕刻以增加該第二凹 陷區之寬度。 20.—種製造半導體元件之凹陷閘極之方法，該方法包括： 蝕刻矽基板而形成界定主動區之溝槽； 於該溝槽中形成元件隔離層； 於該矽基板上形成硬遮罩層，該硬遮罩層包含氧化層 及非晶質碳層，其中該硬遮罩層暴露該主動區之通道目 標區； 使用該非晶質碳層作爲蝕刻阻障而將該通道目標區 進行第一蝕刻以形成第一凹陷區； 移除該非晶質碳層； 使用氧化層作爲蝕刻阻障而將第一凹陷區底部進行 第二蝕刻以形成第二凹陷區，其中該第二凹陷區比該第 —凹陷區寬。 2 1 .如申請專利範圍第20項之方法，其中進一步包括將該 凹陷區實施第三蝕刻以加寬該第二凹陷區。 22.—種形成半導體元件之凹陷通道之方法’該方法包括： 於半導體基板上形成硬遮罩層，該硬遮罩層包括鈍化 層及非晶質碳層’其中該硬遮罩層暴露該半導體基板之 -21- 200915439 通道目標區； 使用該非晶質碳層作爲蝕刻阻障而蝕刻該通道目標 區以形成第一凹陷區； 移除該非晶質碳層；及 使用該鈍化層作爲蝕刻阻障而蝕刻該第一凹陷區底 部以形成第二凹陷區，其中該第二凹陷區比該第一凹陷 區寬。 2 3.如申請專利範圍第22項之方法，其中進一步包括蝕刻 該第二凹陷區之側邊以增加該第二凹陷區之寬度。 -22-200915439 X. Patent Application Range: 1. A method for manufacturing a recessed gate of a semiconductor device, the method comprising: etching a germanium substrate to form a trench defining an active region; forming a gap-filling the trench a component isolation layer; forming a hard mask layer on the germanium substrate, the hard mask layer comprising a stack of oxidized stomach and amorphous carbon layers, wherein the hard mask layer exposes a channel target region of the active region; The hard mask layer is used as an etch barrier to perform a first etch and a second etch of the channel target region to form a recessed region having a double profile, wherein the second etch is performed after removing the amorphous carbon layer. 2. The method of claim 1, further comprising performing an in-situ third etch after the second etch to increase the width of the recessed region. 3. The method of claim 1, wherein the forming the recessed region comprises: performing the first etching to form a first recessed region using the amorphous carbon layer as an etch barrier; removing the amorphous carbon layer; And performing the second etching using the oxide layer as an etch barrier to form a second recessed region, wherein the second recessed region is wider than the first recessed region. 4. The method of claim 3, wherein the first etching, the removal of the amorphous carbon layer, and the second etching are performed in situ in a plasma etching apparatus. 5. The method of claim 4, wherein the chlorine gas and the mixture of bromo -18-200915439 hot bodies are used to carry out the hunger and the second hungry. 6. The method of claim 5, wherein η B r : C12 is a flow ratio of about 5:1, a pressure of about 5 mtorr to about 20 mtorr, and a source power of about 500 W to about 1500 W ( The first hungry and the second etch are performed by source p〇wer) and a bias power of about 1 〇〇V to about 300 V. 7. The method of claim 4, wherein the amorphous carbon layer is removed by using a plasma having a flow rate of from about 200 to about 1000 seem and applying a source of power without applying a bias power. . 8. The method of claim 2, wherein the third etching is performed by adding a mixture of a fluorine-based gas and an oxygen gas to a mixture of a chlorine-based gas and a bromine-based gas. 9. The method of claim 8, wherein the fluorine-based gas comprises one of a sulfur fluoride gas, a nitrogen fluoride gas, and a carbon fluoride gas. 10. The method of claim 8, wherein the applying is performed by applying a pressure of about 20 mtorr to about 100 mtorr, a source power of about 500 W to about 1500 W, and a bias power of about 50 W or less. Third uranium engraving 11. The method of claim 8, wherein the bromine-based gas is HBr and the chlorine-based gas is Cl2. 1 2. The method of claim 4, wherein the plasma etching apparatus uses magnetic field enhanced reactive ion etching (MERIE), variable pressure coupling plasma (TCP), inductively coupled plasma (ICP) 'microwave One of the downflow (MDS), electron cyclotron resonance (ECR), and spiral (Helical) is used as a plasma source for 200915439. 13. A method of forming a recessed via of a semiconductor device, the method comprising: forming a hard mask layer on a semiconductor substrate, the hard mask layer comprising a passivation layer and a stack of amorphous carbon layers, wherein a hard mask layer exposing a channel target region of the semiconductor substrate; etching the channel target region using the amorphous carbon layer as an etch barrier to form a first recess region: removing the amorphous carbon layer; and using the passivation layer as Etching the barrier to etch the bottom of the first recessed region to form a second recessed region. The method of claim 13, wherein the etching channel target region, the removing the amorphous carbon layer, and the etching the bottom of the first recess region are performed in situ in the plasma etching apparatus. The method of claim 14, wherein the etching channel target region and the etching first recess region are implemented using the same etching gas, the same pressure, the same source power, and the same bias power. The bottom portion is a method of claim 14, wherein the amorphous carbon layer is removed using a 〇2 electric paddle and by applying source power without applying bias power. 1 7 . The method of claim 14, wherein the electric device is hungry and has a magnetic field enhanced reactive ion etching (MERIE), a variable-pressure coupled plasma (TCP), and an inductively coupled plasma (ICP). ), one of microwave descending flow (MDS), electron cyclotron resonance (ECR), and spiral type (Helical) is -2〇- 200915439 is a plasma source. The method of claim 13, wherein the semiconductor substrate comprises a germanium substrate and the passivation layer comprises an oxide layer. The method of claim 13, wherein the method further comprises performing an in-situ etch to increase the width of the second recessed region after etching the bottom of the first recessed region. 20. A method of fabricating a recessed gate of a semiconductor device, the method comprising: etching a germanium substrate to form a trench defining an active region; forming an element isolation layer in the trench; forming a hard mask layer on the germanium substrate The hard mask layer includes an oxide layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the active region; and the channel target region is first used by using the amorphous carbon layer as an etch barrier Etching to form a first recessed region; removing the amorphous carbon layer; performing a second etching on the bottom of the first recessed region to form a second recessed region using the oxide layer as an etch barrier, wherein the second recessed region is - The width of the depression is wide. The method of claim 20, further comprising performing a third etch of the recessed region to widen the second recessed region. 22. A method of forming a recessed via of a semiconductor device. The method comprises: forming a hard mask layer on a semiconductor substrate, the hard mask layer comprising a passivation layer and an amorphous carbon layer 'where the hard mask layer exposes the a semiconductor substrate - 21-200915439 channel target region; etching the channel target region using the amorphous carbon layer as an etch barrier to form a first recess region; removing the amorphous carbon layer; and using the passivation layer as an etch stop The bottom of the first recessed region is etched to form a second recessed region, wherein the second recessed region is wider than the first recessed region. 2. The method of claim 22, further comprising etching a side of the second recessed region to increase a width of the second recessed region. -twenty two-
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